From ff5097ef2a975a0132b5ac41da31df4f1a5a2e19 Mon Sep 17 00:00:00 2001 From: Narayan Reddy Date: Mon, 18 Jul 2022 10:17:12 +0000 Subject: [PATCH] NVIDIA: SAUCE: net: phy: aqr: configure 1G, 100M of aqr PHY to XFI/2 BugLink: https://bugs.launchpad.net/bugs/2072591 Issue: In case of MAC/UPHY operating at 5G speed in XFI mode, Data transfers should work with the line speeds 5G/2.5G/1G/100M. Currently data transfers are not working when the line speed is at 1G. Fix: Configure 1G and 100M of aquantia PHY registers to XFI/2 mode when MAC and UPHY speeds are configured to 5G. http://nvbugs/3599876 http://nvbugs/3708826 http://nvbugs/3660440 Signed-off-by: Narayan Reddy Signed-off-by: Revanth Kumar Uppala Tested-by: Abhilash G Reviewed-by: Abhilash G Signed-off-by: Laxman Dewangan Acked-by: Jacob Martin Acked-by: Noah Wager Signed-off-by: Noah Wager --- drivers/net/phy/aquantia/aquantia_main.c | 57 +++++++++++++++++++++--- 1 file changed, 51 insertions(+), 6 deletions(-) diff --git a/drivers/net/phy/aquantia/aquantia_main.c b/drivers/net/phy/aquantia/aquantia_main.c index 5c85d4504867..f623810a430b 100644 --- a/drivers/net/phy/aquantia/aquantia_main.c +++ b/drivers/net/phy/aquantia/aquantia_main.c @@ -334,14 +334,59 @@ static int aqr_config_aneg(struct phy_device *phydev) if (!err) { if (phy_mode == 1) { phydev_info(phydev, "Configuring AQR PHY to 5G Mode\n"); - phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_2_5G, 0x0106); - phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_5G, 0x0106); - phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_10G, 0x0000); + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_2_5G, 0x0106); + if (ret < 0) { + phydev_info(phydev, "Fail to configure VEND1_GLOBAL_CFG_2_5GT\n"); + return ret; + } + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_5G, 0x0106); + if (ret < 0) { + phydev_info(phydev, "Fail to configure VEND1_GLOBAL_CFG_5G\n"); + return ret; + } + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_SYS_CONFIG_1G, + 0x0106); + if (ret < 0) { + phydev_info(phydev, "Fail to configure VEND1_GLOBAL_SYS_CONFIG_1G\n"); + return ret; + } + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_SYS_CONFIG_100M, + 0x0106); + if (ret < 0) { + phydev_info(phydev, "Fail to configure VEND1_GLOBAL_SYS_CONFIG_100M\n"); + return ret; + } + + ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_10G, 0x0000); + if (ret < 0) { + phydev_info(phydev, "Fail to configure VEND1_GLOBAL_CFG_10G\n"); + return ret; + } + /* Disable 10G advertizement and restart autoneg */ - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 0x01E1); + ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 0x01E1); + if (ret < 0) { + phydev_info(phydev, "Fail to configure MDIO_AN_10GBT_CTRL\n"); + return ret; + } + /* restart auto-negotiation */ - genphy_c45_restart_aneg(phydev); - phy_write_mmd(phydev, MDIO_MMD_PHYXS, VEND1_GLOBAL_MDIO_PHYXS_PROV2, 0x8); + ret = genphy_c45_restart_aneg(phydev); + if (ret < 0) { + phydev_info(phydev, "Fail to restart auto neg\n"); + return ret; + } + + ret = phy_write_mmd(phydev, MDIO_MMD_PHYXS, VEND1_GLOBAL_MDIO_PHYXS_PROV2, + 0x8); + if (ret < 0) { + phydev_info(phydev, "Fail to configure VEND1_GLOBAL_MDIO_PHYXS_PROV2\n"); + return ret; + } } } else { phydev_info(phydev, "No AQR phy_mode setting in DT\n");