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NVIDIA: SAUCE: net: phy: aqr: configure 1G, 100M of aqr PHY to XFI/2

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BugLink: https://bugs.launchpad.net/bugs/2072591

Issue: In case of MAC/UPHY operating at 5G speed in XFI mode,
Data transfers should work with the line speeds 5G/2.5G/1G/100M.
Currently data transfers are not working when the line speed
is at 1G.

Fix: Configure 1G and 100M of aquantia PHY registers to XFI/2 mode
when MAC and UPHY speeds are configured to 5G.

http://nvbugs/3599876
http://nvbugs/3708826
http://nvbugs/3660440

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com>
Tested-by: Abhilash G <abhilashg@nvidia.com>
Reviewed-by: Abhilash G <abhilashg@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
This commit is contained in:
Narayan Reddy
2022-07-18 10:17:12 +00:00
committed by Noah Wager
parent d8a2ae8d16
commit ff5097ef2a
1 changed files with 51 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/net/phy/aquantia/aquantia_main.c
+51 -6
View File
@@ -334,14 +334,59 @@ static int aqr_config_aneg(struct phy_device *phydev)
if (!err) {
if (phy_mode == 1) {
phydev_info(phydev, "Configuring AQR PHY to 5G Mode\n");
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_2_5G, 0x0106);
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_5G, 0x0106);
phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_10G, 0x0000);
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_2_5G, 0x0106);
if (ret < 0) {
phydev_info(phydev, "Fail to configure VEND1_GLOBAL_CFG_2_5GT\n");
return ret;
}
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_5G, 0x0106);
if (ret < 0) {
phydev_info(phydev, "Fail to configure VEND1_GLOBAL_CFG_5G\n");
return ret;
}
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_SYS_CONFIG_1G,
0x0106);
if (ret < 0) {
phydev_info(phydev, "Fail to configure VEND1_GLOBAL_SYS_CONFIG_1G\n");
return ret;
}
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_SYS_CONFIG_100M,
0x0106);
if (ret < 0) {
phydev_info(phydev, "Fail to configure VEND1_GLOBAL_SYS_CONFIG_100M\n");
return ret;
}
ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_10G, 0x0000);
if (ret < 0) {
phydev_info(phydev, "Fail to configure VEND1_GLOBAL_CFG_10G\n");
return ret;
}
/* Disable 10G advertizement and restart autoneg */
phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 0x01E1);
ret = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 0x01E1);
if (ret < 0) {
phydev_info(phydev, "Fail to configure MDIO_AN_10GBT_CTRL\n");
return ret;
}
/* restart auto-negotiation */
genphy_c45_restart_aneg(phydev);
phy_write_mmd(phydev, MDIO_MMD_PHYXS, VEND1_GLOBAL_MDIO_PHYXS_PROV2, 0x8);
ret = genphy_c45_restart_aneg(phydev);
if (ret < 0) {
phydev_info(phydev, "Fail to restart auto neg\n");
return ret;
}
ret = phy_write_mmd(phydev, MDIO_MMD_PHYXS, VEND1_GLOBAL_MDIO_PHYXS_PROV2,
0x8);
if (ret < 0) {
phydev_info(phydev, "Fail to configure VEND1_GLOBAL_MDIO_PHYXS_PROV2\n");
return ret;
}
}
} else {
phydev_info(phydev, "No AQR phy_mode setting in DT\n");