Merge tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC specific changes from Arnd Bergmann:
"Lots of changes specific to one of the SoC families. Some that stick
out are:
- mach-qcom gains new features, most importantly SMP support for the
newer chips (Stephen Boyd, Rohit Vaswani)
- mvebu gains support for three new SoCs: Armada 375, 380 and 385
(Thomas Petazzoni and Free-electrons team)
- SMP support for Rockchips (Heiko Stübner)
- Lots of i.MX changes (Shawn Guo)
- Added support for BCM5301x SoC (Hauke Mehrtens)
- Multiplatform support for Marvell Kirkwood and Dove (Andrew Lunn
and Sebastian Hesselbarth doing the final part of a long journey)
- Unify davinci platforms and remove obsolete ones (Sekhar Nori, Arnd
Bergmann)"
* tag 'soc-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (126 commits)
ARM: sunxi: Select HAVE_ARM_ARCH_TIMER
ARM: cache-tauros2: remove ARMv6 code
ARM: mvebu: don't select CONFIG_NEON
ARM: davinci: fix DT booting with default defconfig
ARM: configs: bcm_defconfig: enable bcm590xx regulator support
ARM: davinci: remove tnetv107x support
MAINTAINERS: Update ARM STi maintainers
ARM: restrict BCM_KONA_UART to ARCH_BCM_MOBILE
ARM: bcm21664: Add board support.
ARM: sunxi: Add the new watchog compatibles to the reboot code
ARM: enable ARM_HAS_SG_CHAIN for multiplatform
ARM: davinci: remove da8xx_omapl_defconfig
ARM: davinci: da8xx: fix multiple watchdog device registration
ARM: davinci: add da8xx specific configs to davinci_all_defconfig
ARM: davinci: enable da8xx build concurrently with older devices
ARM: BCM5301X: workaround suppress fault
ARM: BCM5301X: add early debugging support
ARM: BCM5301X: initial support for the BCM5301X/BCM470X SoCs with ARM CPU
ARM: mach-bcm: Remove GENERIC_TIME
ARM: shmobile: APMU: Fix warnings due to improper printk formats
...
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@@ -242,6 +242,24 @@
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#define IMX6Q_GPR5_L2_CLK_STOP BIT(8)
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#define IMX6Q_GPR6_IPU1_ID00_WR_QOS_MASK (0xf << 0)
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#define IMX6Q_GPR6_IPU1_ID01_WR_QOS_MASK (0xf << 4)
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#define IMX6Q_GPR6_IPU1_ID10_WR_QOS_MASK (0xf << 8)
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#define IMX6Q_GPR6_IPU1_ID11_WR_QOS_MASK (0xf << 12)
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#define IMX6Q_GPR6_IPU1_ID00_RD_QOS_MASK (0xf << 16)
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#define IMX6Q_GPR6_IPU1_ID01_RD_QOS_MASK (0xf << 20)
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#define IMX6Q_GPR6_IPU1_ID10_RD_QOS_MASK (0xf << 24)
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#define IMX6Q_GPR6_IPU1_ID11_RD_QOS_MASK (0xf << 28)
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#define IMX6Q_GPR7_IPU2_ID00_WR_QOS_MASK (0xf << 0)
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#define IMX6Q_GPR7_IPU2_ID01_WR_QOS_MASK (0xf << 4)
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#define IMX6Q_GPR7_IPU2_ID10_WR_QOS_MASK (0xf << 8)
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#define IMX6Q_GPR7_IPU2_ID11_WR_QOS_MASK (0xf << 12)
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#define IMX6Q_GPR7_IPU2_ID00_RD_QOS_MASK (0xf << 16)
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#define IMX6Q_GPR7_IPU2_ID01_RD_QOS_MASK (0xf << 20)
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#define IMX6Q_GPR7_IPU2_ID10_RD_QOS_MASK (0xf << 24)
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#define IMX6Q_GPR7_IPU2_ID11_RD_QOS_MASK (0xf << 28)
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#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25)
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#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18)
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#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12)
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