Merge tag 'imx-drm-next-2015-01-09' of git://git.pengutronix.de/git/pza/linux into drm-next
imx-drm mode fixup support, imx-hdmi bridge conversion and imx-drm cleanup - Implement mode_fixup for a DI vertical timing limitation - Use generic DRM OF helpers in DRM core - Convert imx-hdmi to dw_hdmi drm_bridge and add rockchip driver - Add DC use counter to fix multi-display support - Simplify handling of DI clock flags - A few small fixes and cleanup * tag 'imx-drm-next-2015-01-09' of git://git.pengutronix.de/git/pza/linux: (26 commits) imx-drm: core: handling of DI clock flags to ipu_crtc_mode_set() gpu: ipu-di: Switch to DIV_ROUND_CLOSEST for DI clock divider calc gpu: ipu-v3: Use videomode in struct ipu_di_signal_cfg imx-drm: encoder prepare/mode_set must use adjusted mode imx-drm: ipuv3-crtc: Implement mode_fixup drm_modes: add drm_display_mode_to_videomode gpu: ipu-di: remove some non-functional code gpu: ipu-di: Add ipu_di_adjust_videomode() drm: rockchip: export functions needed by rockchip dw_hdmi bridge driver drm: bridge/dw_hdmi: request interrupt only after initializing the mutes drm: bridge/dw_hdmi: add rockchip rk3288 support dt-bindings: Add documentation for rockchip dw hdmi drm: bridge/dw_hdmi: add function dw_hdmi_phy_enable_spare drm: bridge/dw_hdmi: clear i2cmphy_stat0 reg in hdmi_phy_wait_i2c_done drm: bridge/dw_hdmi: add mode_valid support drm: bridge/dw_hdmi: add support for multi-byte register width access dt-bindings: add document for dw_hdmi drm: imx: imx-hdmi: move imx-hdmi to bridge/dw_hdmi drm: imx: imx-hdmi: split phy configuration to platform driver drm: imx: imx-hdmi: convert imx-hdmi to drm_bridge mode ...
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/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __DW_HDMI__
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#define __DW_HDMI__
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#include <drm/drmP.h>
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enum {
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DW_HDMI_RES_8,
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DW_HDMI_RES_10,
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DW_HDMI_RES_12,
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DW_HDMI_RES_MAX,
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};
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enum dw_hdmi_devtype {
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IMX6Q_HDMI,
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IMX6DL_HDMI,
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RK3288_HDMI,
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};
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struct dw_hdmi_mpll_config {
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unsigned long mpixelclock;
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struct {
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u16 cpce;
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u16 gmp;
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} res[DW_HDMI_RES_MAX];
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};
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struct dw_hdmi_curr_ctrl {
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unsigned long mpixelclock;
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u16 curr[DW_HDMI_RES_MAX];
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};
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struct dw_hdmi_sym_term {
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unsigned long mpixelclock;
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u16 sym_ctr; /*clock symbol and transmitter control*/
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u16 term; /*transmission termination value*/
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};
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struct dw_hdmi_plat_data {
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enum dw_hdmi_devtype dev_type;
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const struct dw_hdmi_mpll_config *mpll_cfg;
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const struct dw_hdmi_curr_ctrl *cur_ctr;
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const struct dw_hdmi_sym_term *sym_term;
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enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
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struct drm_display_mode *mode);
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};
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void dw_hdmi_unbind(struct device *dev, struct device *master, void *data);
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int dw_hdmi_bind(struct device *dev, struct device *master,
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void *data, struct drm_encoder *encoder,
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struct resource *iores, int irq,
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const struct dw_hdmi_plat_data *plat_data);
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#endif /* __IMX_HDMI_H__ */
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@@ -200,6 +200,8 @@ struct drm_display_mode *drm_gtf_mode_complex(struct drm_device *dev,
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int GTF_K, int GTF_2J);
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void drm_display_mode_from_videomode(const struct videomode *vm,
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struct drm_display_mode *dmode);
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void drm_display_mode_to_videomode(const struct drm_display_mode *dmode,
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struct videomode *vm);
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int of_get_drm_display_mode(struct device_node *np,
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struct drm_display_mode *dmode,
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int index);
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