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Merge master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6

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* master.kernel.org:/pub/scm/linux/kernel/git/lethal/sh-2.6: (35 commits)
  sh: rts7751r2d board updates.
  sh: Kill off dead bigsur and ec3104 boards.
  sh: Fixup r7780rp pata_platform for devres conversion.
  sh: Revert TLB miss fast-path changes that broke PTEA parts.
  sh: Compile fix for heartbeat consolidation.
  sh: heartbeat consolidation for banked LEDs.
  sh: define dma noncoherent API functions.
  sh: Missing flush_dcache_all() proto in cacheflush.h.
  sh: Kill dead/unused ISA code from __ioremap().
  sh: Add cpu-features header to asm/Kbuild.
  sh: Move __KERNEL__ up in asm/page.h.
  sh: Fix syscall numbering breakage.
  sh: dcache write-back for R7780RP PIO.
  sh: Switch to local TLB flush variants in additional callsites.
  sh: Local TLB flushing variants for SMP prep.
  sh: Fixup cpu_data references for the non-boot CPUs.
  sh: Use a per-cpu ASID cache.
  sh: add SH_CLK_MD Kconfig default.
  sh: Fixup SHMIN INTC register definitions.
  sh: SH-DMAC compile fixes
  ...
This commit is contained in:
Linus Torvalds
2007-02-15 10:01:15 -08:00
parent e0a04cffa4 9c57548f17
commit f99c6bb6e2
125 changed files with 2014 additions and 3585 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/asm-sh/Kbuild
+2
View File
@@ -1 +1,3 @@
include include/asm-generic/Kbuild.asm
header-y += cpu-features.h
include/asm-sh/bigsur/bigsur.h
-80
View File
@@ -1,80 +0,0 @@
/*
*
* Hitachi Big Sur Eval Board support
*
* Dustin McIntire (dustin@sensoria.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* Derived from Hitachi SH7751 reference manual
*
*/
#ifndef _ASM_BIGSUR_H_
#define _ASM_BIGSUR_H_
#include <asm/irq.h>
#include <asm/hd64465/hd64465.h>
/* 7751 Internal IRQ's used by external CPLD controller */
#define BIGSUR_IRQ_LOW 0
#define BIGSUR_IRQ_NUM 14 /* External CPLD level 1 IRQs */
#define BIGSUR_IRQ_HIGH (BIGSUR_IRQ_LOW + BIGSUR_IRQ_NUM)
#define BIGSUR_2NDLVL_IRQ_LOW (HD64465_IRQ_BASE+HD64465_IRQ_NUM)
#define BIGSUR_2NDLVL_IRQ_NUM 32 /* Level 2 IRQs = 4 regs * 8 bits */
#define BIGSUR_2NDLVL_IRQ_HIGH (BIGSUR_2NDLVL_IRQ_LOW + \
BIGSUR_2NDLVL_IRQ_NUM)
/* PCI interrupt base number (A_INTA-A_INTD) */
#define BIGSUR_SH7751_PCI_IRQ_BASE (BIGSUR_2NDLVL_IRQ_LOW+10)
/* CPLD registers and external chip addresses */
#define BIGSUR_HD64464_ADDR 0xB2000000
#define BIGSUR_DGDR 0xB1FFFE00
#define BIGSUR_BIDR 0xB1FFFD00
#define BIGSUR_CSLR 0xB1FFFC00
#define BIGSUR_SW1R 0xB1FFFB00
#define BIGSUR_DBGR 0xB1FFFA00
#define BIGSUR_BDTR 0xB1FFF900
#define BIGSUR_BDRR 0xB1FFF800
#define BIGSUR_PPR1 0xB1FFF700
#define BIGSUR_PPR2 0xB1FFF600
#define BIGSUR_IDE2 0xB1FFF500
#define BIGSUR_IDE3 0xB1FFF400
#define BIGSUR_SPCR 0xB1FFF300
#define BIGSUR_ETHR 0xB1FE0000
#define BIGSUR_PPDR 0xB1FDFF00
#define BIGSUR_ICTL 0xB1FDFE00
#define BIGSUR_ICMD 0xB1FDFD00
#define BIGSUR_DMA0 0xB1FDFC00
#define BIGSUR_DMA1 0xB1FDFB00
#define BIGSUR_IRQ0 0xB1FDFA00
#define BIGSUR_IRQ1 0xB1FDF900
#define BIGSUR_IRQ2 0xB1FDF800
#define BIGSUR_IRQ3 0xB1FDF700
#define BIGSUR_IMR0 0xB1FDF600
#define BIGSUR_IMR1 0xB1FDF500
#define BIGSUR_IMR2 0xB1FDF400
#define BIGSUR_IMR3 0xB1FDF300
#define BIGSUR_IRLMR0 0xB1FDF200
#define BIGSUR_IRLMR1 0xB1FDF100
#define BIGSUR_V320USC_ADDR 0xB1000000
#define BIGSUR_HD64465_ADDR 0xB0000000
#define BIGSUR_INTERNAL_BASE 0xB0000000
/* SMC ethernet card parameters */
#define BIGSUR_ETHER_IOPORT 0x220
/* IDE register paramters */
#define BIGSUR_IDECMD_IOPORT 0x1f0
#define BIGSUR_IDECTL_IOPORT 0x1f8
/* LED bit position in BIGSUR_CSLR */
#define BIGSUR_LED (1<<4)
/* PCI: default LOCAL memory window sizes (seen from PCI bus) */
#define BIGSUR_LSR0_SIZE (64*(1<<20)) //64MB
#define BIGSUR_LSR1_SIZE (64*(1<<20)) //64MB
#endif /* _ASM_BIGSUR_H_ */
include/asm-sh/bigsur/io.h
-35
View File
@@ -1,35 +0,0 @@
/*
* include/asm-sh/bigsur/io.h
*
* By Dustin McIntire (dustin@sensoria.com) (c)2001
* Derived from io_hd64465.h, which bore the message:
* By Greg Banks <gbanks@pocketpenguins.com>
* (c) 2000 PocketPenguins Inc.
* and from io_hd64461.h, which bore the message:
* Copyright 2000 Stuart Menefy (stuart.menefy@st.com)
*
* May be copied or modified under the terms of the GNU General Public
* License. See linux/COPYING for more information.
*
* IO functions for a Hitachi Big Sur Evaluation Board.
*/
#ifndef _ASM_SH_IO_BIGSUR_H
#define _ASM_SH_IO_BIGSUR_H
#include <linux/types.h>
extern unsigned long bigsur_isa_port2addr(unsigned long offset);
extern int bigsur_irq_demux(int irq);
/* Provision for generic secondary demux step -- used by PCMCIA code */
extern void bigsur_register_irq_demux(int irq,
int (*demux)(int irq, void *dev), void *dev);
extern void bigsur_unregister_irq_demux(int irq);
/* Set this variable to 1 to see port traffic */
extern int bigsur_io_debug;
/* Map a range of ports to a range of kernel virtual memory. */
extern void bigsur_port_map(u32 baseport, u32 nports, u32 addr, u8 shift);
extern void bigsur_port_unmap(u32 baseport, u32 nports);
#endif /* _ASM_SH_IO_BIGSUR_H */
include/asm-sh/bigsur/serial.h
-24
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@@ -1,24 +0,0 @@
/*
* include/asm-sh/bigsur/serial.h
*
* Configuration details for Big Sur 16550 based serial ports
* i.e. HD64465, PCMCIA, etc.
*/
#ifndef _ASM_SERIAL_BIGSUR_H
#define _ASM_SERIAL_BIGSUR_H
#include <asm/hd64465.h>
#define BASE_BAUD (3379200 / 16)
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
#define SERIAL_PORT_DFNS \
/* UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, 0x3F8, HD64465_IRQ_UART, STD_COM_FLAGS } /* ttyS0 */
/* XXX: This should be moved ino irq.h */
#define irq_cannonicalize(x) (x)
#endif /* _ASM_SERIAL_BIGSUR_H */
include/asm-sh/bugs.h
+3 -3
View File
@@ -19,9 +19,9 @@ static void __init check_bugs(void)
extern unsigned long loops_per_jiffy;
char *p = &init_utsname()->machine[2]; /* "sh" */
cpu_data->loops_per_jiffy = loops_per_jiffy;
current_cpu_data.loops_per_jiffy = loops_per_jiffy;
switch (cpu_data->type) {
switch (current_cpu_data.type) {
case CPU_SH7604 ... CPU_SH7619:
*p++ = '2';
break;
@@ -54,7 +54,7 @@ static void __init check_bugs(void)
break;
}
printk("CPU: %s\n", get_cpu_subtype());
printk("CPU: %s\n", get_cpu_subtype(&current_cpu_data));
#ifndef __LITTLE_ENDIAN__
/* 'eb' means 'Endian Big' */
include/asm-sh/cacheflush.h
+3
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@@ -30,5 +30,8 @@ extern void __flush_invalidate_region(void *start, int size);
#define HAVE_ARCH_UNMAPPED_AREA
/* Page flag for lazy dcache write-back for the aliasing UP caches */
#define PG_dcache_dirty PG_arch_1
#endif /* __KERNEL__ */
#endif /* __ASM_SH_CACHEFLUSH_H */
include/asm-sh/cpu-sh3/cacheflush.h
-2
View File
@@ -36,8 +36,6 @@
/* 32KB cache, 4kb PAGE sizes need to check bit 12 */
#define CACHE_ALIAS 0x00001000
#define PG_mapped PG_arch_1
void flush_cache_all(void);
void flush_cache_mm(struct mm_struct *mm);
#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
include/asm-sh/cpu-sh4/cacheflush.h
+1 -12
View File
@@ -17,6 +17,7 @@
* so we need them.
*/
void flush_cache_all(void);
void flush_dcache_all(void);
void flush_cache_mm(struct mm_struct *mm);
#define flush_cache_dup_mm(mm) flush_cache_mm(mm)
void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
@@ -38,16 +39,4 @@ void flush_icache_user_range(struct vm_area_struct *vma, struct page *page,
/* Initialization of P3 area for copy_user_page */
void p3_cache_init(void);
#define PG_mapped PG_arch_1
#ifdef CONFIG_MMU
extern int remap_area_pages(unsigned long addr, unsigned long phys_addr,
unsigned long size, unsigned long flags);
#else /* CONFIG_MMU */
static inline int remap_area_pages(unsigned long addr, unsigned long phys_addr,
unsigned long size, unsigned long flags)
{
return 0;
}
#endif /* CONFIG_MMU */
#endif /* __ASM_CPU_SH4_CACHEFLUSH_H */
include/asm-sh/cpu-sh4/dma.h
+11
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@@ -3,6 +3,17 @@
#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
/* SH7751/7760/7780 DMA IRQ sources */
#define DMTE0_IRQ 34
#define DMTE1_IRQ 35
#define DMTE2_IRQ 36
#define DMTE3_IRQ 37
#define DMTE4_IRQ 44
#define DMTE5_IRQ 45
#define DMTE6_IRQ 46
#define DMTE7_IRQ 47
#define DMAE_IRQ 38
#ifdef CONFIG_CPU_SH4A
#define SH_DMAC_BASE 0xfc808020
include/asm-sh/dma-mapping.h
+4
View File
@@ -53,6 +53,10 @@ static inline void dma_free_coherent(struct device *dev, size_t size,
consistent_free(vaddr, size);
}
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
#define dma_is_consistent(d, h) (1)
static inline void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
enum dma_data_direction dir)
{
include/asm-sh/ec3104/ec3104.h
-43
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@@ -1,43 +0,0 @@
#ifndef __ASM_EC3104_H
#define __ASM_EC3104_H
/*
* Most of the register set is at 0xb0ec0000 - 0xb0ecffff.
*
* as far as I've figured it out the register map is:
* 0xb0ec0000 - id string
* 0xb0ec0XXX - power management
* 0xb0ec1XXX - interrupt control
* 0xb0ec3XXX - ps2 port (touch pad on aero 8000)
* 0xb0ec6XXX - i2c
* 0xb0ec7000 - first serial port (proprietary connector on aero 8000)
* 0xb0ec8000 - second serial port
* 0xb0ec9000 - third serial port
* 0xb0eca000 - fourth serial port (keyboard controller on aero 8000)
* 0xb0eccXXX - GPIO
* 0xb0ecdXXX - GPIO
*/
#define EC3104_BASE 0xb0ec0000
#define EC3104_SER4_DATA (EC3104_BASE+0xa000)
#define EC3104_SER4_IIR (EC3104_BASE+0xa008)
#define EC3104_SER4_MCR (EC3104_BASE+0xa010)
#define EC3104_SER4_LSR (EC3104_BASE+0xa014)
#define EC3104_SER4_MSR (EC3104_BASE+0xa018)
/*
* our ISA bus. this seems to be real ISA.
*/
#define EC3104_ISA_BASE 0xa5000000
#define EC3104_IRQ 11
#define EC3104_IRQBASE 64
#define EC3104_IRQ_SER1 EC3104_IRQBASE + 7
#define EC3104_IRQ_SER2 EC3104_IRQBASE + 8
#define EC3104_IRQ_SER3 EC3104_IRQBASE + 9
#define EC3104_IRQ_SER4 EC3104_IRQBASE + 10
#endif /* __ASM_EC3104_H */
include/asm-sh/ec3104/io.h
-16
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@@ -1,16 +0,0 @@
#ifndef _ASM_SH_IO_EC3104_H
#define _ASM_SH_IO_EC3104_H
#include <linux/types.h>
extern unsigned char ec3104_inb(unsigned long port);
extern unsigned short ec3104_inw(unsigned long port);
extern unsigned long ec3104_inl(unsigned long port);
extern void ec3104_outb(unsigned char value, unsigned long port);
extern void ec3104_outw(unsigned short value, unsigned long port);
extern void ec3104_outl(unsigned long value, unsigned long port);
extern int ec3104_irq_demux(int irq);
#endif /* _ASM_SH_IO_EC3104_H */
include/asm-sh/ec3104/keyboard.h
-15
View File
@@ -1,15 +0,0 @@
extern unsigned char ec3104_kbd_sysrq_xlate[];
extern int ec3104_kbd_setkeycode(unsigned int scancode, unsigned int keycode);
extern int ec3104_kbd_getkeycode(unsigned int scancode);
extern int ec3104_kbd_translate(unsigned char, unsigned char *, char);
extern char ec3104_kbd_unexpected_up(unsigned char);
extern void ec3104_kbd_leds(unsigned char);
extern void ec3104_kbd_init_hw(void);
#define kbd_sysrq_xlate ec3104_kbd_sysrq_xlate
#define kbd_setkeycode ec3104_kbd_setkeycode
#define kbd_getkeycode ec3104_kbd_getkeycode
#define kbd_translate ec3104_kbd_translate
#define kbd_unexpected_up ec3104_kbd_unexpected_up
#define kbd_leds ec3104_kbd_leds
#define kbd_init_hw ec3104_kbd_init_hw
include/asm-sh/ec3104/serial.h
-20
View File
@@ -1,20 +0,0 @@
#include <asm/ec3104.h>
/* Naturally we don't know the exact value but 115200 baud has a divisor
* of 9 and 19200 baud has a divisor of 52, so this seems like a good
* guess. */
#define BASE_BAUD (16800000 / 16)
#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
/* there is a fourth serial port with the expected values as well, but
* it's got the keyboard controller behind it so we can't really use it
* (without moving the keyboard driver to userspace, which doesn't sound
* like a very good idea) */
#define SERIAL_PORT_DFNS \
/* UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, 0x11C00, EC3104_IRQBASE+7, STD_COM_FLAGS }, /* ttyS0 */ \
{ 0, BASE_BAUD, 0x12000, EC3104_IRQBASE+8, STD_COM_FLAGS }, /* ttyS1 */ \
{ 0, BASE_BAUD, 0x12400, EC3104_IRQBASE+9, STD_COM_FLAGS }, /* ttyS2 */
/* XXX: This should be moved ino irq.h */
#define irq_cannonicalize(x) (x)
include/asm-sh/irq.h
-4
View File
@@ -66,12 +66,8 @@
/* 3. OFFCHIP_NR_IRQS */
#if defined(CONFIG_HD64461)
# define OFFCHIP_NR_IRQS 18
#elif defined (CONFIG_SH_BIGSUR) /* must be before CONFIG_HD64465 */
# define OFFCHIP_NR_IRQS 48
#elif defined(CONFIG_HD64465)
# define OFFCHIP_NR_IRQS 16
#elif defined (CONFIG_SH_EC3104)
# define OFFCHIP_NR_IRQS 16
#elif defined (CONFIG_SH_DREAMCAST)
# define OFFCHIP_NR_IRQS 96
#elif defined (CONFIG_SH_TITAN)
include/asm-sh/kgdb.h
+4 -4
View File
@@ -85,10 +85,10 @@ extern int setjmp(jmp_buf __jmpb);
#define KGDB_PRINTK(...) printk("KGDB: " __VA_ARGS__)
/* Forced breakpoint */
#define BREAKPOINT() do { \
if (kgdb_enabled) { \
asm volatile("trapa #0xff"); \
} \
#define BREAKPOINT() \
do { \
if (kgdb_enabled) \
__asm__ __volatile__("trapa #0x3c"); \
} while (0)
/* KGDB should be able to flush all kernel text space */
include/asm-sh/mmu.h
+7 -13
View File
@@ -1,25 +1,19 @@
#ifndef __MMU_H
#define __MMU_H
#if !defined(CONFIG_MMU)
/* Default "unsigned long" context */
typedef unsigned long mm_context_id_t[NR_CPUS];
typedef struct {
#ifdef CONFIG_MMU
mm_context_id_t id;
void *vdso;
#else
struct vm_list_struct *vmlist;
unsigned long end_brk;
#endif
} mm_context_t;
#else
/* Default "unsigned long" context */
typedef unsigned long mm_context_id_t;
typedef struct {
mm_context_id_t id;
void *vdso;
} mm_context_t;
#endif /* CONFIG_MMU */
/*
* Privileged Space Mapping Buffer (PMB) definitions
*/
include/asm-sh/mmu_context.h
+36 -25
View File
@@ -1,6 +1,6 @@
/*
* Copyright (C) 1999 Niibe Yutaka
* Copyright (C) 2003 Paul Mundt
* Copyright (C) 2003 - 2006 Paul Mundt
*
* ASID handling idea taken from MIPS implementation.
*/
@@ -19,11 +19,6 @@
* (b) ASID (Address Space IDentifier)
*/
/*
* Cache of MMU context last used.
*/
extern unsigned long mmu_context_cache;
#define MMU_CONTEXT_ASID_MASK 0x000000ff
#define MMU_CONTEXT_VERSION_MASK 0xffffff00
#define MMU_CONTEXT_FIRST_VERSION 0x00000100
@@ -32,6 +27,11 @@ extern unsigned long mmu_context_cache;
/* ASID is 8-bit value, so it can't be 0x100 */
#define MMU_NO_ASID 0x100
#define cpu_context(cpu, mm) ((mm)->context.id[cpu])
#define cpu_asid(cpu, mm) (cpu_context((cpu), (mm)) & \
MMU_CONTEXT_ASID_MASK)
#define asid_cache(cpu) (cpu_data[cpu].asid_cache)
/*
* Virtual Page Number mask
*/
@@ -41,18 +41,17 @@ extern unsigned long mmu_context_cache;
/*
* Get MMU context if needed.
*/
static inline void get_mmu_context(struct mm_struct *mm)
static inline void get_mmu_context(struct mm_struct *mm, unsigned int cpu)
{
unsigned long mc = mmu_context_cache;
unsigned long asid = asid_cache(cpu);
/* Check if we have old version of context. */
if (((mm->context.id ^ mc) & MMU_CONTEXT_VERSION_MASK) == 0)
if (((cpu_context(cpu, mm) ^ asid) & MMU_CONTEXT_VERSION_MASK) == 0)
/* It's up to date, do nothing */
return;
/* It's old, we need to get new context with new version. */
mc = ++mmu_context_cache;
if (!(mc & MMU_CONTEXT_ASID_MASK)) {
if (!(++asid & MMU_CONTEXT_ASID_MASK)) {
/*
* We exhaust ASID of this version.
* Flush all TLB and start new cycle.
@@ -63,10 +62,11 @@ static inline void get_mmu_context(struct mm_struct *mm)
* Fix version; Note that we avoid version #0
* to distingush NO_CONTEXT.
*/
if (!mc)
mmu_context_cache = mc = MMU_CONTEXT_FIRST_VERSION;
if (!asid)
asid = MMU_CONTEXT_FIRST_VERSION;
}
mm->context.id = mc;
cpu_context(cpu, mm) = asid_cache(cpu) = asid;
}
/*
@@ -74,9 +74,13 @@ static inline void get_mmu_context(struct mm_struct *mm)
* instance.
*/
static inline int init_new_context(struct task_struct *tsk,
struct mm_struct *mm)
struct mm_struct *mm)
{
mm->context.id = NO_CONTEXT;
int i;
for (i = 0; i < num_online_cpus(); i++)
cpu_context(i, mm) = NO_CONTEXT;
return 0;
}
@@ -117,10 +121,10 @@ static inline unsigned long get_asid(void)
* After we have set current->mm to a new value, this activates
* the context for the new mm so we see the new mappings.
*/
static inline void activate_context(struct mm_struct *mm)
static inline void activate_context(struct mm_struct *mm, unsigned int cpu)
{
get_mmu_context(mm);
set_asid(mm->context.id & MMU_CONTEXT_ASID_MASK);
get_mmu_context(mm, cpu);
set_asid(cpu_asid(cpu, mm));
}
/* MMU_TTB is used for optimizing the fault handling. */
@@ -138,10 +142,15 @@ static inline void switch_mm(struct mm_struct *prev,
struct mm_struct *next,
struct task_struct *tsk)
{
unsigned int cpu = smp_processor_id();
if (likely(prev != next)) {
cpu_set(cpu, next->cpu_vm_mask);
set_TTB(next->pgd);
activate_context(next);
}
activate_context(next, cpu);
} else
if (!cpu_test_and_set(cpu, next->cpu_vm_mask))
activate_context(next, cpu);
}
#define deactivate_mm(tsk,mm) do { } while (0)
@@ -159,7 +168,7 @@ enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
#define destroy_context(mm) do { } while (0)
#define set_asid(asid) do { } while (0)
#define get_asid() (0)
#define activate_context(mm) do { } while (0)
#define activate_context(mm,cpu) do { } while (0)
#define switch_mm(prev,next,tsk) do { } while (0)
#define deactivate_mm(tsk,mm) do { } while (0)
#define activate_mm(prev,next) do { } while (0)
@@ -174,14 +183,16 @@ enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
*/
static inline void enable_mmu(void)
{
unsigned int cpu = smp_processor_id();
/* Enable MMU */
ctrl_outl(MMU_CONTROL_INIT, MMUCR);
ctrl_barrier();
if (mmu_context_cache == NO_CONTEXT)
mmu_context_cache = MMU_CONTEXT_FIRST_VERSION;
if (asid_cache(cpu) == NO_CONTEXT)
asid_cache(cpu) = MMU_CONTEXT_FIRST_VERSION;
set_asid(mmu_context_cache & MMU_CONTEXT_ASID_MASK);
set_asid(asid_cache(cpu) & MMU_CONTEXT_ASID_MASK);
}
static inline void disable_mmu(void)
include/asm-sh/page.h
+2 -1
View File
@@ -13,6 +13,8 @@
[ P4 control ] 0xE0000000
*/
#ifdef __KERNEL__
/* PAGE_SHIFT determines the page size */
#if defined(CONFIG_PAGE_SIZE_4KB)
# define PAGE_SHIFT 12
@@ -51,7 +53,6 @@
#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT-PAGE_SHIFT)
#endif
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
extern void (*clear_page)(void *to);
include/asm-sh/pgtable.h
+3 -8
View File
@@ -43,17 +43,17 @@ extern unsigned long empty_zero_page[PAGE_SIZE / sizeof(unsigned long)];
/* PGD bits */
#define PGDIR_SHIFT (PTE_SHIFT + PTE_BITS)
#define PGDIR_BITS (32 - PGDIR_SHIFT)
#define PGDIR_SIZE (1 << PGDIR_SHIFT)
#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
#define PGDIR_MASK (~(PGDIR_SIZE-1))
/* Entries per level */
#define PTRS_PER_PTE (PAGE_SIZE / 4)
#define PTRS_PER_PTE (PAGE_SIZE / (1 << PTE_MAGNITUDE))
#define PTRS_PER_PGD (PAGE_SIZE / 4)
#define USER_PTRS_PER_PGD (TASK_SIZE/PGDIR_SIZE)
#define FIRST_USER_ADDRESS 0
#define PTE_PHYS_MASK 0x1ffff000
#define PTE_PHYS_MASK (0x20000000 - PAGE_SIZE)
/*
* First 1MB map is used by fixed purpose.
@@ -583,11 +583,6 @@ struct mm_struct;
extern unsigned int kobjsize(const void *objp);
#endif /* !CONFIG_MMU */
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_SH7705_CACHE_32KB)
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
extern pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep);
#endif
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
extern void paging_init(void);
include/asm-sh/processor.h
+4 -2
View File
@@ -27,8 +27,6 @@
#define CCN_CVR 0xff000040
#define CCN_PRR 0xff000044
const char *get_cpu_subtype(void);
/*
* CPU type and hardware bug flags. Kept separately for each CPU.
*
@@ -66,6 +64,7 @@ enum cpu_type {
struct sh_cpuinfo {
unsigned int type;
unsigned long loops_per_jiffy;
unsigned long asid_cache;
struct cache_info icache; /* Primary I-cache */
struct cache_info dcache; /* Primary D-cache */
@@ -288,5 +287,8 @@ extern int vsyscall_init(void);
#define vsyscall_init() do { } while (0)
#endif
/* arch/sh/kernel/setup.c */
const char *get_cpu_subtype(struct sh_cpuinfo *c);
#endif /* __KERNEL__ */
#endif /* __ASM_SH_PROCESSOR_H */
include/asm-sh/rts7751r2d.h
+4
View File
@@ -68,6 +68,10 @@
#define IRQ_PCISLOT2 10 /* PCI Slot #2 IRQ */
#define IRQ_EXTENTION 11 /* EXTn IRQ */
/* arch/sh/boards/renesas/rts7751r2d/irq.c */
void init_rts7751r2d_IRQ(void);
int rts7751r2d_irq_demux(int);
#define __IO_PREFIX rts7751r2d
#include <asm/io_generic.h>
include/asm-sh/serial.h
+1 -10
View File
@@ -9,11 +9,6 @@
#include <linux/kernel.h>
#ifdef CONFIG_SH_EC3104
#include <asm/serial-ec3104.h>
#elif defined (CONFIG_SH_BIGSUR)
#include <asm/serial-bigsur.h>
#else
/*
* This assumes you have a 1.8432 MHz clock for your UART.
*
@@ -34,12 +29,8 @@
#else
#define SERIAL_PORT_DFNS \
/* UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
{ 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS } /* ttyS1 */
#define SERIAL_PORT_DFNS
#endif
#endif
#endif /* _ASM_SERIAL_H */
include/asm-sh/thread_info.h
+12 -4
View File
@@ -32,12 +32,20 @@ struct thread_info {
#define PREEMPT_ACTIVE 0x10000000
#ifdef CONFIG_4KSTACKS
#define THREAD_SIZE (PAGE_SIZE)
#if defined(CONFIG_4KSTACKS)
#define THREAD_SIZE_ORDER (0)
#elif defined(CONFIG_PAGE_SIZE_4KB)
#define THREAD_SIZE_ORDER (1)
#elif defined(CONFIG_PAGE_SIZE_8KB)
#define THREAD_SIZE_ORDER (1)
#elif defined(CONFIG_PAGE_SIZE_64KB)
#define THREAD_SIZE_ORDER (0)
#else
#define THREAD_SIZE (PAGE_SIZE * 2)
#error "Unknown thread size"
#endif
#define STACK_WARN (THREAD_SIZE / 8)
#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
#define STACK_WARN (THREAD_SIZE >> 3)
/*
* macros/functions for gaining access to the thread information structure
include/asm-sh/tlbflush.h
+31 -7
View File
@@ -4,7 +4,6 @@
/*
* TLB flushing:
*
* - flush_tlb() flushes the current mm struct TLBs
* - flush_tlb_all() flushes all processes TLBs
* - flush_tlb_mm(mm) flushes the specified mm context TLB's
* - flush_tlb_page(vma, vmaddr) flushes one page
@@ -12,20 +11,45 @@
* - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
* - flush_tlb_pgtables(mm, start, end) flushes a range of page tables
*/
extern void local_flush_tlb_all(void);
extern void local_flush_tlb_mm(struct mm_struct *mm);
extern void local_flush_tlb_range(struct vm_area_struct *vma,
unsigned long start,
unsigned long end);
extern void local_flush_tlb_page(struct vm_area_struct *vma,
unsigned long page);
extern void local_flush_tlb_kernel_range(unsigned long start,
unsigned long end);
extern void local_flush_tlb_one(unsigned long asid, unsigned long page);
#ifdef CONFIG_SMP
extern void flush_tlb(void);
extern void flush_tlb_all(void);
extern void flush_tlb_mm(struct mm_struct *mm);
extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end);
extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
extern void __flush_tlb_page(unsigned long asid, unsigned long page);
extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
extern void flush_tlb_one(unsigned long asid, unsigned long page);
#else
#define flush_tlb_all() local_flush_tlb_all()
#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
#define flush_tlb_page(vma, page) local_flush_tlb_page(vma, page)
#define flush_tlb_one(asid, page) local_flush_tlb_one(asid, page)
#define flush_tlb_range(vma, start, end) \
local_flush_tlb_range(vma, start, end)
#define flush_tlb_kernel_range(start, end) \
local_flush_tlb_kernel_range(start, end)
#endif /* CONFIG_SMP */
static inline void flush_tlb_pgtables(struct mm_struct *mm,
unsigned long start, unsigned long end)
{ /* Nothing to do */
{
/* Nothing to do */
}
extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
#endif /* __ASM_SH_TLBFLUSH_H */
include/asm-sh/ubc.h
+1 -1
View File
@@ -17,7 +17,7 @@
/* User Break Controller */
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
defined(CONFIG_CPU_SUBTYPE_SH7300)
#define UBC_TYPE_SH7729 (cpu_data->type == CPU_SH7729)
#define UBC_TYPE_SH7729 (current_cpu_data.type == CPU_SH7729)
#else
#define UBC_TYPE_SH7729 0
#endif
include/asm-sh/unistd.h
+10 -10
View File
@@ -292,22 +292,22 @@
#define __NR_mq_getsetattr (__NR_mq_open+5)
#define __NR_kexec_load 283
#define __NR_waitid 284
/* #define __NR_sys_setaltroot 285 */
#define __NR_add_key 286
#define __NR_request_key 287
#define __NR_keyctl 288
#define __NR_ioprio_set 289
#define __NR_ioprio_get 290
#define __NR_inotify_init 291
#define __NR_inotify_add_watch 292
#define __NR_inotify_rm_watch 293
#define __NR_add_key 285
#define __NR_request_key 286
#define __NR_keyctl 287
#define __NR_ioprio_set 288
#define __NR_ioprio_get 289
#define __NR_inotify_init 290
#define __NR_inotify_add_watch 291
#define __NR_inotify_rm_watch 292
/* 293 is unused */
#define __NR_migrate_pages 294
#define __NR_openat 295
#define __NR_mkdirat 296
#define __NR_mknodat 297
#define __NR_fchownat 298
#define __NR_futimesat 299
#define __NR_newfstatat 300
#define __NR_fstatat64 300
#define __NR_unlinkat 301
#define __NR_renameat 302
#define __NR_linkat 303
include/asm-sh/voyagergx.h
+4 -1
View File
@@ -308,6 +308,9 @@
#define AC97C_READ (1 << 19)
#define AC97C_WD_BIT (1 << 2)
#define AC97C_INDEX_MASK 0x7f
/* -------------------------------------------------------------------- */
/* arch/sh/cchips/voyagergx/consistent.c */
void *voyagergx_consistent_alloc(struct device *, size_t, dma_addr_t *, gfp_t);
int voyagergx_consistent_free(struct device *, size_t, void *, dma_addr_t);
#endif /* _VOYAGER_GX_REG_H */