tmakin/tegra-linux-noble
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Merge ../linux-2.6

Browse Source
This commit is contained in:
James Bottomley
2006-06-10 13:47:26 -05:00
parent 60eef25701 128e6ced24
commit f0cd91a68a
1551 changed files with 37163 additions and 20091 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/asm-alpha/smp.h
+1 -3
View File
@@ -45,10 +45,8 @@ extern struct cpuinfo_alpha cpu_data[NR_CPUS];
#define hard_smp_processor_id() __hard_smp_processor_id()
#define raw_smp_processor_id() (current_thread_info()->cpu)
extern cpumask_t cpu_present_mask;
extern cpumask_t cpu_online_map;
extern int smp_num_cpus;
#define cpu_possible_map cpu_present_mask
#define cpu_possible_map cpu_present_map
int smp_call_function_on_cpu(void (*func) (void *info), void *info,int retry, int wait, cpumask_t cpu);
include/asm-alpha/termbits.h
+1
View File
@@ -148,6 +148,7 @@ struct termios {
#define HUPCL 00040000
#define CLOCAL 00100000
#define CMSPAR 010000000000 /* mark or space (stick) parity */
#define CRTSCTS 020000000000 /* flow control */
/* c_lflag bits */
include/asm-arm/arch-aaec2000/debug-macro.S
+1
View File
@@ -9,6 +9,7 @@
* published by the Free Software Foundation.
*/
#include "hardware.h"
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
include/asm-arm/arch-aaec2000/entry-macro.S
+1
View File
@@ -10,6 +10,7 @@
* published by the Free Software Foundation.
*
*/
#include <asm/arch/irqs.h>
.macro disable_fiq
.endm
include/asm-arm/arch-imx/debug-macro.S
+1 -1
View File
@@ -16,7 +16,7 @@
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x00000000 @ physical
movne \rx, #0xe0000000 @ virtual
orr \rx, \rx, #0x00200000
orreq \rx, \rx, #0x00200000 @ physical
orr \rx, \rx, #0x00006000 @ UART1 offset
.endm
include/asm-arm/arch-imx/imx-uart.h
+10
View File
@@ -0,0 +1,10 @@
#ifndef ASMARM_ARCH_UART_H
#define ASMARM_ARCH_UART_H
#define IMXUART_HAVE_RTSCTS (1<<0)
struct imxuart_platform_data {
unsigned int flags;
};
#endif
include/asm-arm/arch-ixp23xx/memory.h
+1 -1
View File
@@ -49,7 +49,7 @@ static inline int __ixp23xx_arch_is_coherent(void)
{
extern unsigned int processor_id;
if (((processor_id & 15) >= 2) || machine_is_roadrunner())
if (((processor_id & 15) >= 4) || machine_is_roadrunner())
return 1;
return 0;
include/asm-arm/arch-ixp4xx/io.h
+7
View File
@@ -260,6 +260,12 @@ out:
#endif
#ifndef CONFIG_PCI
#define __io(v) v
#else
/*
* IXP4xx does not have a transparent cpu -> PCI I/O translation
* window. Instead, it has a set of registers that must be tweaked
@@ -578,6 +584,7 @@ __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
#define ioport_unmap(addr)
#endif // !CONFIG_PCI
#endif // __ASM_ARM_ARCH_IO_H
include/asm-arm/arch-ixp4xx/memory.h
+1 -1
View File
@@ -14,7 +14,7 @@
*/
#define PHYS_OFFSET UL(0x00000000)
#ifndef __ASSEMBLY__
#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes);
include/asm-arm/arch-l7200/serial_l7200.h
+1 -1
View File
@@ -28,7 +28,7 @@
#define UARTDR 0x00 /* Tx/Rx data */
#define RXSTAT 0x04 /* Rx status */
#define H_UBRLCR 0x08 /* mode register high */
#define M_UBRLCR 0x0C /* mode reg mid (MSB of buad)*/
#define M_UBRLCR 0x0C /* mode reg mid (MSB of baud)*/
#define L_UBRLCR 0x10 /* mode reg low (LSB of baud)*/
#define UARTCON 0x14 /* control register */
#define UARTFLG 0x18 /* flag register */
include/asm-arm/arch-l7200/uncompress.h
+1 -1
View File
@@ -6,7 +6,7 @@
* Changelog:
* 05-01-2000 SJH Created
* 05-13-2000 SJH Filled in function bodies
* 07-26-2000 SJH Removed hard coded buad rate
* 07-26-2000 SJH Removed hard coded baud rate
*/
#include <asm/hardware.h>
include/asm-arm/arch-pxa/dma.h
+14 -12
View File
@@ -24,27 +24,29 @@ typedef struct pxa_dma_desc {
volatile u32 dcmd; /* DCMD value for the current transfer */
} pxa_dma_desc;
typedef enum {
DMA_PRIO_HIGH = 0,
DMA_PRIO_MEDIUM = 1,
DMA_PRIO_LOW = 2
} pxa_dma_prio;
#if defined(CONFIG_PXA27x)
#define PXA_DMA_CHANNELS 32
#define PXA_DMA_NBCH(prio) ((prio == DMA_PRIO_LOW) ? 16 : 8)
typedef enum {
DMA_PRIO_HIGH = 0,
DMA_PRIO_MEDIUM = 8,
DMA_PRIO_LOW = 16
} pxa_dma_prio;
#define pxa_for_each_dma_prio(ch, prio) \
for ( \
ch = prio * 4; \
ch != (4 << prio) + 16; \
ch = (ch + 1 == (4 << prio)) ? (prio * 4 + 16) : (ch + 1) \
)
#elif defined(CONFIG_PXA25x)
#define PXA_DMA_CHANNELS 16
#define PXA_DMA_NBCH(prio) ((prio == DMA_PRIO_LOW) ? 8 : 4)
typedef enum {
DMA_PRIO_HIGH = 0,
DMA_PRIO_MEDIUM = 4,
DMA_PRIO_LOW = 8
} pxa_dma_prio;
#define pxa_for_each_dma_prio(ch, prio) \
for (ch = prio * 4; ch != (4 << prio); ch++)
#endif
include/asm-arm/arch-pxa/pxa2xx_spi.h
+71
View File
@@ -0,0 +1,71 @@
/*
* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef PXA2XX_SPI_H_
#define PXA2XX_SPI_H_
#define PXA2XX_CS_ASSERT (0x01)
#define PXA2XX_CS_DEASSERT (0x02)
#if defined(CONFIG_PXA25x)
#define CLOCK_SPEED_HZ 3686400
#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/2/(x+1))<<8)&0x0000ff00)
#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#define SSP_TIMEOUT_SCALE (2712)
#elif defined(CONFIG_PXA27x)
#define CLOCK_SPEED_HZ 13000000
#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#define SSP_TIMEOUT_SCALE (769)
#endif
#define SSP_TIMEOUT(x) ((x*10000)/SSP_TIMEOUT_SCALE)
#define SSP1_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(1)))))
#define SSP2_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(2)))))
#define SSP3_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(3)))))
enum pxa_ssp_type {
SSP_UNDEFINED = 0,
PXA25x_SSP, /* pxa 210, 250, 255, 26x */
PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
PXA27x_SSP,
};
/* device.platform_data for SSP controller devices */
struct pxa2xx_spi_master {
enum pxa_ssp_type ssp_type;
u32 clock_enable;
u16 num_chipselect;
u8 enable_dma;
};
/* spi_board_info.controller_data for SPI slave devices,
* copied to spi_device.platform_data ... mostly for dma tuning
*/
struct pxa2xx_spi_chip {
u8 tx_threshold;
u8 rx_threshold;
u8 dma_burst_size;
u32 timeout_microsecs;
u8 enable_loopback;
void (*cs_control)(u32 command);
};
#endif /*PXA2XX_SPI_H_*/
include/asm-arm/arch-s3c2410/spi-gpio.h
+31
View File
@@ -0,0 +1,31 @@
/* linux/include/asm-arm/arch-s3c2410/spi.h
*
* Copyright (c) 2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - SPI Controller platfrom_device info
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_SPIGPIO_H
#define __ASM_ARCH_SPIGPIO_H __FILE__
struct s3c2410_spigpio_info;
struct spi_board_info;
struct s3c2410_spigpio_info {
unsigned long pin_clk;
unsigned long pin_mosi;
unsigned long pin_miso;
unsigned long board_size;
struct spi_board_info *board_info;
void (*chip_select)(struct s3c2410_spigpio_info *spi, int cs);
};
#endif /* __ASM_ARCH_SPIGPIO_H */
include/asm-arm/arch-s3c2410/spi.h
+29
View File
@@ -0,0 +1,29 @@
/* linux/include/asm-arm/arch-s3c2410/spi.h
*
* Copyright (c) 2006 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
*
* S3C2410 - SPI Controller platform_device info
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_SPI_H
#define __ASM_ARCH_SPI_H __FILE__
struct s3c2410_spi_info;
struct spi_board_info;
struct s3c2410_spi_info {
unsigned long pin_cs; /* simple gpio cs */
unsigned long board_size;
struct spi_board_info *board_info;
void (*set_cs)(struct s3c2410_spi_info *spi, int cs, int pol);
};
#endif /* __ASM_ARCH_SPI_H */
include/asm-arm/bug.h
+1
View File
@@ -2,6 +2,7 @@
#define _ASMARM_BUG_H
#include <linux/config.h>
#include <linux/stddef.h>
#ifdef CONFIG_BUG
#ifdef CONFIG_DEBUG_BUGVERBOSE
include/asm-arm/procinfo.h
-2
View File
@@ -45,8 +45,6 @@ extern unsigned int elf_hwcap;
#endif /* __ASSEMBLY__ */
#define PROC_INFO_SZ 48
#define HWCAP_SWP 1
#define HWCAP_HALF 2
#define HWCAP_THUMB 4
include/asm-arm/spinlock.h
+6
View File
@@ -142,6 +142,9 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
: "cc");
}
/* write_can_lock - would write_trylock() succeed? */
#define __raw_write_can_lock(x) ((x)->lock == 0x80000000)
/*
* Read locks are a bit more hairy:
* - Exclusively load the lock value.
@@ -198,4 +201,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
/* read_can_lock - would read_trylock() succeed? */
#define __raw_read_can_lock(x) ((x)->lock < 0x80000000)
#endif /* __ASM_SPINLOCK_H */
include/asm-arm/system.h
+6
View File
@@ -127,6 +127,12 @@ static inline int cpu_is_xsc3(void)
}
#endif
#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3)
#define cpu_is_xscale() 0
#else
#define cpu_is_xscale() 1
#endif
#define set_cr(x) \
__asm__ __volatile__( \
"mcr p15, 0, %0, c1, c0, 0 @ set CR" \
include/asm-arm/unistd.h
+32 -7
View File
@@ -360,6 +360,24 @@
#define __ARM_NR_usr32 (__ARM_NR_BASE+4)
#define __ARM_NR_set_tls (__ARM_NR_BASE+5)
/*
* The following syscalls are obsolete and no longer available for EABI.
*/
#if defined(__ARM_EABI__) && !defined(__KERNEL__)
#undef __NR_time
#undef __NR_umount
#undef __NR_stime
#undef __NR_alarm
#undef __NR_utime
#undef __NR_getrlimit
#undef __NR_select
#undef __NR_readdir
#undef __NR_mmap
#undef __NR_socketcall
#undef __NR_syscall
#undef __NR_ipc
#endif
#define __sys2(x) #x
#define __sys1(x) __sys2(x)
@@ -392,7 +410,8 @@ type name(void) { \
__asm__ __volatile__ ( \
__syscall(name) \
: "=r" (__res_r0) \
: __SYS_REG_LIST() ); \
: __SYS_REG_LIST() \
: "memory" ); \
__res = __res_r0; \
__syscall_return(type,__res); \
}
@@ -406,7 +425,8 @@ type name(type1 arg1) { \
__asm__ __volatile__ ( \
__syscall(name) \
: "=r" (__res_r0) \
: __SYS_REG_LIST( "0" (__r0) ) ); \
: __SYS_REG_LIST( "0" (__r0) ) \
: "memory" ); \
__res = __res_r0; \
__syscall_return(type,__res); \
}
@@ -421,7 +441,8 @@ type name(type1 arg1,type2 arg2) { \
__asm__ __volatile__ ( \
__syscall(name) \
: "=r" (__res_r0) \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1) ) ); \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1) ) \
: "memory" ); \
__res = __res_r0; \
__syscall_return(type,__res); \
}
@@ -438,7 +459,8 @@ type name(type1 arg1,type2 arg2,type3 arg3) { \
__asm__ __volatile__ ( \
__syscall(name) \
: "=r" (__res_r0) \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2) ) ); \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2) ) \
: "memory" ); \
__res = __res_r0; \
__syscall_return(type,__res); \
}
@@ -456,7 +478,8 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) { \
__asm__ __volatile__ ( \
__syscall(name) \
: "=r" (__res_r0) \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) ) ); \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) ) \
: "memory" ); \
__res = __res_r0; \
__syscall_return(type,__res); \
}
@@ -476,7 +499,8 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) { \
__syscall(name) \
: "=r" (__res_r0) \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2), \
"r" (__r3), "r" (__r4) ) ); \
"r" (__r3), "r" (__r4) ) \
: "memory" ); \
__res = __res_r0; \
__syscall_return(type,__res); \
}
@@ -496,7 +520,8 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
__syscall(name) \
: "=r" (__res_r0) \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2), \
"r" (__r3), "r" (__r4), "r" (__r5) ) ); \
"r" (__r3), "r" (__r4), "r" (__r5) ) \
: "memory" ); \
__res = __res_r0; \
__syscall_return(type,__res); \
}
include/asm-generic/pgtable.h
+1 -10
View File
@@ -159,17 +159,8 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addres
#define lazy_mmu_prot_update(pte) do { } while (0)
#endif
#ifndef __HAVE_ARCH_MULTIPLE_ZERO_PAGE
#ifndef __HAVE_ARCH_MOVE_PTE
#define move_pte(pte, prot, old_addr, new_addr) (pte)
#else
#define move_pte(pte, prot, old_addr, new_addr) \
({ \
pte_t newpte = (pte); \
if (pte_present(pte) && pfn_valid(pte_pfn(pte)) && \
pte_page(pte) == ZERO_PAGE(old_addr)) \
newpte = mk_pte(ZERO_PAGE(new_addr), (prot)); \
newpte; \
})
#endif
/*
include/asm-i386/atomic.h
+3 -2
View File
@@ -183,6 +183,7 @@ static __inline__ int atomic_add_return(int i, atomic_t *v)
{
int __i;
#ifdef CONFIG_M386
unsigned long flags;
if(unlikely(boot_cpu_data.x86==3))
goto no_xadd;
#endif
@@ -196,10 +197,10 @@ static __inline__ int atomic_add_return(int i, atomic_t *v)
#ifdef CONFIG_M386
no_xadd: /* Legacy 386 processor */
local_irq_disable();
local_irq_save(flags);
__i = atomic_read(v);
atomic_set(v, i + __i);
local_irq_enable();
local_irq_restore(flags);
return i + __i;
#endif
}
include/asm-i386/cpufeature.h
+1
View File
@@ -71,6 +71,7 @@
#define X86_FEATURE_P4 (3*32+ 7) /* P4 */
#define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
#define X86_FEATURE_UP (3*32+ 9) /* smp kernel running on up */
#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */
/* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
#define X86_FEATURE_XMM3 (4*32+ 0) /* Streaming SIMD Extensions-3 */
include/asm-i386/i387.h
+26 -4
View File
@@ -13,6 +13,7 @@
#include <linux/sched.h>
#include <linux/init.h>
#include <linux/kernel_stat.h>
#include <asm/processor.h>
#include <asm/sigcontext.h>
#include <asm/user.h>
@@ -38,17 +39,38 @@ extern void init_fpu(struct task_struct *);
extern void kernel_fpu_begin(void);
#define kernel_fpu_end() do { stts(); preempt_enable(); } while(0)
/* We need a safe address that is cheap to find and that is already
in L1 during context switch. The best choices are unfortunately
different for UP and SMP */
#ifdef CONFIG_SMP
#define safe_address (__per_cpu_offset[0])
#else
#define safe_address (kstat_cpu(0).cpustat.user)
#endif
/*
* These must be called with preempt disabled
*/
static inline void __save_init_fpu( struct task_struct *tsk )
{
/* Use more nops than strictly needed in case the compiler
varies code */
alternative_input(
"fnsave %1 ; fwait ;" GENERIC_NOP2,
"fxsave %1 ; fnclex",
"fnsave %[fx] ;fwait;" GENERIC_NOP8 GENERIC_NOP4,
"fxsave %[fx]\n"
"bt $7,%[fsw] ; jnc 1f ; fnclex\n1:",
X86_FEATURE_FXSR,
"m" (tsk->thread.i387.fxsave)
:"memory");
[fx] "m" (tsk->thread.i387.fxsave),
[fsw] "m" (tsk->thread.i387.fxsave.swd) : "memory");
/* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
is pending. Clear the x87 state here by setting it to fixed
values. safe_address is a random variable that should be in L1 */
alternative_input(
GENERIC_NOP8 GENERIC_NOP2,
"emms\n\t" /* clear stack tags */
"fildl %[addr]", /* set F?P to defined value */
X86_FEATURE_FXSAVE_LEAK,
[addr] "m" (safe_address));
task_thread_info(tsk)->status &= ~TS_USEDFPU;
}
include/asm-i386/io_apic.h
+1
View File
@@ -200,6 +200,7 @@ extern int io_apic_get_unique_id (int ioapic, int apic_id);
extern int io_apic_get_version (int ioapic);
extern int io_apic_get_redir_entries (int ioapic);
extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low);
extern int timer_uses_ioapic_pin_0;
#endif /* CONFIG_ACPI */
extern int (*ioapic_renumber_irq)(int ioapic, int irq);
include/asm-i386/pgtable-2level.h
+3
View File
@@ -18,6 +18,9 @@
#define set_pte_atomic(pteptr, pteval) set_pte(pteptr,pteval)
#define set_pmd(pmdptr, pmdval) (*(pmdptr) = (pmdval))
#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
#define ptep_get_and_clear(mm,addr,xp) __pte(xchg(&(xp)->pte_low, 0))
#define pte_same(a, b) ((a).pte_low == (b).pte_low)
#define pte_page(x) pfn_to_page(pte_pfn(x))
include/asm-i386/pgtable-3level.h
+20
View File
@@ -85,6 +85,26 @@ static inline void pud_clear (pud_t * pud) { }
#define pmd_offset(pud, address) ((pmd_t *) pud_page(*(pud)) + \
pmd_index(address))
/*
* For PTEs and PDEs, we must clear the P-bit first when clearing a page table
* entry, so clear the bottom half first and enforce ordering with a compiler
* barrier.
*/
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
ptep->pte_low = 0;
smp_wmb();
ptep->pte_high = 0;
}
static inline void pmd_clear(pmd_t *pmd)
{
u32 *tmp = (u32 *)pmd;
*tmp = 0;
smp_wmb();
*(tmp + 1) = 0;
}
static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
pte_t res;
include/asm-i386/pgtable.h
+1 -3
View File
@@ -204,12 +204,10 @@ extern unsigned long long __PAGE_KERNEL, __PAGE_KERNEL_EXEC;
extern unsigned long pg0[];
#define pte_present(x) ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
/* To avoid harmful races, pmd_none(x) should check only the lower when PAE */
#define pmd_none(x) (!(unsigned long)pmd_val(x))
#define pmd_present(x) (pmd_val(x) & _PAGE_PRESENT)
#define pmd_clear(xp) do { set_pmd(xp, __pmd(0)); } while (0)
#define pmd_bad(x) ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
@@ -268,7 +266,7 @@ static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long
pte_t pte;
if (full) {
pte = *ptep;
*ptep = __pte(0);
pte_clear(mm, addr, ptep);
} else {
pte = ptep_get_and_clear(mm, addr, ptep);
}
include/asm-i386/unistd.h
+3 -1
View File
@@ -320,8 +320,10 @@
#define __NR_get_robust_list 312
#define __NR_splice 313
#define __NR_sync_file_range 314
#define __NR_tee 315
#define __NR_vmsplice 316
#define NR_syscalls 315
#define NR_syscalls 317
/*
* user-visible error numbers are in the range -1 - -128: see
include/asm-ia64/acpi.h
+2 -3
View File
@@ -110,9 +110,8 @@ extern void prefill_possible_map(void);
extern int additional_cpus;
#ifdef CONFIG_ACPI_NUMA
/* Proximity bitmap length; _PXM is at most 255 (8 bit)*/
#ifdef CONFIG_IA64_NR_NODES
#define MAX_PXM_DOMAINS CONFIG_IA64_NR_NODES
#if MAX_NUMNODES > 256
#define MAX_PXM_DOMAINS MAX_NUMNODES
#else
#define MAX_PXM_DOMAINS (256)
#endif
include/asm-ia64/bitops.h
-1
View File
@@ -11,7 +11,6 @@
#include <linux/compiler.h>
#include <linux/types.h>
#include <asm/bitops.h>
#include <asm/intrinsics.h>
/**
include/asm-ia64/machvec.h
+2
View File
@@ -347,9 +347,11 @@ extern ia64_mv_dma_supported swiotlb_dma_supported;
#endif
#ifndef platform_pci_legacy_read
# define platform_pci_legacy_read ia64_pci_legacy_read
extern int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size);
#endif
#ifndef platform_pci_legacy_write
# define platform_pci_legacy_write ia64_pci_legacy_write
extern int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size);
#endif
#ifndef platform_inb
# define platform_inb __ia64_inb
include/asm-ia64/sn/sn2/sn_hwperf.h
+5 -1
View File
@@ -45,8 +45,12 @@ struct sn_hwperf_object_info {
#define SN_HWPERF_IS_NODE(x) ((x) && strstr((x)->name, "SHub"))
#define SN_HWPERF_IS_NODE_SHUB2(x) ((x) && strstr((x)->name, "SHub 2."))
#define SN_HWPERF_IS_IONODE(x) ((x) && strstr((x)->name, "TIO"))
#define SN_HWPERF_IS_ROUTER(x) ((x) && strstr((x)->name, "Router"))
#define SN_HWPERF_IS_NL3ROUTER(x) ((x) && strstr((x)->name, "NL3Router"))
#define SN_HWPERF_IS_NL4ROUTER(x) ((x) && strstr((x)->name, "NL4Router"))
#define SN_HWPERF_IS_OLDROUTER(x) ((x) && strstr((x)->name, "Router"))
#define SN_HWPERF_IS_ROUTER(x) (SN_HWPERF_IS_NL3ROUTER(x) || \
SN_HWPERF_IS_NL4ROUTER(x) || \
SN_HWPERF_IS_OLDROUTER(x))
#define SN_HWPERF_FOREIGN(x) ((x) && !(x)->sn_hwp_this_part && !(x)->sn_hwp_is_shared)
#define SN_HWPERF_SAME_OBJTYPE(x,y) ((SN_HWPERF_IS_NODE(x) && SN_HWPERF_IS_NODE(y)) ||\
(SN_HWPERF_IS_IONODE(x) && SN_HWPERF_IS_IONODE(y)) ||\
include/asm-ia64/sn/sn_sal.h
+14 -3
View File
@@ -8,7 +8,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 2000-2005 Silicon Graphics, Inc. All rights reserved.
* Copyright (c) 2000-2006 Silicon Graphics, Inc. All rights reserved.
*/
@@ -85,6 +85,7 @@
#define SN_SAL_GET_PROM_FEATURE_SET 0x02000065
#define SN_SAL_SET_OS_FEATURE_SET 0x02000066
#define SN_SAL_INJECT_ERROR 0x02000067
/*
* Service-specific constants
@@ -705,10 +706,8 @@ static inline int
sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array)
{
struct ia64_sal_retval ret_stuff;
int cnodeid;
unsigned long irq_flags;
cnodeid = nasid_to_cnodeid(get_node_number(paddr));
local_irq_save(irq_flags);
ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_MEMPROTECT, paddr, len,
(u64)nasid_array, perms, 0, 0, 0);
@@ -1140,4 +1139,16 @@ ia64_sn_set_os_feature(int feature)
return rv.status;
}
static inline int
sn_inject_error(u64 paddr, u64 *data, u64 *ecc)
{
struct ia64_sal_retval ret_stuff;
unsigned long irq_flags;
local_irq_save(irq_flags);
ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_INJECT_ERROR, paddr, (u64)data,
(u64)ecc, 0, 0, 0, 0);
local_irq_restore(irq_flags);
return ret_stuff.status;
}
#endif /* _ASM_IA64_SN_SN_SAL_H */
include/asm-ia64/thread_info.h
+1 -1
View File
@@ -67,7 +67,7 @@ struct thread_info {
#define end_of_stack(p) (unsigned long *)((void *)(p) + IA64_RBS_OFFSET)
#define __HAVE_ARCH_TASK_STRUCT_ALLOCATOR
#define alloc_task_struct() ((task_t *)__get_free_pages(GFP_KERNEL, KERNEL_STACK_SIZE_ORDER))
#define alloc_task_struct() ((task_t *)__get_free_pages(GFP_KERNEL | __GFP_COMP, KERNEL_STACK_SIZE_ORDER))
#define free_task_struct(tsk) free_pages((unsigned long) (tsk), KERNEL_STACK_SIZE_ORDER)
#endif /* !__ASSEMBLY */
include/asm-ia64/topology.h
+5
View File
@@ -22,6 +22,11 @@
/* Nodes w/o CPUs are preferred for memory allocations, see build_zonelists */
#define PENALTY_FOR_NODE_WITH_CPUS 255
/*
* Distance above which we begin to use zone reclaim
*/
#define RECLAIM_DISTANCE 15
/*
* Returns the number of the node containing CPU 'cpu'
*/
include/asm-ia64/unistd.h
+3 -1
View File
@@ -289,12 +289,14 @@
#define __NR_set_robust_list 1298
#define __NR_get_robust_list 1299
#define __NR_sync_file_range 1300
#define __NR_tee 1301
#define __NR_vmsplice 1302
#ifdef __KERNEL__
#include <linux/config.h>
#define NR_syscalls 277 /* length of syscall table */
#define NR_syscalls 279 /* length of syscall table */
#define __ARCH_WANT_SYS_RT_SIGACTION
include/asm-m32r/assembler.h
+5
View File
@@ -109,6 +109,9 @@
push r13
mvfachi r13
push r13
ldi r13, #0
push r13 ; dummy push acc1h
push r13 ; dummy push acc1l
#else
#error unknown isa configuration
#endif
@@ -156,6 +159,8 @@
pop r13
mvtaclo r13, a1
#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
pop r13 ; dummy pop acc1h
pop r13 ; dummy pop acc1l
pop r13
mvtachi r13
pop r13
include/asm-m32r/mappi3/mappi3_pld.h
+11 -11
View File
@@ -53,16 +53,14 @@
/* Power Control of MMC and CF */
#define PLD_CPCR __reg16(PLD_BASE + 0x14000)
/*==== ICU ====*/
#define M32R_IRQ_PC104 (5) /* INT4(PC/104) */
#define M32R_IRQ_I2C (28) /* I2C-BUS */
#define PLD_IRQ_CFIREQ (6) /* INT5 CFC Card Interrupt */
#define PLD_IRQ_CFC_INSERT (7) /* INT6 CFC Card Insert */
#define PLD_IRQ_IDEIREQ (8) /* INT7 IDE Interrupt */
#define PLD_IRQ_MMCCARD (43) /* MMC Card Insert */
#define PLD_IRQ_MMCIRQ (44) /* MMC Transfer Done */
/* ICU */
#define M32R_IRQ_PC104 (5) /* INT4(PC/104) */
#define M32R_IRQ_I2C (28) /* I2C-BUS */
#define PLD_IRQ_CFIREQ (6) /* INT5 CFC Card Interrupt */
#define PLD_IRQ_CFC_INSERT (7) /* INT6 CFC Card Insert & Eject */
#define PLD_IRQ_IDEIREQ (8) /* INT7 IDE Interrupt */
#define PLD_IRQ_MMCCARD (43) /* MMC Card Insert */
#define PLD_IRQ_MMCIRQ (44) /* MMC Transfer Done */
#if 0
/* LED Control
@@ -97,7 +95,6 @@
#define PLD_CRC16ADATA __reg16(PLD_BASE + 0x18008)
#define PLD_CRC16AINDATA __reg16(PLD_BASE + 0x1800a)
#if 0
/* RTC */
#define PLD_RTCCR __reg16(PLD_BASE + 0x1c000)
@@ -140,4 +137,7 @@
#endif
/* Reset Control */
#define PLD_REBOOT __reg16(PLD_BASE + 0x38000)
#endif /* _MAPPI3_PLD.H */
include/asm-m32r/ptrace.h
+10 -15
View File
@@ -43,6 +43,14 @@
#define PT_ACC1L 18
#define PT_ACCH PT_ACC0H
#define PT_ACCL PT_ACC0L
#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
#define PT_ACCH 15
#define PT_ACCL 16
#define PT_DUMMY_ACC1H 17
#define PT_DUMMY_ACC1L 18
#else
#error unknown isa conifiguration
#endif
#define PT_PSW 19
#define PT_BPC 20
#define PT_BBPSW 21
@@ -52,21 +60,6 @@
#define PT_LR 25
#define PT_SPI 26
#define PT_ORIGR0 27
#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
#define PT_ACCH 15
#define PT_ACCL 16
#define PT_PSW 17
#define PT_BPC 18
#define PT_BBPSW 19
#define PT_BBPC 20
#define PT_SPU 21
#define PT_FP 22
#define PT_LR 23
#define PT_SPI 24
#define PT_ORIGR0 25
#else
#error unknown isa conifiguration
#endif
/* virtual pt_reg entry for gdb */
#define PT_PC 30
@@ -121,6 +114,8 @@ struct pt_regs {
#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
unsigned long acch;
unsigned long accl;
unsigned long dummy_acc1h;
unsigned long dummy_acc1l;
#else
#error unknown isa configuration
#endif
include/asm-m32r/semaphore.h
+4 -60
View File
@@ -9,7 +9,7 @@
* SMP- and interrupt-safe semaphores..
*
* Copyright (C) 1996 Linus Torvalds
* Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
* Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
*/
#include <linux/config.h>
@@ -77,27 +77,8 @@ asmlinkage void __up(struct semaphore * sem);
*/
static inline void down(struct semaphore * sem)
{
unsigned long flags;
long count;
might_sleep();
local_irq_save(flags);
__asm__ __volatile__ (
"# down \n\t"
DCACHE_CLEAR("%0", "r4", "%1")
M32R_LOCK" %0, @%1; \n\t"
"addi %0, #-1; \n\t"
M32R_UNLOCK" %0, @%1; \n\t"
: "=&r" (count)
: "r" (&sem->count)
: "memory"
#ifdef CONFIG_CHIP_M32700_TS1
, "r4"
#endif /* CONFIG_CHIP_M32700_TS1 */
);
local_irq_restore(flags);
if (unlikely(count < 0))
if (unlikely(atomic_dec_return(&sem->count) < 0))
__down(sem);
}
@@ -107,28 +88,10 @@ static inline void down(struct semaphore * sem)
*/
static inline int down_interruptible(struct semaphore * sem)
{
unsigned long flags;
long count;
int result = 0;
might_sleep();
local_irq_save(flags);
__asm__ __volatile__ (
"# down_interruptible \n\t"
DCACHE_CLEAR("%0", "r4", "%1")
M32R_LOCK" %0, @%1; \n\t"
"addi %0, #-1; \n\t"
M32R_UNLOCK" %0, @%1; \n\t"
: "=&r" (count)
: "r" (&sem->count)
: "memory"
#ifdef CONFIG_CHIP_M32700_TS1
, "r4"
#endif /* CONFIG_CHIP_M32700_TS1 */
);
local_irq_restore(flags);
if (unlikely(count < 0))
if (unlikely(atomic_dec_return(&sem->count) < 0))
result = __down_interruptible(sem);
return result;
@@ -174,26 +137,7 @@ static inline int down_trylock(struct semaphore * sem)
*/
static inline void up(struct semaphore * sem)
{
unsigned long flags;
long count;
local_irq_save(flags);
__asm__ __volatile__ (
"# up \n\t"
DCACHE_CLEAR("%0", "r4", "%1")
M32R_LOCK" %0, @%1; \n\t"
"addi %0, #1; \n\t"
M32R_UNLOCK" %0, @%1; \n\t"
: "=&r" (count)
: "r" (&sem->count)
: "memory"
#ifdef CONFIG_CHIP_M32700_TS1
, "r4"
#endif /* CONFIG_CHIP_M32700_TS1 */
);
local_irq_restore(flags);
if (unlikely(count <= 0))
if (unlikely(atomic_inc_return(&sem->count) <= 0))
__up(sem);
}
include/asm-m32r/sigcontext.h
+2
View File
@@ -32,6 +32,8 @@ struct sigcontext {
#elif defined(CONFIG_ISA_M32R2) || defined(CONFIG_ISA_M32R)
unsigned long sc_acch;
unsigned long sc_accl;
unsigned long sc_dummy_acc1h;
unsigned long sc_dummy_acc1l;
#else
#error unknown isa configuration
#endif
include/asm-m32r/system.h
+23 -44
View File
@@ -6,8 +6,8 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2001 by Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
* Copyright (C) 2004 Hirokazu Takata <takata at linux-m32r.org>
* Copyright (C) 2001 Hiroyuki Kondo, Hirokazu Takata, and Hitoshi Yamamoto
* Copyright (C) 2004, 2006 Hirokazu Takata <takata at linux-m32r.org>
*/
#include <linux/config.h>
@@ -19,49 +19,28 @@
* switch_to(prev, next) should switch from task `prev' to `next'
* `prev' will never be the same as `next'.
*
* `next' and `prev' should be struct task_struct, but it isn't always defined
* `next' and `prev' should be task_t, but it isn't always defined
*/
#define switch_to(prev, next, last) do { \
register unsigned long arg0 __asm__ ("r0") = (unsigned long)prev; \
register unsigned long arg1 __asm__ ("r1") = (unsigned long)next; \
register unsigned long *oldsp __asm__ ("r2") = &(prev->thread.sp); \
register unsigned long *newsp __asm__ ("r3") = &(next->thread.sp); \
register unsigned long *oldlr __asm__ ("r4") = &(prev->thread.lr); \
register unsigned long *newlr __asm__ ("r5") = &(next->thread.lr); \
register struct task_struct *__last __asm__ ("r6"); \
__asm__ __volatile__ ( \
"st r8, @-r15 \n\t" \
"st r9, @-r15 \n\t" \
"st r10, @-r15 \n\t" \
"st r11, @-r15 \n\t" \
"st r12, @-r15 \n\t" \
"st r13, @-r15 \n\t" \
"st r14, @-r15 \n\t" \
"seth r14, #high(1f) \n\t" \
"or3 r14, r14, #low(1f) \n\t" \
"st r14, @r4 ; store old LR \n\t" \
"st r15, @r2 ; store old SP \n\t" \
"ld r15, @r3 ; load new SP \n\t" \
"st r0, @-r15 ; store 'prev' onto new stack \n\t" \
"ld r14, @r5 ; load new LR \n\t" \
"jmp r14 \n\t" \
".fillinsn \n " \
"1: \n\t" \
"ld r6, @r15+ ; load 'prev' from new stack \n\t" \
"ld r14, @r15+ \n\t" \
"ld r13, @r15+ \n\t" \
"ld r12, @r15+ \n\t" \
"ld r11, @r15+ \n\t" \
"ld r10, @r15+ \n\t" \
"ld r9, @r15+ \n\t" \
"ld r8, @r15+ \n\t" \
: "=&r" (__last) \
: "r" (arg0), "r" (arg1), "r" (oldsp), "r" (newsp), \
"r" (oldlr), "r" (newlr) \
: "memory" \
" seth lr, #high(1f) \n" \
" or3 lr, lr, #low(1f) \n" \
" st lr, @%4 ; store old LR \n" \
" ld lr, @%5 ; load new LR \n" \
" st sp, @%2 ; store old SP \n" \
" ld sp, @%3 ; load new SP \n" \
" push %1 ; store `prev' on new stack \n" \
" jmp lr \n" \
" .fillinsn \n" \
"1: \n" \
" pop %0 ; restore `__last' from new stack \n" \
: "=r" (last) \
: "0" (prev), \
"r" (&(prev->thread.sp)), "r" (&(next->thread.sp)), \
"r" (&(prev->thread.lr)), "r" (&(next->thread.lr)) \
: "memory", "lr" \
); \
last = __last; \
} while(0)
/*
@@ -167,8 +146,8 @@ extern void __xchg_called_with_bad_pointer(void);
#define DCACHE_CLEAR(reg0, reg1, addr)
#endif /* CONFIG_CHIP_M32700_TS1 */
static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr,
int size)
static inline unsigned long
__xchg(unsigned long x, volatile void * ptr, int size)
{
unsigned long flags;
unsigned long tmp = 0;
@@ -220,7 +199,7 @@ static __inline__ unsigned long __xchg(unsigned long x, volatile void * ptr,
#define __HAVE_ARCH_CMPXCHG 1
static __inline__ unsigned long
static inline unsigned long
__cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
{
unsigned long flags;
@@ -254,7 +233,7 @@ __cmpxchg_u32(volatile unsigned int *p, unsigned int old, unsigned int new)
if something tries to do an invalid cmpxchg(). */
extern void __cmpxchg_called_with_bad_pointer(void);
static __inline__ unsigned long
static inline unsigned long
__cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
{
switch (size) {
include/asm-mips/addrspace.h
+1
View File
@@ -129,6 +129,7 @@
#if defined (CONFIG_CPU_R4300) \
|| defined (CONFIG_CPU_R4X00) \
|| defined (CONFIG_CPU_R5000) \
|| defined (CONFIG_CPU_RM7000) \
|| defined (CONFIG_CPU_NEVADA) \
|| defined (CONFIG_CPU_TX49XX) \
|| defined (CONFIG_CPU_MIPS64)
include/asm-mips/asmmacro.h
+47
View File
@@ -17,7 +17,26 @@
#ifdef CONFIG_64BIT
#include <asm/asmmacro-64.h>
#endif
#ifdef CONFIG_MIPS_MT_SMTC
#include <asm/mipsmtregs.h>
#endif
#ifdef CONFIG_MIPS_MT_SMTC
.macro local_irq_enable reg=t0
mfc0 \reg, CP0_TCSTATUS
ori \reg, \reg, TCSTATUS_IXMT
xori \reg, \reg, TCSTATUS_IXMT
mtc0 \reg, CP0_TCSTATUS
ehb
.endm
.macro local_irq_disable reg=t0
mfc0 \reg, CP0_TCSTATUS
ori \reg, \reg, TCSTATUS_IXMT
mtc0 \reg, CP0_TCSTATUS
ehb
.endm
#else
.macro local_irq_enable reg=t0
mfc0 \reg, CP0_STATUS
ori \reg, \reg, 1
@@ -32,6 +51,7 @@
mtc0 \reg, CP0_STATUS
irq_disable_hazard
.endm
#endif /* CONFIG_MIPS_MT_SMTC */
#ifdef CONFIG_CPU_SB1
.macro fpu_enable_hazard
@@ -48,4 +68,31 @@
.endm
#endif
/*
* Temporary until all gas have MT ASE support
*/
.macro DMT reg=0
.word (0x41600bc1 | (\reg << 16))
.endm
.macro EMT reg=0
.word (0x41600be1 | (\reg << 16))
.endm
.macro DVPE reg=0
.word (0x41600001 | (\reg << 16))
.endm
.macro EVPE reg=0
.word (0x41600021 | (\reg << 16))
.endm
.macro MFTR rt=0, rd=0, u=0, sel=0
.word (0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel))
.endm
.macro MTTR rt=0, rd=0, u=0, sel=0
.word (0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel))
.endm
#endif /* _ASM_ASMMACRO_H */
include/asm-mips/bitops.h
+32 -40
View File
@@ -466,65 +466,57 @@ static inline unsigned long __ffs(unsigned long word)
return __ilog2(word & -word);
}
/*
* fls - find last bit set.
* @word: The word to search
*
* This is defined the same way as ffs.
* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
*/
static inline int fls(int word)
{
__asm__ ("clz %0, %1" : "=r" (word) : "r" (word));
return 32 - word;
}
#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64)
static inline int fls64(__u64 word)
{
__asm__ ("dclz %0, %1" : "=r" (word) : "r" (word));
return 64 - word;
}
#else
#include <asm-generic/bitops/fls64.h>
#endif
/*
* ffs - find first bit set.
* @word: The word to search
*
* Returns 1..SZLONG
* Returns 0 if no bit exists
* This is defined the same way as
* the libc and compiler builtin ffs routines, therefore
* differs in spirit from the above ffz (man ffs).
*/
static inline unsigned long ffs(unsigned long word)
static inline int ffs(int word)
{
if (!word)
return 0;
return __ffs(word) + 1;
}
/*
* ffz - find first zero in word.
* @word: The word to search
*
* Undefined if no zero exists, so code should check against ~0UL first.
*/
static inline unsigned long ffz(unsigned long word)
{
return __ffs (~word);
}
/*
* fls - find last bit set.
* @word: The word to search
*
* Returns 1..SZLONG
* Returns 0 if no bit exists
*/
static inline unsigned long fls(unsigned long word)
{
#ifdef CONFIG_CPU_MIPS32
__asm__ ("clz %0, %1" : "=r" (word) : "r" (word));
return 32 - word;
#endif
#ifdef CONFIG_CPU_MIPS64
__asm__ ("dclz %0, %1" : "=r" (word) : "r" (word));
return 64 - word;
#endif
return fls(word & -word);
}
#else
#include <asm-generic/bitops/__ffs.h>
#include <asm-generic/bitops/ffs.h>
#include <asm-generic/bitops/ffz.h>
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/fls64.h>
#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */
#include <asm-generic/bitops/fls64.h>
#include <asm-generic/bitops/ffz.h>
#include <asm-generic/bitops/find.h>
#ifdef __KERNEL__
include/asm-mips/cacheflush.h
+1
View File
@@ -74,6 +74,7 @@ static inline void copy_from_user_page(struct vm_area_struct *vma,
extern void (*flush_cache_sigtramp)(unsigned long addr);
extern void (*flush_icache_all)(void);
extern void (*local_flush_data_cache_page)(void * addr);
extern void (*flush_data_cache_page)(unsigned long addr);
/*
include/asm-mips/cpu-features.h
+1 -1
View File
@@ -40,7 +40,7 @@
#define cpu_has_sb1_cache (cpu_data[0].options & MIPS_CPU_SB1_CACHE)
#endif
#ifndef cpu_has_fpu
#define cpu_has_fpu (cpu_data[0].options & MIPS_CPU_FPU)
#define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU)
#endif
#ifndef cpu_has_32fpr
#define cpu_has_32fpr (cpu_data[0].options & MIPS_CPU_32FPR)
include/asm-mips/cpu-info.h
+10
View File
@@ -73,6 +73,16 @@ struct cpuinfo_mips {
struct cache_desc dcache; /* Primary D or combined I/D cache */
struct cache_desc scache; /* Secondary cache */
struct cache_desc tcache; /* Tertiary/split secondary cache */
#if defined(CONFIG_MIPS_MT_SMTC)
/*
* In the MIPS MT "SMTC" model, each TC is considered
* to be a "CPU" for the purposes of scheduling, but
* exception resources, ASID spaces, etc, are common
* to all TCs within the same VPE.
*/
int vpe_id; /* Virtual Processor number */
int tc_id; /* Thread Context number */
#endif /* CONFIG_MIPS_MT */
void *data; /* Additional data */
} __attribute__((aligned(SMP_CACHE_BYTES)));
include/asm-mips/cpu.h
+5 -1
View File
@@ -51,6 +51,7 @@
#define PRID_IMP_R4300 0x0b00
#define PRID_IMP_VR41XX 0x0c00
#define PRID_IMP_R12000 0x0e00
#define PRID_IMP_R14000 0x0f00
#define PRID_IMP_R8000 0x1000
#define PRID_IMP_PR4450 0x1200
#define PRID_IMP_R4600 0x2000
@@ -87,6 +88,7 @@
#define PRID_IMP_24K 0x9300
#define PRID_IMP_34K 0x9500
#define PRID_IMP_24KE 0x9600
#define PRID_IMP_74K 0x9700
/*
* These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
@@ -196,7 +198,9 @@
#define CPU_34K 60
#define CPU_PR4450 61
#define CPU_SB1A 62
#define CPU_LAST 62
#define CPU_74K 63
#define CPU_R14000 64
#define CPU_LAST 64
/*
* ISA Level encodings
include/asm-mips/delay.h
+12 -10
View File
@@ -19,20 +19,22 @@ static inline void __delay(unsigned long loops)
{
if (sizeof(long) == 4)
__asm__ __volatile__ (
".set\tnoreorder\n"
"1:\tbnez\t%0,1b\n\t"
"subu\t%0,1\n\t"
".set\treorder"
" .set noreorder \n"
" .align 3 \n"
"1: bnez %0, 1b \n"
" subu %0, 1 \n"
" .set reorder \n"
: "=r" (loops)
: "0" (loops));
else if (sizeof(long) == 8)
__asm__ __volatile__ (
".set\tnoreorder\n"
"1:\tbnez\t%0,1b\n\t"
"dsubu\t%0,1\n\t"
".set\treorder"
:"=r" (loops)
:"0" (loops));
" .set noreorder \n"
" .align 3 \n"
"1: bnez %0, 1b \n"
" dsubu %0, 1 \n"
" .set reorder \n"
: "=r" (loops)
: "0" (loops));
}
include/asm-mips/ds1742.h
+13
View File
@@ -0,0 +1,13 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
*/
#ifndef _ASM_DS1742_H
#define _ASM_DS1742_H
#include <ds1742.h>
#endif /* _ASM_DS1742_H */
include/asm-mips/elf.h
+42 -1
View File
@@ -119,8 +119,49 @@
#define SHT_MIPS_CONFLICT 0x70000002
#define SHT_MIPS_GPTAB 0x70000003
#define SHT_MIPS_UCODE 0x70000004
#define SHT_MIPS_DEBUG 0x70000005
#define SHT_MIPS_REGINFO 0x70000006
#define SHT_MIPS_PACKAGE 0x70000007
#define SHT_MIPS_PACKSYM 0x70000008
#define SHT_MIPS_RELD 0x70000009
#define SHT_MIPS_IFACE 0x7000000b
#define SHT_MIPS_CONTENT 0x7000000c
#define SHT_MIPS_OPTIONS 0x7000000d
#define SHT_MIPS_SHDR 0x70000010
#define SHT_MIPS_FDESC 0x70000011
#define SHT_MIPS_EXTSYM 0x70000012
#define SHT_MIPS_DENSE 0x70000013
#define SHT_MIPS_PDESC 0x70000014
#define SHT_MIPS_LOCSYM 0x70000015
#define SHT_MIPS_AUXSYM 0x70000016
#define SHT_MIPS_OPTSYM 0x70000017
#define SHT_MIPS_LOCSTR 0x70000018
#define SHT_MIPS_LINE 0x70000019
#define SHT_MIPS_RFDESC 0x7000001a
#define SHT_MIPS_DELTASYM 0x7000001b
#define SHT_MIPS_DELTAINST 0x7000001c
#define SHT_MIPS_DELTACLASS 0x7000001d
#define SHT_MIPS_DWARF 0x7000001e
#define SHT_MIPS_DELTADECL 0x7000001f
#define SHT_MIPS_SYMBOL_LIB 0x70000020
#define SHT_MIPS_EVENTS 0x70000021
#define SHT_MIPS_TRANSLATE 0x70000022
#define SHT_MIPS_PIXIE 0x70000023
#define SHT_MIPS_XLATE 0x70000024
#define SHT_MIPS_XLATE_DEBUG 0x70000025
#define SHT_MIPS_WHIRL 0x70000026
#define SHT_MIPS_EH_REGION 0x70000027
#define SHT_MIPS_XLATE_OLD 0x70000028
#define SHT_MIPS_PDR_EXCEPTION 0x70000029
#define SHF_MIPS_GPREL 0x10000000
#define SHF_MIPS_GPREL 0x10000000
#define SHF_MIPS_MERGE 0x20000000
#define SHF_MIPS_ADDR 0x40000000
#define SHF_MIPS_STRING 0x80000000
#define SHF_MIPS_NOSTRIP 0x08000000
#define SHF_MIPS_LOCAL 0x04000000
#define SHF_MIPS_NAMES 0x02000000
#define SHF_MIPS_NODUPES 0x01000000
#ifndef ELF_ARCH
/* ELF register definitions */
include/asm-mips/fpu.h
+4
View File
@@ -21,6 +21,10 @@
#include <asm/processor.h>
#include <asm/current.h>
#ifdef CONFIG_MIPS_MT_FPAFF
#include <asm/mips_mt.h>
#endif
struct sigcontext;
struct sigcontext32;
include/asm-mips/futex.h
+116 -25
View File
@@ -7,6 +7,7 @@
#include <linux/futex.h>
#include <asm/errno.h>
#include <asm/uaccess.h>
#include <asm/war.h>
#ifdef CONFIG_SMP
#define __FUTEX_SMP_SYNC " sync \n"
@@ -16,30 +17,58 @@
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
{ \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" .set mips3 \n" \
"1: ll %1, (%3) # __futex_atomic_op1 \n" \
" .set mips0 \n" \
" " insn " \n" \
" .set mips3 \n" \
"2: sc $1, (%3) \n" \
" beqzl $1, 1b \n" \
__FUTEX_SMP_SYNC \
"3: \n" \
" .set pop \n" \
" .set mips0 \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %5 \n" \
" j 2b \n" \
" .previous \n" \
" .section __ex_table,\"a\" \n" \
" "__UA_ADDR "\t1b, 4b \n" \
" "__UA_ADDR "\t2b, 4b \n" \
" .previous \n" \
: "=r" (ret), "=r" (oldval) \
: "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \
if (cpu_has_llsc && R10000_LLSC_WAR) { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" .set mips3 \n" \
"1: ll %1, (%3) # __futex_atomic_op \n" \
" .set mips0 \n" \
" " insn " \n" \
" .set mips3 \n" \
"2: sc $1, (%3) \n" \
" beqzl $1, 1b \n" \
__FUTEX_SMP_SYNC \
"3: \n" \
" .set pop \n" \
" .set mips0 \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %5 \n" \
" j 2b \n" \
" .previous \n" \
" .section __ex_table,\"a\" \n" \
" "__UA_ADDR "\t1b, 4b \n" \
" "__UA_ADDR "\t2b, 4b \n" \
" .previous \n" \
: "=r" (ret), "=r" (oldval) \
: "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \
} else if (cpu_has_llsc) { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" .set mips3 \n" \
"1: ll %1, (%3) # __futex_atomic_op \n" \
" .set mips0 \n" \
" " insn " \n" \
" .set mips3 \n" \
"2: sc $1, (%3) \n" \
" beqz $1, 1b \n" \
__FUTEX_SMP_SYNC \
"3: \n" \
" .set pop \n" \
" .set mips0 \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %5 \n" \
" j 2b \n" \
" .previous \n" \
" .section __ex_table,\"a\" \n" \
" "__UA_ADDR "\t1b, 4b \n" \
" "__UA_ADDR "\t2b, 4b \n" \
" .previous \n" \
: "=r" (ret), "=r" (oldval) \
: "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \
} else \
ret = -ENOSYS; \
}
static inline int
@@ -102,7 +131,69 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
static inline int
futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
{
return -ENOSYS;
int retval;
if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
return -EFAULT;
if (cpu_has_llsc && R10000_LLSC_WAR) {
__asm__ __volatile__(
"# futex_atomic_cmpxchg_inatomic \n"
" .set push \n"
" .set noat \n"
" .set mips3 \n"
"1: ll %0, %2 \n"
" bne %0, %z3, 3f \n"
" .set mips0 \n"
" move $1, %z4 \n"
" .set mips3 \n"
"2: sc $1, %1 \n"
" beqzl $1, 1b \n"
__FUTEX_SMP_SYNC
"3: \n"
" .set pop \n"
" .section .fixup,\"ax\" \n"
"4: li %0, %5 \n"
" j 3b \n"
" .previous \n"
" .section __ex_table,\"a\" \n"
" "__UA_ADDR "\t1b, 4b \n"
" "__UA_ADDR "\t2b, 4b \n"
" .previous \n"
: "=&r" (retval), "=R" (*uaddr)
: "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
: "memory");
} else if (cpu_has_llsc) {
__asm__ __volatile__(
"# futex_atomic_cmpxchg_inatomic \n"
" .set push \n"
" .set noat \n"
" .set mips3 \n"
"1: ll %0, %2 \n"
" bne %0, %z3, 3f \n"
" .set mips0 \n"
" move $1, %z4 \n"
" .set mips3 \n"
"2: sc $1, %1 \n"
" beqz $1, 1b \n"
__FUTEX_SMP_SYNC
"3: \n"
" .set pop \n"
" .section .fixup,\"ax\" \n"
"4: li %0, %5 \n"
" j 3b \n"
" .previous \n"
" .section __ex_table,\"a\" \n"
" "__UA_ADDR "\t1b, 4b \n"
" "__UA_ADDR "\t2b, 4b \n"
" .previous \n"
: "=&r" (retval), "=R" (*uaddr)
: "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
: "memory");
} else
return -ENOSYS;
return retval;
}
#endif
include/asm-mips/hazards.h
+2
View File
@@ -284,6 +284,8 @@ do { \
#define instruction_hazard() do { } while (0)
#endif
extern void mips_ihb(void);
#endif /* __ASSEMBLY__ */
#endif /* _ASM_HAZARDS_H */
include/asm-mips/inst.h
+28 -5
View File
@@ -6,6 +6,7 @@
* for more details.
*
* Copyright (C) 1996, 2000 by Ralf Baechle
* Copyright (C) 2006 by Thiemo Seufer
*/
#ifndef _ASM_INST_H
#define _ASM_INST_H
@@ -21,14 +22,14 @@ enum major_op {
cop0_op, cop1_op, cop2_op, cop1x_op,
beql_op, bnel_op, blezl_op, bgtzl_op,
daddi_op, daddiu_op, ldl_op, ldr_op,
major_1c_op, jalx_op, major_1e_op, major_1f_op,
spec2_op, jalx_op, mdmx_op, spec3_op,
lb_op, lh_op, lwl_op, lw_op,
lbu_op, lhu_op, lwr_op, lwu_op,
sb_op, sh_op, swl_op, sw_op,
sdl_op, sdr_op, swr_op, cache_op,
ll_op, lwc1_op, lwc2_op, pref_op,
lld_op, ldc1_op, ldc2_op, ld_op,
sc_op, swc1_op, swc2_op, rdhwr_op,
sc_op, swc1_op, swc2_op, major_3b_op,
scd_op, sdc1_op, sdc2_op, sd_op
};
@@ -37,7 +38,7 @@ enum major_op {
*/
enum spec_op {
sll_op, movc_op, srl_op, sra_op,
sllv_op, srlv_op, srav_op, spec1_unused_op, /* Opcode 0x07 is unused */
sllv_op, pmon_op, srlv_op, srav_op,
jr_op, jalr_op, movz_op, movn_op,
syscall_op, break_op, spim_op, sync_op,
mfhi_op, mthi_op, mflo_op, mtlo_op,
@@ -54,6 +55,28 @@ enum spec_op {
dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
};
/*
* func field of spec2 opcode.
*/
enum spec2_op {
madd_op, maddu_op, mul_op, spec2_3_unused_op,
msub_op, msubu_op, /* more unused ops */
clz_op = 0x20, clo_op,
dclz_op = 0x24, dclo_op,
sdbpp_op = 0x3f
};
/*
* func field of spec3 opcode.
*/
enum spec3_op {
ext_op, dextm_op, dextu_op, dext_op,
ins_op, dinsm_op, dinsu_op, dins_op,
bshfl_op = 0x20,
dbshfl_op = 0x24,
rdhwr_op = 0x3f
};
/*
* rt field of bcond opcodes.
*/
@@ -151,8 +174,8 @@ enum cop1x_func {
* func field for mad opcodes (MIPS IV).
*/
enum mad_func {
madd_op = 0x08, msub_op = 0x0a,
nmadd_op = 0x0c, nmsub_op = 0x0e
madd_fp_op = 0x08, msub_fp_op = 0x0a,
nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
};
/*
include/asm-mips/interrupt.h
+55 -10
View File
@@ -19,7 +19,12 @@ __asm__ (
" .set push \n"
" .set reorder \n"
" .set noat \n"
#ifdef CONFIG_CPU_MIPSR2
#ifdef CONFIG_MIPS_MT_SMTC
" mfc0 $1, $2, 1 # SMTC - clear TCStatus.IXMT \n"
" ori $1, 0x400 \n"
" xori $1, 0x400 \n"
" mtc0 $1, $2, 1 \n"
#elif defined(CONFIG_CPU_MIPSR2)
" ei \n"
#else
" mfc0 $1,$12 \n"
@@ -62,7 +67,12 @@ __asm__ (
" .macro local_irq_disable\n"
" .set push \n"
" .set noat \n"
#ifdef CONFIG_CPU_MIPSR2
#ifdef CONFIG_MIPS_MT_SMTC
" mfc0 $1, $2, 1 \n"
" ori $1, 0x400 \n"
" .set noreorder \n"
" mtc0 $1, $2, 1 \n"
#elif defined(CONFIG_CPU_MIPSR2)
" di \n"
#else
" mfc0 $1,$12 \n"
@@ -88,7 +98,11 @@ __asm__ (
" .macro local_save_flags flags \n"
" .set push \n"
" .set reorder \n"
#ifdef CONFIG_MIPS_MT_SMTC
" mfc0 \\flags, $2, 1 \n"
#else
" mfc0 \\flags, $12 \n"
#endif
" .set pop \n"
" .endm \n");
@@ -102,7 +116,13 @@ __asm__ (
" .set push \n"
" .set reorder \n"
" .set noat \n"
#ifdef CONFIG_CPU_MIPSR2
#ifdef CONFIG_MIPS_MT_SMTC
" mfc0 \\result, $2, 1 \n"
" ori $1, \\result, 0x400 \n"
" .set noreorder \n"
" mtc0 $1, $2, 1 \n"
" andi \\result, \\result, 0x400 \n"
#elif defined(CONFIG_CPU_MIPSR2)
" di \\result \n"
" andi \\result, 1 \n"
#else
@@ -128,7 +148,14 @@ __asm__ (
" .set push \n"
" .set noreorder \n"
" .set noat \n"
#if defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
#ifdef CONFIG_MIPS_MT_SMTC
"mfc0 $1, $2, 1 \n"
"andi \\flags, 0x400 \n"
"ori $1, 0x400 \n"
"xori $1, 0x400 \n"
"or \\flags, $1 \n"
"mtc0 \\flags, $2, 1 \n"
#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
/*
* Slow, but doesn't suffer from a relativly unlikely race
* condition we're having since days 1.
@@ -167,11 +194,29 @@ do { \
: "memory"); \
} while(0)
#define irqs_disabled() \
({ \
unsigned long flags; \
local_save_flags(flags); \
!(flags & 1); \
})
static inline int irqs_disabled(void)
{
#ifdef CONFIG_MIPS_MT_SMTC
/*
* SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU
*/
unsigned long __result;
__asm__ __volatile__(
" .set noreorder \n"
" mfc0 %0, $2, 1 \n"
" andi %0, 0x400 \n"
" slt %0, $0, %0 \n"
" .set reorder \n"
: "=r" (__result));
return __result;
#else
unsigned long flags;
local_save_flags(flags);
return !(flags & 1);
#endif
}
#endif /* _ASM_INTERRUPT_H */
include/asm-mips/irq.h
+30
View File
@@ -11,6 +11,9 @@
#include <linux/config.h>
#include <linux/linkage.h>
#include <asm/mipsmtregs.h>
#include <irq.h>
#ifdef CONFIG_I8259
@@ -26,6 +29,23 @@ struct pt_regs;
extern asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs);
#ifdef CONFIG_MIPS_MT_SMTC
/*
* Clear interrupt mask handling "backstop" if irq_hwmask
* entry so indicates. This implies that the ack() or end()
* functions will take over re-enabling the low-level mask.
* Otherwise it will be done on return from exception.
*/
#define __DO_IRQ_SMTC_HOOK() \
do { \
if (irq_hwmask[irq] & 0x0000ff00) \
write_c0_tccontext(read_c0_tccontext() & \
~(irq_hwmask[irq] & 0x0000ff00)); \
} while (0)
#else
#define __DO_IRQ_SMTC_HOOK() do { } while (0)
#endif
#ifdef CONFIG_PREEMPT
/*
@@ -39,6 +59,7 @@ extern asmlinkage unsigned int do_IRQ(unsigned int irq, struct pt_regs *regs);
#define do_IRQ(irq, regs) \
do { \
irq_enter(); \
__DO_IRQ_SMTC_HOOK(); \
__do_IRQ((irq), (regs)); \
irq_exit(); \
} while (0)
@@ -46,5 +67,14 @@ do { \
#endif
extern void arch_init_irq(void);
extern void spurious_interrupt(struct pt_regs *regs);
#ifdef CONFIG_MIPS_MT_SMTC
struct irqaction;
extern unsigned long irq_hwmask[];
extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
unsigned long hwmask);
#endif /* CONFIG_MIPS_MT_SMTC */
#endif /* _ASM_IRQ_H */
include/asm-mips/kspd.h
+36
View File
@@ -0,0 +1,36 @@
/*
* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
*/
#ifndef _ASM_KSPD_H
#define _ASM_KSPD_H
struct kspd_notifications {
void (*kspd_sp_exit)(int sp_id);
struct list_head list;
};
#ifdef CONFIG_MIPS_APSP_KSPD
extern void kspd_notify(struct kspd_notifications *notify);
#else
static inline void kspd_notify(struct kspd_notifications *notify)
{
}
#endif
#endif
include/asm-mips/mach-generic/ide.h
+44 -2
View File
@@ -104,65 +104,107 @@ static __inline__ unsigned long ide_default_io_base(int index)
#endif
/* MIPS port and memory-mapped I/O string operations. */
static inline void __ide_flush_prologue(void)
{
#ifdef CONFIG_SMP
if (cpu_has_dc_aliases)
preempt_disable();
#endif
}
static inline void __ide_flush_epilogue(void)
{
#ifdef CONFIG_SMP
if (cpu_has_dc_aliases)
preempt_enable();
#endif
}
static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
{
if (cpu_has_dc_aliases) {
unsigned long end = addr + size;
for (; addr < end; addr += PAGE_SIZE)
flush_dcache_page(virt_to_page(addr));
while (addr < end) {
local_flush_data_cache_page((void *)addr);
addr += PAGE_SIZE;
}
}
}
/*
* insw() and gang might be called with interrupts disabled, so we can't
* send IPIs for flushing due to the potencial of deadlocks, see the comment
* above smp_call_function() in arch/mips/kernel/smp.c. We work around the
* problem by disabling preemption so we know we actually perform the flush
* on the processor that actually has the lines to be flushed which hopefully
* is even better for performance anyway.
*/
static inline void __ide_insw(unsigned long port, void *addr,
unsigned int count)
{
__ide_flush_prologue();
insw(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 2);
__ide_flush_epilogue();
}
static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
{
__ide_flush_prologue();
insl(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 4);
__ide_flush_epilogue();
}
static inline void __ide_outsw(unsigned long port, const void *addr,
unsigned long count)
{
__ide_flush_prologue();
outsw(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 2);
__ide_flush_epilogue();
}
static inline void __ide_outsl(unsigned long port, const void *addr,
unsigned long count)
{
__ide_flush_prologue();
outsl(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 4);
__ide_flush_epilogue();
}
static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
{
__ide_flush_prologue();
readsw(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 2);
__ide_flush_epilogue();
}
static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
{
__ide_flush_prologue();
readsl(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 4);
__ide_flush_epilogue();
}
static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
{
__ide_flush_prologue();
writesw(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 2);
__ide_flush_epilogue();
}
static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
{
__ide_flush_prologue();
writesl(port, addr, count);
__ide_flush_dcache_range((unsigned long)addr, count * 4);
__ide_flush_epilogue();
}
/* ide_insw calls insw, not __ide_insw. Why? */
include/asm-mips/mach-jmr3927/ds1742.h
+2 -2
View File
@@ -3,14 +3,14 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 by Ralf Baechle
* Copyright (C) 2003, 06 by Ralf Baechle
*/
#ifndef __ASM_MACH_JMR3927_DS1742_H
#define __ASM_MACH_JMR3927_DS1742_H
#include <asm/jmr3927/jmr3927.h>
#define rtc_read(reg) (jmr3927_nvram_in(addr))
#define rtc_read(reg) (jmr3927_nvram_in(reg))
#define rtc_write(data, reg) (jmr3927_nvram_out((data),(reg)))
#endif /* __ASM_MACH_JMR3927_DS1742_H */
include/asm-mips/mach-mips/param.h
+13
View File
@@ -0,0 +1,13 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 by Ralf Baechle
*/
#ifndef __ASM_MACH_MIPS_PARAM_H
#define __ASM_MACH_MIPS_PARAM_H
#define HZ 100 /* Internal kernel timer frequency */
#endif /* __ASM_MACH_MIPS_PARAM_H */
include/asm-mips/marvell.h
+2
View File
@@ -53,4 +53,6 @@ struct mv_pci_controller {
unsigned long config_vreg;
};
extern void ll_mv64340_irq(struct pt_regs *regs);
#endif /* __ASM_MIPS_MARVELL_H */
include/asm-mips/mips-boards/atlas.h
+17 -1
View File
@@ -33,12 +33,28 @@
#define ATLAS_RTC_ADR_REG 0x1f000800
#define ATLAS_RTC_DAT_REG 0x1f000808
/*
* Atlas interrupt controller register base.
*/
#define ATLAS_ICTRL_REGS_BASE 0x1f000000
/*
* Atlas registers are memory mapped on 64-bit aligned boundaries and
* only word access are allowed.
*/
struct atlas_ictrl_regs {
volatile unsigned int intraw;
int dummy1;
volatile unsigned int intseten;
int dummy2;
volatile unsigned int intrsten;
int dummy3;
volatile unsigned int intenable;
int dummy4;
volatile unsigned int intstatus;
int dummy5;
};
/*
* Atlas UART register base.
*/
include/asm-mips/mips-boards/atlasint.h
-19
View File
@@ -62,23 +62,4 @@
#define ATLASINT_RES31 (ATLASINT_BASE+31)
#define ATLASINT_END (ATLASINT_BASE+31)
/*
* Atlas registers are memory mapped on 64-bit aligned boundaries and
* only word access are allowed.
*/
struct atlas_ictrl_regs {
volatile unsigned int intraw;
int dummy1;
volatile unsigned int intseten;
int dummy2;
volatile unsigned int intrsten;
int dummy3;
volatile unsigned int intenable;
int dummy4;
volatile unsigned int intstatus;
int dummy5;
};
extern void atlasint_init(void);
#endif /* !(_MIPS_ATLASINT_H) */
include/asm-mips/mips-boards/generic.h
+1
View File
@@ -67,6 +67,7 @@
#define MIPS_REVISION_CORID_CORE_FPGA2 7
#define MIPS_REVISION_CORID_CORE_FPGAR2 8
#define MIPS_REVISION_CORID_CORE_FPGA3 9
#define MIPS_REVISION_CORID_CORE_24K 10
/**** Artificial corid defines ****/
/*
include/asm-mips/mips_mt.h
+15
View File
@@ -0,0 +1,15 @@
/*
* Definitions and decalrations for MIPS MT support
* that are common between SMTC, VSMP, and/or AP/SP
* kernel models.
*/
#ifndef __ASM_MIPS_MT_H
#define __ASM_MIPS_MT_H
extern cpumask_t mt_fpu_cpumask;
extern unsigned long mt_fpemul_threshold;
extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value);
extern void mips_mt_set_cpuoptions(void);
#endif /* __ASM_MIPS_MT_H */
include/asm-mips/mipsmtregs.h
+10 -6
View File
@@ -165,7 +165,7 @@
#ifndef __ASSEMBLY__
extern void mips_mt_regdump(void);
extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value);
static inline unsigned int dvpe(void)
{
@@ -234,7 +234,7 @@ static inline void __raw_emt(void)
__asm__ __volatile__(
" .set noreorder \n"
" .set mips32r2 \n"
" emt \n"
" .word 0x41600be1 # emt \n"
" ehb \n"
" .set mips0 \n"
" .set reorder");
@@ -282,8 +282,11 @@ static inline void ehb(void)
\
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" .set mips32r2 \n" \
" mftgpr %0," #rt " \n" \
" # mftgpr $1," #rt " \n" \
" .word 0x41000820 | (" #rt " << 16) \n" \
" move %0, $1 \n" \
" .set pop \n" \
: "=r" (__res)); \
\
@@ -295,9 +298,7 @@ static inline void ehb(void)
unsigned long __res; \
\
__asm__ __volatile__( \
".set noat\n\t" \
"mftr\t%0, " #rt ", " #u ", " #sel "\n\t" \
".set at\n\t" \
" mftr %0, " #rt ", " #u ", " #sel " \n" \
: "=r" (__res)); \
\
__res; \
@@ -364,6 +365,9 @@ do { \
#define read_vpe_c0_ebase() mftc0(15,1)
#define write_vpe_c0_ebase(val) mttc0(15, 1, val)
#define write_vpe_c0_compare(val) mttc0(11, 0, val)
#define read_vpe_c0_badvaddr() mftc0(8, 0)
#define read_vpe_c0_epc() mftc0(14, 0)
#define write_vpe_c0_epc(val) mttc0(14, 0, val)
/* TC */
include/asm-mips/mipsregs.h
+137 -1
View File
@@ -291,7 +291,7 @@
#define ST0_DL (_ULCAST_(1) << 24)
/*
* Enable the MIPS DSP ASE
* Enable the MIPS MDMX and DSP ASEs
*/
#define ST0_MX 0x01000000
@@ -836,6 +836,9 @@ do { \
#define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
#define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
#define read_c0_badvaddr() __read_ulong_c0_register($8, 0)
#define write_c0_badvaddr(val) __write_ulong_c0_register($8, 0, val)
#define read_c0_count() __read_32bit_c0_register($9, 0)
#define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
@@ -858,7 +861,19 @@ do { \
#define write_c0_compare3(val) __write_32bit_c0_register($11, 7, val)
#define read_c0_status() __read_32bit_c0_register($12, 0)
#ifdef CONFIG_MIPS_MT_SMTC
#define write_c0_status(val) \
do { \
__write_32bit_c0_register($12, 0, val); \
__ehb(); \
} while (0)
#else
/*
* Legacy non-SMTC code, which may be hazardous
* but which might not support EHB
*/
#define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
#endif /* CONFIG_MIPS_MT_SMTC */
#define read_c0_cause() __read_32bit_c0_register($13, 0)
#define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
@@ -1001,6 +1016,9 @@ do { \
#define read_c0_taglo() __read_32bit_c0_register($28, 0)
#define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
#define read_c0_dtaglo() __read_32bit_c0_register($28, 2)
#define write_c0_dtaglo(val) __write_32bit_c0_register($28, 2, val)
#define read_c0_taghi() __read_32bit_c0_register($29, 0)
#define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
@@ -1354,6 +1372,11 @@ static inline void tlb_write_random(void)
/*
* Manipulate bits in a c0 register.
*/
#ifndef CONFIG_MIPS_MT_SMTC
/*
* SMTC Linux requires shutting-down microthread scheduling
* during CP0 register read-modify-write sequences.
*/
#define __BUILD_SET_C0(name) \
static inline unsigned int \
set_c0_##name(unsigned int set) \
@@ -1392,6 +1415,119 @@ change_c0_##name(unsigned int change, unsigned int new) \
return res; \
}
#else /* SMTC versions that manage MT scheduling */
#include <asm/interrupt.h>
/*
* This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
* header file recursion.
*/
static inline unsigned int __dmt(void)
{
int res;
__asm__ __volatile__(
" .set push \n"
" .set mips32r2 \n"
" .set noat \n"
" .word 0x41610BC1 # dmt $1 \n"
" ehb \n"
" move %0, $1 \n"
" .set pop \n"
: "=r" (res));
instruction_hazard();
return res;
}
#define __VPECONTROL_TE_SHIFT 15
#define __VPECONTROL_TE (1UL << __VPECONTROL_TE_SHIFT)
#define __EMT_ENABLE __VPECONTROL_TE
static inline void __emt(unsigned int previous)
{
if ((previous & __EMT_ENABLE))
__asm__ __volatile__(
" .set noreorder \n"
" .set mips32r2 \n"
" .word 0x41600be1 # emt \n"
" ehb \n"
" .set mips0 \n"
" .set reorder \n");
}
static inline void __ehb(void)
{
__asm__ __volatile__(
" ehb \n");
}
/*
* Note that local_irq_save/restore affect TC-specific IXMT state,
* not Status.IE as in non-SMTC kernel.
*/
#define __BUILD_SET_C0(name) \
static inline unsigned int \
set_c0_##name(unsigned int set) \
{ \
unsigned int res; \
unsigned int omt; \
unsigned int flags; \
\
local_irq_save(flags); \
omt = __dmt(); \
res = read_c0_##name(); \
res |= set; \
write_c0_##name(res); \
__emt(omt); \
local_irq_restore(flags); \
\
return res; \
} \
\
static inline unsigned int \
clear_c0_##name(unsigned int clear) \
{ \
unsigned int res; \
unsigned int omt; \
unsigned int flags; \
\
local_irq_save(flags); \
omt = __dmt(); \
res = read_c0_##name(); \
res &= ~clear; \
write_c0_##name(res); \
__emt(omt); \
local_irq_restore(flags); \
\
return res; \
} \
\
static inline unsigned int \
change_c0_##name(unsigned int change, unsigned int new) \
{ \
unsigned int res; \
unsigned int omt; \
unsigned int flags; \
\
local_irq_save(flags); \
\
omt = __dmt(); \
res = read_c0_##name(); \
res &= ~change; \
res |= (new & change); \
write_c0_##name(res); \
__emt(omt); \
local_irq_restore(flags); \
\
return res; \
}
#endif
__BUILD_SET_C0(status)
__BUILD_SET_C0(cause)
__BUILD_SET_C0(config)
include/asm-mips/mmu_context.h
+109 -3
View File
@@ -17,6 +17,10 @@
#include <linux/slab.h>
#include <asm/cacheflush.h>
#include <asm/tlbflush.h>
#ifdef CONFIG_MIPS_MT_SMTC
#include <asm/mipsmtregs.h>
#include <asm/smtc.h>
#endif /* SMTC */
/*
* For the fast tlb miss handlers, we keep a per cpu array of pointers
@@ -54,6 +58,14 @@ extern unsigned long pgd_current[];
#define ASID_INC 0x1
#define ASID_MASK 0xfff
/* SMTC/34K debug hack - but maybe we'll keep it */
#elif defined(CONFIG_MIPS_MT_SMTC)
#define ASID_INC 0x1
extern unsigned long smtc_asid_mask;
#define ASID_MASK (smtc_asid_mask)
#define HW_ASID_MASK 0xff
/* End SMTC/34K debug hack */
#else /* FIXME: not correct for R6000 */
#define ASID_INC 0x1
@@ -76,6 +88,8 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
#define ASID_VERSION_MASK ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
#ifndef CONFIG_MIPS_MT_SMTC
/* Normal, classic MIPS get_new_mmu_context */
static inline void
get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
{
@@ -91,6 +105,12 @@ get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
cpu_context(cpu, mm) = asid_cache(cpu) = asid;
}
#else /* CONFIG_MIPS_MT_SMTC */
#define get_new_mmu_context(mm,cpu) smtc_get_new_mmu_context((mm),(cpu))
#endif /* CONFIG_MIPS_MT_SMTC */
/*
* Initialize the context related info for a new mm_struct
* instance.
@@ -111,14 +131,46 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
{
unsigned int cpu = smp_processor_id();
unsigned long flags;
#ifdef CONFIG_MIPS_MT_SMTC
unsigned long oldasid;
unsigned long mtflags;
int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
local_irq_save(flags);
mtflags = dvpe();
#else /* Not SMTC */
local_irq_save(flags);
#endif /* CONFIG_MIPS_MT_SMTC */
/* Check if our ASID is of an older version and thus invalid */
if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
get_new_mmu_context(next, cpu);
#ifdef CONFIG_MIPS_MT_SMTC
/*
* If the EntryHi ASID being replaced happens to be
* the value flagged at ASID recycling time as having
* an extended life, clear the bit showing it being
* in use by this "CPU", and if that's the last bit,
* free up the ASID value for use and flush any old
* instances of it from the TLB.
*/
oldasid = (read_c0_entryhi() & ASID_MASK);
if(smtc_live_asid[mytlb][oldasid]) {
smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
if(smtc_live_asid[mytlb][oldasid] == 0)
smtc_flush_tlb_asid(oldasid);
}
/*
* Tread softly on EntryHi, and so long as we support
* having ASID_MASK smaller than the hardware maximum,
* make sure no "soft" bits become "hard"...
*/
write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
| (cpu_context(cpu, next) & ASID_MASK));
ehb(); /* Make sure it propagates to TCStatus */
evpe(mtflags);
#else
write_c0_entryhi(cpu_context(cpu, next));
#endif /* CONFIG_MIPS_MT_SMTC */
TLBMISS_HANDLER_SETUP_PGD(next->pgd);
/*
@@ -151,12 +203,34 @@ activate_mm(struct mm_struct *prev, struct mm_struct *next)
unsigned long flags;
unsigned int cpu = smp_processor_id();
#ifdef CONFIG_MIPS_MT_SMTC
unsigned long oldasid;
unsigned long mtflags;
int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
#endif /* CONFIG_MIPS_MT_SMTC */
local_irq_save(flags);
/* Unconditionally get a new ASID. */
get_new_mmu_context(next, cpu);
#ifdef CONFIG_MIPS_MT_SMTC
/* See comments for similar code above */
mtflags = dvpe();
oldasid = read_c0_entryhi() & ASID_MASK;
if(smtc_live_asid[mytlb][oldasid]) {
smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
if(smtc_live_asid[mytlb][oldasid] == 0)
smtc_flush_tlb_asid(oldasid);
}
/* See comments for similar code above */
write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
(cpu_context(cpu, next) & ASID_MASK));
ehb(); /* Make sure it propagates to TCStatus */
evpe(mtflags);
#else
write_c0_entryhi(cpu_context(cpu, next));
#endif /* CONFIG_MIPS_MT_SMTC */
TLBMISS_HANDLER_SETUP_PGD(next->pgd);
/* mark mmu ownership change */
@@ -174,17 +248,49 @@ static inline void
drop_mmu_context(struct mm_struct *mm, unsigned cpu)
{
unsigned long flags;
#ifdef CONFIG_MIPS_MT_SMTC
unsigned long oldasid;
/* Can't use spinlock because called from TLB flush within DVPE */
unsigned int prevvpe;
int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
#endif /* CONFIG_MIPS_MT_SMTC */
local_irq_save(flags);
if (cpu_isset(cpu, mm->cpu_vm_mask)) {
get_new_mmu_context(mm, cpu);
#ifdef CONFIG_MIPS_MT_SMTC
/* See comments for similar code above */
prevvpe = dvpe();
oldasid = (read_c0_entryhi() & ASID_MASK);
if(smtc_live_asid[mytlb][oldasid]) {
smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
if(smtc_live_asid[mytlb][oldasid] == 0)
smtc_flush_tlb_asid(oldasid);
}
/* See comments for similar code above */
write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
| cpu_asid(cpu, mm));
ehb(); /* Make sure it propagates to TCStatus */
evpe(prevvpe);
#else /* not CONFIG_MIPS_MT_SMTC */
write_c0_entryhi(cpu_asid(cpu, mm));
#endif /* CONFIG_MIPS_MT_SMTC */
} else {
/* will get a new context next time */
#ifndef CONFIG_MIPS_MT_SMTC
cpu_context(cpu, mm) = 0;
}
#else /* SMTC */
int i;
/* SMTC shares the TLB (and ASIDs) across VPEs */
for (i = 0; i < num_online_cpus(); i++) {
if((smtc_status & SMTC_TLB_SHARED)
|| (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
cpu_context(i, mm) = 0;
}
#endif /* CONFIG_MIPS_MT_SMTC */
}
local_irq_restore(flags);
}
include/asm-mips/page.h
+2
View File
@@ -139,9 +139,11 @@ typedef struct { unsigned long pgprot; } pgprot_t;
#define pfn_to_kaddr(pfn) __va((pfn) << PAGE_SHIFT)
#ifndef CONFIG_SPARSEMEM
#ifndef CONFIG_NEED_MULTIPLE_NODES
#define pfn_valid(pfn) ((pfn) < max_mapnr)
#endif
#endif
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
include/asm-mips/pgtable-32.h
+41 -22
View File
@@ -177,48 +177,67 @@ pfn_pte(unsigned long pfn, pgprot_t prot)
((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
/*
* Bits 0, 1, 2, 9 and 10 are taken, split up the 27 bits of offset
* into this range:
* Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
*/
#define PTE_FILE_MAX_BITS 27
#define PTE_FILE_MAX_BITS 28
#define pte_to_pgoff(_pte) \
((((_pte).pte >> 3) & 0x3f ) + (((_pte).pte >> 11) << 8 ))
#define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) | \
(((_pte).pte >> 2 ) & 0x38) | \
(((_pte).pte >> 10) << 6 ))
#define pgoff_to_pte(off) \
((pte_t) { (((off) & 0x3f) << 3) + (((off) >> 8) << 11) + _PAGE_FILE })
#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) | \
(((off) & 0x38) << 2 ) | \
(((off) >> 6 ) << 10) | \
_PAGE_FILE })
#else
/* Swap entries must have VALID and GLOBAL bits cleared. */
#define __swp_type(x) (((x).val >> 8) & 0x1f)
#define __swp_offset(x) ((x).val >> 13)
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
#define __swp_type(x) (((x).val >> 2) & 0x1f)
#define __swp_offset(x) ((x).val >> 7)
#define __swp_entry(type,offset) \
((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
((swp_entry_t) { ((type) << 2) | ((offset) << 7) })
#else
#define __swp_type(x) (((x).val >> 8) & 0x1f)
#define __swp_offset(x) ((x).val >> 13)
#define __swp_entry(type,offset) \
((swp_entry_t) { ((type) << 8) | ((offset) << 13) })
#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
/*
* Bits 0, 1, 2, 7 and 8 are taken, split up the 27 bits of offset
* into this range:
* Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
*/
#define PTE_FILE_MAX_BITS 27
#define PTE_FILE_MAX_BITS 30
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
/* fixme */
#define pte_to_pgoff(_pte) (((_pte).pte_high >> 6) + ((_pte).pte_high & 0x3f))
#define pgoff_to_pte(off) \
((pte_t){(((off) & 0x3f) + ((off) << 6) + _PAGE_FILE)})
#define pte_to_pgoff(_pte) ((_pte).pte_high >> 2)
#define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 })
#else
#define pte_to_pgoff(_pte) \
((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 ))
/*
* Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
*/
#define PTE_FILE_MAX_BITS 28
#define pgoff_to_pte(off) \
((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE })
#define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) | \
(((_pte).pte >> 2) & 0x8) | \
(((_pte).pte >> 8) << 4))
#define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) | \
(((off) & 0x8) << 2) | \
(((off) >> 4) << 8) | \
_PAGE_FILE })
#endif
#endif
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
#define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val })
#else
#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
#endif
#endif /* _ASM_PGTABLE_32_H */
include/asm-mips/pgtable-64.h
+5 -8
View File
@@ -224,15 +224,12 @@ static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
#define __swp_entry_to_pte(x) ((pte_t) { (x).val })
/*
* Bits 0, 1, 2, 7 and 8 are taken, split up the 32 bits of offset
* into this range:
* Bits 0, 4, 6, and 7 are taken. Let's leave bits 1, 2, 3, and 5 alone to
* make things easier, and only use the upper 56 bits for the page offset...
*/
#define PTE_FILE_MAX_BITS 32
#define PTE_FILE_MAX_BITS 56
#define pte_to_pgoff(_pte) \
((((_pte).pte >> 3) & 0x1f ) + (((_pte).pte >> 9) << 6 ))
#define pgoff_to_pte(off) \
((pte_t) { (((off) & 0x1f) << 3) + (((off) >> 6) << 9) + _PAGE_FILE })
#define pte_to_pgoff(_pte) ((_pte).pte >> 8)
#define pgoff_to_pte(off) ((pte_t) { ((off) << 8) | _PAGE_FILE })
#endif /* _ASM_PGTABLE_64_H */
include/asm-mips/pgtable.h
+61 -42
View File
@@ -70,7 +70,15 @@ extern unsigned long zero_page_mask;
#define ZERO_PAGE(vaddr) \
(virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask)))
#define __HAVE_ARCH_MULTIPLE_ZERO_PAGE
#define __HAVE_ARCH_MOVE_PTE
#define move_pte(pte, prot, old_addr, new_addr) \
({ \
pte_t newpte = (pte); \
if (pte_present(pte) && pfn_valid(pte_pfn(pte)) && \
pte_page(pte) == ZERO_PAGE(old_addr)) \
newpte = mk_pte(ZERO_PAGE(new_addr), (prot)); \
newpte; \
})
extern void paging_init(void);
@@ -82,10 +90,11 @@ extern void paging_init(void);
#define pmd_page(pmd) (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
#define pmd_page_kernel(pmd) pmd_val(pmd)
#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
#define pte_none(pte) (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
#define pte_present(pte) ((pte).pte_low & _PAGE_PRESENT)
static inline void set_pte(pte_t *ptep, pte_t pte)
{
ptep->pte_high = pte.pte_high;
@@ -93,27 +102,35 @@ static inline void set_pte(pte_t *ptep, pte_t pte)
ptep->pte_low = pte.pte_low;
//printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low);
if (pte_val(pte) & _PAGE_GLOBAL) {
if (pte.pte_low & _PAGE_GLOBAL) {
pte_t *buddy = ptep_buddy(ptep);
/*
* Make sure the buddy is global too (if it's !none,
* it better already be global)
*/
if (pte_none(*buddy))
buddy->pte_low |= _PAGE_GLOBAL;
if (pte_none(*buddy)) {
buddy->pte_low |= _PAGE_GLOBAL;
buddy->pte_high |= _PAGE_GLOBAL;
}
}
}
#define set_pte_at(mm,addr,ptep,pteval) set_pte(ptep,pteval)
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
pte_t null = __pte(0);
/* Preserve global status for the pair */
if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL));
else
set_pte_at(mm, addr, ptep, __pte(0));
if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL)
null.pte_low = null.pte_high = _PAGE_GLOBAL;
set_pte_at(mm, addr, ptep, null);
}
#else
#define pte_none(pte) (!(pte_val(pte) & ~_PAGE_GLOBAL))
#define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
/*
* Certain architectures need to do special things when pte's
* within a page table are directly modified. Thus, the following
@@ -174,75 +191,76 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
*/
static inline int pte_user(pte_t pte) { BUG(); return 0; }
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
static inline int pte_read(pte_t pte) { return (pte).pte_low & _PAGE_READ; }
static inline int pte_write(pte_t pte) { return (pte).pte_low & _PAGE_WRITE; }
static inline int pte_dirty(pte_t pte) { return (pte).pte_low & _PAGE_MODIFIED; }
static inline int pte_young(pte_t pte) { return (pte).pte_low & _PAGE_ACCESSED; }
static inline int pte_file(pte_t pte) { return (pte).pte_low & _PAGE_FILE; }
static inline int pte_read(pte_t pte) { return pte.pte_low & _PAGE_READ; }
static inline int pte_write(pte_t pte) { return pte.pte_low & _PAGE_WRITE; }
static inline int pte_dirty(pte_t pte) { return pte.pte_low & _PAGE_MODIFIED; }
static inline int pte_young(pte_t pte) { return pte.pte_low & _PAGE_ACCESSED; }
static inline int pte_file(pte_t pte) { return pte.pte_low & _PAGE_FILE; }
static inline pte_t pte_wrprotect(pte_t pte)
{
(pte).pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
(pte).pte_high &= ~_PAGE_SILENT_WRITE;
pte.pte_low &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
pte.pte_high &= ~_PAGE_SILENT_WRITE;
return pte;
}
static inline pte_t pte_rdprotect(pte_t pte)
{
(pte).pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ);
(pte).pte_high &= ~_PAGE_SILENT_READ;
pte.pte_low &= ~(_PAGE_READ | _PAGE_SILENT_READ);
pte.pte_high &= ~_PAGE_SILENT_READ;
return pte;
}
static inline pte_t pte_mkclean(pte_t pte)
{
(pte).pte_low &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE);
(pte).pte_high &= ~_PAGE_SILENT_WRITE;
pte.pte_low &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
pte.pte_high &= ~_PAGE_SILENT_WRITE;
return pte;
}
static inline pte_t pte_mkold(pte_t pte)
{
(pte).pte_low &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
(pte).pte_high &= ~_PAGE_SILENT_READ;
pte.pte_low &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
pte.pte_high &= ~_PAGE_SILENT_READ;
return pte;
}
static inline pte_t pte_mkwrite(pte_t pte)
{
(pte).pte_low |= _PAGE_WRITE;
if ((pte).pte_low & _PAGE_MODIFIED) {
(pte).pte_low |= _PAGE_SILENT_WRITE;
(pte).pte_high |= _PAGE_SILENT_WRITE;
pte.pte_low |= _PAGE_WRITE;
if (pte.pte_low & _PAGE_MODIFIED) {
pte.pte_low |= _PAGE_SILENT_WRITE;
pte.pte_high |= _PAGE_SILENT_WRITE;
}
return pte;
}
static inline pte_t pte_mkread(pte_t pte)
{
(pte).pte_low |= _PAGE_READ;
if ((pte).pte_low & _PAGE_ACCESSED) {
(pte).pte_low |= _PAGE_SILENT_READ;
(pte).pte_high |= _PAGE_SILENT_READ;
pte.pte_low |= _PAGE_READ;
if (pte.pte_low & _PAGE_ACCESSED) {
pte.pte_low |= _PAGE_SILENT_READ;
pte.pte_high |= _PAGE_SILENT_READ;
}
return pte;
}
static inline pte_t pte_mkdirty(pte_t pte)
{
(pte).pte_low |= _PAGE_MODIFIED;
if ((pte).pte_low & _PAGE_WRITE) {
(pte).pte_low |= _PAGE_SILENT_WRITE;
(pte).pte_high |= _PAGE_SILENT_WRITE;
pte.pte_low |= _PAGE_MODIFIED;
if (pte.pte_low & _PAGE_WRITE) {
pte.pte_low |= _PAGE_SILENT_WRITE;
pte.pte_high |= _PAGE_SILENT_WRITE;
}
return pte;
}
static inline pte_t pte_mkyoung(pte_t pte)
{
(pte).pte_low |= _PAGE_ACCESSED;
if ((pte).pte_low & _PAGE_READ)
(pte).pte_low |= _PAGE_SILENT_READ;
(pte).pte_high |= _PAGE_SILENT_READ;
pte.pte_low |= _PAGE_ACCESSED;
if (pte.pte_low & _PAGE_READ)
pte.pte_low |= _PAGE_SILENT_READ;
pte.pte_high |= _PAGE_SILENT_READ;
return pte;
}
#else
@@ -335,8 +353,9 @@ static inline pgprot_t pgprot_noncached(pgprot_t _prot)
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
pte.pte_low &= _PAGE_CHG_MASK;
pte.pte_low |= pgprot_val(newprot);
pte.pte_low &= _PAGE_CHG_MASK;
pte.pte_high &= ~0x3f;
pte.pte_low |= pgprot_val(newprot);
pte.pte_high |= pgprot_val(newprot) & 0x3f;
return pte;
}
include/asm-mips/processor.h
+22
View File
@@ -12,6 +12,7 @@
#define _ASM_PROCESSOR_H
#include <linux/config.h>
#include <linux/cpumask.h>
#include <linux/threads.h>
#include <asm/cachectl.h>
@@ -107,6 +108,10 @@ struct mips_dsp_state {
#define INIT_DSP {{0,},}
#define INIT_CPUMASK { \
{0,} \
}
typedef struct {
unsigned long seg;
} mm_segment_t;
@@ -129,6 +134,12 @@ struct thread_struct {
/* Saved fpu/fpu emulator stuff. */
union mips_fpu_union fpu;
#ifdef CONFIG_MIPS_MT_FPAFF
/* Emulated instruction count */
unsigned long emulated_fp;
/* Saved per-thread scheduler affinity mask */
cpumask_t user_cpus_allowed;
#endif /* CONFIG_MIPS_MT_FPAFF */
/* Saved state of the DSP ASE, if available. */
struct mips_dsp_state dsp;
@@ -142,6 +153,7 @@ struct thread_struct {
#define MF_LOGADE 2 /* Log address errors to syslog */
#define MF_32BIT_REGS 4 /* also implies 16/32 fprs */
#define MF_32BIT_ADDR 8 /* 32-bit address space (o32/n32) */
#define MF_FPUBOUND 0x10 /* thread bound to FPU-full CPU set */
unsigned long mflags;
unsigned long irix_trampoline; /* Wheee... */
unsigned long irix_oldctx;
@@ -153,6 +165,12 @@ struct thread_struct {
#define MF_N32 MF_32BIT_ADDR
#define MF_N64 0
#ifdef CONFIG_MIPS_MT_FPAFF
#define FPAFF_INIT 0, INIT_CPUMASK,
#else
#define FPAFF_INIT
#endif /* CONFIG_MIPS_MT_FPAFF */
#define INIT_THREAD { \
/* \
* saved main processor registers \
@@ -167,6 +185,10 @@ struct thread_struct {
* saved fpu/fpu emulator stuff \
*/ \
INIT_FPU, \
/* \
* fpu affinity state (null if not FPAFF) \
*/ \
FPAFF_INIT \
/* \
* saved dsp/dsp emulator stuff \
*/ \
include/asm-mips/ptrace.h
+4
View File
@@ -45,6 +45,10 @@ struct pt_regs {
unsigned long cp0_badvaddr;
unsigned long cp0_cause;
unsigned long cp0_epc;
#ifdef CONFIG_MIPS_MT_SMTC
unsigned long cp0_tcstatus;
unsigned long smtc_pad;
#endif /* CONFIG_MIPS_MT_SMTC */
};
/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
include/asm-mips/r4kcache.h
+129 -1
View File
@@ -15,6 +15,7 @@
#include <asm/asm.h>
#include <asm/cacheops.h>
#include <asm/cpu-features.h>
#include <asm/mipsmtregs.h>
/*
* This macro return a properly sign-extended address suitable as base address
@@ -37,16 +38,120 @@
" cache %0, %1 \n" \
" .set pop \n" \
: \
: "i" (op), "m" (*(unsigned char *)(addr)))
: "i" (op), "R" (*(unsigned char *)(addr)))
#ifdef CONFIG_MIPS_MT
/*
* Temporary hacks for SMTC debug. Optionally force single-threaded
* execution during I-cache flushes.
*/
#define PROTECT_CACHE_FLUSHES 1
#ifdef PROTECT_CACHE_FLUSHES
extern int mt_protiflush;
extern int mt_protdflush;
extern void mt_cflush_lockdown(void);
extern void mt_cflush_release(void);
#define BEGIN_MT_IPROT \
unsigned long flags = 0; \
unsigned long mtflags = 0; \
if(mt_protiflush) { \
local_irq_save(flags); \
ehb(); \
mtflags = dvpe(); \
mt_cflush_lockdown(); \
}
#define END_MT_IPROT \
if(mt_protiflush) { \
mt_cflush_release(); \
evpe(mtflags); \
local_irq_restore(flags); \
}
#define BEGIN_MT_DPROT \
unsigned long flags = 0; \
unsigned long mtflags = 0; \
if(mt_protdflush) { \
local_irq_save(flags); \
ehb(); \
mtflags = dvpe(); \
mt_cflush_lockdown(); \
}
#define END_MT_DPROT \
if(mt_protdflush) { \
mt_cflush_release(); \
evpe(mtflags); \
local_irq_restore(flags); \
}
#else
#define BEGIN_MT_IPROT
#define BEGIN_MT_DPROT
#define END_MT_IPROT
#define END_MT_DPROT
#endif /* PROTECT_CACHE_FLUSHES */
#define __iflush_prologue \
unsigned long redundance; \
extern int mt_n_iflushes; \
BEGIN_MT_IPROT \
for (redundance = 0; redundance < mt_n_iflushes; redundance++) {
#define __iflush_epilogue \
END_MT_IPROT \
}
#define __dflush_prologue \
unsigned long redundance; \
extern int mt_n_dflushes; \
BEGIN_MT_DPROT \
for (redundance = 0; redundance < mt_n_dflushes; redundance++) {
#define __dflush_epilogue \
END_MT_DPROT \
}
#define __inv_dflush_prologue __dflush_prologue
#define __inv_dflush_epilogue __dflush_epilogue
#define __sflush_prologue {
#define __sflush_epilogue }
#define __inv_sflush_prologue __sflush_prologue
#define __inv_sflush_epilogue __sflush_epilogue
#else /* CONFIG_MIPS_MT */
#define __iflush_prologue {
#define __iflush_epilogue }
#define __dflush_prologue {
#define __dflush_epilogue }
#define __inv_dflush_prologue {
#define __inv_dflush_epilogue }
#define __sflush_prologue {
#define __sflush_epilogue }
#define __inv_sflush_prologue {
#define __inv_sflush_epilogue }
#endif /* CONFIG_MIPS_MT */
static inline void flush_icache_line_indexed(unsigned long addr)
{
__iflush_prologue
cache_op(Index_Invalidate_I, addr);
__iflush_epilogue
}
static inline void flush_dcache_line_indexed(unsigned long addr)
{
__dflush_prologue
cache_op(Index_Writeback_Inv_D, addr);
__dflush_epilogue
}
static inline void flush_scache_line_indexed(unsigned long addr)
@@ -56,17 +161,23 @@ static inline void flush_scache_line_indexed(unsigned long addr)
static inline void flush_icache_line(unsigned long addr)
{
__iflush_prologue
cache_op(Hit_Invalidate_I, addr);
__iflush_epilogue
}
static inline void flush_dcache_line(unsigned long addr)
{
__dflush_prologue
cache_op(Hit_Writeback_Inv_D, addr);
__dflush_epilogue
}
static inline void invalidate_dcache_line(unsigned long addr)
{
__dflush_prologue
cache_op(Hit_Invalidate_D, addr);
__dflush_epilogue
}
static inline void invalidate_scache_line(unsigned long addr)
@@ -239,9 +350,13 @@ static inline void blast_##pfx##cache##lsize(void) \
current_cpu_data.desc.waybit; \
unsigned long ws, addr; \
\
__##pfx##flush_prologue \
\
for (ws = 0; ws < ws_end; ws += ws_inc) \
for (addr = start; addr < end; addr += lsize * 32) \
cache##lsize##_unroll32(addr|ws,indexop); \
\
__##pfx##flush_epilogue \
} \
\
static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \
@@ -249,10 +364,14 @@ static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \
unsigned long start = page; \
unsigned long end = page + PAGE_SIZE; \
\
__##pfx##flush_prologue \
\
do { \
cache##lsize##_unroll32(start,hitop); \
start += lsize * 32; \
} while (start < end); \
\
__##pfx##flush_epilogue \
} \
\
static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
@@ -265,9 +384,13 @@ static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page)
current_cpu_data.desc.waybit; \
unsigned long ws, addr; \
\
__##pfx##flush_prologue \
\
for (ws = 0; ws < ws_end; ws += ws_inc) \
for (addr = start; addr < end; addr += lsize * 32) \
cache##lsize##_unroll32(addr|ws,indexop); \
\
__##pfx##flush_epilogue \
}
__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
@@ -288,12 +411,17 @@ static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
unsigned long lsize = cpu_##desc##_line_size(); \
unsigned long addr = start & ~(lsize - 1); \
unsigned long aend = (end - 1) & ~(lsize - 1); \
\
__##pfx##flush_prologue \
\
while (1) { \
prot##cache_op(hitop, addr); \
if (addr == aend) \
break; \
addr += lsize; \
} \
\
__##pfx##flush_epilogue \
}
__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
include/asm-mips/rtc.h
+2 -2
View File
@@ -32,7 +32,7 @@ static inline unsigned int get_rtc_time(struct rtc_time *time)
{
unsigned long nowtime;
nowtime = rtc_get_time();
nowtime = rtc_mips_get_time();
to_tm(nowtime, time);
time->tm_year -= 1900;
@@ -47,7 +47,7 @@ static inline int set_rtc_time(struct rtc_time *time)
nowtime = mktime(time->tm_year+1900, time->tm_mon+1,
time->tm_mday, time->tm_hour, time->tm_min,
time->tm_sec);
ret = rtc_set_time(nowtime);
ret = rtc_mips_set_time(nowtime);
return ret;
}
include/asm-mips/rtlx.h
+25 -13
View File
@@ -3,32 +3,46 @@
*
*/
#ifndef _RTLX_H
#define _RTLX_H_
#ifndef __ASM_RTLX_H
#define __ASM_RTLX_H_
#define LX_NODE_BASE 10
#define MIPSCPU_INT_BASE 16
#define MIPS_CPU_RTLX_IRQ 0
#define RTLX_VERSION 1
#define RTLX_VERSION 2
#define RTLX_xID 0x12345600
#define RTLX_ID (RTLX_xID | RTLX_VERSION)
#define RTLX_CHANNELS 8
#define RTLX_BUFFER_SIZE 1024
#define RTLX_CHANNEL_STDIO 0
#define RTLX_CHANNEL_DBG 1
#define RTLX_CHANNEL_SYSIO 2
/*
* lx_state bits
*/
#define RTLX_STATE_OPENED 1UL
extern int rtlx_open(int index, int can_sleep);
extern int rtlx_release(int index);
extern ssize_t rtlx_read(int index, void *buff, size_t count, int user);
extern ssize_t rtlx_write(int index, void *buffer, size_t count, int user);
extern unsigned int rtlx_read_poll(int index, int can_sleep);
extern unsigned int rtlx_write_poll(int index);
enum rtlx_state {
RTLX_STATE_UNUSED,
RTLX_STATE_INITIALISED,
RTLX_STATE_REMOTE_READY,
RTLX_STATE_OPENED
};
#define RTLX_BUFFER_SIZE 1024
/* each channel supports read and write.
linux (vpe0) reads lx_buffer and writes rt_buffer
SP (vpe1) reads rt_buffer and writes lx_buffer
*/
struct rtlx_channel {
unsigned long lx_state;
enum rtlx_state rt_state;
enum rtlx_state lx_state;
int buffer_size;
@@ -38,15 +52,13 @@ struct rtlx_channel {
int lx_write, lx_read;
char *lx_buffer;
void *queues;
};
struct rtlx_info {
unsigned long id;
enum rtlx_state state;
struct rtlx_channel channel[RTLX_CHANNELS];
};
#endif /* _RTLX_H_ */
#endif /* __ASM_RTLX_H_ */
include/asm-mips/serial.h
+6 -6
View File
@@ -77,15 +77,15 @@
#include <asm/it8712.h>
#define ITE_SERIAL_PORT_DEFNS \
{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
.irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
.irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
{ .baud_base = (24000000/(16*13)), .port = (IT8172_PCI_IO_BASE + IT8712_UART1_PORT), \
.irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .type = 0x3 }, \
.irq = IT8172_SERIRQ_4, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
/* Smart Card Reader 0 */ \
{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR0_BASE), \
.irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
.irq = IT8172_SCR0_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
/* Smart Card Reader 1 */ \
{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
.irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
.irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 },
#else
#define ITE_SERIAL_PORT_DEFNS
#endif
@@ -95,10 +95,10 @@
#include <asm/it8172/it8172_int.h>
#define IVR_SERIAL_PORT_DEFNS \
{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_UART_BASE), \
.irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 }, \
.irq = IT8172_UART_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 }, \
/* Smart Card Reader 1 */ \
{ .baud_base = BASE_BAUD, .port = (IT8172_PCI_IO_BASE + IT_SCR1_BASE), \
.irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .type = 0x3 },
.irq = IT8172_SCR1_IRQ, .flags = STD_COM_FLAGS, .port = PORT_16550 },
#else
#define IVR_SERIAL_PORT_DEFNS
#endif
include/asm-mips/sigcontext.h
+8 -2
View File
@@ -55,8 +55,14 @@ struct sigcontext {
struct sigcontext {
unsigned long sc_regs[32];
unsigned long sc_fpregs[32];
unsigned long sc_hi[4];
unsigned long sc_lo[4];
unsigned long sc_mdhi;
unsigned long sc_hi1;
unsigned long sc_hi2;
unsigned long sc_hi3;
unsigned long sc_mdlo;
unsigned long sc_lo1;
unsigned long sc_lo2;
unsigned long sc_lo3;
unsigned long sc_pc;
unsigned int sc_fpc_csr;
unsigned int sc_used_math;
include/asm-mips/smp.h
+2 -3
View File
@@ -48,7 +48,6 @@ extern struct call_data_struct *call_data;
#define SMP_CALL_FUNCTION 0x2
extern cpumask_t phys_cpu_present_map;
extern cpumask_t cpu_online_map;
#define cpu_possible_map phys_cpu_present_map
extern cpumask_t cpu_callout_map;
@@ -86,9 +85,9 @@ extern void prom_init_secondary(void);
extern void plat_smp_setup(void);
/*
* Called after init_IRQ but before __cpu_up.
* Called in smp_prepare_cpus.
*/
extern void prom_prepare_cpus(unsigned int max_cpus);
extern void plat_prepare_cpus(unsigned int max_cpus);
/*
* Last chance for the board code to finish SMP initialization before
include/asm-mips/smtc.h
+55
View File
@@ -0,0 +1,55 @@
#ifndef _ASM_SMTC_MT_H
#define _ASM_SMTC_MT_H
/*
* Definitions for SMTC multitasking on MIPS MT cores
*/
#include <asm/mips_mt.h>
/*
* System-wide SMTC status information
*/
extern unsigned int smtc_status;
#define SMTC_TLB_SHARED 0x00000001
#define SMTC_MTC_ACTIVE 0x00000002
/*
* TLB/ASID Management information
*/
#define MAX_SMTC_TLBS 2
#define MAX_SMTC_ASIDS 256
#if NR_CPUS <= 8
typedef char asiduse;
#else
#if NR_CPUS <= 16
typedef short asiduse;
#else
typedef long asiduse;
#endif
#endif
extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);
void smtc_flush_tlb_asid(unsigned long asid);
extern int mipsmt_build_cpu_map(int startslot);
extern void mipsmt_prepare_cpus(void);
extern void smtc_smp_finish(void);
extern void smtc_boot_secondary(int cpu, struct task_struct *t);
/*
* Sharing the TLB between multiple VPEs means that the
* "random" index selection function is not allowed to
* select the current value of the Index register. To
* avoid additional TLB pressure, the Index registers
* are "parked" with an non-Valid value.
*/
#define PARKED_INDEX ((unsigned int)0x80000000)
#endif /* _ASM_SMTC_MT_H */
include/asm-mips/smtc_ipi.h
+118
View File
@@ -0,0 +1,118 @@
/*
* Definitions used in MIPS MT SMTC "Interprocessor Interrupt" code.
*/
#ifndef __ASM_SMTC_IPI_H
#define __ASM_SMTC_IPI_H
//#define SMTC_IPI_DEBUG
#ifdef SMTC_IPI_DEBUG
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#endif /* SMTC_IPI_DEBUG */
/*
* An IPI "message"
*/
struct smtc_ipi {
struct smtc_ipi *flink;
int type;
void *arg;
int dest;
#ifdef SMTC_IPI_DEBUG
int sender;
long stamp;
#endif /* SMTC_IPI_DEBUG */
};
/*
* Defined IPI Types
*/
#define LINUX_SMP_IPI 1
#define SMTC_CLOCK_TICK 2
/*
* A queue of IPI messages
*/
struct smtc_ipi_q {
struct smtc_ipi *head;
spinlock_t lock;
struct smtc_ipi *tail;
int depth;
};
extern struct smtc_ipi_q IPIQ[NR_CPUS];
extern struct smtc_ipi_q freeIPIq;
static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p)
{
long flags;
spin_lock_irqsave(&q->lock, flags);
if (q->head == NULL)
q->head = q->tail = p;
else
q->tail->flink = p;
p->flink = NULL;
q->tail = p;
q->depth++;
#ifdef SMTC_IPI_DEBUG
p->sender = read_c0_tcbind();
p->stamp = read_c0_count();
#endif /* SMTC_IPI_DEBUG */
spin_unlock_irqrestore(&q->lock, flags);
}
static inline struct smtc_ipi *smtc_ipi_dq(struct smtc_ipi_q *q)
{
struct smtc_ipi *p;
long flags;
spin_lock_irqsave(&q->lock, flags);
if (q->head == NULL)
p = NULL;
else {
p = q->head;
q->head = q->head->flink;
q->depth--;
/* Arguably unnecessary, but leaves queue cleaner */
if (q->head == NULL)
q->tail = NULL;
}
spin_unlock_irqrestore(&q->lock, flags);
return p;
}
static inline void smtc_ipi_req(struct smtc_ipi_q *q, struct smtc_ipi *p)
{
long flags;
spin_lock_irqsave(&q->lock, flags);
if (q->head == NULL) {
q->head = q->tail = p;
p->flink = NULL;
} else {
p->flink = q->head;
q->head = p;
}
q->depth++;
spin_unlock_irqrestore(&q->lock, flags);
}
static inline int smtc_ipi_qdepth(struct smtc_ipi_q *q)
{
long flags;
int retval;
spin_lock_irqsave(&q->lock, flags);
retval = q->depth;
spin_unlock_irqrestore(&q->lock, flags);
return retval;
}
extern void smtc_send_ipi(int cpu, int type, unsigned int action);
#endif /* __ASM_SMTC_IPI_H */
include/asm-mips/smtc_proc.h
+23
View File
@@ -0,0 +1,23 @@
/*
* Definitions for SMTC /proc entries
* Copyright(C) 2005 MIPS Technologies Inc.
*/
#ifndef __ASM_SMTC_PROC_H
#define __ASM_SMTC_PROC_H
/*
* per-"CPU" statistics
*/
struct smtc_cpu_proc {
unsigned long timerints;
unsigned long selfipis;
};
extern struct smtc_cpu_proc smtc_cpu_stats[NR_CPUS];
/* Count of number of recoveries of "stolen" FPU access rights on 34K */
extern atomic_t smtc_fpu_recoveries;
#endif /* __ASM_SMTC_PROC_H */
include/asm-mips/sparsemem.h
+14
View File
@@ -0,0 +1,14 @@
#ifndef _MIPS_SPARSEMEM_H
#define _MIPS_SPARSEMEM_H
#ifdef CONFIG_SPARSEMEM
/*
* SECTION_SIZE_BITS 2^N: how big each section will be
* MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space
*/
#define SECTION_SIZE_BITS 28
#define MAX_PHYSMEM_BITS 35
#endif /* CONFIG_SPARSEMEM */
#endif /* _MIPS_SPARSEMEM_H */
include/asm-mips/stackframe.h
+184 -3
View File
@@ -14,9 +14,14 @@
#include <linux/threads.h>
#include <asm/asm.h>
#include <asm/asmmacro.h>
#include <asm/mipsregs.h>
#include <asm/asm-offsets.h>
#ifdef CONFIG_MIPS_MT_SMTC
#include <asm/mipsmtregs.h>
#endif /* CONFIG_MIPS_MT_SMTC */
.macro SAVE_AT
.set push
.set noat
@@ -57,13 +62,30 @@
#ifdef CONFIG_SMP
.macro get_saved_sp /* SMP variation */
#ifdef CONFIG_32BIT
#ifdef CONFIG_MIPS_MT_SMTC
.set mips32
mfc0 k0, CP0_TCBIND;
.set mips0
lui k1, %hi(kernelsp)
srl k0, k0, 19
/* No need to shift down and up to clear bits 0-1 */
#else
mfc0 k0, CP0_CONTEXT
lui k1, %hi(kernelsp)
srl k0, k0, 23
#endif
addu k1, k0
LONG_L k1, %lo(kernelsp)(k1)
#endif
#ifdef CONFIG_64BIT
#ifdef CONFIG_MIPS_MT_SMTC
.set mips64
mfc0 k0, CP0_TCBIND;
.set mips0
lui k0, %highest(kernelsp)
dsrl k1, 19
/* No need to shift down and up to clear bits 0-2 */
#else
MFC0 k1, CP0_CONTEXT
lui k0, %highest(kernelsp)
dsrl k1, 23
@@ -71,19 +93,30 @@
dsll k0, k0, 16
daddiu k0, %hi(kernelsp)
dsll k0, k0, 16
#endif /* CONFIG_MIPS_MT_SMTC */
daddu k1, k1, k0
LONG_L k1, %lo(kernelsp)(k1)
#endif
#endif /* CONFIG_64BIT */
.endm
.macro set_saved_sp stackp temp temp2
#ifdef CONFIG_32BIT
#ifdef CONFIG_MIPS_MT_SMTC
mfc0 \temp, CP0_TCBIND
srl \temp, 19
#else
mfc0 \temp, CP0_CONTEXT
srl \temp, 23
#endif
#endif
#ifdef CONFIG_64BIT
#ifdef CONFIG_MIPS_MT_SMTC
mfc0 \temp, CP0_TCBIND
dsrl \temp, 19
#else
MFC0 \temp, CP0_CONTEXT
dsrl \temp, 23
#endif
#endif
LONG_S \stackp, kernelsp(\temp)
.endm
@@ -122,10 +155,25 @@
PTR_SUBU sp, k1, PT_SIZE
LONG_S k0, PT_R29(sp)
LONG_S $3, PT_R3(sp)
/*
* You might think that you don't need to save $0,
* but the FPU emulator and gdb remote debug stub
* need it to operate correctly
*/
LONG_S $0, PT_R0(sp)
mfc0 v1, CP0_STATUS
LONG_S $2, PT_R2(sp)
LONG_S v1, PT_STATUS(sp)
#ifdef CONFIG_MIPS_MT_SMTC
/*
* Ideally, these instructions would be shuffled in
* to cover the pipeline delay.
*/
.set mips32
mfc0 v1, CP0_TCSTATUS
.set mips0
LONG_S v1, PT_TCSTATUS(sp)
#endif /* CONFIG_MIPS_MT_SMTC */
LONG_S $4, PT_R4(sp)
mfc0 v1, CP0_CAUSE
LONG_S $5, PT_R5(sp)
@@ -234,14 +282,36 @@
.endm
#else
/*
* For SMTC kernel, global IE should be left set, and interrupts
* controlled exclusively via IXMT.
*/
#ifdef CONFIG_MIPS_MT_SMTC
#define STATMASK 0x1e
#else
#define STATMASK 0x1f
#endif
.macro RESTORE_SOME
.set push
.set reorder
.set noat
#ifdef CONFIG_MIPS_MT_SMTC
.set mips32r2
/*
* This may not really be necessary if ints are already
* inhibited here.
*/
mfc0 v0, CP0_TCSTATUS
ori v0, TCSTATUS_IXMT
mtc0 v0, CP0_TCSTATUS
ehb
DMT 5 # dmt a1
jal mips_ihb
#endif /* CONFIG_MIPS_MT_SMTC */
mfc0 a0, CP0_STATUS
ori a0, 0x1f
xori a0, 0x1f
ori a0, STATMASK
xori a0, STATMASK
mtc0 a0, CP0_STATUS
li v1, 0xff00
and a0, v1
@@ -250,6 +320,26 @@
and v0, v1
or v0, a0
mtc0 v0, CP0_STATUS
#ifdef CONFIG_MIPS_MT_SMTC
/*
* Only after EXL/ERL have been restored to status can we
* restore TCStatus.IXMT.
*/
LONG_L v1, PT_TCSTATUS(sp)
ehb
mfc0 v0, CP0_TCSTATUS
andi v1, TCSTATUS_IXMT
/* We know that TCStatua.IXMT should be set from above */
xori v0, v0, TCSTATUS_IXMT
or v0, v0, v1
mtc0 v0, CP0_TCSTATUS
ehb
andi a1, a1, VPECONTROL_TE
beqz a1, 1f
emt
1:
.set mips0
#endif /* CONFIG_MIPS_MT_SMTC */
LONG_L v1, PT_EPC(sp)
MTC0 v1, CP0_EPC
LONG_L $31, PT_R31(sp)
@@ -302,11 +392,33 @@
* Set cp0 enable bit as sign that we're running on the kernel stack
*/
.macro CLI
#if !defined(CONFIG_MIPS_MT_SMTC)
mfc0 t0, CP0_STATUS
li t1, ST0_CU0 | 0x1f
or t0, t1
xori t0, 0x1f
mtc0 t0, CP0_STATUS
#else /* CONFIG_MIPS_MT_SMTC */
/*
* For SMTC, we need to set privilege
* and disable interrupts only for the
* current TC, using the TCStatus register.
*/
mfc0 t0,CP0_TCSTATUS
/* Fortunately CU 0 is in the same place in both registers */
/* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
li t1, ST0_CU0 | 0x08001c00
or t0,t1
/* Clear TKSU, leave IXMT */
xori t0, 0x00001800
mtc0 t0, CP0_TCSTATUS
ehb
/* We need to leave the global IE bit set, but clear EXL...*/
mfc0 t0, CP0_STATUS
ori t0, ST0_EXL | ST0_ERL
xori t0, ST0_EXL | ST0_ERL
mtc0 t0, CP0_STATUS
#endif /* CONFIG_MIPS_MT_SMTC */
irq_disable_hazard
.endm
@@ -315,11 +427,35 @@
* Set cp0 enable bit as sign that we're running on the kernel stack
*/
.macro STI
#if !defined(CONFIG_MIPS_MT_SMTC)
mfc0 t0, CP0_STATUS
li t1, ST0_CU0 | 0x1f
or t0, t1
xori t0, 0x1e
mtc0 t0, CP0_STATUS
#else /* CONFIG_MIPS_MT_SMTC */
/*
* For SMTC, we need to set privilege
* and enable interrupts only for the
* current TC, using the TCStatus register.
*/
ehb
mfc0 t0,CP0_TCSTATUS
/* Fortunately CU 0 is in the same place in both registers */
/* Set TCU0, TKSU (for later inversion) and IXMT */
li t1, ST0_CU0 | 0x08001c00
or t0,t1
/* Clear TKSU *and* IXMT */
xori t0, 0x00001c00
mtc0 t0, CP0_TCSTATUS
ehb
/* We need to leave the global IE bit set, but clear EXL...*/
mfc0 t0, CP0_STATUS
ori t0, ST0_EXL
xori t0, ST0_EXL
mtc0 t0, CP0_STATUS
/* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
#endif /* CONFIG_MIPS_MT_SMTC */
irq_enable_hazard
.endm
@@ -328,11 +464,56 @@
* Set cp0 enable bit as sign that we're running on the kernel stack
*/
.macro KMODE
#ifdef CONFIG_MIPS_MT_SMTC
/*
* This gets baroque in SMTC. We want to
* protect the non-atomic clearing of EXL
* with DMT/EMT, but we don't want to take
* an interrupt while DMT is still in effect.
*/
/* KMODE gets invoked from both reorder and noreorder code */
.set push
.set mips32r2
.set noreorder
mfc0 v0, CP0_TCSTATUS
andi v1, v0, TCSTATUS_IXMT
ori v0, TCSTATUS_IXMT
mtc0 v0, CP0_TCSTATUS
ehb
DMT 2 # dmt v0
/*
* We don't know a priori if ra is "live"
*/
move t0, ra
jal mips_ihb
nop /* delay slot */
move ra, t0
#endif /* CONFIG_MIPS_MT_SMTC */
mfc0 t0, CP0_STATUS
li t1, ST0_CU0 | 0x1e
or t0, t1
xori t0, 0x1e
mtc0 t0, CP0_STATUS
#ifdef CONFIG_MIPS_MT_SMTC
ehb
andi v0, v0, VPECONTROL_TE
beqz v0, 2f
nop /* delay slot */
emt
2:
mfc0 v0, CP0_TCSTATUS
/* Clear IXMT, then OR in previous value */
ori v0, TCSTATUS_IXMT
xori v0, TCSTATUS_IXMT
or v0, v1, v0
mtc0 v0, CP0_TCSTATUS
/*
* irq_disable_hazard below should expand to EHB
* on 24K/34K CPUS
*/
.set pop
#endif /* CONFIG_MIPS_MT_SMTC */
irq_disable_hazard
.endm
include/asm-mips/system.h
+33 -1
View File
@@ -155,6 +155,37 @@ extern asmlinkage void *resume(void *last, void *next, void *next_ti);
struct task_struct;
#ifdef CONFIG_MIPS_MT_FPAFF
/*
* Handle the scheduler resume end of FPU affinity management. We do this
* inline to try to keep the overhead down. If we have been forced to run on
* a "CPU" with an FPU because of a previous high level of FP computation,
* but did not actually use the FPU during the most recent time-slice (CU1
* isn't set), we undo the restriction on cpus_allowed.
*
* We're not calling set_cpus_allowed() here, because we have no need to
* force prompt migration - we're already switching the current CPU to a
* different thread.
*/
#define switch_to(prev,next,last) \
do { \
if (cpu_has_fpu && \
(prev->thread.mflags & MF_FPUBOUND) && \
(!(KSTK_STATUS(prev) & ST0_CU1))) { \
prev->thread.mflags &= ~MF_FPUBOUND; \
prev->cpus_allowed = prev->thread.user_cpus_allowed; \
} \
if (cpu_has_dsp) \
__save_dsp(prev); \
next->thread.emulated_fp = 0; \
(last) = resume(prev, next, next->thread_info); \
if (cpu_has_dsp) \
__restore_dsp(current); \
} while(0)
#else
#define switch_to(prev,next,last) \
do { \
if (cpu_has_dsp) \
@@ -163,6 +194,7 @@ do { \
if (cpu_has_dsp) \
__restore_dsp(current); \
} while(0)
#endif
/*
* On SMP systems, when the scheduler does migration-cost autodetection,
@@ -440,8 +472,8 @@ static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
extern void set_handler (unsigned long offset, void *addr, unsigned long len);
extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
extern void *set_vi_handler (int n, void *addr);
extern void *set_vi_srs_handler (int n, void *addr, int regset);
extern void *set_except_vector(int n, void *addr);
extern unsigned long ebase;
extern void per_cpu_trap_init(void);
extern NORET_TYPE void die(const char *, struct pt_regs *);
include/asm-mips/unistd.h
+12 -6
View File
@@ -324,16 +324,18 @@
#define __NR_pselect6 (__NR_Linux + 301)
#define __NR_ppoll (__NR_Linux + 302)
#define __NR_unshare (__NR_Linux + 303)
#define __NR_splice (__NR_Linux + 304)
#define __NR_sync_file_range (__NR_Linux + 305)
/*
* Offset of the last Linux o32 flavoured syscall
*/
#define __NR_Linux_syscalls 303
#define __NR_Linux_syscalls 305
#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
#define __NR_O32_Linux 4000
#define __NR_O32_Linux_syscalls 303
#define __NR_O32_Linux_syscalls 305
#if _MIPS_SIM == _MIPS_SIM_ABI64
@@ -604,16 +606,18 @@
#define __NR_pselect6 (__NR_Linux + 260)
#define __NR_ppoll (__NR_Linux + 261)
#define __NR_unshare (__NR_Linux + 262)
#define __NR_splice (__NR_Linux + 263)
#define __NR_sync_file_range (__NR_Linux + 264)
/*
* Offset of the last Linux 64-bit flavoured syscall
*/
#define __NR_Linux_syscalls 262
#define __NR_Linux_syscalls 264
#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
#define __NR_64_Linux 5000
#define __NR_64_Linux_syscalls 262
#define __NR_64_Linux_syscalls 264
#if _MIPS_SIM == _MIPS_SIM_NABI32
@@ -888,16 +892,18 @@
#define __NR_pselect6 (__NR_Linux + 264)
#define __NR_ppoll (__NR_Linux + 265)
#define __NR_unshare (__NR_Linux + 266)
#define __NR_splice (__NR_Linux + 267)
#define __NR_sync_file_range (__NR_Linux + 268)
/*
* Offset of the last N32 flavoured syscall
*/
#define __NR_Linux_syscalls 266
#define __NR_Linux_syscalls 268
#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
#define __NR_N32_Linux 6000
#define __NR_N32_Linux_syscalls 266
#define __NR_N32_Linux_syscalls 268
#ifndef __ASSEMBLY__
include/asm-mips/vpe.h
+37
View File
@@ -0,0 +1,37 @@
/*
* Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
*
* This program is free software; you can distribute it and/or modify it
* under the terms of the GNU General Public License (Version 2) as
* published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
* for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
*/
#ifndef _ASM_VPE_H
#define _ASM_VPE_H
struct vpe_notifications {
void (*start)(int vpe);
void (*stop)(int vpe);
struct list_head list;
};
extern int vpe_notify(int index, struct vpe_notifications *notify);
extern void *vpe_get_shared(int index);
extern int vpe_getuid(int index);
extern int vpe_getgid(int index);
extern char *vpe_getcwd(int index);
#endif /* _ASM_VPE_H */
include/asm-parisc/io.h
+5 -12
View File
@@ -126,24 +126,17 @@ static inline void gsc_writeq(unsigned long long val, unsigned long addr)
extern void __iomem * __ioremap(unsigned long offset, unsigned long size, unsigned long flags);
/* Most machines react poorly to I/O-space being cacheable... Instead let's
* define ioremap() in terms of ioremap_nocache().
*/
extern inline void __iomem * ioremap(unsigned long offset, unsigned long size)
{
return __ioremap(offset, size, 0);
}
/*
* This one maps high address device memory and turns off caching for that area.
* it's useful if some control registers are in such an area and write combining
* or read caching is not desirable:
*/
extern inline void * ioremap_nocache(unsigned long offset, unsigned long size)
{
return __ioremap(offset, size, _PAGE_NO_CACHE /* _PAGE_PCD */);
return __ioremap(offset, size, _PAGE_NO_CACHE);
}
#define ioremap_nocache(off, sz) ioremap((off), (sz))
extern void iounmap(void __iomem *addr);
static inline unsigned char __raw_readb(const volatile void __iomem *addr)
{
return (*(volatile unsigned char __force *) (addr));
include/asm-parisc/page.h
+21 -4
View File
@@ -1,13 +1,30 @@
#ifndef _PARISC_PAGE_H
#define _PARISC_PAGE_H
/* PAGE_SHIFT determines the page size */
#define PAGE_SHIFT 12
#define PAGE_SIZE (1UL << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
#if !defined(__KERNEL__)
/* this is for userspace applications (4k page size) */
# define PAGE_SHIFT 12 /* 4k */
# define PAGE_SIZE (1UL << PAGE_SHIFT)
# define PAGE_MASK (~(PAGE_SIZE-1))
#endif
#ifdef __KERNEL__
#include <linux/config.h>
#if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
# define PAGE_SHIFT 12 /* 4k */
#elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
# define PAGE_SHIFT 14 /* 16k */
#elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
# define PAGE_SHIFT 16 /* 64k */
#else
# error "unknown default kernel page size"
#endif
#define PAGE_SIZE (1UL << PAGE_SHIFT)
#define PAGE_MASK (~(PAGE_SIZE-1))
#ifndef __ASSEMBLY__
#include <asm/types.h>
include/asm-parisc/pgtable.h
+44 -19
View File
@@ -59,16 +59,15 @@
#define ISTACK_SIZE 32768 /* Interrupt Stack Size */
#define ISTACK_ORDER 3
/* This is the size of the initially mapped kernel memory (i.e. currently
* 0 to 1<<23 == 8MB */
/* This is the size of the initially mapped kernel memory */
#ifdef CONFIG_64BIT
#define KERNEL_INITIAL_ORDER 24
#define KERNEL_INITIAL_ORDER 24 /* 0 to 1<<24 = 16MB */
#else
#define KERNEL_INITIAL_ORDER 23
#define KERNEL_INITIAL_ORDER 23 /* 0 to 1<<23 = 8MB */
#endif
#define KERNEL_INITIAL_SIZE (1 << KERNEL_INITIAL_ORDER)
#ifdef CONFIG_64BIT
#if defined(CONFIG_64BIT) && defined(CONFIG_PARISC_PAGE_SIZE_4KB)
#define PT_NLEVELS 3
#define PGD_ORDER 1 /* Number of pages per pgd */
#define PMD_ORDER 1 /* Number of pages per pmd */
@@ -111,11 +110,15 @@
#define MAX_ADDRBITS (PGDIR_SHIFT + BITS_PER_PGD)
#define MAX_ADDRESS (1UL << MAX_ADDRBITS)
#define SPACEID_SHIFT (MAX_ADDRBITS - 32)
#define SPACEID_SHIFT (MAX_ADDRBITS - 32)
/* This calculates the number of initial pages we need for the initial
* page tables */
#define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
#if (KERNEL_INITIAL_ORDER) >= (PMD_SHIFT)
# define PT_INITIAL (1 << (KERNEL_INITIAL_ORDER - PMD_SHIFT))
#else
# define PT_INITIAL (1) /* all initial PTEs fit into one page */
#endif
/*
* pgd entries used up by user/kernel:
@@ -160,6 +163,10 @@ extern void *vmalloc_start;
* to zero */
#define PTE_SHIFT xlate_pabit(_PAGE_USER_BIT)
/* PFN_PTE_SHIFT defines the shift of a PTE value to access the PFN field */
#define PFN_PTE_SHIFT 12
/* this is how many bits may be used by the file functions */
#define PTE_FILE_MAX_BITS (BITS_PER_LONG - PTE_SHIFT)
@@ -188,7 +195,8 @@ extern void *vmalloc_start;
/* The pgd/pmd contains a ptr (in phys addr space); since all pgds/pmds
* are page-aligned, we don't care about the PAGE_OFFSET bits, except
* for a few meta-information bits, so we shift the address to be
* able to effectively address 40-bits of physical address space. */
* able to effectively address 40/42/44-bits of physical address space
* depending on 4k/16k/64k PAGE_SIZE */
#define _PxD_PRESENT_BIT 31
#define _PxD_ATTACHED_BIT 30
#define _PxD_VALID_BIT 29
@@ -198,7 +206,7 @@ extern void *vmalloc_start;
#define PxD_FLAG_VALID (1 << xlate_pabit(_PxD_VALID_BIT))
#define PxD_FLAG_MASK (0xf)
#define PxD_FLAG_SHIFT (4)
#define PxD_VALUE_SHIFT (8)
#define PxD_VALUE_SHIFT (8) /* (PAGE_SHIFT-PxD_FLAG_SHIFT) */
#ifndef __ASSEMBLY__
@@ -246,6 +254,7 @@ extern void *vmalloc_start;
#define __S110 PAGE_RWX
#define __S111 PAGE_RWX
extern pgd_t swapper_pg_dir[]; /* declared in init_task.c */
/* initial page tables for 0-8MB for kernel */
@@ -272,7 +281,7 @@ extern unsigned long *empty_zero_page;
#define pgd_flag(x) (pgd_val(x) & PxD_FLAG_MASK)
#define pgd_address(x) ((unsigned long)(pgd_val(x) &~ PxD_FLAG_MASK) << PxD_VALUE_SHIFT)
#ifdef CONFIG_64BIT
#if PT_NLEVELS == 3
/* The first entry of the permanent pmd is not there if it contains
* the gateway marker */
#define pmd_none(x) (!pmd_val(x) || pmd_flag(x) == PxD_FLAG_ATTACHED)
@@ -282,7 +291,7 @@ extern unsigned long *empty_zero_page;
#define pmd_bad(x) (!(pmd_flag(x) & PxD_FLAG_VALID))
#define pmd_present(x) (pmd_flag(x) & PxD_FLAG_PRESENT)
static inline void pmd_clear(pmd_t *pmd) {
#ifdef CONFIG_64BIT
#if PT_NLEVELS == 3
if (pmd_flag(*pmd) & PxD_FLAG_ATTACHED)
/* This is the entry pointing to the permanent pmd
* attached to the pgd; cannot clear it */
@@ -303,7 +312,7 @@ static inline void pmd_clear(pmd_t *pmd) {
#define pgd_bad(x) (!(pgd_flag(x) & PxD_FLAG_VALID))
#define pgd_present(x) (pgd_flag(x) & PxD_FLAG_PRESENT)
static inline void pgd_clear(pgd_t *pgd) {
#ifdef CONFIG_64BIT
#if PT_NLEVELS == 3
if(pgd_flag(*pgd) & PxD_FLAG_ATTACHED)
/* This is the permanent pmd attached to the pgd; cannot
* free it */
@@ -351,7 +360,7 @@ extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return
({ \
pte_t __pte; \
\
pte_val(__pte) = ((addr)+pgprot_val(pgprot)); \
pte_val(__pte) = ((((addr)>>PAGE_SHIFT)<<PFN_PTE_SHIFT) + pgprot_val(pgprot)); \
\
__pte; \
})
@@ -361,20 +370,16 @@ extern inline pte_t pte_mkwrite(pte_t pte) { pte_val(pte) |= _PAGE_WRITE; return
static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
{
pte_t pte;
pte_val(pte) = (pfn << PAGE_SHIFT) | pgprot_val(pgprot);
pte_val(pte) = (pfn << PFN_PTE_SHIFT) | pgprot_val(pgprot);
return pte;
}
/* This takes a physical page address that is used by the remapping functions */
#define mk_pte_phys(physpage, pgprot) \
({ pte_t __pte; pte_val(__pte) = physpage + pgprot_val(pgprot); __pte; })
extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{ pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot); return pte; }
/* Permanent address of a page. On parisc we don't have highmem. */
#define pte_pfn(x) (pte_val(x) >> PAGE_SHIFT)
#define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT)
#define pte_page(pte) (pfn_to_page(pte_pfn(pte)))
@@ -499,6 +504,26 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
#endif /* !__ASSEMBLY__ */
/* TLB page size encoding - see table 3-1 in parisc20.pdf */
#define _PAGE_SIZE_ENCODING_4K 0
#define _PAGE_SIZE_ENCODING_16K 1
#define _PAGE_SIZE_ENCODING_64K 2
#define _PAGE_SIZE_ENCODING_256K 3
#define _PAGE_SIZE_ENCODING_1M 4
#define _PAGE_SIZE_ENCODING_4M 5
#define _PAGE_SIZE_ENCODING_16M 6
#define _PAGE_SIZE_ENCODING_64M 7
#if defined(CONFIG_PARISC_PAGE_SIZE_4KB)
# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_4K
#elif defined(CONFIG_PARISC_PAGE_SIZE_16KB)
# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_16K
#elif defined(CONFIG_PARISC_PAGE_SIZE_64KB)
# define _PAGE_SIZE_ENCODING_DEFAULT _PAGE_SIZE_ENCODING_64K
#endif
#define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
remap_pfn_range(vma, vaddr, pfn, size, prot)
include/asm-parisc/unistd.h
+7 -1
View File
@@ -780,8 +780,14 @@
#define __NR_readlinkat (__NR_Linux + 285)
#define __NR_fchmodat (__NR_Linux + 286)
#define __NR_faccessat (__NR_Linux + 287)
#define __NR_unshare (__NR_Linux + 288)
#define __NR_set_robust_list (__NR_Linux + 289)
#define __NR_get_robust_list (__NR_Linux + 290)
#define __NR_splice (__NR_Linux + 291)
#define __NR_sync_file_range (__NR_Linux + 292)
#define __NR_tee (__NR_Linux + 293)
#define __NR_Linux_syscalls 288
#define __NR_Linux_syscalls 294
#define HPUX_GATEWAY_ADDR 0xC0000004
#define LINUX_GATEWAY_ADDR 0x100
include/asm-powerpc/cputable.h
+10 -4
View File
@@ -22,6 +22,7 @@
#define PPC_FEATURE_BOOKE 0x00008000
#define PPC_FEATURE_SMT 0x00004000
#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
#define PPC_FEATURE_ARCH_2_05 0x00001000
#ifdef __KERNEL__
#ifndef __ASSEMBLY__
@@ -320,6 +321,11 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
CPU_FTR_MMCRA_SIHV | CPU_FTR_PURR)
#define CPU_FTRS_POWER6 (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
CPU_FTR_PURR | CPU_FTR_CI_LARGE_PAGE)
#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
@@ -331,8 +337,8 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
#ifdef __powerpc64__
#define CPU_FTRS_POSSIBLE \
(CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_CELL | \
CPU_FTR_CI_LARGE_PAGE)
CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
CPU_FTRS_CELL | CPU_FTR_CI_LARGE_PAGE)
#else
enum {
CPU_FTRS_POSSIBLE =
@@ -376,8 +382,8 @@ enum {
#ifdef __powerpc64__
#define CPU_FTRS_ALWAYS \
(CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_CELL & \
CPU_FTRS_POSSIBLE)
CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
CPU_FTRS_CELL & CPU_FTRS_POSSIBLE)
#else
enum {
CPU_FTRS_ALWAYS =
include/asm-powerpc/io.h
+3 -3
View File
@@ -9,6 +9,9 @@
* 2 of the License, or (at your option) any later version.
*/
/* Check of existence of legacy devices */
extern int check_legacy_ioport(unsigned long base_port);
#ifndef CONFIG_PPC64
#include <asm-ppc/io.h>
#else
@@ -437,9 +440,6 @@ out:
#define dma_cache_wback(_start,_size) do { } while (0)
#define dma_cache_wback_inv(_start,_size) do { } while (0)
/* Check of existence of legacy devices */
extern int check_legacy_ioport(unsigned long base_port);
/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
include/asm-powerpc/iommu.h
+4 -3
View File
@@ -70,17 +70,18 @@ extern void iommu_free_table(struct device_node *dn);
extern struct iommu_table *iommu_init_table(struct iommu_table * tbl);
extern int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
struct scatterlist *sglist, int nelems,
struct scatterlist *sglist, int nelems, unsigned long mask,
enum dma_data_direction direction);
extern void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
int nelems, enum dma_data_direction direction);
extern void *iommu_alloc_coherent(struct iommu_table *tbl, size_t size,
dma_addr_t *dma_handle, gfp_t flag);
dma_addr_t *dma_handle, unsigned long mask, gfp_t flag);
extern void iommu_free_coherent(struct iommu_table *tbl, size_t size,
void *vaddr, dma_addr_t dma_handle);
extern dma_addr_t iommu_map_single(struct iommu_table *tbl, void *vaddr,
size_t size, enum dma_data_direction direction);
size_t size, unsigned long mask,
enum dma_data_direction direction);
extern void iommu_unmap_single(struct iommu_table *tbl, dma_addr_t dma_handle,
size_t size, enum dma_data_direction direction);
include/asm-powerpc/irq.h
+7
View File
@@ -54,6 +54,13 @@
*/
extern unsigned int virt_irq_to_real_map[NR_IRQS];
/* The maximum virtual IRQ number that we support. This
* can be set by the platform and will be reduced by the
* value of __irq_offset_value. It defaults to and is
* capped by (NR_IRQS - 1).
*/
extern unsigned int virt_irq_max;
/* Create a mapping for a real_irq if it doesn't already exist.
* Return the virtual irq as a convenience.
*/
include/asm-powerpc/machdep.h
+5 -1
View File
@@ -253,7 +253,11 @@ extern struct machdep_calls *machine_id;
#define __machine_desc __attribute__ ((__section__ (".machine.desc")))
#define define_machine(name) struct machdep_calls mach_##name __machine_desc =
#define define_machine(name) \
extern struct machdep_calls mach_##name; \
EXPORT_SYMBOL(mach_##name); \
struct machdep_calls mach_##name __machine_desc =
#define machine_is(name) \
({ \
extern struct machdep_calls mach_##name \

Some files were not shown because too many files have changed in this diff Show More