Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (130 commits) [ARM] 3856/1: Add clocksource for Intel IXP4xx platforms [ARM] 3855/1: Add generic time support [ARM] 3873/1: S3C24XX: Add irq_chip names [ARM] 3872/1: S3C24XX: Apply consistant tabbing to irq_chips [ARM] 3871/1: S3C24XX: Fix ordering of EINT4..23 [ARM] nommu: confirms the CR_V bit in nommu mode [ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores. [ARM] 3870/1: AT91: Start removing static memory mappings [ARM] 3869/1: AT91: NAND support for DK and KB9202 boards [ARM] 3868/1: AT91 hardware header update [ARM] 3867/1: AT91 GPIO update [ARM] 3866/1: AT91 clock update [ARM] 3865/1: AT91RM9200 header updates [ARM] 3862/2: S3C2410 - add basic power management support for AML M5900 series [ARM] kthread: switch arch/arm/kernel/apm.c [ARM] Off-by-one in arch/arm/common/icst* [ARM] 3864/1: Refactore sharpsl_pm [ARM] 3863/1: Add Locomo SPI Device [ARM] 3847/2: Convert LOMOMO to use struct device for GPIOs [ARM] Use CPU_CACHE_* where possible in asm/cacheflush.h ...
This commit is contained in:
Linus Torvalds
@@ -19,66 +19,79 @@
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/*
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* Peripheral identifiers/interrupts.
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*/
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#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
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#define AT91_ID_SYS 1 /* System Peripheral */
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#define AT91_ID_PIOA 2 /* Parallel IO Controller A */
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#define AT91_ID_PIOB 3 /* Parallel IO Controller B */
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#define AT91_ID_PIOC 4 /* Parallel IO Controller C */
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#define AT91_ID_PIOD 5 /* Parallel IO Controller D */
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#define AT91_ID_US0 6 /* USART 0 */
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#define AT91_ID_US1 7 /* USART 1 */
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#define AT91_ID_US2 8 /* USART 2 */
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#define AT91_ID_US3 9 /* USART 3 */
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#define AT91_ID_MCI 10 /* Multimedia Card Interface */
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#define AT91_ID_UDP 11 /* USB Device Port */
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#define AT91_ID_TWI 12 /* Two-Wire Interface */
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#define AT91_ID_SPI 13 /* Serial Peripheral Interface */
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#define AT91_ID_SSC0 14 /* Serial Synchronous Controller 0 */
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#define AT91_ID_SSC1 15 /* Serial Synchronous Controller 1 */
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#define AT91_ID_SSC2 16 /* Serial Synchronous Controller 2 */
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#define AT91_ID_TC0 17 /* Timer Counter 0 */
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#define AT91_ID_TC1 18 /* Timer Counter 1 */
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#define AT91_ID_TC2 19 /* Timer Counter 2 */
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#define AT91_ID_TC3 20 /* Timer Counter 3 */
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#define AT91_ID_TC4 21 /* Timer Counter 4 */
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#define AT91_ID_TC5 22 /* Timer Counter 5 */
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#define AT91_ID_UHP 23 /* USB Host port */
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#define AT91_ID_EMAC 24 /* Ethernet MAC */
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#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
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#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
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#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
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#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
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#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
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#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
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#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
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#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
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#define AT91_ID_SYS 1 /* System Peripheral */
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#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
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#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
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#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
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#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */
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#define AT91RM9200_ID_US0 6 /* USART 0 */
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#define AT91RM9200_ID_US1 7 /* USART 1 */
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#define AT91RM9200_ID_US2 8 /* USART 2 */
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#define AT91RM9200_ID_US3 9 /* USART 3 */
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#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */
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#define AT91RM9200_ID_UDP 11 /* USB Device Port */
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#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */
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#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */
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#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */
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#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */
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#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */
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#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */
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#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */
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#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */
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#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */
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#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */
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#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */
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#define AT91RM9200_ID_UHP 23 /* USB Host port */
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#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */
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#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
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#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
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#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
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#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
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#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
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#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
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#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
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/*
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* Peripheral physical base addresses.
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*/
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#define AT91_BASE_TCB0 0xfffa0000
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#define AT91_BASE_TC0 0xfffa0000
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#define AT91_BASE_TC1 0xfffa0040
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#define AT91_BASE_TC2 0xfffa0080
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#define AT91_BASE_TCB1 0xfffa4000
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#define AT91_BASE_TC3 0xfffa4000
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#define AT91_BASE_TC4 0xfffa4040
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#define AT91_BASE_TC5 0xfffa4080
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#define AT91_BASE_UDP 0xfffb0000
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#define AT91_BASE_MCI 0xfffb4000
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#define AT91_BASE_TWI 0xfffb8000
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#define AT91_BASE_EMAC 0xfffbc000
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#define AT91_BASE_US0 0xfffc0000
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#define AT91_BASE_US1 0xfffc4000
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#define AT91_BASE_US2 0xfffc8000
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#define AT91_BASE_US3 0xfffcc000
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#define AT91_BASE_SSC0 0xfffd0000
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#define AT91_BASE_SSC1 0xfffd4000
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#define AT91_BASE_SSC2 0xfffd8000
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#define AT91_BASE_SPI 0xfffe0000
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#define AT91RM9200_BASE_TCB0 0xfffa0000
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#define AT91RM9200_BASE_TC0 0xfffa0000
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#define AT91RM9200_BASE_TC1 0xfffa0040
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#define AT91RM9200_BASE_TC2 0xfffa0080
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#define AT91RM9200_BASE_TCB1 0xfffa4000
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#define AT91RM9200_BASE_TC3 0xfffa4000
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#define AT91RM9200_BASE_TC4 0xfffa4040
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#define AT91RM9200_BASE_TC5 0xfffa4080
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#define AT91RM9200_BASE_UDP 0xfffb0000
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#define AT91RM9200_BASE_MCI 0xfffb4000
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#define AT91RM9200_BASE_TWI 0xfffb8000
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#define AT91RM9200_BASE_EMAC 0xfffbc000
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#define AT91RM9200_BASE_US0 0xfffc0000
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#define AT91RM9200_BASE_US1 0xfffc4000
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#define AT91RM9200_BASE_US2 0xfffc8000
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#define AT91RM9200_BASE_US3 0xfffcc000
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#define AT91RM9200_BASE_SSC0 0xfffd0000
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#define AT91RM9200_BASE_SSC1 0xfffd4000
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#define AT91RM9200_BASE_SSC2 0xfffd8000
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#define AT91RM9200_BASE_SPI 0xfffe0000
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#define AT91_BASE_SYS 0xfffff000
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/*
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* Internal Memory.
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*/
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#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */
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#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
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#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */
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#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
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#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */
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#if 0
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/*
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* PIO pin definitions (peripheral A/B multiplexing).
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*/
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@@ -257,5 +270,6 @@
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#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */
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#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */
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#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */
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#endif
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#endif
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@@ -80,6 +80,9 @@
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#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
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#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
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#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
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#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
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#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
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/*
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* PIO Controllers.
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@@ -0,0 +1,57 @@
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/*
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* include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Two-wire Interface (TWI) registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91RM9200_TWI_H
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#define AT91RM9200_TWI_H
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#define AT91_TWI_CR 0x00 /* Control Register */
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#define AT91_TWI_START (1 << 0) /* Send a Start Condition */
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#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */
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#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */
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#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */
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#define AT91_TWI_SWRST (1 << 7) /* Software Reset */
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#define AT91_TWI_MMR 0x04 /* Master Mode Register */
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#define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */
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#define AT91_TWI_IADRSZ_NO (0 << 8)
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#define AT91_TWI_IADRSZ_1 (1 << 8)
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#define AT91_TWI_IADRSZ_2 (2 << 8)
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#define AT91_TWI_IADRSZ_3 (3 << 8)
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#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */
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#define AT91_TWI_DADR (0x7f << 16) /* Device Address */
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#define AT91_TWI_IADR 0x0c /* Internal Address Register */
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#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */
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#define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */
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#define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */
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#define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */
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#define AT91_TWI_SR 0x20 /* Status Register */
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#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
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#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
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#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
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#define AT91_TWI_OVRE (1 << 6) /* Overrun Error */
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#define AT91_TWI_UNRE (1 << 7) /* Underrun Error */
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#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
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#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
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#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */
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#define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */
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#define AT91_TWI_RHR 0x30 /* Receive Holding Register */
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#define AT91_TWI_THR 0x34 /* Transmit Holding Register */
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#endif
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@@ -17,10 +17,9 @@
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#define PIN_BASE NR_AIC_IRQS
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#define PQFP_GPIO_BANKS 3 /* PQFP package has 3 banks */
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#define BGA_GPIO_BANKS 4 /* BGA package has 4 banks */
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#define MAX_GPIO_BANKS 4
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/* these pin numbers double as IRQ numbers, like AT91_ID_* values */
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/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
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#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
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#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
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@@ -180,17 +179,18 @@
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#ifndef __ASSEMBLY__
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/* setup setup routines, called from board init or driver probe() */
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extern int at91_set_A_periph(unsigned pin, int use_pullup);
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extern int at91_set_B_periph(unsigned pin, int use_pullup);
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extern int at91_set_gpio_input(unsigned pin, int use_pullup);
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extern int at91_set_gpio_output(unsigned pin, int value);
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extern int at91_set_deglitch(unsigned pin, int is_on);
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extern int at91_set_multi_drive(unsigned pin, int is_on);
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extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
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extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
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extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
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extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
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extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
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extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
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/* callable at any time */
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extern int at91_set_gpio_value(unsigned pin, int value);
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extern int at91_get_gpio_value(unsigned pin);
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/* callable only from core power-management code */
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extern void at91_gpio_suspend(void);
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extern void at91_gpio_resume(void);
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#endif
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@@ -34,27 +34,14 @@
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* Virtual to Physical Address mapping for IO devices.
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*/
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#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
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#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91_BASE_SPI)
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#define AT91_VA_BASE_SSC2 AT91_IO_P2V(AT91_BASE_SSC2)
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#define AT91_VA_BASE_SSC1 AT91_IO_P2V(AT91_BASE_SSC1)
|
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#define AT91_VA_BASE_SSC0 AT91_IO_P2V(AT91_BASE_SSC0)
|
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#define AT91_VA_BASE_US3 AT91_IO_P2V(AT91_BASE_US3)
|
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#define AT91_VA_BASE_US2 AT91_IO_P2V(AT91_BASE_US2)
|
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#define AT91_VA_BASE_US1 AT91_IO_P2V(AT91_BASE_US1)
|
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#define AT91_VA_BASE_US0 AT91_IO_P2V(AT91_BASE_US0)
|
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#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91_BASE_EMAC)
|
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#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91_BASE_TWI)
|
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#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91_BASE_MCI)
|
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#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91_BASE_UDP)
|
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#define AT91_VA_BASE_TCB1 AT91_IO_P2V(AT91_BASE_TCB1)
|
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#define AT91_VA_BASE_TCB0 AT91_IO_P2V(AT91_BASE_TCB0)
|
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|
||||
/* Internal SRAM */
|
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#define AT91_SRAM_BASE 0x00200000 /* Internal SRAM base address */
|
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#define AT91_SRAM_SIZE 0x00004000 /* Internal SRAM SIZE (16Kb) */
|
||||
#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91RM9200_BASE_SPI)
|
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#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC)
|
||||
#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91RM9200_BASE_TWI)
|
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#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91RM9200_BASE_MCI)
|
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#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91RM9200_BASE_UDP)
|
||||
|
||||
/* Internal SRAM is mapped below the IO devices */
|
||||
#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_SIZE)
|
||||
#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE)
|
||||
|
||||
/* Serial ports */
|
||||
#define AT91_NR_UART 5 /* 4 USART3's and one DBGU port */
|
||||
@@ -71,9 +58,6 @@
|
||||
/* Compact Flash */
|
||||
#define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */
|
||||
|
||||
/* Multi-Master Memory controller */
|
||||
#define AT91_UHP_BASE 0x00300000 /* USB Host controller */
|
||||
|
||||
/* Clocks */
|
||||
#define AT91_SLOW_CLOCK 32768 /* slow clock */
|
||||
|
||||
|
||||
@@ -32,7 +32,7 @@
|
||||
|
||||
|
||||
/*
|
||||
* IRQ interrupt symbols are the AT91_ID_* symbols in at91rm9200.h
|
||||
* IRQ interrupt symbols are the AT91xxx_ID_* symbols
|
||||
* for IRQs handled directly through the AIC, or else the AT91_PIN_*
|
||||
* symbols in gpio.h for ones handled indirectly as GPIOs.
|
||||
* We make provision for 4 banks of GPIO.
|
||||
|
||||
@@ -0,0 +1,20 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop32x/debug-macro.S
|
||||
*
|
||||
* Debugging macro include header
|
||||
*
|
||||
* Copyright (C) 1994-1999 Russell King
|
||||
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
.macro addruart, rx
|
||||
mov \rx, #0xfe000000 @ physical as well as virtual
|
||||
orr \rx, \rx, #0x00800000 @ location of the UART
|
||||
.endm
|
||||
|
||||
#define UART_SHIFT 0
|
||||
#include <asm/hardware/debug-8250.S>
|
||||
@@ -1,7 +1,7 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-iop3xx/dma.h
|
||||
* include/asm-arm/arch-iop32x/dma.h
|
||||
*
|
||||
* Copyright (C) 2004 Intel Corp.
|
||||
* Copyright (C) 2004 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop32x/entry-macro.S
|
||||
*
|
||||
* Low-level IRQ helper macros for IOP32x-based platforms
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
#include <asm/arch/iop32x.h>
|
||||
|
||||
.macro disable_fiq
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
ldr \base, =IOP3XX_REG_ADDR(0x07D8)
|
||||
ldr \irqstat, [\base] @ Read IINTSRC
|
||||
cmp \irqstat, #0
|
||||
clzne \irqnr, \irqstat
|
||||
rsbne \irqnr, \irqnr, #31
|
||||
.endm
|
||||
@@ -0,0 +1,13 @@
|
||||
/*
|
||||
* include/asm/arch-iop32x/glantank.h
|
||||
*
|
||||
* IO-Data GLAN Tank board registers
|
||||
*/
|
||||
|
||||
#ifndef __GLANTANK_H
|
||||
#define __GLANTANK_H
|
||||
|
||||
#define GLANTANK_UART 0xfe800000 /* UART */
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop32x/hardware.h
|
||||
*/
|
||||
|
||||
#ifndef __HARDWARE_H
|
||||
#define __HARDWARE_H
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
/*
|
||||
* Note about PCI IO space mappings
|
||||
*
|
||||
* To make IO space accesses efficient, we store virtual addresses in
|
||||
* the IO resources.
|
||||
*
|
||||
* The PCI IO space is located at virtual 0xfe000000 from physical
|
||||
* 0x90000000. The PCI BARs must be programmed with physical addresses,
|
||||
* but when we read them, we convert them to virtual addresses. See
|
||||
* arch/arm/plat-iop/pci.c.
|
||||
*/
|
||||
#define pcibios_assign_all_busses() 1
|
||||
#define PCIBIOS_MIN_IO 0x00000000
|
||||
#define PCIBIOS_MIN_MEM 0x00000000
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
void iop32x_init_irq(void);
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Generic chipset bits
|
||||
*/
|
||||
#include "iop32x.h"
|
||||
|
||||
/*
|
||||
* Board specific bits
|
||||
*/
|
||||
#include "glantank.h"
|
||||
#include "iq80321.h"
|
||||
#include "iq31244.h"
|
||||
#include "n2100.h"
|
||||
|
||||
|
||||
#endif
|
||||
@@ -1,21 +1,22 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-iop3xx/io.h
|
||||
* include/asm-arm/arch-iop32x/io.h
|
||||
*
|
||||
* Copyright (C) 2001 MontaVista Software, Inc.
|
||||
* Copyright (C) 2001 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_ARCH_IO_H
|
||||
#define __ASM_ARM_ARCH_IO_H
|
||||
#ifndef __IO_H
|
||||
#define __IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
|
||||
#define __io(p) ((void __iomem *)(p))
|
||||
#define __mem_pci(a) (a)
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,28 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop32x/iop32x.h
|
||||
*
|
||||
* Intel IOP32X Chip definitions
|
||||
*
|
||||
* Author: Rory Bolt <rorybolt@pacbell.net>
|
||||
* Copyright (C) 2002 Rory Bolt
|
||||
* Copyright (C) 2004 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __IOP32X_H
|
||||
#define __IOP32X_H
|
||||
|
||||
/*
|
||||
* Peripherals that are shared between the iop32x and iop33x but
|
||||
* located at different addresses.
|
||||
*/
|
||||
#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07c0 + (reg))
|
||||
#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07e0 + (reg))
|
||||
|
||||
#include <asm/hardware/iop3xx.h>
|
||||
|
||||
|
||||
#endif
|
||||
@@ -1,15 +1,11 @@
|
||||
/*
|
||||
* linux/include/asm/arch-iop3xx/iq31244.h
|
||||
* include/asm-arm/arch-iop32x/iq31244.h
|
||||
*
|
||||
* Intel IQ31244 evaluation board registers
|
||||
*/
|
||||
|
||||
#ifndef _IQ31244_H_
|
||||
#define _IQ31244_H_
|
||||
|
||||
#define IQ31244_FLASHBASE 0xf0000000 /* Flash */
|
||||
#define IQ31244_FLASHSIZE 0x00800000
|
||||
#define IQ31244_FLASHWIDTH 2
|
||||
#ifndef __IQ31244_H
|
||||
#define __IQ31244_H
|
||||
|
||||
#define IQ31244_UART 0xfe800000 /* UART #1 */
|
||||
#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */
|
||||
@@ -17,8 +13,5 @@
|
||||
#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
|
||||
#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void iq31244_map_io(void);
|
||||
#endif
|
||||
|
||||
#endif // _IQ31244_H_
|
||||
#endif
|
||||
@@ -1,15 +1,11 @@
|
||||
/*
|
||||
* linux/include/asm/arch-iop3xx/iq80321.h
|
||||
* include/asm-arm/arch-iop32x/iq80321.h
|
||||
*
|
||||
* Intel IQ80321 evaluation board registers
|
||||
*/
|
||||
|
||||
#ifndef _IQ80321_H_
|
||||
#define _IQ80321_H_
|
||||
|
||||
#define IQ80321_FLASHBASE 0xf0000000 /* Flash */
|
||||
#define IQ80321_FLASHSIZE 0x00800000
|
||||
#define IQ80321_FLASHWIDTH 1
|
||||
#ifndef __IQ80321_H
|
||||
#define __IQ80321_H
|
||||
|
||||
#define IQ80321_UART 0xfe800000 /* UART #1 */
|
||||
#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */
|
||||
@@ -17,8 +13,5 @@
|
||||
#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
|
||||
#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void iq80321_map_io(void);
|
||||
#endif
|
||||
|
||||
#endif // _IQ80321_H_
|
||||
#endif
|
||||
@@ -0,0 +1,50 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop32x/irqs.h
|
||||
*
|
||||
* Author: Rory Bolt <rorybolt@pacbell.net>
|
||||
* Copyright: (C) 2002 Rory Bolt
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __IRQS_H
|
||||
#define __IRQS_H
|
||||
|
||||
/*
|
||||
* IOP80321 chipset interrupts
|
||||
*/
|
||||
#define IRQ_IOP32X_DMA0_EOT 0
|
||||
#define IRQ_IOP32X_DMA0_EOC 1
|
||||
#define IRQ_IOP32X_DMA1_EOT 2
|
||||
#define IRQ_IOP32X_DMA1_EOC 3
|
||||
#define IRQ_IOP32X_AA_EOT 6
|
||||
#define IRQ_IOP32X_AA_EOC 7
|
||||
#define IRQ_IOP32X_CORE_PMON 8
|
||||
#define IRQ_IOP32X_TIMER0 9
|
||||
#define IRQ_IOP32X_TIMER1 10
|
||||
#define IRQ_IOP32X_I2C_0 11
|
||||
#define IRQ_IOP32X_I2C_1 12
|
||||
#define IRQ_IOP32X_MESSAGING 13
|
||||
#define IRQ_IOP32X_ATU_BIST 14
|
||||
#define IRQ_IOP32X_PERFMON 15
|
||||
#define IRQ_IOP32X_CORE_PMU 16
|
||||
#define IRQ_IOP32X_BIU_ERR 17
|
||||
#define IRQ_IOP32X_ATU_ERR 18
|
||||
#define IRQ_IOP32X_MCU_ERR 19
|
||||
#define IRQ_IOP32X_DMA0_ERR 20
|
||||
#define IRQ_IOP32X_DMA1_ERR 21
|
||||
#define IRQ_IOP32X_AA_ERR 23
|
||||
#define IRQ_IOP32X_MSG_ERR 24
|
||||
#define IRQ_IOP32X_SSP 25
|
||||
#define IRQ_IOP32X_XINT0 27
|
||||
#define IRQ_IOP32X_XINT1 28
|
||||
#define IRQ_IOP32X_XINT2 29
|
||||
#define IRQ_IOP32X_XINT3 30
|
||||
#define IRQ_IOP32X_HPI 31
|
||||
|
||||
#define NR_IRQS 32
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop32x/memory.h
|
||||
*/
|
||||
|
||||
#ifndef __MEMORY_H
|
||||
#define __MEMORY_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
/*
|
||||
* Physical DRAM offset.
|
||||
*/
|
||||
#define PHYS_OFFSET UL(0xa0000000)
|
||||
|
||||
/*
|
||||
* Virtual view <-> PCI DMA view memory address translations
|
||||
* virt_to_bus: Used to translate the virtual address to an
|
||||
* address suitable to be passed to set_dma_addr
|
||||
* bus_to_virt: Used to convert an address for DMA operations
|
||||
* to an address that the kernel can use.
|
||||
*/
|
||||
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
|
||||
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* include/asm/arch-iop32x/n2100.h
|
||||
*
|
||||
* Thecus N2100 board registers
|
||||
*/
|
||||
|
||||
#ifndef __N2100_H
|
||||
#define __N2100_H
|
||||
|
||||
#define N2100_UART 0xfe800000 /* UART */
|
||||
|
||||
#define N2100_COPY_BUTTON IOP3XX_GPIO_LINE(0)
|
||||
#define N2100_PCA9532_RESET IOP3XX_GPIO_LINE(2)
|
||||
#define N2100_RESET_BUTTON IOP3XX_GPIO_LINE(3)
|
||||
#define N2100_HARDWARE_RESET IOP3XX_GPIO_LINE(4)
|
||||
#define N2100_POWER_BUTTON IOP3XX_GPIO_LINE(5)
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop32x/system.h
|
||||
*
|
||||
* Copyright (C) 2001 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static inline void arch_reset(char mode)
|
||||
{
|
||||
local_irq_disable();
|
||||
|
||||
if (machine_is_n2100()) {
|
||||
gpio_line_set(N2100_HARDWARE_RESET, GPIO_LOW);
|
||||
gpio_line_config(N2100_HARDWARE_RESET, GPIO_OUT);
|
||||
while (1)
|
||||
;
|
||||
}
|
||||
|
||||
*IOP3XX_PCSR = 0x30;
|
||||
|
||||
/* Jump into ROM at address 0 */
|
||||
cpu_reset(0);
|
||||
}
|
||||
@@ -0,0 +1,9 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop32x/timex.h
|
||||
*
|
||||
* IOP32x architecture timex specifications
|
||||
*/
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define CLOCK_TICK_RATE (100 * HZ)
|
||||
@@ -0,0 +1,39 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop32x/uncompress.h
|
||||
*/
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <linux/serial_reg.h>
|
||||
#include <asm/hardware.h>
|
||||
|
||||
static volatile u8 *uart_base;
|
||||
|
||||
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
|
||||
|
||||
static inline void putc(char c)
|
||||
{
|
||||
while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
|
||||
barrier();
|
||||
uart_base[UART_TX] = c;
|
||||
}
|
||||
|
||||
static inline void flush(void)
|
||||
{
|
||||
}
|
||||
|
||||
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
|
||||
{
|
||||
if (machine_is_iq80321())
|
||||
uart_base = (volatile u8 *)IQ80321_UART;
|
||||
else if (machine_is_iq31244())
|
||||
uart_base = (volatile u8 *)IQ31244_UART;
|
||||
else
|
||||
uart_base = (volatile u8 *)0xfe800000;
|
||||
}
|
||||
|
||||
/*
|
||||
* nothing to do
|
||||
*/
|
||||
#define arch_decomp_setup() __arch_decomp_setup(arch_id)
|
||||
#define arch_decomp_wdog()
|
||||
@@ -0,0 +1,5 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop32x/vmalloc.h
|
||||
*/
|
||||
|
||||
#define VMALLOC_END 0xfe000000
|
||||
@@ -0,0 +1,24 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop33x/debug-macro.S
|
||||
*
|
||||
* Debugging macro include header
|
||||
*
|
||||
* Copyright (C) 1994-1999 Russell King
|
||||
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
.macro addruart, rx
|
||||
mrc p15, 0, \rx, c1, c0
|
||||
tst \rx, #1 @ mmu enabled?
|
||||
moveq \rx, #0xff000000 @ physical
|
||||
movne \rx, #0xfe000000 @ virtual
|
||||
orr \rx, \rx, #0x00ff0000
|
||||
orr \rx, \rx, #0x0000f700
|
||||
.endm
|
||||
|
||||
#define UART_SHIFT 2
|
||||
#include <asm/hardware/debug-8250.S>
|
||||
@@ -0,0 +1,9 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop33x/dma.h
|
||||
*
|
||||
* Copyright (C) 2004 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop33x/entry-macro.S
|
||||
*
|
||||
* Low-level IRQ helper macros for IOP33x-based platforms
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
#include <asm/arch/iop33x.h>
|
||||
|
||||
.macro disable_fiq
|
||||
.endm
|
||||
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
ldr \base, =IOP3XX_REG_ADDR(0x07C8)
|
||||
ldr \irqstat, [\base] @ Read IINTVEC
|
||||
cmp \irqstat, #0
|
||||
ldreq \irqstat, [\base] @ erratum 63 workaround
|
||||
adds \irqnr, \irqstat, #1
|
||||
movne \irqnr, \irqstat, lsr #2
|
||||
.endm
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop33x/hardware.h
|
||||
*/
|
||||
|
||||
#ifndef __HARDWARE_H
|
||||
#define __HARDWARE_H
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
/*
|
||||
* Note about PCI IO space mappings
|
||||
*
|
||||
* To make IO space accesses efficient, we store virtual addresses in
|
||||
* the IO resources.
|
||||
*
|
||||
* The PCI IO space is located at virtual 0xfe000000 from physical
|
||||
* 0x90000000. The PCI BARs must be programmed with physical addresses,
|
||||
* but when we read them, we convert them to virtual addresses. See
|
||||
* arch/arm/mach-iop3xx/iop3xx-pci.c
|
||||
*/
|
||||
#define pcibios_assign_all_busses() 1
|
||||
#define PCIBIOS_MIN_IO 0x00000000
|
||||
#define PCIBIOS_MIN_MEM 0x00000000
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
void iop33x_init_irq(void);
|
||||
|
||||
extern struct platform_device iop33x_uart0_device;
|
||||
extern struct platform_device iop33x_uart1_device;
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* Generic chipset bits
|
||||
*
|
||||
*/
|
||||
#include "iop33x.h"
|
||||
|
||||
/*
|
||||
* Board specific bits
|
||||
*/
|
||||
#include "iq80331.h"
|
||||
#include "iq80332.h"
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,21 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop33x/io.h
|
||||
*
|
||||
* Copyright (C) 2001 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __IO_H
|
||||
#define __IO_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define IO_SPACE_LIMIT 0xffffffff
|
||||
#define __io(p) ((void __iomem *)(p))
|
||||
#define __mem_pci(a) (a)
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,33 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop33x/iop33x.h
|
||||
*
|
||||
* Intel IOP33X Chip definitions
|
||||
*
|
||||
* Author: Dave Jiang (dave.jiang@intel.com)
|
||||
* Copyright (C) 2003, 2004 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __IOP33X_H
|
||||
#define __IOP33X_H
|
||||
|
||||
/*
|
||||
* Peripherals that are shared between the iop32x and iop33x but
|
||||
* located at different addresses.
|
||||
*/
|
||||
#define IOP3XX_GPIO_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1780 + (reg))
|
||||
#define IOP3XX_TIMER_REG(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + 0x07d0 + (reg))
|
||||
|
||||
#include <asm/hardware/iop3xx.h>
|
||||
|
||||
/* UARTs */
|
||||
#define IOP33X_UART0_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1700)
|
||||
#define IOP33X_UART0_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1700)
|
||||
#define IOP33X_UART1_PHYS (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
|
||||
#define IOP33X_UART1_VIRT (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
|
||||
|
||||
|
||||
#endif
|
||||
@@ -1,23 +1,16 @@
|
||||
/*
|
||||
* linux/include/asm/arch-iop3xx/iq80331.h
|
||||
* include/asm-arm/arch-iop33x/iq80331.h
|
||||
*
|
||||
* Intel IQ80331 evaluation board registers
|
||||
*/
|
||||
|
||||
#ifndef _IQ80331_H_
|
||||
#define _IQ80331_H_
|
||||
|
||||
#define IQ80331_FLASHBASE 0xc0000000 /* Flash */
|
||||
#define IQ80331_FLASHSIZE 0x00800000
|
||||
#define IQ80331_FLASHWIDTH 1
|
||||
#ifndef __IQ80331_H
|
||||
#define __IQ80331_H
|
||||
|
||||
#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */
|
||||
#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
|
||||
#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */
|
||||
#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void iq80331_map_io(void);
|
||||
#endif
|
||||
|
||||
#endif // _IQ80331_H_
|
||||
#endif
|
||||
@@ -1,23 +1,16 @@
|
||||
/*
|
||||
* linux/include/asm/arch-iop3xx/iq80332.h
|
||||
* include/asm-arm/arch-iop33x/iq80332.h
|
||||
*
|
||||
* Intel IQ80332 evaluation board registers
|
||||
*/
|
||||
|
||||
#ifndef _IQ80332_H_
|
||||
#define _IQ80332_H_
|
||||
|
||||
#define IQ80332_FLASHBASE 0xc0000000 /* Flash */
|
||||
#define IQ80332_FLASHSIZE 0x00800000
|
||||
#define IQ80332_FLASHWIDTH 1
|
||||
#ifndef __IQ80332_H
|
||||
#define __IQ80332_H
|
||||
|
||||
#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */
|
||||
#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
|
||||
#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */
|
||||
#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void iq80332_map_io(void);
|
||||
#endif
|
||||
|
||||
#endif // _IQ80332_H_
|
||||
#endif
|
||||
@@ -0,0 +1,60 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop33x/irqs.h
|
||||
*
|
||||
* Author: Dave Jiang (dave.jiang@intel.com)
|
||||
* Copyright: (C) 2003 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __IRQS_H
|
||||
#define __IRQS_H
|
||||
|
||||
/*
|
||||
* IOP80331 chipset interrupts
|
||||
*/
|
||||
#define IRQ_IOP33X_DMA0_EOT 0
|
||||
#define IRQ_IOP33X_DMA0_EOC 1
|
||||
#define IRQ_IOP33X_DMA1_EOT 2
|
||||
#define IRQ_IOP33X_DMA1_EOC 3
|
||||
#define IRQ_IOP33X_AA_EOT 6
|
||||
#define IRQ_IOP33X_AA_EOC 7
|
||||
#define IRQ_IOP33X_TIMER0 8
|
||||
#define IRQ_IOP33X_TIMER1 9
|
||||
#define IRQ_IOP33X_I2C_0 10
|
||||
#define IRQ_IOP33X_I2C_1 11
|
||||
#define IRQ_IOP33X_MSG 12
|
||||
#define IRQ_IOP33X_MSGIBQ 13
|
||||
#define IRQ_IOP33X_ATU_BIST 14
|
||||
#define IRQ_IOP33X_PERFMON 15
|
||||
#define IRQ_IOP33X_CORE_PMU 16
|
||||
#define IRQ_IOP33X_XINT0 24
|
||||
#define IRQ_IOP33X_XINT1 25
|
||||
#define IRQ_IOP33X_XINT2 26
|
||||
#define IRQ_IOP33X_XINT3 27
|
||||
#define IRQ_IOP33X_XINT8 32
|
||||
#define IRQ_IOP33X_XINT9 33
|
||||
#define IRQ_IOP33X_XINT10 34
|
||||
#define IRQ_IOP33X_XINT11 35
|
||||
#define IRQ_IOP33X_XINT12 36
|
||||
#define IRQ_IOP33X_XINT13 37
|
||||
#define IRQ_IOP33X_XINT14 38
|
||||
#define IRQ_IOP33X_XINT15 39
|
||||
#define IRQ_IOP33X_UART0 51
|
||||
#define IRQ_IOP33X_UART1 52
|
||||
#define IRQ_IOP33X_PBIE 53
|
||||
#define IRQ_IOP33X_ATU_CRW 54
|
||||
#define IRQ_IOP33X_ATU_ERR 55
|
||||
#define IRQ_IOP33X_MCU_ERR 56
|
||||
#define IRQ_IOP33X_DMA0_ERR 57
|
||||
#define IRQ_IOP33X_DMA1_ERR 58
|
||||
#define IRQ_IOP33X_AA_ERR 60
|
||||
#define IRQ_IOP33X_MSG_ERR 62
|
||||
#define IRQ_IOP33X_HPI 63
|
||||
|
||||
#define NR_IRQS 64
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,26 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop33x/memory.h
|
||||
*/
|
||||
|
||||
#ifndef __MEMORY_H
|
||||
#define __MEMORY_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
/*
|
||||
* Physical DRAM offset.
|
||||
*/
|
||||
#define PHYS_OFFSET UL(0x00000000)
|
||||
|
||||
/*
|
||||
* Virtual view <-> PCI DMA view memory address translations
|
||||
* virt_to_bus: Used to translate the virtual address to an
|
||||
* address suitable to be passed to set_dma_addr
|
||||
* bus_to_virt: Used to convert an address for DMA operations
|
||||
* to an address that the kernel can use.
|
||||
*/
|
||||
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
|
||||
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
|
||||
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,22 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop33x/system.h
|
||||
*
|
||||
* Copyright (C) 2001 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
static inline void arch_reset(char mode)
|
||||
{
|
||||
*IOP3XX_PCSR = 0x30;
|
||||
|
||||
/* Jump into ROM at address 0 */
|
||||
cpu_reset(0);
|
||||
}
|
||||
@@ -0,0 +1,9 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop33x/timex.h
|
||||
*
|
||||
* IOP3xx architecture timex specifications
|
||||
*/
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#define CLOCK_TICK_RATE (100 * HZ)
|
||||
@@ -0,0 +1,37 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop33x/uncompress.h
|
||||
*/
|
||||
|
||||
#include <asm/types.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <linux/serial_reg.h>
|
||||
#include <asm/hardware.h>
|
||||
|
||||
static volatile u32 *uart_base;
|
||||
|
||||
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
|
||||
|
||||
static inline void putc(char c)
|
||||
{
|
||||
while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
|
||||
barrier();
|
||||
uart_base[UART_TX] = c;
|
||||
}
|
||||
|
||||
static inline void flush(void)
|
||||
{
|
||||
}
|
||||
|
||||
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
|
||||
{
|
||||
if (machine_is_iq80331() || machine_is_iq80332())
|
||||
uart_base = (volatile u32 *)IOP33X_UART0_PHYS;
|
||||
else
|
||||
uart_base = (volatile u32 *)0xfe800000;
|
||||
}
|
||||
|
||||
/*
|
||||
* nothing to do
|
||||
*/
|
||||
#define arch_decomp_setup() __arch_decomp_setup(arch_id)
|
||||
#define arch_decomp_wdog()
|
||||
@@ -0,0 +1,5 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop33x/vmalloc.h
|
||||
*/
|
||||
|
||||
#define VMALLOC_END 0xfe000000
|
||||
@@ -1,35 +0,0 @@
|
||||
/* linux/include/asm-arm/arch-iop3xx/debug-macro.S
|
||||
*
|
||||
* Debugging macro include header
|
||||
*
|
||||
* Copyright (C) 1994-1999 Russell King
|
||||
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
.macro addruart,rx
|
||||
mov \rx, #0xfe000000 @ physical
|
||||
#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244)
|
||||
orr \rx, \rx, #0x00800000 @ location of the UART
|
||||
#elif defined(CONFIG_ARCH_IOP331)
|
||||
mrc p15, 0, \rx, c1, c0
|
||||
tst \rx, #1 @ MMU enabled?
|
||||
moveq \rx, #0x000fe000 @ Physical Base
|
||||
movne \rx, #0
|
||||
orr \rx, \rx, #0xfe000000
|
||||
orr \rx, \rx, #0x00f00000 @ Virtual Base
|
||||
orr \rx, \rx, #0x00001700 @ location of the UART
|
||||
#else
|
||||
#error Unknown IOP3XX implementation
|
||||
#endif
|
||||
.endm
|
||||
|
||||
#if !defined(CONFIG_ARCH_IQ80321) || !defined(CONFIG_ARCH_IQ31244) || !defined(CONFIG_ARCH_IQ80331)
|
||||
#define FLOW_CONTROL
|
||||
#endif
|
||||
#define UART_SHIFT 0
|
||||
#include <asm/hardware/debug-8250.S>
|
||||
@@ -1,57 +0,0 @@
|
||||
/*
|
||||
* include/asm-arm/arch-iop3xx/entry-macro.S
|
||||
*
|
||||
* Low-level IRQ helper macros for IOP3xx-based platforms
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
||||
* warranty of any kind, whether express or implied.
|
||||
*/
|
||||
#include <asm/arch/irqs.h>
|
||||
|
||||
#if defined(CONFIG_ARCH_IOP321)
|
||||
.macro disable_fiq
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Note: only deal with normal interrupts, not FIQ
|
||||
*/
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
mov \irqnr, #0
|
||||
mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC
|
||||
cmp \irqstat, #0
|
||||
beq 1001f
|
||||
clz \irqnr, \irqstat
|
||||
mov \base, #31
|
||||
subs \irqnr,\base,\irqnr
|
||||
add \irqnr,\irqnr,#IRQ_IOP321_DMA0_EOT
|
||||
1001:
|
||||
.endm
|
||||
|
||||
#elif defined(CONFIG_ARCH_IOP331)
|
||||
.macro disable_fiq
|
||||
.endm
|
||||
|
||||
/*
|
||||
* Note: only deal with normal interrupts, not FIQ
|
||||
*/
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
|
||||
mov \irqnr, #0
|
||||
mrc p6, 0, \irqstat, c4, c0, 0 @ Read IINTSRC0
|
||||
cmp \irqstat, #0
|
||||
bne 1002f
|
||||
mrc p6, 0, \irqstat, c5, c0, 0 @ Read IINTSRC1
|
||||
cmp \irqstat, #0
|
||||
beq 1001f
|
||||
clz \irqnr, \irqstat
|
||||
rsbs \irqnr,\irqnr,#31 @ recommend by RMK
|
||||
add \irqnr,\irqnr,#IRQ_IOP331_XINT8
|
||||
b 1001f
|
||||
1002: clz \irqnr, \irqstat
|
||||
rsbs \irqnr,\irqnr,#31 @ recommend by RMK
|
||||
add \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT
|
||||
1001:
|
||||
.endm
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,57 +0,0 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-iop3xx/hardware.h
|
||||
*/
|
||||
#ifndef __ASM_ARCH_HARDWARE_H
|
||||
#define __ASM_ARCH_HARDWARE_H
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
/*
|
||||
* Note about PCI IO space mappings
|
||||
*
|
||||
* To make IO space accesses efficient, we store virtual addresses in
|
||||
* the IO resources.
|
||||
*
|
||||
* The PCI IO space is located at virtual 0xfe000000 from physical
|
||||
* 0x90000000. The PCI BARs must be programmed with physical addresses,
|
||||
* but when we read them, we convert them to virtual addresses. See
|
||||
* arch/arm/mach-iop3xx/iop3xx-pci.c
|
||||
*/
|
||||
|
||||
#define pcibios_assign_all_busses() 1
|
||||
|
||||
|
||||
/*
|
||||
* The min PCI I/O and MEM space are dependent on what specific
|
||||
* chipset/platform we are running on, so instead of hardcoding with
|
||||
* #ifdefs, we just fill these in the platform level PCI init code.
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
extern unsigned long iop3xx_pcibios_min_io;
|
||||
extern unsigned long iop3xx_pcibios_min_mem;
|
||||
|
||||
extern unsigned int processor_id;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* We just set these to zero since they are really bogus anyways
|
||||
*/
|
||||
#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io)
|
||||
#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem)
|
||||
|
||||
/*
|
||||
* Generic chipset bits
|
||||
*
|
||||
*/
|
||||
#include "iop321.h"
|
||||
#include "iop331.h"
|
||||
|
||||
/*
|
||||
* Board specific bits
|
||||
*/
|
||||
#include "iq80321.h"
|
||||
#include "iq31244.h"
|
||||
#include "iq80331.h"
|
||||
#include "iq80332.h"
|
||||
|
||||
#endif /* _ASM_ARCH_HARDWARE_H */
|
||||
@@ -1,100 +0,0 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-iop3xx/irqs.h
|
||||
*
|
||||
* Author: Rory Bolt <rorybolt@pacbell.net>
|
||||
* Copyright: (C) 2002 Rory Bolt
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
#ifndef _IOP321_IRQS_H_
|
||||
#define _IOP321_IRQS_H_
|
||||
|
||||
/*
|
||||
* IOP80321 chipset interrupts
|
||||
*/
|
||||
#define IOP321_IRQ_OFS 0
|
||||
#define IOP321_IRQ(x) (IOP321_IRQ_OFS + (x))
|
||||
|
||||
/*
|
||||
* On IRQ or FIQ register
|
||||
*/
|
||||
#define IRQ_IOP321_DMA0_EOT IOP321_IRQ(0)
|
||||
#define IRQ_IOP321_DMA0_EOC IOP321_IRQ(1)
|
||||
#define IRQ_IOP321_DMA1_EOT IOP321_IRQ(2)
|
||||
#define IRQ_IOP321_DMA1_EOC IOP321_IRQ(3)
|
||||
#define IRQ_IOP321_RSVD_4 IOP321_IRQ(4)
|
||||
#define IRQ_IOP321_RSVD_5 IOP321_IRQ(5)
|
||||
#define IRQ_IOP321_AA_EOT IOP321_IRQ(6)
|
||||
#define IRQ_IOP321_AA_EOC IOP321_IRQ(7)
|
||||
#define IRQ_IOP321_CORE_PMON IOP321_IRQ(8)
|
||||
#define IRQ_IOP321_TIMER0 IOP321_IRQ(9)
|
||||
#define IRQ_IOP321_TIMER1 IOP321_IRQ(10)
|
||||
#define IRQ_IOP321_I2C_0 IOP321_IRQ(11)
|
||||
#define IRQ_IOP321_I2C_1 IOP321_IRQ(12)
|
||||
#define IRQ_IOP321_MESSAGING IOP321_IRQ(13)
|
||||
#define IRQ_IOP321_ATU_BIST IOP321_IRQ(14)
|
||||
#define IRQ_IOP321_PERFMON IOP321_IRQ(15)
|
||||
#define IRQ_IOP321_CORE_PMU IOP321_IRQ(16)
|
||||
#define IRQ_IOP321_BIU_ERR IOP321_IRQ(17)
|
||||
#define IRQ_IOP321_ATU_ERR IOP321_IRQ(18)
|
||||
#define IRQ_IOP321_MCU_ERR IOP321_IRQ(19)
|
||||
#define IRQ_IOP321_DMA0_ERR IOP321_IRQ(20)
|
||||
#define IRQ_IOP321_DMA1_ERR IOP321_IRQ(21)
|
||||
#define IRQ_IOP321_RSVD_22 IOP321_IRQ(22)
|
||||
#define IRQ_IOP321_AA_ERR IOP321_IRQ(23)
|
||||
#define IRQ_IOP321_MSG_ERR IOP321_IRQ(24)
|
||||
#define IRQ_IOP321_SSP IOP321_IRQ(25)
|
||||
#define IRQ_IOP321_RSVD_26 IOP321_IRQ(26)
|
||||
#define IRQ_IOP321_XINT0 IOP321_IRQ(27)
|
||||
#define IRQ_IOP321_XINT1 IOP321_IRQ(28)
|
||||
#define IRQ_IOP321_XINT2 IOP321_IRQ(29)
|
||||
#define IRQ_IOP321_XINT3 IOP321_IRQ(30)
|
||||
#define IRQ_IOP321_HPI IOP321_IRQ(31)
|
||||
|
||||
#define NR_IOP321_IRQS (IOP321_IRQ(31) + 1)
|
||||
|
||||
#define NR_IRQS NR_IOP321_IRQS
|
||||
|
||||
|
||||
/*
|
||||
* Interrupts available on the IQ80321 board
|
||||
*/
|
||||
|
||||
/*
|
||||
* On board devices
|
||||
*/
|
||||
#define IRQ_IQ80321_I82544 IRQ_IOP321_XINT0
|
||||
#define IRQ_IQ80321_UART IRQ_IOP321_XINT1
|
||||
|
||||
/*
|
||||
* PCI interrupts
|
||||
*/
|
||||
#define IRQ_IQ80321_INTA IRQ_IOP321_XINT0
|
||||
#define IRQ_IQ80321_INTB IRQ_IOP321_XINT1
|
||||
#define IRQ_IQ80321_INTC IRQ_IOP321_XINT2
|
||||
#define IRQ_IQ80321_INTD IRQ_IOP321_XINT3
|
||||
|
||||
/*
|
||||
* Interrupts on the IQ31244 board
|
||||
*/
|
||||
|
||||
/*
|
||||
* On board devices
|
||||
*/
|
||||
#define IRQ_IQ31244_UART IRQ_IOP321_XINT1
|
||||
#define IRQ_IQ31244_I82546 IRQ_IOP321_XINT0
|
||||
#define IRQ_IQ31244_SATA IRQ_IOP321_XINT2
|
||||
#define IRQ_IQ31244_PCIX_SLOT IRQ_IOP321_XINT3
|
||||
|
||||
/*
|
||||
* PCI interrupts
|
||||
*/
|
||||
#define IRQ_IQ31244_INTA IRQ_IOP321_XINT0
|
||||
#define IRQ_IQ31244_INTB IRQ_IOP321_XINT1
|
||||
#define IRQ_IQ31244_INTC IRQ_IOP321_XINT2
|
||||
#define IRQ_IQ31244_INTD IRQ_IOP321_XINT3
|
||||
|
||||
#endif // _IOP321_IRQ_H_
|
||||
@@ -1,345 +0,0 @@
|
||||
/*
|
||||
* linux/include/asm/arch-iop3xx/iop321.h
|
||||
*
|
||||
* Intel IOP321 Chip definitions
|
||||
*
|
||||
* Author: Rory Bolt <rorybolt@pacbell.net>
|
||||
* Copyright (C) 2002 Rory Bolt
|
||||
* Copyright (C) 2004 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _IOP321_HW_H_
|
||||
#define _IOP321_HW_H_
|
||||
|
||||
|
||||
/*
|
||||
* This is needed for mixed drivers that need to work on all
|
||||
* IOP3xx variants but behave slightly differently on each.
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef CONFIG_ARCH_IOP321
|
||||
#define iop_is_321() (((processor_id & 0xfffff5e0) == 0x69052420))
|
||||
#else
|
||||
#define iop_is_321() 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IOP321 I/O and Mem space regions for PCI autoconfiguration
|
||||
*/
|
||||
#define IOP321_PCI_IO_WINDOW_SIZE 0x00010000
|
||||
#define IOP321_PCI_LOWER_IO_PA 0x90000000
|
||||
#define IOP321_PCI_LOWER_IO_VA 0xfe000000
|
||||
#define IOP321_PCI_LOWER_IO_BA (*IOP321_OIOWTVR)
|
||||
#define IOP321_PCI_UPPER_IO_PA (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1)
|
||||
#define IOP321_PCI_UPPER_IO_VA (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1)
|
||||
#define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
|
||||
#define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
|
||||
|
||||
/* #define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1) */
|
||||
#define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
|
||||
#define IOP321_PCI_LOWER_MEM_PA 0x80000000
|
||||
#define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0)
|
||||
#define IOP321_PCI_UPPER_MEM_PA (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
|
||||
#define IOP321_PCI_UPPER_MEM_BA (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
|
||||
#define IOP321_PCI_MEM_OFFSET (IOP321_PCI_LOWER_MEM_PA - IOP321_PCI_LOWER_MEM_BA)
|
||||
|
||||
|
||||
/*
|
||||
* IOP321 chipset registers
|
||||
*/
|
||||
#define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
|
||||
#define IOP321_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
|
||||
#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg))
|
||||
|
||||
/* Reserved 0x00000000 through 0x000000FF */
|
||||
|
||||
/* Address Translation Unit 0x00000100 through 0x000001FF */
|
||||
#define IOP321_ATUVID (volatile u16 *)IOP321_REG_ADDR(0x00000100)
|
||||
#define IOP321_ATUDID (volatile u16 *)IOP321_REG_ADDR(0x00000102)
|
||||
#define IOP321_ATUCMD (volatile u16 *)IOP321_REG_ADDR(0x00000104)
|
||||
#define IOP321_ATUSR (volatile u16 *)IOP321_REG_ADDR(0x00000106)
|
||||
#define IOP321_ATURID (volatile u8 *)IOP321_REG_ADDR(0x00000108)
|
||||
#define IOP321_ATUCCR (volatile u32 *)IOP321_REG_ADDR(0x00000109)
|
||||
#define IOP321_ATUCLSR (volatile u8 *)IOP321_REG_ADDR(0x0000010C)
|
||||
#define IOP321_ATULT (volatile u8 *)IOP321_REG_ADDR(0x0000010D)
|
||||
#define IOP321_ATUHTR (volatile u8 *)IOP321_REG_ADDR(0x0000010E)
|
||||
#define IOP321_ATUBIST (volatile u8 *)IOP321_REG_ADDR(0x0000010F)
|
||||
#define IOP321_IABAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000110)
|
||||
#define IOP321_IAUBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000114)
|
||||
#define IOP321_IABAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000118)
|
||||
#define IOP321_IAUBAR1 (volatile u32 *)IOP321_REG_ADDR(0x0000011C)
|
||||
#define IOP321_IABAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000120)
|
||||
#define IOP321_IAUBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000124)
|
||||
#define IOP321_ASVIR (volatile u16 *)IOP321_REG_ADDR(0x0000012C)
|
||||
#define IOP321_ASIR (volatile u16 *)IOP321_REG_ADDR(0x0000012E)
|
||||
#define IOP321_ERBAR (volatile u32 *)IOP321_REG_ADDR(0x00000130)
|
||||
/* Reserved 0x00000134 through 0x0000013B */
|
||||
#define IOP321_ATUILR (volatile u8 *)IOP321_REG_ADDR(0x0000013C)
|
||||
#define IOP321_ATUIPR (volatile u8 *)IOP321_REG_ADDR(0x0000013D)
|
||||
#define IOP321_ATUMGNT (volatile u8 *)IOP321_REG_ADDR(0x0000013E)
|
||||
#define IOP321_ATUMLAT (volatile u8 *)IOP321_REG_ADDR(0x0000013F)
|
||||
#define IOP321_IALR0 (volatile u32 *)IOP321_REG_ADDR(0x00000140)
|
||||
#define IOP321_IATVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000144)
|
||||
#define IOP321_ERLR (volatile u32 *)IOP321_REG_ADDR(0x00000148)
|
||||
#define IOP321_ERTVR (volatile u32 *)IOP321_REG_ADDR(0x0000014C)
|
||||
#define IOP321_IALR1 (volatile u32 *)IOP321_REG_ADDR(0x00000150)
|
||||
#define IOP321_IALR2 (volatile u32 *)IOP321_REG_ADDR(0x00000154)
|
||||
#define IOP321_IATVR2 (volatile u32 *)IOP321_REG_ADDR(0x00000158)
|
||||
#define IOP321_OIOWTVR (volatile u32 *)IOP321_REG_ADDR(0x0000015C)
|
||||
#define IOP321_OMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000160)
|
||||
#define IOP321_OUMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000164)
|
||||
#define IOP321_OMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x00000168)
|
||||
#define IOP321_OUMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x0000016C)
|
||||
/* Reserved 0x00000170 through 0x00000177*/
|
||||
#define IOP321_OUDWTVR (volatile u32 *)IOP321_REG_ADDR(0x00000178)
|
||||
/* Reserved 0x0000017C through 0x0000017F*/
|
||||
#define IOP321_ATUCR (volatile u32 *)IOP321_REG_ADDR(0x00000180)
|
||||
#define IOP321_PCSR (volatile u32 *)IOP321_REG_ADDR(0x00000184)
|
||||
#define IOP321_ATUISR (volatile u32 *)IOP321_REG_ADDR(0x00000188)
|
||||
#define IOP321_ATUIMR (volatile u32 *)IOP321_REG_ADDR(0x0000018C)
|
||||
#define IOP321_IABAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000190)
|
||||
#define IOP321_IAUBAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000194)
|
||||
#define IOP321_IALR3 (volatile u32 *)IOP321_REG_ADDR(0x00000198)
|
||||
#define IOP321_IATVR3 (volatile u32 *)IOP321_REG_ADDR(0x0000019C)
|
||||
/* Reserved 0x000001A0 through 0x000001A3*/
|
||||
#define IOP321_OCCAR (volatile u32 *)IOP321_REG_ADDR(0x000001A4)
|
||||
/* Reserved 0x000001A8 through 0x000001AB*/
|
||||
#define IOP321_OCCDR (volatile u32 *)IOP321_REG_ADDR(0x000001AC)
|
||||
/* Reserved 0x000001B0 through 0x000001BB*/
|
||||
#define IOP321_PDSCR (volatile u32 *)IOP321_REG_ADDR(0x000001BC)
|
||||
#define IOP321_PMCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001C0)
|
||||
#define IOP321_PMNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001C1)
|
||||
#define IOP321_APMCR (volatile u16 *)IOP321_REG_ADDR(0x000001C2)
|
||||
#define IOP321_APMCSR (volatile u16 *)IOP321_REG_ADDR(0x000001C4)
|
||||
/* Reserved 0x000001C6 through 0x000001DF */
|
||||
#define IOP321_PCIXCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001E0)
|
||||
#define IOP321_PCIXNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001E1)
|
||||
#define IOP321_PCIXCMD (volatile u16 *)IOP321_REG_ADDR(0x000001E2)
|
||||
#define IOP321_PCIXSR (volatile u32 *)IOP321_REG_ADDR(0x000001E4)
|
||||
#define IOP321_PCIIRSR (volatile u32 *)IOP321_REG_ADDR(0x000001EC)
|
||||
|
||||
/* Messaging Unit 0x00000300 through 0x000003FF */
|
||||
|
||||
/* Reserved 0x00000300 through 0x0000030c */
|
||||
#define IOP321_IMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000310)
|
||||
#define IOP321_IMR1 (volatile u32 *)IOP321_REG_ADDR(0x00000314)
|
||||
#define IOP321_OMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000318)
|
||||
#define IOP321_OMR1 (volatile u32 *)IOP321_REG_ADDR(0x0000031C)
|
||||
#define IOP321_IDR (volatile u32 *)IOP321_REG_ADDR(0x00000320)
|
||||
#define IOP321_IISR (volatile u32 *)IOP321_REG_ADDR(0x00000324)
|
||||
#define IOP321_IIMR (volatile u32 *)IOP321_REG_ADDR(0x00000328)
|
||||
#define IOP321_ODR (volatile u32 *)IOP321_REG_ADDR(0x0000032C)
|
||||
#define IOP321_OISR (volatile u32 *)IOP321_REG_ADDR(0x00000330)
|
||||
#define IOP321_OIMR (volatile u32 *)IOP321_REG_ADDR(0x00000334)
|
||||
/* Reserved 0x00000338 through 0x0000034F */
|
||||
#define IOP321_MUCR (volatile u32 *)IOP321_REG_ADDR(0x00000350)
|
||||
#define IOP321_QBAR (volatile u32 *)IOP321_REG_ADDR(0x00000354)
|
||||
/* Reserved 0x00000358 through 0x0000035C */
|
||||
#define IOP321_IFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000360)
|
||||
#define IOP321_IFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000364)
|
||||
#define IOP321_IPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000368)
|
||||
#define IOP321_IPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000036C)
|
||||
#define IOP321_OFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000370)
|
||||
#define IOP321_OFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000374)
|
||||
#define IOP321_OPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000378)
|
||||
#define IOP321_OPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000037C)
|
||||
#define IOP321_IAR (volatile u32 *)IOP321_REG_ADDR(0x00000380)
|
||||
|
||||
#define IOP321_IIxR_MASK 0x7f /* masks all */
|
||||
#define IOP321_IIxR_IRI 0x40 /* RC Index Register Interrupt */
|
||||
#define IOP321_IIxR_OFQF 0x20 /* RC Output Free Q Full (ERROR) */
|
||||
#define IOP321_IIxR_ipq 0x10 /* RC Inbound Post Q (post) */
|
||||
#define IOP321_IIxR_ERRDI 0x08 /* RO Error Doorbell Interrupt */
|
||||
#define IOP321_IIxR_IDI 0x04 /* RO Inbound Doorbell Interrupt */
|
||||
#define IOP321_IIxR_IM1 0x02 /* RC Inbound Message 1 Interrupt */
|
||||
#define IOP321_IIxR_IM0 0x01 /* RC Inbound Message 0 Interrupt */
|
||||
|
||||
/* Reserved 0x00000384 through 0x000003FF */
|
||||
|
||||
/* DMA Controller 0x00000400 through 0x000004FF */
|
||||
#define IOP321_DMA0_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000400)
|
||||
#define IOP321_DMA0_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000404)
|
||||
#define IOP321_DMA0_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000040C)
|
||||
#define IOP321_DMA0_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000410)
|
||||
#define IOP321_DMA0_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000414)
|
||||
#define IOP321_DMA0_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000418)
|
||||
#define IOP321_DMA0_LADR (volatile u32 *)IOP321_REG_ADDR(0X0000041C)
|
||||
#define IOP321_DMA0_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000420)
|
||||
#define IOP321_DMA0_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000424)
|
||||
/* Reserved 0x00000428 through 0x0000043C */
|
||||
#define IOP321_DMA1_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000440)
|
||||
#define IOP321_DMA1_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000444)
|
||||
#define IOP321_DMA1_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000044C)
|
||||
#define IOP321_DMA1_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000450)
|
||||
#define IOP321_DMA1_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000454)
|
||||
#define IOP321_DMA1_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000458)
|
||||
#define IOP321_DMA1_LADR (volatile u32 *)IOP321_REG_ADDR(0x0000045C)
|
||||
#define IOP321_DMA1_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000460)
|
||||
#define IOP321_DMA1_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000464)
|
||||
/* Reserved 0x00000468 through 0x000004FF */
|
||||
|
||||
/* Memory controller 0x00000500 through 0x0005FF */
|
||||
|
||||
/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
|
||||
#define IOP321_PBCR (volatile u32 *)IOP321_REG_ADDR(0x00000680)
|
||||
#define IOP321_PBISR (volatile u32 *)IOP321_REG_ADDR(0x00000684)
|
||||
#define IOP321_PBBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000688)
|
||||
#define IOP321_PBLR0 (volatile u32 *)IOP321_REG_ADDR(0x0000068C)
|
||||
#define IOP321_PBBAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000690)
|
||||
#define IOP321_PBLR1 (volatile u32 *)IOP321_REG_ADDR(0x00000694)
|
||||
#define IOP321_PBBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000698)
|
||||
#define IOP321_PBLR2 (volatile u32 *)IOP321_REG_ADDR(0x0000069C)
|
||||
#define IOP321_PBBAR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A0)
|
||||
#define IOP321_PBLR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A4)
|
||||
#define IOP321_PBBAR4 (volatile u32 *)IOP321_REG_ADDR(0x000006A8)
|
||||
#define IOP321_PBLR4 (volatile u32 *)IOP321_REG_ADDR(0x000006AC)
|
||||
#define IOP321_PBBAR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B0)
|
||||
#define IOP321_PBLR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B4)
|
||||
#define IOP321_PBDSCR (volatile u32 *)IOP321_REG_ADDR(0x000006B8)
|
||||
/* Reserved 0x000006BC */
|
||||
#define IOP321_PMBR0 (volatile u32 *)IOP321_REG_ADDR(0x000006C0)
|
||||
/* Reserved 0x000006C4 through 0x000006DC */
|
||||
#define IOP321_PMBR1 (volatile u32 *)IOP321_REG_ADDR(0x000006E0)
|
||||
#define IOP321_PMBR2 (volatile u32 *)IOP321_REG_ADDR(0x000006E4)
|
||||
|
||||
#define IOP321_PBCR_EN 0x1
|
||||
|
||||
#define IOP321_PBISR_BOOR_ERR 0x1
|
||||
|
||||
/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
|
||||
#define IOP321_GTMR (volatile u32 *)IOP321_REG_ADDR(0x00000700)
|
||||
#define IOP321_ESR (volatile u32 *)IOP321_REG_ADDR(0x00000704)
|
||||
#define IOP321_EMISR (volatile u32 *)IOP321_REG_ADDR(0x00000708)
|
||||
/* reserved 0x00000070c */
|
||||
#define IOP321_GTSR (volatile u32 *)IOP321_REG_ADDR(0x00000710)
|
||||
/* PERC0 DOESN'T EXIST - index from 1! */
|
||||
#define IOP321_PERCR0 (volatile u32 *)IOP321_REG_ADDR(0x00000710)
|
||||
|
||||
#define IOP321_GTMR_NGCE 0x04 /* (Not) Global Counter Enable */
|
||||
|
||||
/* Internal arbitration unit 0x00000780 through 0x0007BF */
|
||||
#define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780)
|
||||
#define IOP321_MTTR1 (volatile u32 *)IOP321_REG_ADDR(0x00000784)
|
||||
#define IOP321_MTTR2 (volatile u32 *)IOP321_REG_ADDR(0x00000788)
|
||||
|
||||
/* General Purpose I/O Registers */
|
||||
#define IOP321_GPOE (volatile u32 *)IOP321_REG_ADDR(0x000007C4)
|
||||
#define IOP321_GPID (volatile u32 *)IOP321_REG_ADDR(0x000007C8)
|
||||
#define IOP321_GPOD (volatile u32 *)IOP321_REG_ADDR(0x000007CC)
|
||||
|
||||
/* Interrupt Controller */
|
||||
#define IOP321_INTCTL (volatile u32 *)IOP321_REG_ADDR(0x000007D0)
|
||||
#define IOP321_INTSTR (volatile u32 *)IOP321_REG_ADDR(0x000007D4)
|
||||
#define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8)
|
||||
#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC)
|
||||
|
||||
/* Timers */
|
||||
|
||||
#define IOP321_TU_TMR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E0)
|
||||
#define IOP321_TU_TMR1 (volatile u32 *)IOP321_REG_ADDR(0x000007E4)
|
||||
|
||||
#ifdef CONFIG_ARCH_IQ80321
|
||||
#define IOP321_TICK_RATE 200000000 /* 200 MHz clock */
|
||||
#elif defined(CONFIG_ARCH_IQ31244)
|
||||
#define IOP321_TICK_RATE 198000000 /* 33.000 MHz crystal */
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_EP80219
|
||||
#undef IOP321_TICK_RATE
|
||||
#define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */
|
||||
#endif
|
||||
|
||||
#define IOP321_TMR_TC 0x01
|
||||
#define IOP321_TMR_EN 0x02
|
||||
#define IOP321_TMR_RELOAD 0x04
|
||||
#define IOP321_TMR_PRIVILEGED 0x09
|
||||
|
||||
#define IOP321_TMR_RATIO_1_1 0x00
|
||||
#define IOP321_TMR_RATIO_4_1 0x10
|
||||
#define IOP321_TMR_RATIO_8_1 0x20
|
||||
#define IOP321_TMR_RATIO_16_1 0x30
|
||||
|
||||
#define IOP321_TU_TCR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E8)
|
||||
#define IOP321_TU_TCR1 (volatile u32 *)IOP321_REG_ADDR(0x000007EC)
|
||||
#define IOP321_TU_TRR0 (volatile u32 *)IOP321_REG_ADDR(0x000007F0)
|
||||
#define IOP321_TU_TRR1 (volatile u32 *)IOP321_REG_ADDR(0x000007F4)
|
||||
#define IOP321_TU_TISR (volatile u32 *)IOP321_REG_ADDR(0x000007F8)
|
||||
#define IOP321_TU_WDTCR (volatile u32 *)IOP321_REG_ADDR(0x000007FC)
|
||||
|
||||
/* Application accelerator unit 0x00000800 - 0x000008FF */
|
||||
#define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800)
|
||||
#define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804)
|
||||
#define IOP321_AAU_ADAR (volatile u32 *)IOP321_REG_ADDR(0x00000808)
|
||||
#define IOP321_AAU_ANDAR (volatile u32 *)IOP321_REG_ADDR(0x0000080C)
|
||||
#define IOP321_AAU_SAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000810)
|
||||
#define IOP321_AAU_SAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000814)
|
||||
#define IOP321_AAU_SAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000818)
|
||||
#define IOP321_AAU_SAR4 (volatile u32 *)IOP321_REG_ADDR(0x0000081C)
|
||||
#define IOP321_AAU_SAR5 (volatile u32 *)IOP321_REG_ADDR(0x0000082C)
|
||||
#define IOP321_AAU_SAR6 (volatile u32 *)IOP321_REG_ADDR(0x00000830)
|
||||
#define IOP321_AAU_SAR7 (volatile u32 *)IOP321_REG_ADDR(0x00000834)
|
||||
#define IOP321_AAU_SAR8 (volatile u32 *)IOP321_REG_ADDR(0x00000838)
|
||||
#define IOP321_AAU_SAR9 (volatile u32 *)IOP321_REG_ADDR(0x00000840)
|
||||
#define IOP321_AAU_SAR10 (volatile u32 *)IOP321_REG_ADDR(0x00000844)
|
||||
#define IOP321_AAU_SAR11 (volatile u32 *)IOP321_REG_ADDR(0x00000848)
|
||||
#define IOP321_AAU_SAR12 (volatile u32 *)IOP321_REG_ADDR(0x0000084C)
|
||||
#define IOP321_AAU_SAR13 (volatile u32 *)IOP321_REG_ADDR(0x00000850)
|
||||
#define IOP321_AAU_SAR14 (volatile u32 *)IOP321_REG_ADDR(0x00000854)
|
||||
#define IOP321_AAU_SAR15 (volatile u32 *)IOP321_REG_ADDR(0x00000858)
|
||||
#define IOP321_AAU_SAR16 (volatile u32 *)IOP321_REG_ADDR(0x0000085C)
|
||||
#define IOP321_AAU_SAR17 (volatile u32 *)IOP321_REG_ADDR(0x00000864)
|
||||
#define IOP321_AAU_SAR18 (volatile u32 *)IOP321_REG_ADDR(0x00000868)
|
||||
#define IOP321_AAU_SAR19 (volatile u32 *)IOP321_REG_ADDR(0x0000086C)
|
||||
#define IOP321_AAU_SAR20 (volatile u32 *)IOP321_REG_ADDR(0x00000870)
|
||||
#define IOP321_AAU_SAR21 (volatile u32 *)IOP321_REG_ADDR(0x00000874)
|
||||
#define IOP321_AAU_SAR22 (volatile u32 *)IOP321_REG_ADDR(0x00000878)
|
||||
#define IOP321_AAU_SAR23 (volatile u32 *)IOP321_REG_ADDR(0x0000087C)
|
||||
#define IOP321_AAU_SAR24 (volatile u32 *)IOP321_REG_ADDR(0x00000880)
|
||||
#define IOP321_AAU_SAR25 (volatile u32 *)IOP321_REG_ADDR(0x00000888)
|
||||
#define IOP321_AAU_SAR26 (volatile u32 *)IOP321_REG_ADDR(0x0000088C)
|
||||
#define IOP321_AAU_SAR27 (volatile u32 *)IOP321_REG_ADDR(0x00000890)
|
||||
#define IOP321_AAU_SAR28 (volatile u32 *)IOP321_REG_ADDR(0x00000894)
|
||||
#define IOP321_AAU_SAR29 (volatile u32 *)IOP321_REG_ADDR(0x00000898)
|
||||
#define IOP321_AAU_SAR30 (volatile u32 *)IOP321_REG_ADDR(0x0000089C)
|
||||
#define IOP321_AAU_SAR31 (volatile u32 *)IOP321_REG_ADDR(0x000008A0)
|
||||
#define IOP321_AAU_SAR32 (volatile u32 *)IOP321_REG_ADDR(0x000008A4)
|
||||
#define IOP321_AAU_DAR (volatile u32 *)IOP321_REG_ADDR(0x00000820)
|
||||
#define IOP321_AAU_ABCR (volatile u32 *)IOP321_REG_ADDR(0x00000824)
|
||||
#define IOP321_AAU_ADCR (volatile u32 *)IOP321_REG_ADDR(0x00000828)
|
||||
#define IOP321_AAU_EDCR0 (volatile u32 *)IOP321_REG_ADDR(0x0000083c)
|
||||
#define IOP321_AAU_EDCR1 (volatile u32 *)IOP321_REG_ADDR(0x00000860)
|
||||
#define IOP321_AAU_EDCR2 (volatile u32 *)IOP321_REG_ADDR(0x00000884)
|
||||
|
||||
|
||||
/* SSP serial port unit 0x00001600 - 0x0000167F */
|
||||
/* I2C bus interface unit 0x00001680 - 0x000016FF */
|
||||
#define IOP321_ICR0 (volatile u32 *)IOP321_REG_ADDR(0x00001680)
|
||||
#define IOP321_ISR0 (volatile u32 *)IOP321_REG_ADDR(0x00001684)
|
||||
#define IOP321_ISAR0 (volatile u32 *)IOP321_REG_ADDR(0x00001688)
|
||||
#define IOP321_IDBR0 (volatile u32 *)IOP321_REG_ADDR(0x0000168C)
|
||||
/* Reserved 0x00001690 */
|
||||
#define IOP321_IBMR0 (volatile u32 *)IOP321_REG_ADDR(0x00001694)
|
||||
/* Reserved 0x00001698 */
|
||||
/* Reserved 0x0000169C */
|
||||
#define IOP321_ICR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A0)
|
||||
#define IOP321_ISR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A4)
|
||||
#define IOP321_ISAR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A8)
|
||||
#define IOP321_IDBR1 (volatile u32 *)IOP321_REG_ADDR(0x000016AC)
|
||||
#define IOP321_IBMR1 (volatile u32 *)IOP321_REG_ADDR(0x000016B4)
|
||||
/* Reserved 0x000016B8 through 0x000016FC */
|
||||
|
||||
/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void iop321_map_io(void);
|
||||
extern void iop321_init_irq(void);
|
||||
extern void iop321_time_init(void);
|
||||
#endif
|
||||
|
||||
#endif // _IOP321_HW_H_
|
||||
@@ -1,132 +0,0 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-iop3xx/irqs.h
|
||||
*
|
||||
* Author: Dave Jiang (dave.jiang@intel.com)
|
||||
* Copyright: (C) 2003 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
#ifndef _IOP331_IRQS_H_
|
||||
#define _IOP331_IRQS_H_
|
||||
|
||||
/*
|
||||
* IOP80331 chipset interrupts
|
||||
*/
|
||||
#define IOP331_IRQ_OFS 0
|
||||
#define IOP331_IRQ(x) (IOP331_IRQ_OFS + (x))
|
||||
|
||||
/*
|
||||
* On IRQ or FIQ register
|
||||
*/
|
||||
#define IRQ_IOP331_DMA0_EOT IOP331_IRQ(0)
|
||||
#define IRQ_IOP331_DMA0_EOC IOP331_IRQ(1)
|
||||
#define IRQ_IOP331_DMA1_EOT IOP331_IRQ(2)
|
||||
#define IRQ_IOP331_DMA1_EOC IOP331_IRQ(3)
|
||||
#define IRQ_IOP331_RSVD_4 IOP331_IRQ(4)
|
||||
#define IRQ_IOP331_RSVD_5 IOP331_IRQ(5)
|
||||
#define IRQ_IOP331_AA_EOT IOP331_IRQ(6)
|
||||
#define IRQ_IOP331_AA_EOC IOP331_IRQ(7)
|
||||
#define IRQ_IOP331_TIMER0 IOP331_IRQ(8)
|
||||
#define IRQ_IOP331_TIMER1 IOP331_IRQ(9)
|
||||
#define IRQ_IOP331_I2C_0 IOP331_IRQ(10)
|
||||
#define IRQ_IOP331_I2C_1 IOP331_IRQ(11)
|
||||
#define IRQ_IOP331_MSG IOP331_IRQ(12)
|
||||
#define IRQ_IOP331_MSGIBQ IOP331_IRQ(13)
|
||||
#define IRQ_IOP331_ATU_BIST IOP331_IRQ(14)
|
||||
#define IRQ_IOP331_PERFMON IOP331_IRQ(15)
|
||||
#define IRQ_IOP331_CORE_PMU IOP331_IRQ(16)
|
||||
#define IRQ_IOP331_RSVD_17 IOP331_IRQ(17)
|
||||
#define IRQ_IOP331_RSVD_18 IOP331_IRQ(18)
|
||||
#define IRQ_IOP331_RSVD_19 IOP331_IRQ(19)
|
||||
#define IRQ_IOP331_RSVD_20 IOP331_IRQ(20)
|
||||
#define IRQ_IOP331_RSVD_21 IOP331_IRQ(21)
|
||||
#define IRQ_IOP331_RSVD_22 IOP331_IRQ(22)
|
||||
#define IRQ_IOP331_RSVD_23 IOP331_IRQ(23)
|
||||
#define IRQ_IOP331_XINT0 IOP331_IRQ(24)
|
||||
#define IRQ_IOP331_XINT1 IOP331_IRQ(25)
|
||||
#define IRQ_IOP331_XINT2 IOP331_IRQ(26)
|
||||
#define IRQ_IOP331_XINT3 IOP331_IRQ(27)
|
||||
#define IRQ_IOP331_RSVD_28 IOP331_IRQ(28)
|
||||
#define IRQ_IOP331_RSVD_29 IOP331_IRQ(29)
|
||||
#define IRQ_IOP331_RSVD_30 IOP331_IRQ(30)
|
||||
#define IRQ_IOP331_RSVD_31 IOP331_IRQ(31)
|
||||
#define IRQ_IOP331_XINT8 IOP331_IRQ(32) // 0
|
||||
#define IRQ_IOP331_XINT9 IOP331_IRQ(33) // 1
|
||||
#define IRQ_IOP331_XINT10 IOP331_IRQ(34) // 2
|
||||
#define IRQ_IOP331_XINT11 IOP331_IRQ(35) // 3
|
||||
#define IRQ_IOP331_XINT12 IOP331_IRQ(36) // 4
|
||||
#define IRQ_IOP331_XINT13 IOP331_IRQ(37) // 5
|
||||
#define IRQ_IOP331_XINT14 IOP331_IRQ(38) // 6
|
||||
#define IRQ_IOP331_XINT15 IOP331_IRQ(39) // 7
|
||||
#define IRQ_IOP331_RSVD_40 IOP331_IRQ(40) // 8
|
||||
#define IRQ_IOP331_RSVD_41 IOP331_IRQ(41) // 9
|
||||
#define IRQ_IOP331_RSVD_42 IOP331_IRQ(42) // 10
|
||||
#define IRQ_IOP331_RSVD_43 IOP331_IRQ(43) // 11
|
||||
#define IRQ_IOP331_RSVD_44 IOP331_IRQ(44) // 12
|
||||
#define IRQ_IOP331_RSVD_45 IOP331_IRQ(45) // 13
|
||||
#define IRQ_IOP331_RSVD_46 IOP331_IRQ(46) // 14
|
||||
#define IRQ_IOP331_RSVD_47 IOP331_IRQ(47) // 15
|
||||
#define IRQ_IOP331_RSVD_48 IOP331_IRQ(48) // 16
|
||||
#define IRQ_IOP331_RSVD_49 IOP331_IRQ(49) // 17
|
||||
#define IRQ_IOP331_RSVD_50 IOP331_IRQ(50) // 18
|
||||
#define IRQ_IOP331_UART0 IOP331_IRQ(51) // 19
|
||||
#define IRQ_IOP331_UART1 IOP331_IRQ(52) // 20
|
||||
#define IRQ_IOP331_PBIE IOP331_IRQ(53) // 21
|
||||
#define IRQ_IOP331_ATU_CRW IOP331_IRQ(54) // 22
|
||||
#define IRQ_IOP331_ATU_ERR IOP331_IRQ(55) // 23
|
||||
#define IRQ_IOP331_MCU_ERR IOP331_IRQ(56) // 24
|
||||
#define IRQ_IOP331_DMA0_ERR IOP331_IRQ(57) // 25
|
||||
#define IRQ_IOP331_DMA1_ERR IOP331_IRQ(58) // 26
|
||||
#define IRQ_IOP331_RSVD_59 IOP331_IRQ(59) // 27
|
||||
#define IRQ_IOP331_AA_ERR IOP331_IRQ(60) // 28
|
||||
#define IRQ_IOP331_RSVD_61 IOP331_IRQ(61) // 29
|
||||
#define IRQ_IOP331_MSG_ERR IOP331_IRQ(62) // 30
|
||||
#define IRQ_IOP331_HPI IOP331_IRQ(63) // 31
|
||||
|
||||
#define NR_IOP331_IRQS (IOP331_IRQ(63) + 1)
|
||||
|
||||
#define NR_IRQS NR_IOP331_IRQS
|
||||
|
||||
|
||||
/*
|
||||
* Interrupts available on the IQ80331 board
|
||||
*/
|
||||
|
||||
/*
|
||||
* On board devices
|
||||
*/
|
||||
#define IRQ_IQ80331_I82544 IRQ_IOP331_XINT0
|
||||
#define IRQ_IQ80331_UART0 IRQ_IOP331_UART0
|
||||
#define IRQ_IQ80331_UART1 IRQ_IOP331_UART1
|
||||
|
||||
/*
|
||||
* PCI interrupts
|
||||
*/
|
||||
#define IRQ_IQ80331_INTA IRQ_IOP331_XINT0
|
||||
#define IRQ_IQ80331_INTB IRQ_IOP331_XINT1
|
||||
#define IRQ_IQ80331_INTC IRQ_IOP331_XINT2
|
||||
#define IRQ_IQ80331_INTD IRQ_IOP331_XINT3
|
||||
|
||||
/*
|
||||
* Interrupts available on the IQ80332 board
|
||||
*/
|
||||
|
||||
/*
|
||||
* On board devices
|
||||
*/
|
||||
#define IRQ_IQ80332_I82544 IRQ_IOP331_XINT0
|
||||
#define IRQ_IQ80332_UART0 IRQ_IOP331_UART0
|
||||
#define IRQ_IQ80332_UART1 IRQ_IOP331_UART1
|
||||
|
||||
/*
|
||||
* PCI interrupts
|
||||
*/
|
||||
#define IRQ_IQ80332_INTA IRQ_IOP331_XINT0
|
||||
#define IRQ_IQ80332_INTB IRQ_IOP331_XINT1
|
||||
#define IRQ_IQ80332_INTC IRQ_IOP331_XINT2
|
||||
#define IRQ_IQ80332_INTD IRQ_IOP331_XINT3
|
||||
|
||||
#endif // _IOP331_IRQ_H_
|
||||
@@ -1,363 +0,0 @@
|
||||
/*
|
||||
* linux/include/asm/arch-iop3xx/iop331.h
|
||||
*
|
||||
* Intel IOP331 Chip definitions
|
||||
*
|
||||
* Author: Dave Jiang (dave.jiang@intel.com)
|
||||
* Copyright (C) 2003, 2004 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _IOP331_HW_H_
|
||||
#define _IOP331_HW_H_
|
||||
|
||||
|
||||
/*
|
||||
* This is needed for mixed drivers that need to work on all
|
||||
* IOP3xx variants but behave slightly differently on each.
|
||||
*/
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef CONFIG_ARCH_IOP331
|
||||
/*#define iop_is_331() ((processor_id & 0xffffffb0) == 0x69054090) */
|
||||
#define iop_is_331() ((processor_id & 0xffffff30) == 0x69054010)
|
||||
#else
|
||||
#define iop_is_331() 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* IOP331 I/O and Mem space regions for PCI autoconfiguration
|
||||
*/
|
||||
#define IOP331_PCI_IO_WINDOW_SIZE 0x00010000
|
||||
#define IOP331_PCI_LOWER_IO_PA 0x90000000
|
||||
#define IOP331_PCI_LOWER_IO_VA 0xfe000000
|
||||
#define IOP331_PCI_LOWER_IO_BA (*IOP331_OIOWTVR)
|
||||
#define IOP331_PCI_UPPER_IO_PA (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1)
|
||||
#define IOP331_PCI_UPPER_IO_VA (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1)
|
||||
#define IOP331_PCI_UPPER_IO_BA (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1)
|
||||
#define IOP331_PCI_IO_OFFSET (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA)
|
||||
|
||||
/* this can be 128M if OMWTVR1 is set */
|
||||
#define IOP331_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
|
||||
/* #define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1) */
|
||||
#define IOP331_PCI_LOWER_MEM_PA 0x80000000
|
||||
#define IOP331_PCI_LOWER_MEM_BA (*IOP331_OMWTVR0)
|
||||
#define IOP331_PCI_UPPER_MEM_PA (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
|
||||
#define IOP331_PCI_UPPER_MEM_BA (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
|
||||
#define IOP331_PCI_MEM_OFFSET (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA)
|
||||
|
||||
/*
|
||||
* IOP331 chipset registers
|
||||
*/
|
||||
#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
|
||||
#define IOP331_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
|
||||
#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg))
|
||||
|
||||
/* Reserved 0x00000000 through 0x000000FF */
|
||||
|
||||
/* Address Translation Unit 0x00000100 through 0x000001FF */
|
||||
#define IOP331_ATUVID (volatile u16 *)IOP331_REG_ADDR(0x00000100)
|
||||
#define IOP331_ATUDID (volatile u16 *)IOP331_REG_ADDR(0x00000102)
|
||||
#define IOP331_ATUCMD (volatile u16 *)IOP331_REG_ADDR(0x00000104)
|
||||
#define IOP331_ATUSR (volatile u16 *)IOP331_REG_ADDR(0x00000106)
|
||||
#define IOP331_ATURID (volatile u8 *)IOP331_REG_ADDR(0x00000108)
|
||||
#define IOP331_ATUCCR (volatile u32 *)IOP331_REG_ADDR(0x00000109)
|
||||
#define IOP331_ATUCLSR (volatile u8 *)IOP331_REG_ADDR(0x0000010C)
|
||||
#define IOP331_ATULT (volatile u8 *)IOP331_REG_ADDR(0x0000010D)
|
||||
#define IOP331_ATUHTR (volatile u8 *)IOP331_REG_ADDR(0x0000010E)
|
||||
#define IOP331_ATUBIST (volatile u8 *)IOP331_REG_ADDR(0x0000010F)
|
||||
#define IOP331_IABAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000110)
|
||||
#define IOP331_IAUBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000114)
|
||||
#define IOP331_IABAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000118)
|
||||
#define IOP331_IAUBAR1 (volatile u32 *)IOP331_REG_ADDR(0x0000011C)
|
||||
#define IOP331_IABAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000120)
|
||||
#define IOP331_IAUBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000124)
|
||||
#define IOP331_ASVIR (volatile u16 *)IOP331_REG_ADDR(0x0000012C)
|
||||
#define IOP331_ASIR (volatile u16 *)IOP331_REG_ADDR(0x0000012E)
|
||||
#define IOP331_ERBAR (volatile u32 *)IOP331_REG_ADDR(0x00000130)
|
||||
#define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134)
|
||||
/* Reserved 0x00000138 through 0x0000013B */
|
||||
#define IOP331_ATUILR (volatile u8 *)IOP331_REG_ADDR(0x0000013C)
|
||||
#define IOP331_ATUIPR (volatile u8 *)IOP331_REG_ADDR(0x0000013D)
|
||||
#define IOP331_ATUMGNT (volatile u8 *)IOP331_REG_ADDR(0x0000013E)
|
||||
#define IOP331_ATUMLAT (volatile u8 *)IOP331_REG_ADDR(0x0000013F)
|
||||
#define IOP331_IALR0 (volatile u32 *)IOP331_REG_ADDR(0x00000140)
|
||||
#define IOP331_IATVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000144)
|
||||
#define IOP331_ERLR (volatile u32 *)IOP331_REG_ADDR(0x00000148)
|
||||
#define IOP331_ERTVR (volatile u32 *)IOP331_REG_ADDR(0x0000014C)
|
||||
#define IOP331_IALR1 (volatile u32 *)IOP331_REG_ADDR(0x00000150)
|
||||
#define IOP331_IALR2 (volatile u32 *)IOP331_REG_ADDR(0x00000154)
|
||||
#define IOP331_IATVR2 (volatile u32 *)IOP331_REG_ADDR(0x00000158)
|
||||
#define IOP331_OIOWTVR (volatile u32 *)IOP331_REG_ADDR(0x0000015C)
|
||||
#define IOP331_OMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000160)
|
||||
#define IOP331_OUMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000164)
|
||||
#define IOP331_OMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x00000168)
|
||||
#define IOP331_OUMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x0000016C)
|
||||
/* Reserved 0x00000170 through 0x00000177*/
|
||||
#define IOP331_OUDWTVR (volatile u32 *)IOP331_REG_ADDR(0x00000178)
|
||||
/* Reserved 0x0000017C through 0x0000017F*/
|
||||
#define IOP331_ATUCR (volatile u32 *)IOP331_REG_ADDR(0x00000180)
|
||||
#define IOP331_PCSR (volatile u32 *)IOP331_REG_ADDR(0x00000184)
|
||||
#define IOP331_ATUISR (volatile u32 *)IOP331_REG_ADDR(0x00000188)
|
||||
#define IOP331_ATUIMR (volatile u32 *)IOP331_REG_ADDR(0x0000018C)
|
||||
#define IOP331_IABAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000190)
|
||||
#define IOP331_IAUBAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000194)
|
||||
#define IOP331_IALR3 (volatile u32 *)IOP331_REG_ADDR(0x00000198)
|
||||
#define IOP331_IATVR3 (volatile u32 *)IOP331_REG_ADDR(0x0000019C)
|
||||
/* Reserved 0x000001A0 through 0x000001A3*/
|
||||
#define IOP331_OCCAR (volatile u32 *)IOP331_REG_ADDR(0x000001A4)
|
||||
/* Reserved 0x000001A8 through 0x000001AB*/
|
||||
#define IOP331_OCCDR (volatile u32 *)IOP331_REG_ADDR(0x000001AC)
|
||||
/* Reserved 0x000001B0 through 0x000001BB*/
|
||||
#define IOP331_VPDCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001B8)
|
||||
#define IOP331_VPDNXTP (volatile u8 *)IOP331_REG_ADDR(0x000001B9)
|
||||
#define IOP331_VPDAR (volatile u16 *)IOP331_REG_ADDR(0x000001BA)
|
||||
#define IOP331_VPDDR (volatile u32 *)IOP331_REG_ADDR(0x000001BC)
|
||||
#define IOP331_PMCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001C0)
|
||||
#define IOP331_PMNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001C1)
|
||||
#define IOP331_APMCR (volatile u16 *)IOP331_REG_ADDR(0x000001C2)
|
||||
#define IOP331_APMCSR (volatile u16 *)IOP331_REG_ADDR(0x000001C4)
|
||||
/* Reserved 0x000001C6 through 0x000001CF */
|
||||
#define IOP331_MSICAPID (volatile u8 *)IOP331_REG_ADDR(0x000001D0)
|
||||
#define IOP331_MSINXTP (volatile u8 *)IOP331_REG_ADDR(0x000001D1)
|
||||
#define IOP331_MSIMCR (volatile u16 *)IOP331_REG_ADDR(0x000001D2)
|
||||
#define IOP331_MSIMAR (volatile u32 *)IOP331_REG_ADDR(0x000001D4)
|
||||
#define IOP331_MSIMUAR (volatile u32 *)IOP331_REG_ADDR(0x000001D8)
|
||||
#define IOP331_MSIMDR (volatile u32 *)IOP331_REG_ADDR(0x000001DC)
|
||||
#define IOP331_PCIXCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001E0)
|
||||
#define IOP331_PCIXNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001E1)
|
||||
#define IOP331_PCIXCMD (volatile u16 *)IOP331_REG_ADDR(0x000001E2)
|
||||
#define IOP331_PCIXSR (volatile u32 *)IOP331_REG_ADDR(0x000001E4)
|
||||
#define IOP331_PCIIRSR (volatile u32 *)IOP331_REG_ADDR(0x000001EC)
|
||||
|
||||
/* Messaging Unit 0x00000300 through 0x000003FF */
|
||||
|
||||
/* Reserved 0x00000300 through 0x0000030c */
|
||||
#define IOP331_IMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000310)
|
||||
#define IOP331_IMR1 (volatile u32 *)IOP331_REG_ADDR(0x00000314)
|
||||
#define IOP331_OMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000318)
|
||||
#define IOP331_OMR1 (volatile u32 *)IOP331_REG_ADDR(0x0000031C)
|
||||
#define IOP331_IDR (volatile u32 *)IOP331_REG_ADDR(0x00000320)
|
||||
#define IOP331_IISR (volatile u32 *)IOP331_REG_ADDR(0x00000324)
|
||||
#define IOP331_IIMR (volatile u32 *)IOP331_REG_ADDR(0x00000328)
|
||||
#define IOP331_ODR (volatile u32 *)IOP331_REG_ADDR(0x0000032C)
|
||||
#define IOP331_OISR (volatile u32 *)IOP331_REG_ADDR(0x00000330)
|
||||
#define IOP331_OIMR (volatile u32 *)IOP331_REG_ADDR(0x00000334)
|
||||
/* Reserved 0x00000338 through 0x0000034F */
|
||||
#define IOP331_MUCR (volatile u32 *)IOP331_REG_ADDR(0x00000350)
|
||||
#define IOP331_QBAR (volatile u32 *)IOP331_REG_ADDR(0x00000354)
|
||||
/* Reserved 0x00000358 through 0x0000035C */
|
||||
#define IOP331_IFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000360)
|
||||
#define IOP331_IFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000364)
|
||||
#define IOP331_IPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000368)
|
||||
#define IOP331_IPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000036C)
|
||||
#define IOP331_OFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000370)
|
||||
#define IOP331_OFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000374)
|
||||
#define IOP331_OPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000378)
|
||||
#define IOP331_OPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000037C)
|
||||
#define IOP331_IAR (volatile u32 *)IOP331_REG_ADDR(0x00000380)
|
||||
/* Reserved 0x00000384 through 0x000003FF */
|
||||
|
||||
/* DMA Controller 0x00000400 through 0x000004FF */
|
||||
#define IOP331_DMA0_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000400)
|
||||
#define IOP331_DMA0_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000404)
|
||||
#define IOP331_DMA0_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000040C)
|
||||
#define IOP331_DMA0_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000410)
|
||||
#define IOP331_DMA0_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000414)
|
||||
#define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418)
|
||||
#define IOP331_DMA0_LADR (volatile u32 *)IOP331_REG_ADDR(0X0000041C)
|
||||
#define IOP331_DMA0_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000420)
|
||||
#define IOP331_DMA0_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000424)
|
||||
/* Reserved 0x00000428 through 0x0000043C */
|
||||
#define IOP331_DMA1_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000440)
|
||||
#define IOP331_DMA1_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000444)
|
||||
#define IOP331_DMA1_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000044C)
|
||||
#define IOP331_DMA1_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000450)
|
||||
#define IOP331_DMA1_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000454)
|
||||
#define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458)
|
||||
#define IOP331_DMA1_LADR (volatile u32 *)IOP331_REG_ADDR(0x0000045C)
|
||||
#define IOP331_DMA1_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000460)
|
||||
#define IOP331_DMA1_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000464)
|
||||
/* Reserved 0x00000468 through 0x000004FF */
|
||||
|
||||
/* Memory controller 0x00000500 through 0x0005FF */
|
||||
|
||||
/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
|
||||
#define IOP331_PBCR (volatile u32 *)IOP331_REG_ADDR(0x00000680)
|
||||
#define IOP331_PBISR (volatile u32 *)IOP331_REG_ADDR(0x00000684)
|
||||
#define IOP331_PBBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000688)
|
||||
#define IOP331_PBLR0 (volatile u32 *)IOP331_REG_ADDR(0x0000068C)
|
||||
#define IOP331_PBBAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000690)
|
||||
#define IOP331_PBLR1 (volatile u32 *)IOP331_REG_ADDR(0x00000694)
|
||||
#define IOP331_PBBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000698)
|
||||
#define IOP331_PBLR2 (volatile u32 *)IOP331_REG_ADDR(0x0000069C)
|
||||
#define IOP331_PBBAR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A0)
|
||||
#define IOP331_PBLR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A4)
|
||||
#define IOP331_PBBAR4 (volatile u32 *)IOP331_REG_ADDR(0x000006A8)
|
||||
#define IOP331_PBLR4 (volatile u32 *)IOP331_REG_ADDR(0x000006AC)
|
||||
#define IOP331_PBBAR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B0)
|
||||
#define IOP331_PBLR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B4)
|
||||
#define IOP331_PBDSCR (volatile u32 *)IOP331_REG_ADDR(0x000006B8)
|
||||
/* Reserved 0x000006BC */
|
||||
#define IOP331_PMBR0 (volatile u32 *)IOP331_REG_ADDR(0x000006C0)
|
||||
/* Reserved 0x000006C4 through 0x000006DC */
|
||||
#define IOP331_PMBR1 (volatile u32 *)IOP331_REG_ADDR(0x000006E0)
|
||||
#define IOP331_PMBR2 (volatile u32 *)IOP331_REG_ADDR(0x000006E4)
|
||||
|
||||
#define IOP331_PBCR_EN 0x1
|
||||
|
||||
#define IOP331_PBISR_BOOR_ERR 0x1
|
||||
|
||||
|
||||
|
||||
/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
|
||||
/* Internal arbitration unit 0x00000780 through 0x0007BF */
|
||||
|
||||
/* Interrupt Controller */
|
||||
#define IOP331_INTCTL0 (volatile u32 *)IOP331_REG_ADDR(0x00000790)
|
||||
#define IOP331_INTCTL1 (volatile u32 *)IOP331_REG_ADDR(0x00000794)
|
||||
#define IOP331_INTSTR0 (volatile u32 *)IOP331_REG_ADDR(0x00000798)
|
||||
#define IOP331_INTSTR1 (volatile u32 *)IOP331_REG_ADDR(0x0000079C)
|
||||
#define IOP331_IINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A0)
|
||||
#define IOP331_IINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007A4)
|
||||
#define IOP331_FINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A8)
|
||||
#define IOP331_FINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007AC)
|
||||
#define IOP331_IPR0 (volatile u32 *)IOP331_REG_ADDR(0x000007B0)
|
||||
#define IOP331_IPR1 (volatile u32 *)IOP331_REG_ADDR(0x000007B4)
|
||||
#define IOP331_IPR2 (volatile u32 *)IOP331_REG_ADDR(0x000007B8)
|
||||
#define IOP331_IPR3 (volatile u32 *)IOP331_REG_ADDR(0x000007BC)
|
||||
#define IOP331_INTBASE (volatile u32 *)IOP331_REG_ADDR(0x000007C0)
|
||||
#define IOP331_INTSIZE (volatile u32 *)IOP331_REG_ADDR(0x000007C4)
|
||||
#define IOP331_IINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007C8)
|
||||
#define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC)
|
||||
|
||||
|
||||
/* Timers */
|
||||
|
||||
#define IOP331_TU_TMR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D0)
|
||||
#define IOP331_TU_TMR1 (volatile u32 *)IOP331_REG_ADDR(0x000007D4)
|
||||
|
||||
#define IOP331_TMR_TC 0x01
|
||||
#define IOP331_TMR_EN 0x02
|
||||
#define IOP331_TMR_RELOAD 0x04
|
||||
#define IOP331_TMR_PRIVILEGED 0x09
|
||||
|
||||
#define IOP331_TMR_RATIO_1_1 0x00
|
||||
#define IOP331_TMR_RATIO_4_1 0x10
|
||||
#define IOP331_TMR_RATIO_8_1 0x20
|
||||
#define IOP331_TMR_RATIO_16_1 0x30
|
||||
|
||||
#define IOP331_TU_TCR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D8)
|
||||
#define IOP331_TU_TCR1 (volatile u32 *)IOP331_REG_ADDR(0x000007DC)
|
||||
#define IOP331_TU_TRR0 (volatile u32 *)IOP331_REG_ADDR(0x000007E0)
|
||||
#define IOP331_TU_TRR1 (volatile u32 *)IOP331_REG_ADDR(0x000007E4)
|
||||
#define IOP331_TU_TISR (volatile u32 *)IOP331_REG_ADDR(0x000007E8)
|
||||
#define IOP331_TU_WDTCR (volatile u32 *)IOP331_REG_ADDR(0x000007EC)
|
||||
|
||||
#if defined(CONFIG_ARCH_IOP331)
|
||||
#define IOP331_TICK_RATE 266000000 /* 266 MHz IB clock */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_IOP331_STEPD) || defined(CONFIG_ARCH_IQ80333)
|
||||
#undef IOP331_TICK_RATE
|
||||
#define IOP331_TICK_RATE 333000000 /* 333 Mhz IB clock */
|
||||
#endif
|
||||
|
||||
/* Application accelerator unit 0x00000800 - 0x000008FF */
|
||||
#define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800)
|
||||
#define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804)
|
||||
#define IOP331_AAU_ADAR (volatile u32 *)IOP331_REG_ADDR(0x00000808)
|
||||
#define IOP331_AAU_ANDAR (volatile u32 *)IOP331_REG_ADDR(0x0000080C)
|
||||
#define IOP331_AAU_SAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000810)
|
||||
#define IOP331_AAU_SAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000814)
|
||||
#define IOP331_AAU_SAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000818)
|
||||
#define IOP331_AAU_SAR4 (volatile u32 *)IOP331_REG_ADDR(0x0000081C)
|
||||
#define IOP331_AAU_SAR5 (volatile u32 *)IOP331_REG_ADDR(0x0000082C)
|
||||
#define IOP331_AAU_SAR6 (volatile u32 *)IOP331_REG_ADDR(0x00000830)
|
||||
#define IOP331_AAU_SAR7 (volatile u32 *)IOP331_REG_ADDR(0x00000834)
|
||||
#define IOP331_AAU_SAR8 (volatile u32 *)IOP331_REG_ADDR(0x00000838)
|
||||
#define IOP331_AAU_SAR9 (volatile u32 *)IOP331_REG_ADDR(0x00000840)
|
||||
#define IOP331_AAU_SAR10 (volatile u32 *)IOP331_REG_ADDR(0x00000844)
|
||||
#define IOP331_AAU_SAR11 (volatile u32 *)IOP331_REG_ADDR(0x00000848)
|
||||
#define IOP331_AAU_SAR12 (volatile u32 *)IOP331_REG_ADDR(0x0000084C)
|
||||
#define IOP331_AAU_SAR13 (volatile u32 *)IOP331_REG_ADDR(0x00000850)
|
||||
#define IOP331_AAU_SAR14 (volatile u32 *)IOP331_REG_ADDR(0x00000854)
|
||||
#define IOP331_AAU_SAR15 (volatile u32 *)IOP331_REG_ADDR(0x00000858)
|
||||
#define IOP331_AAU_SAR16 (volatile u32 *)IOP331_REG_ADDR(0x0000085C)
|
||||
#define IOP331_AAU_SAR17 (volatile u32 *)IOP331_REG_ADDR(0x00000864)
|
||||
#define IOP331_AAU_SAR18 (volatile u32 *)IOP331_REG_ADDR(0x00000868)
|
||||
#define IOP331_AAU_SAR19 (volatile u32 *)IOP331_REG_ADDR(0x0000086C)
|
||||
#define IOP331_AAU_SAR20 (volatile u32 *)IOP331_REG_ADDR(0x00000870)
|
||||
#define IOP331_AAU_SAR21 (volatile u32 *)IOP331_REG_ADDR(0x00000874)
|
||||
#define IOP331_AAU_SAR22 (volatile u32 *)IOP331_REG_ADDR(0x00000878)
|
||||
#define IOP331_AAU_SAR23 (volatile u32 *)IOP331_REG_ADDR(0x0000087C)
|
||||
#define IOP331_AAU_SAR24 (volatile u32 *)IOP331_REG_ADDR(0x00000880)
|
||||
#define IOP331_AAU_SAR25 (volatile u32 *)IOP331_REG_ADDR(0x00000888)
|
||||
#define IOP331_AAU_SAR26 (volatile u32 *)IOP331_REG_ADDR(0x0000088C)
|
||||
#define IOP331_AAU_SAR27 (volatile u32 *)IOP331_REG_ADDR(0x00000890)
|
||||
#define IOP331_AAU_SAR28 (volatile u32 *)IOP331_REG_ADDR(0x00000894)
|
||||
#define IOP331_AAU_SAR29 (volatile u32 *)IOP331_REG_ADDR(0x00000898)
|
||||
#define IOP331_AAU_SAR30 (volatile u32 *)IOP331_REG_ADDR(0x0000089C)
|
||||
#define IOP331_AAU_SAR31 (volatile u32 *)IOP331_REG_ADDR(0x000008A0)
|
||||
#define IOP331_AAU_SAR32 (volatile u32 *)IOP331_REG_ADDR(0x000008A4)
|
||||
#define IOP331_AAU_DAR (volatile u32 *)IOP331_REG_ADDR(0x00000820)
|
||||
#define IOP331_AAU_ABCR (volatile u32 *)IOP331_REG_ADDR(0x00000824)
|
||||
#define IOP331_AAU_ADCR (volatile u32 *)IOP331_REG_ADDR(0x00000828)
|
||||
#define IOP331_AAU_EDCR0 (volatile u32 *)IOP331_REG_ADDR(0x0000083c)
|
||||
#define IOP331_AAU_EDCR1 (volatile u32 *)IOP331_REG_ADDR(0x00000860)
|
||||
#define IOP331_AAU_EDCR2 (volatile u32 *)IOP331_REG_ADDR(0x00000884)
|
||||
|
||||
|
||||
#define IOP331_SPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C0)
|
||||
#define IOP331_PPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C8)
|
||||
/* SSP serial port unit 0x00001600 - 0x0000167F */
|
||||
|
||||
/* I2C bus interface unit 0x00001680 - 0x000016FF */
|
||||
/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
|
||||
|
||||
#define IOP331_ICR0 (volatile u32 *)IOP331_REG_ADDR(0x00001680)
|
||||
#define IOP331_ISR0 (volatile u32 *)IOP331_REG_ADDR(0x00001684)
|
||||
#define IOP331_ISAR0 (volatile u32 *)IOP331_REG_ADDR(0x00001688)
|
||||
#define IOP331_IDBR0 (volatile u32 *)IOP331_REG_ADDR(0x0000168C)
|
||||
/* Reserved 0x00001690 */
|
||||
#define IOP331_IBMR0 (volatile u32 *)IOP331_REG_ADDR(0x00001694)
|
||||
/* Reserved 0x00001698 */
|
||||
/* Reserved 0x0000169C */
|
||||
#define IOP331_ICR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A0)
|
||||
#define IOP331_ISR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A4)
|
||||
#define IOP331_ISAR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A8)
|
||||
#define IOP331_IDBR1 (volatile u32 *)IOP331_REG_ADDR(0x000016AC)
|
||||
#define IOP331_IBMR1 (volatile u32 *)IOP331_REG_ADDR(0x000016B4)
|
||||
/* Reserved 0x000016B8 through 0x000016FF */
|
||||
|
||||
/* 0x00001700 through 0x0000172C UART 0 */
|
||||
|
||||
/* Reserved 0x00001730 through 0x0000173F */
|
||||
|
||||
/* 0x00001740 through 0x0000176C UART 1 */
|
||||
|
||||
#define IOP331_UART0_PHYS (IOP331_PHYS_MEM_BASE | 0x00001700) /* UART #1 physical */
|
||||
#define IOP331_UART1_PHYS (IOP331_PHYS_MEM_BASE | 0x00001740) /* UART #2 physical */
|
||||
#define IOP331_UART0_VIRT (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */
|
||||
#define IOP331_UART1_VIRT (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */
|
||||
|
||||
/* Reserved 0x00001770 through 0x0000177F */
|
||||
|
||||
/* General Purpose I/O Registers */
|
||||
#define IOP331_GPOE (volatile u32 *)IOP331_REG_ADDR(0x00001780)
|
||||
#define IOP331_GPID (volatile u32 *)IOP331_REG_ADDR(0x00001784)
|
||||
#define IOP331_GPOD (volatile u32 *)IOP331_REG_ADDR(0x00001788)
|
||||
|
||||
/* Reserved 0x0000178c through 0x000019ff */
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void iop331_map_io(void);
|
||||
extern void iop331_init_irq(void);
|
||||
extern void iop331_time_init(void);
|
||||
#endif
|
||||
|
||||
#endif // _IOP331_HW_H_
|
||||
@@ -1,21 +0,0 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-iop3xx/irqs.h
|
||||
*
|
||||
* Copyright: (C) 2001-2003 MontaVista Software Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
/*
|
||||
* Chipset-specific bits
|
||||
*/
|
||||
#ifdef CONFIG_ARCH_IOP321
|
||||
#include "iop321-irqs.h"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_IOP331
|
||||
#include "iop331-irqs.h"
|
||||
#endif
|
||||
@@ -1,38 +0,0 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-iop3xx/memory.h
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MEMORY_H
|
||||
#define __ASM_ARCH_MEMORY_H
|
||||
|
||||
#include <asm/hardware.h>
|
||||
|
||||
/*
|
||||
* Physical DRAM offset.
|
||||
*/
|
||||
#ifndef CONFIG_ARCH_IOP331
|
||||
#define PHYS_OFFSET UL(0xa0000000)
|
||||
#else
|
||||
#define PHYS_OFFSET UL(0x00000000)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Virtual view <-> PCI DMA view memory address translations
|
||||
* virt_to_bus: Used to translate the virtual address to an
|
||||
* address suitable to be passed to set_dma_addr
|
||||
* bus_to_virt: Used to convert an address for DMA operations
|
||||
* to an address that the kernel can use.
|
||||
*/
|
||||
#if defined(CONFIG_ARCH_IOP321)
|
||||
|
||||
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0))
|
||||
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2)))
|
||||
|
||||
#elif defined(CONFIG_ARCH_IOP331)
|
||||
|
||||
#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP331_IATVR2)) | ((*IOP331_IABAR2) & 0xfffffff0))
|
||||
#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP331_IALR2)) | ( *IOP331_IATVR2)))
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,35 +0,0 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-iop3xx/system.h
|
||||
*
|
||||
* Copyright (C) 2001 MontaVista Software, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
static inline void arch_idle(void)
|
||||
{
|
||||
cpu_do_idle();
|
||||
}
|
||||
|
||||
|
||||
static inline void arch_reset(char mode)
|
||||
{
|
||||
#ifdef CONFIG_ARCH_IOP321
|
||||
*IOP321_PCSR = 0x30;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_IOP331
|
||||
*IOP331_PCSR = 0x30;
|
||||
#endif
|
||||
|
||||
if ( 1 && mode == 's') {
|
||||
/* Jump into ROM at address 0 */
|
||||
cpu_reset(0);
|
||||
} else {
|
||||
/* No on-chip reset capability */
|
||||
cpu_reset(0);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,20 +0,0 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-iop3xx/timex.h
|
||||
*
|
||||
* IOP3xx architecture timex specifications
|
||||
*/
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244)
|
||||
|
||||
#define CLOCK_TICK_RATE IOP321_TICK_RATE
|
||||
|
||||
#elif defined(CONFIG_ARCH_IQ80331) || defined(CONFIG_MACH_IQ80332)
|
||||
|
||||
#define CLOCK_TICK_RATE IOP331_TICK_RATE
|
||||
|
||||
#else
|
||||
|
||||
#error "No IOP3xx timex information for this architecture"
|
||||
|
||||
#endif
|
||||
@@ -1,48 +0,0 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-iop3xx/uncompress.h
|
||||
*/
|
||||
#include <asm/types.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <linux/serial_reg.h>
|
||||
#include <asm/hardware.h>
|
||||
|
||||
#ifdef CONFIG_ARCH_IOP321
|
||||
#define UTYPE unsigned char *
|
||||
#elif defined(CONFIG_ARCH_IOP331)
|
||||
#define UTYPE u32 *
|
||||
#else
|
||||
#error "Missing IOP3xx arch type def"
|
||||
#endif
|
||||
|
||||
static volatile UTYPE uart_base;
|
||||
|
||||
#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
|
||||
|
||||
static inline void putc(char c)
|
||||
{
|
||||
while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE)
|
||||
barrier();
|
||||
*uart_base = c;
|
||||
}
|
||||
|
||||
static inline void flush(void)
|
||||
{
|
||||
}
|
||||
|
||||
static __inline__ void __arch_decomp_setup(unsigned long arch_id)
|
||||
{
|
||||
if(machine_is_iq80321())
|
||||
uart_base = (volatile UTYPE)IQ80321_UART;
|
||||
else if(machine_is_iq31244())
|
||||
uart_base = (volatile UTYPE)IQ31244_UART;
|
||||
else if(machine_is_iq80331() || machine_is_iq80332())
|
||||
uart_base = (volatile UTYPE)IOP331_UART0_PHYS;
|
||||
else
|
||||
uart_base = (volatile UTYPE)0xfe800000;
|
||||
}
|
||||
|
||||
/*
|
||||
* nothing to do
|
||||
*/
|
||||
#define arch_decomp_setup() __arch_decomp_setup(arch_id)
|
||||
#define arch_decomp_wdog()
|
||||
@@ -1,16 +0,0 @@
|
||||
/*
|
||||
* linux/include/asm-arm/arch-iop3xx/vmalloc.h
|
||||
*/
|
||||
|
||||
/*
|
||||
* Just any arbitrary offset to the start of the vmalloc VM area: the
|
||||
* current 8MB value just means that there will be a 8MB "hole" after the
|
||||
* physical memory until the kernel virtual memory starts. That means that
|
||||
* any out-of-bounds memory accesses will hopefully be caught.
|
||||
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
|
||||
* area for the same reason. ;)
|
||||
*/
|
||||
//#define VMALLOC_END (0xe8000000)
|
||||
/* increase usable physical RAM to ~992M per RMK */
|
||||
#define VMALLOC_END (0xfe000000)
|
||||
|
||||
@@ -89,6 +89,11 @@ struct ixp4xx_i2c_pins {
|
||||
|
||||
struct sys_timer;
|
||||
|
||||
/*
|
||||
* Frequency of clock used for primary clocksource
|
||||
*/
|
||||
extern unsigned long ixp4xx_timer_freq;
|
||||
|
||||
/*
|
||||
* Functions used by platform-level setup code
|
||||
*/
|
||||
|
||||
@@ -31,9 +31,9 @@
|
||||
static inline unsigned int __arch_getw(unsigned long a)
|
||||
{
|
||||
unsigned int value;
|
||||
__asm__ __volatile__("ldr%?h %0, [%1, #0] @ getw"
|
||||
__asm__ __volatile__("ldrh %0, [%1, #0] @ getw"
|
||||
: "=&r" (value)
|
||||
: "r" (a));
|
||||
: "r" (a) : "cc");
|
||||
return value;
|
||||
}
|
||||
|
||||
@@ -42,8 +42,8 @@ static inline unsigned int __arch_getw(unsigned long a)
|
||||
|
||||
static inline void __arch_putw(unsigned int value, unsigned long a)
|
||||
{
|
||||
__asm__ __volatile__("str%?h %0, [%1, #0] @ putw"
|
||||
: : "r" (value), "r" (a));
|
||||
__asm__ __volatile__("strh %0, [%1, #0] @ putw"
|
||||
: : "r" (value), "r" (a) : "cc");
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@@ -50,9 +50,20 @@
|
||||
#define AMS_DELTA_LATCH2_NAND_NWE 0x0020
|
||||
#define AMS_DELTA_LATCH2_NAND_ALE 0x0040
|
||||
#define AMS_DELTA_LATCH2_NAND_CLE 0x0080
|
||||
#define AMD_DELTA_LATCH2_KEYBRD_PWR 0x0100
|
||||
#define AMD_DELTA_LATCH2_KEYBRD_DATA 0x0200
|
||||
#define AMD_DELTA_LATCH2_SCARD_RSTIN 0x0400
|
||||
#define AMD_DELTA_LATCH2_SCARD_CMDVCC 0x0800
|
||||
#define AMS_DELTA_LATCH2_MODEM_NRESET 0x1000
|
||||
#define AMS_DELTA_LATCH2_MODEM_CODEC 0x2000
|
||||
|
||||
#define AMS_DELTA_GPIO_PIN_KEYBRD_DATA 0
|
||||
#define AMS_DELTA_GPIO_PIN_KEYBRD_CLK 1
|
||||
#define AMS_DELTA_GPIO_PIN_MODEM_IRQ 2
|
||||
#define AMS_DELTA_GPIO_PIN_HOOK_SWITCH 4
|
||||
#define AMS_DELTA_GPIO_PIN_SCARD_NOFF 6
|
||||
#define AMS_DELTA_GPIO_PIN_SCARD_IO 7
|
||||
#define AMS_DELTA_GPIO_PIN_CONFIG 11
|
||||
#define AMS_DELTA_GPIO_PIN_NAND_RB 12
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
@@ -45,6 +45,7 @@ struct clk_functions {
|
||||
struct clk * (*clk_get_parent)(struct clk *clk);
|
||||
void (*clk_allow_idle)(struct clk *clk);
|
||||
void (*clk_deny_idle)(struct clk *clk);
|
||||
void (*clk_disable_unused)(struct clk *clk);
|
||||
};
|
||||
|
||||
extern unsigned int mpurate;
|
||||
|
||||
@@ -331,6 +331,12 @@ enum omap_dma_color_mode {
|
||||
OMAP_DMA_TRANSPARENT_COPY
|
||||
};
|
||||
|
||||
enum omap_dma_write_mode {
|
||||
OMAP_DMA_WRITE_NON_POSTED = 0,
|
||||
OMAP_DMA_WRITE_POSTED,
|
||||
OMAP_DMA_WRITE_LAST_NON_POSTED
|
||||
};
|
||||
|
||||
struct omap_dma_channel_params {
|
||||
int data_type; /* data type 8,16,32 */
|
||||
int elem_count; /* number of elements in a frame */
|
||||
@@ -338,13 +344,13 @@ struct omap_dma_channel_params {
|
||||
|
||||
int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
|
||||
int src_amode; /* constant , post increment, indexed , double indexed */
|
||||
int src_start; /* source address : physical */
|
||||
unsigned long src_start; /* source address : physical */
|
||||
int src_ei; /* source element index */
|
||||
int src_fi; /* source frame index */
|
||||
|
||||
int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
|
||||
int dst_amode; /* constant , post increment, indexed , double indexed */
|
||||
int dst_start; /* source address : physical */
|
||||
unsigned long dst_start; /* source address : physical */
|
||||
int dst_ei; /* source element index */
|
||||
int dst_fi; /* source frame index */
|
||||
|
||||
@@ -356,7 +362,7 @@ struct omap_dma_channel_params {
|
||||
};
|
||||
|
||||
|
||||
extern void omap_set_dma_priority(int dst_port, int priority);
|
||||
extern void omap_set_dma_priority(int lch, int dst_port, int priority);
|
||||
extern int omap_request_dma(int dev_id, const char *dev_name,
|
||||
void (* callback)(int lch, u16 ch_status, void *data),
|
||||
void *data, int *dma_ch);
|
||||
@@ -371,6 +377,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type,
|
||||
int dma_trigger, int src_or_dst_synch);
|
||||
extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
|
||||
u32 color);
|
||||
extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
|
||||
|
||||
extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
|
||||
unsigned long src_start,
|
||||
@@ -394,6 +401,9 @@ extern void omap_set_dma_params(int lch,
|
||||
extern void omap_dma_link_lch (int lch_head, int lch_queue);
|
||||
extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
|
||||
|
||||
extern int omap_set_dma_callback(int lch,
|
||||
void (* callback)(int lch, u16 ch_status, void *data),
|
||||
void *data);
|
||||
extern dma_addr_t omap_get_dma_src_pos(int lch);
|
||||
extern dma_addr_t omap_get_dma_dst_pos(int lch);
|
||||
extern int omap_get_dma_src_addr_counter(int lch);
|
||||
|
||||
@@ -52,6 +52,8 @@ int omap_dm_timer_init(void);
|
||||
struct omap_dm_timer *omap_dm_timer_request(void);
|
||||
struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
|
||||
void omap_dm_timer_free(struct omap_dm_timer *timer);
|
||||
void omap_dm_timer_enable(struct omap_dm_timer *timer);
|
||||
void omap_dm_timer_disable(struct omap_dm_timer *timer);
|
||||
|
||||
int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
|
||||
|
||||
|
||||
@@ -85,7 +85,7 @@ extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
|
||||
extern u32 gpmc_cs_read_reg(int cs, int idx);
|
||||
extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk);
|
||||
extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
|
||||
extern unsigned long gpmc_cs_get_base_addr(int cs);
|
||||
|
||||
extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
|
||||
extern void gpmc_cs_free(int cs);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -237,6 +237,7 @@
|
||||
#define INT_24XX_SDMA_IRQ1 13
|
||||
#define INT_24XX_SDMA_IRQ2 14
|
||||
#define INT_24XX_SDMA_IRQ3 15
|
||||
#define INT_24XX_CAM_IRQ 24
|
||||
#define INT_24XX_DSS_IRQ 25
|
||||
#define INT_24XX_GPIO_BANK1 29
|
||||
#define INT_24XX_GPIO_BANK2 30
|
||||
@@ -261,6 +262,7 @@
|
||||
#define INT_24XX_UART1_IRQ 72
|
||||
#define INT_24XX_UART2_IRQ 73
|
||||
#define INT_24XX_UART3_IRQ 74
|
||||
#define INT_24XX_MMC_IRQ 83
|
||||
|
||||
/* Max. 128 level 2 IRQs (OMAP1610), 192 GPIOs (OMAP730) and
|
||||
* 16 MPUIO lines */
|
||||
|
||||
@@ -320,6 +320,17 @@ enum omap1xxx_index {
|
||||
P15_1610_UWIRE_CS3,
|
||||
N15_1610_UWIRE_CS1,
|
||||
|
||||
/* OMAP-1610 SPI */
|
||||
U19_1610_SPIF_SCK,
|
||||
U18_1610_SPIF_DIN,
|
||||
P20_1610_SPIF_DIN,
|
||||
W21_1610_SPIF_DOUT,
|
||||
R18_1610_SPIF_DOUT,
|
||||
N14_1610_SPIF_CS0,
|
||||
N15_1610_SPIF_CS1,
|
||||
T19_1610_SPIF_CS2,
|
||||
P15_1610_SPIF_CS3,
|
||||
|
||||
/* OMAP-1610 Flash */
|
||||
L3_1610_FLASH_CS2B_OE,
|
||||
M8_1610_FLASH_CS2B_WE,
|
||||
@@ -461,6 +472,20 @@ enum omap24xx_index {
|
||||
K15_24XX_UART3_TX,
|
||||
K14_24XX_UART3_RX,
|
||||
|
||||
/* MMC/SDIO */
|
||||
G19_24XX_MMC_CLKO,
|
||||
H18_24XX_MMC_CMD,
|
||||
F20_24XX_MMC_DAT0,
|
||||
H14_24XX_MMC_DAT1,
|
||||
E19_24XX_MMC_DAT2,
|
||||
D19_24XX_MMC_DAT3,
|
||||
F19_24XX_MMC_DAT_DIR0,
|
||||
E20_24XX_MMC_DAT_DIR1,
|
||||
F18_24XX_MMC_DAT_DIR2,
|
||||
E18_24XX_MMC_DAT_DIR3,
|
||||
G18_24XX_MMC_CMD_DIR,
|
||||
H15_24XX_MMC_CLKI,
|
||||
|
||||
/* Keypad GPIO*/
|
||||
T19_24XX_KBR0,
|
||||
R19_24XX_KBR1,
|
||||
|
||||
@@ -23,6 +23,39 @@
|
||||
#define MAX_DMA_ADDRESS 0x40000000
|
||||
#define MAX_DMA_TRANSFER_SIZE 0x100000 /* Data Unit is half word */
|
||||
|
||||
/* We use `virtual` dma channels to hide the fact we have only a limited
|
||||
* number of DMA channels, and not of all of them (dependant on the device)
|
||||
* can be attached to any DMA source. We therefore let the DMA core handle
|
||||
* the allocation of hardware channels to clients.
|
||||
*/
|
||||
|
||||
enum dma_ch {
|
||||
DMACH_XD0,
|
||||
DMACH_XD1,
|
||||
DMACH_SDI,
|
||||
DMACH_SPI0,
|
||||
DMACH_SPI1,
|
||||
DMACH_UART0,
|
||||
DMACH_UART1,
|
||||
DMACH_UART2,
|
||||
DMACH_TIMER,
|
||||
DMACH_I2S_IN,
|
||||
DMACH_I2S_OUT,
|
||||
DMACH_PCM_IN,
|
||||
DMACH_PCM_OUT,
|
||||
DMACH_MIC_IN,
|
||||
DMACH_USB_EP1,
|
||||
DMACH_USB_EP2,
|
||||
DMACH_USB_EP3,
|
||||
DMACH_USB_EP4,
|
||||
DMACH_UART0_SRC2, /* s3c2412 second uart sources */
|
||||
DMACH_UART1_SRC2,
|
||||
DMACH_UART2_SRC2,
|
||||
DMACH_MAX, /* the end entry */
|
||||
};
|
||||
|
||||
#define DMACH_LOW_LEVEL (1<<28) /* use this to specifiy hardware ch no */
|
||||
|
||||
/* we have 4 dma channels */
|
||||
#define S3C2410_DMA_CHANNELS (4)
|
||||
|
||||
@@ -149,6 +182,8 @@ struct s3c2410_dma_stats {
|
||||
unsigned long timeout_failed;
|
||||
};
|
||||
|
||||
struct s3c2410_dma_map;
|
||||
|
||||
/* struct s3c2410_dma_chan
|
||||
*
|
||||
* full state information for each DMA channel
|
||||
@@ -174,6 +209,8 @@ struct s3c2410_dma_chan {
|
||||
unsigned long load_timeout;
|
||||
unsigned int flags; /* channel flags */
|
||||
|
||||
struct s3c24xx_dma_map *map; /* channel hw maps */
|
||||
|
||||
/* channel's hardware position and configuration */
|
||||
void __iomem *regs; /* channels registers */
|
||||
void __iomem *addr_reg; /* data address register */
|
||||
@@ -283,6 +320,7 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
|
||||
#define S3C2410_DMA_DCSRC (0x18)
|
||||
#define S3C2410_DMA_DCDST (0x1C)
|
||||
#define S3C2410_DMA_DMASKTRIG (0x20)
|
||||
#define S3C2412_DMA_DMAREQSEL (0x24)
|
||||
|
||||
#define S3C2410_DISRCC_INC (1<<0)
|
||||
#define S3C2410_DISRCC_APB (1<<1)
|
||||
@@ -349,4 +387,32 @@ extern int s3c2410_dma_set_buffdone_fn(dmach_t, s3c2410_dma_cbfn_t rtn);
|
||||
#define S3C2440_DCON_CH3_PCMOUT (6<<24)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2412
|
||||
|
||||
#define S3C2412_DMAREQSEL_SRC(x) ((x)<<1)
|
||||
|
||||
#define S3C2412_DMAREQSEL_HW (1)
|
||||
|
||||
#define S3C2412_DMAREQSEL_SPI0TX S3C2412_DMAREQSEL_SRC(0)
|
||||
#define S3C2412_DMAREQSEL_SPI0RX S3C2412_DMAREQSEL_SRC(1)
|
||||
#define S3C2412_DMAREQSEL_SPI1TX S3C2412_DMAREQSEL_SRC(2)
|
||||
#define S3C2412_DMAREQSEL_SPI1RX S3C2412_DMAREQSEL_SRC(3)
|
||||
#define S3C2412_DMAREQSEL_I2STX S3C2412_DMAREQSEL_SRC(4)
|
||||
#define S3C2412_DMAREQSEL_I2SRX S3C2412_DMAREQSEL_SRC(5)
|
||||
#define S3C2412_DMAREQSEL_TIMER S3C2412_DMAREQSEL_SRC(9)
|
||||
#define S3C2412_DMAREQSEL_SDI S3C2412_DMAREQSEL_SRC(10)
|
||||
#define S3C2412_DMAREQSEL_USBEP1 S3C2412_DMAREQSEL_SRC(13)
|
||||
#define S3C2412_DMAREQSEL_USBEP2 S3C2412_DMAREQSEL_SRC(14)
|
||||
#define S3C2412_DMAREQSEL_USBEP3 S3C2412_DMAREQSEL_SRC(15)
|
||||
#define S3C2412_DMAREQSEL_USBEP4 S3C2412_DMAREQSEL_SRC(16)
|
||||
#define S3C2412_DMAREQSEL_XDREQ0 S3C2412_DMAREQSEL_SRC(17)
|
||||
#define S3C2412_DMAREQSEL_XDREQ1 S3C2412_DMAREQSEL_SRC(18)
|
||||
#define S3C2412_DMAREQSEL_UART0_0 S3C2412_DMAREQSEL_SRC(19)
|
||||
#define S3C2412_DMAREQSEL_UART0_1 S3C2412_DMAREQSEL_SRC(20)
|
||||
#define S3C2412_DMAREQSEL_UART1_0 S3C2412_DMAREQSEL_SRC(21)
|
||||
#define S3C2412_DMAREQSEL_UART1_1 S3C2412_DMAREQSEL_SRC(22)
|
||||
#define S3C2412_DMAREQSEL_UART2_0 S3C2412_DMAREQSEL_SRC(23)
|
||||
#define S3C2412_DMAREQSEL_UART2_1 S3C2412_DMAREQSEL_SRC(24)
|
||||
|
||||
#endif
|
||||
#endif /* __ASM_ARCH_DMA_H */
|
||||
|
||||
@@ -160,6 +160,11 @@
|
||||
#define S3C2440_PA_CAMIF (0x4F000000)
|
||||
#define S3C2440_SZ_CAMIF SZ_1M
|
||||
|
||||
/* AC97 */
|
||||
|
||||
#define S3C2440_PA_AC97 (0x5B000000)
|
||||
#define S3C2440_SZ_AC97 SZ_1M
|
||||
|
||||
/* ISA style IO, for each machine to sort out mappings for, if it
|
||||
* implements it. We reserve two 16M regions for ISA.
|
||||
*/
|
||||
|
||||
@@ -18,22 +18,22 @@
|
||||
|
||||
/* start peripherals off after the S3C2410 */
|
||||
|
||||
#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x05000000))
|
||||
#define OSIRIS_IOADDR(x) (S3C2410_ADDR((x) + 0x04000000))
|
||||
|
||||
#define OSIRIS_PA_CPLD (S3C2410_CS1 | (3<<25))
|
||||
#define OSIRIS_PA_CPLD (S3C2410_CS1 | (1<<26))
|
||||
|
||||
/* we put the CPLD registers next, to get them out of the way */
|
||||
|
||||
#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00000000) /* 0x01300000 */
|
||||
#define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00000000)
|
||||
#define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD)
|
||||
|
||||
#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00100000) /* 0x01400000 */
|
||||
#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (1<<24))
|
||||
#define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00100000)
|
||||
#define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (1<<23))
|
||||
|
||||
#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00200000) /* 0x01500000 */
|
||||
#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<24))
|
||||
#define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00200000)
|
||||
#define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23))
|
||||
|
||||
#define OSIRIS_VA_CTRL4 OSIRIS_IOADDR(0x00300000) /* 0x01600000 */
|
||||
#define OSIRIS_PA_CTRL4 (OSIRIS_PA_CPLD + (3<<24))
|
||||
#define OSIRIS_VA_CTRL4 OSIRIS_IOADDR(0x00300000)
|
||||
#define OSIRIS_PA_CTRL4 (OSIRIS_PA_CPLD + (3<<23))
|
||||
|
||||
#endif /* __ASM_ARCH_OSIRISMAP_H */
|
||||
|
||||
@@ -0,0 +1,23 @@
|
||||
/* linux/include/asm-arm/arch-s3c2410/regs-ac97.h
|
||||
*
|
||||
* Copyright (c) 2006 Simtec Electronics <linux@simtec.co.uk>
|
||||
* http://www.simtec.co.uk/products/SWLINUX/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* S3C2440 AC97 Controller
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_AC97_H
|
||||
#define __ASM_ARCH_REGS_AC97_H __FILE__
|
||||
|
||||
#define S3C_AC97_GLBCTRL (0x00)
|
||||
#define S3C_AC97_GLBSTAT (0x04)
|
||||
#define S3C_AC97_CODEC_CMD (0x08)
|
||||
#define S3C_AC97_PCM_ADDR (0x10)
|
||||
#define S3C_AC97_PCM_DATA (0x18)
|
||||
#define S3C_AC97_MIC_DATA (0x1C)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_AC97_H */
|
||||
@@ -63,6 +63,8 @@
|
||||
#define S3C2410_LCDCON3_GET_HBPD(x) ( ((x) >> 19) & 0x7F)
|
||||
#define S3C2410_LCDCON3_GET_HFPD(x) ( ((x) >> 0) & 0xFF)
|
||||
|
||||
/* LDCCON4 changes for STN mode on the S3C2412 */
|
||||
|
||||
#define S3C2410_LCDCON4_MVAL(x) ((x) << 8)
|
||||
#define S3C2410_LCDCON4_HSPW(x) ((x) << 0)
|
||||
#define S3C2410_LCDCON4_WLH(x) ((x) << 0)
|
||||
@@ -113,10 +115,38 @@
|
||||
#define S3C2410_LCDINT_FRSYNC (1<<1)
|
||||
#define S3C2410_LCDINT_FICNT (1<<0)
|
||||
|
||||
/* s3c2442 extra stn registers */
|
||||
|
||||
#define S3C2442_REDLUT S3C2410_LCDREG(0x20)
|
||||
#define S3C2442_GREENLUT S3C2410_LCDREG(0x24)
|
||||
#define S3C2442_BLUELUT S3C2410_LCDREG(0x28)
|
||||
#define S3C2442_DITHMODE S3C2410_LCDREG(0x20)
|
||||
|
||||
#define S3C2410_LPCSEL S3C2410_LCDREG(0x60)
|
||||
|
||||
#define S3C2410_TFTPAL(x) S3C2410_LCDREG((0x400 + (x)*4))
|
||||
|
||||
/* S3C2412 registers */
|
||||
|
||||
#define S3C2412_TPAL S3C2410_LCDREG(0x20)
|
||||
|
||||
#define S3C2412_LCDINTPND S3C2410_LCDREG(0x24)
|
||||
#define S3C2412_LCDSRCPND S3C2410_LCDREG(0x28)
|
||||
#define S3C2412_LCDINTMSK S3C2410_LCDREG(0x2C)
|
||||
|
||||
#define S3C2412_TCONSEL S3C2410_LCDREG(0x30)
|
||||
|
||||
#define S3C2412_LCDCON6 S3C2410_LCDREG(0x34)
|
||||
#define S3C2412_LCDCON7 S3C2410_LCDREG(0x38)
|
||||
#define S3C2412_LCDCON8 S3C2410_LCDREG(0x3C)
|
||||
#define S3C2412_LCDCON9 S3C2410_LCDREG(0x40)
|
||||
|
||||
#define S3C2412_REDLUT(x) S3C2410_LCDREG(0x44 + ((x)*4))
|
||||
#define S3C2412_GREENLUT(x) S3C2410_LCDREG(0x60 + ((x)*4))
|
||||
#define S3C2412_BLUELUT(x) S3C2410_LCDREG(0x98 + ((x)*4))
|
||||
|
||||
#define S3C2412_FRCPAT(x) S3C2410_LCDREG(0xB4 + ((x)*4))
|
||||
|
||||
#endif /* ___ASM_ARCH_REGS_LCD_H */
|
||||
|
||||
|
||||
|
||||
@@ -128,10 +128,10 @@ static inline int atomic_add_return(int i, atomic_t *v)
|
||||
unsigned long flags;
|
||||
int val;
|
||||
|
||||
local_irq_save(flags);
|
||||
raw_local_irq_save(flags);
|
||||
val = v->counter;
|
||||
v->counter = val += i;
|
||||
local_irq_restore(flags);
|
||||
raw_local_irq_restore(flags);
|
||||
|
||||
return val;
|
||||
}
|
||||
@@ -141,10 +141,10 @@ static inline int atomic_sub_return(int i, atomic_t *v)
|
||||
unsigned long flags;
|
||||
int val;
|
||||
|
||||
local_irq_save(flags);
|
||||
raw_local_irq_save(flags);
|
||||
val = v->counter;
|
||||
v->counter = val -= i;
|
||||
local_irq_restore(flags);
|
||||
raw_local_irq_restore(flags);
|
||||
|
||||
return val;
|
||||
}
|
||||
@@ -154,11 +154,11 @@ static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
|
||||
int ret;
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
raw_local_irq_save(flags);
|
||||
ret = v->counter;
|
||||
if (likely(ret == old))
|
||||
v->counter = new;
|
||||
local_irq_restore(flags);
|
||||
raw_local_irq_restore(flags);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@@ -167,9 +167,9 @@ static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
local_irq_save(flags);
|
||||
raw_local_irq_save(flags);
|
||||
*addr &= ~mask;
|
||||
local_irq_restore(flags);
|
||||
raw_local_irq_restore(flags);
|
||||
}
|
||||
|
||||
#endif /* __LINUX_ARM_ARCH__ */
|
||||
|
||||
+12
-12
@@ -37,9 +37,9 @@ static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *
|
||||
|
||||
p += bit >> 5;
|
||||
|
||||
local_irq_save(flags);
|
||||
raw_local_irq_save(flags);
|
||||
*p |= mask;
|
||||
local_irq_restore(flags);
|
||||
raw_local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p)
|
||||
@@ -49,9 +49,9 @@ static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long
|
||||
|
||||
p += bit >> 5;
|
||||
|
||||
local_irq_save(flags);
|
||||
raw_local_irq_save(flags);
|
||||
*p &= ~mask;
|
||||
local_irq_restore(flags);
|
||||
raw_local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p)
|
||||
@@ -61,9 +61,9 @@ static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned lon
|
||||
|
||||
p += bit >> 5;
|
||||
|
||||
local_irq_save(flags);
|
||||
raw_local_irq_save(flags);
|
||||
*p ^= mask;
|
||||
local_irq_restore(flags);
|
||||
raw_local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static inline int
|
||||
@@ -75,10 +75,10 @@ ____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p)
|
||||
|
||||
p += bit >> 5;
|
||||
|
||||
local_irq_save(flags);
|
||||
raw_local_irq_save(flags);
|
||||
res = *p;
|
||||
*p = res | mask;
|
||||
local_irq_restore(flags);
|
||||
raw_local_irq_restore(flags);
|
||||
|
||||
return res & mask;
|
||||
}
|
||||
@@ -92,10 +92,10 @@ ____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p)
|
||||
|
||||
p += bit >> 5;
|
||||
|
||||
local_irq_save(flags);
|
||||
raw_local_irq_save(flags);
|
||||
res = *p;
|
||||
*p = res & ~mask;
|
||||
local_irq_restore(flags);
|
||||
raw_local_irq_restore(flags);
|
||||
|
||||
return res & mask;
|
||||
}
|
||||
@@ -109,10 +109,10 @@ ____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p)
|
||||
|
||||
p += bit >> 5;
|
||||
|
||||
local_irq_save(flags);
|
||||
raw_local_irq_save(flags);
|
||||
res = *p;
|
||||
*p = res ^ mask;
|
||||
local_irq_restore(flags);
|
||||
raw_local_irq_restore(flags);
|
||||
|
||||
return res & mask;
|
||||
}
|
||||
|
||||
@@ -25,7 +25,7 @@
|
||||
#undef _CACHE
|
||||
#undef MULTI_CACHE
|
||||
|
||||
#if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
|
||||
#if defined(CONFIG_CPU_CACHE_V3)
|
||||
# ifdef _CACHE
|
||||
# define MULTI_CACHE 1
|
||||
# else
|
||||
@@ -33,7 +33,7 @@
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_ARM720T)
|
||||
#if defined(CONFIG_CPU_CACHE_V4)
|
||||
# ifdef _CACHE
|
||||
# define MULTI_CACHE 1
|
||||
# else
|
||||
@@ -54,7 +54,23 @@
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SA110) || defined(CONFIG_CPU_SA1100)
|
||||
#if defined(CONFIG_CPU_ARM940T)
|
||||
# ifdef _CACHE
|
||||
# define MULTI_CACHE 1
|
||||
# else
|
||||
# define _CACHE arm940
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_ARM946E)
|
||||
# ifdef _CACHE
|
||||
# define MULTI_CACHE 1
|
||||
# else
|
||||
# define _CACHE arm946
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_CACHE_V4WB)
|
||||
# ifdef _CACHE
|
||||
# define MULTI_CACHE 1
|
||||
# else
|
||||
|
||||
@@ -0,0 +1,16 @@
|
||||
/*
|
||||
* include/asm-arm/flat.h -- uClinux flat-format executables
|
||||
*/
|
||||
|
||||
#ifndef __ARM_FLAT_H__
|
||||
#define __ARM_FLAT_H__
|
||||
|
||||
#define flat_stack_align(sp) /* nothing needed */
|
||||
#define flat_argvp_envp_on_stack() 1
|
||||
#define flat_old_ram_flag(flags) (flags)
|
||||
#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
|
||||
#define flat_get_addr_from_rp(rp, relval, flags) get_unaligned(rp)
|
||||
#define flat_put_addr_at_rp(rp, val, relval) put_unaligned(val,rp)
|
||||
#define flat_get_relocate_addr(rel) (rel)
|
||||
|
||||
#endif /* __ARM_FLAT_H__ */
|
||||
@@ -0,0 +1,301 @@
|
||||
/*
|
||||
* include/asm-arm/hardware/iop3xx.h
|
||||
*
|
||||
* Intel IOP32X and IOP33X register definitions
|
||||
*
|
||||
* Author: Rory Bolt <rorybolt@pacbell.net>
|
||||
* Copyright (C) 2002 Rory Bolt
|
||||
* Copyright (C) 2004 Intel Corp.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __IOP3XX_H
|
||||
#define __IOP3XX_H
|
||||
|
||||
/*
|
||||
* IOP3XX GPIO handling
|
||||
*/
|
||||
#define GPIO_IN 0
|
||||
#define GPIO_OUT 1
|
||||
#define GPIO_LOW 0
|
||||
#define GPIO_HIGH 1
|
||||
#define IOP3XX_GPIO_LINE(x) (x)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
extern void gpio_line_config(int line, int direction);
|
||||
extern int gpio_line_get(int line);
|
||||
extern void gpio_line_set(int line, int value);
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* IOP3XX processor registers
|
||||
*/
|
||||
#define IOP3XX_PERIPHERAL_PHYS_BASE 0xffffe000
|
||||
#define IOP3XX_PERIPHERAL_VIRT_BASE 0xfeffe000
|
||||
#define IOP3XX_PERIPHERAL_SIZE 0x00002000
|
||||
#define IOP3XX_REG_ADDR(reg) (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
|
||||
|
||||
/* Address Translation Unit */
|
||||
#define IOP3XX_ATUVID (volatile u16 *)IOP3XX_REG_ADDR(0x0100)
|
||||
#define IOP3XX_ATUDID (volatile u16 *)IOP3XX_REG_ADDR(0x0102)
|
||||
#define IOP3XX_ATUCMD (volatile u16 *)IOP3XX_REG_ADDR(0x0104)
|
||||
#define IOP3XX_ATUSR (volatile u16 *)IOP3XX_REG_ADDR(0x0106)
|
||||
#define IOP3XX_ATURID (volatile u8 *)IOP3XX_REG_ADDR(0x0108)
|
||||
#define IOP3XX_ATUCCR (volatile u32 *)IOP3XX_REG_ADDR(0x0109)
|
||||
#define IOP3XX_ATUCLSR (volatile u8 *)IOP3XX_REG_ADDR(0x010c)
|
||||
#define IOP3XX_ATULT (volatile u8 *)IOP3XX_REG_ADDR(0x010d)
|
||||
#define IOP3XX_ATUHTR (volatile u8 *)IOP3XX_REG_ADDR(0x010e)
|
||||
#define IOP3XX_ATUBIST (volatile u8 *)IOP3XX_REG_ADDR(0x010f)
|
||||
#define IOP3XX_IABAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0110)
|
||||
#define IOP3XX_IAUBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0114)
|
||||
#define IOP3XX_IABAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0118)
|
||||
#define IOP3XX_IAUBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x011c)
|
||||
#define IOP3XX_IABAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0120)
|
||||
#define IOP3XX_IAUBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0124)
|
||||
#define IOP3XX_ASVIR (volatile u16 *)IOP3XX_REG_ADDR(0x012c)
|
||||
#define IOP3XX_ASIR (volatile u16 *)IOP3XX_REG_ADDR(0x012e)
|
||||
#define IOP3XX_ERBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0130)
|
||||
#define IOP3XX_ATUILR (volatile u8 *)IOP3XX_REG_ADDR(0x013c)
|
||||
#define IOP3XX_ATUIPR (volatile u8 *)IOP3XX_REG_ADDR(0x013d)
|
||||
#define IOP3XX_ATUMGNT (volatile u8 *)IOP3XX_REG_ADDR(0x013e)
|
||||
#define IOP3XX_ATUMLAT (volatile u8 *)IOP3XX_REG_ADDR(0x013f)
|
||||
#define IOP3XX_IALR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0140)
|
||||
#define IOP3XX_IATVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0144)
|
||||
#define IOP3XX_ERLR (volatile u32 *)IOP3XX_REG_ADDR(0x0148)
|
||||
#define IOP3XX_ERTVR (volatile u32 *)IOP3XX_REG_ADDR(0x014c)
|
||||
#define IOP3XX_IALR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0150)
|
||||
#define IOP3XX_IALR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0154)
|
||||
#define IOP3XX_IATVR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0158)
|
||||
#define IOP3XX_OIOWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x015c)
|
||||
#define IOP3XX_OMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0160)
|
||||
#define IOP3XX_OUMWTVR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0164)
|
||||
#define IOP3XX_OMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0168)
|
||||
#define IOP3XX_OUMWTVR1 (volatile u32 *)IOP3XX_REG_ADDR(0x016c)
|
||||
#define IOP3XX_OUDWTVR (volatile u32 *)IOP3XX_REG_ADDR(0x0178)
|
||||
#define IOP3XX_ATUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0180)
|
||||
#define IOP3XX_PCSR (volatile u32 *)IOP3XX_REG_ADDR(0x0184)
|
||||
#define IOP3XX_ATUISR (volatile u32 *)IOP3XX_REG_ADDR(0x0188)
|
||||
#define IOP3XX_ATUIMR (volatile u32 *)IOP3XX_REG_ADDR(0x018c)
|
||||
#define IOP3XX_IABAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0190)
|
||||
#define IOP3XX_IAUBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0194)
|
||||
#define IOP3XX_IALR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0198)
|
||||
#define IOP3XX_IATVR3 (volatile u32 *)IOP3XX_REG_ADDR(0x019c)
|
||||
#define IOP3XX_OCCAR (volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
|
||||
#define IOP3XX_OCCDR (volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
|
||||
#define IOP3XX_PDSCR (volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
|
||||
#define IOP3XX_PMCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01c0)
|
||||
#define IOP3XX_PMNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01c1)
|
||||
#define IOP3XX_APMCR (volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
|
||||
#define IOP3XX_APMCSR (volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
|
||||
#define IOP3XX_PCIXCAPID (volatile u8 *)IOP3XX_REG_ADDR(0x01e0)
|
||||
#define IOP3XX_PCIXNEXT (volatile u8 *)IOP3XX_REG_ADDR(0x01e1)
|
||||
#define IOP3XX_PCIXCMD (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
|
||||
#define IOP3XX_PCIXSR (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
|
||||
#define IOP3XX_PCIIRSR (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
|
||||
|
||||
/* Messaging Unit */
|
||||
#define IOP3XX_IMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
|
||||
#define IOP3XX_IMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0314)
|
||||
#define IOP3XX_OMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0318)
|
||||
#define IOP3XX_OMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x031c)
|
||||
#define IOP3XX_IDR (volatile u32 *)IOP3XX_REG_ADDR(0x0320)
|
||||
#define IOP3XX_IISR (volatile u32 *)IOP3XX_REG_ADDR(0x0324)
|
||||
#define IOP3XX_IIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0328)
|
||||
#define IOP3XX_ODR (volatile u32 *)IOP3XX_REG_ADDR(0x032c)
|
||||
#define IOP3XX_OISR (volatile u32 *)IOP3XX_REG_ADDR(0x0330)
|
||||
#define IOP3XX_OIMR (volatile u32 *)IOP3XX_REG_ADDR(0x0334)
|
||||
#define IOP3XX_MUCR (volatile u32 *)IOP3XX_REG_ADDR(0x0350)
|
||||
#define IOP3XX_QBAR (volatile u32 *)IOP3XX_REG_ADDR(0x0354)
|
||||
#define IOP3XX_IFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0360)
|
||||
#define IOP3XX_IFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0364)
|
||||
#define IOP3XX_IPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0368)
|
||||
#define IOP3XX_IPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x036c)
|
||||
#define IOP3XX_OFHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0370)
|
||||
#define IOP3XX_OFTPR (volatile u32 *)IOP3XX_REG_ADDR(0x0374)
|
||||
#define IOP3XX_OPHPR (volatile u32 *)IOP3XX_REG_ADDR(0x0378)
|
||||
#define IOP3XX_OPTPR (volatile u32 *)IOP3XX_REG_ADDR(0x037c)
|
||||
#define IOP3XX_IAR (volatile u32 *)IOP3XX_REG_ADDR(0x0380)
|
||||
|
||||
/* DMA Controller */
|
||||
#define IOP3XX_DMA0_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0400)
|
||||
#define IOP3XX_DMA0_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0404)
|
||||
#define IOP3XX_DMA0_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x040c)
|
||||
#define IOP3XX_DMA0_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0410)
|
||||
#define IOP3XX_DMA0_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0414)
|
||||
#define IOP3XX_DMA0_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0418)
|
||||
#define IOP3XX_DMA0_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x041c)
|
||||
#define IOP3XX_DMA0_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0420)
|
||||
#define IOP3XX_DMA0_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0424)
|
||||
#define IOP3XX_DMA1_CCR (volatile u32 *)IOP3XX_REG_ADDR(0x0440)
|
||||
#define IOP3XX_DMA1_CSR (volatile u32 *)IOP3XX_REG_ADDR(0x0444)
|
||||
#define IOP3XX_DMA1_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x044c)
|
||||
#define IOP3XX_DMA1_NDAR (volatile u32 *)IOP3XX_REG_ADDR(0x0450)
|
||||
#define IOP3XX_DMA1_PADR (volatile u32 *)IOP3XX_REG_ADDR(0x0454)
|
||||
#define IOP3XX_DMA1_PUADR (volatile u32 *)IOP3XX_REG_ADDR(0x0458)
|
||||
#define IOP3XX_DMA1_LADR (volatile u32 *)IOP3XX_REG_ADDR(0x045c)
|
||||
#define IOP3XX_DMA1_BCR (volatile u32 *)IOP3XX_REG_ADDR(0x0460)
|
||||
#define IOP3XX_DMA1_DCR (volatile u32 *)IOP3XX_REG_ADDR(0x0464)
|
||||
|
||||
/* Peripheral bus interface */
|
||||
#define IOP3XX_PBCR (volatile u32 *)IOP3XX_REG_ADDR(0x0680)
|
||||
#define IOP3XX_PBISR (volatile u32 *)IOP3XX_REG_ADDR(0x0684)
|
||||
#define IOP3XX_PBBAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0688)
|
||||
#define IOP3XX_PBLR0 (volatile u32 *)IOP3XX_REG_ADDR(0x068c)
|
||||
#define IOP3XX_PBBAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0690)
|
||||
#define IOP3XX_PBLR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0694)
|
||||
#define IOP3XX_PBBAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0698)
|
||||
#define IOP3XX_PBLR2 (volatile u32 *)IOP3XX_REG_ADDR(0x069c)
|
||||
#define IOP3XX_PBBAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a0)
|
||||
#define IOP3XX_PBLR3 (volatile u32 *)IOP3XX_REG_ADDR(0x06a4)
|
||||
#define IOP3XX_PBBAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06a8)
|
||||
#define IOP3XX_PBLR4 (volatile u32 *)IOP3XX_REG_ADDR(0x06ac)
|
||||
#define IOP3XX_PBBAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b0)
|
||||
#define IOP3XX_PBLR5 (volatile u32 *)IOP3XX_REG_ADDR(0x06b4)
|
||||
#define IOP3XX_PMBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x06c0)
|
||||
#define IOP3XX_PMBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x06e0)
|
||||
#define IOP3XX_PMBR2 (volatile u32 *)IOP3XX_REG_ADDR(0x06e4)
|
||||
|
||||
/* Peripheral performance monitoring unit */
|
||||
#define IOP3XX_GTMR (volatile u32 *)IOP3XX_REG_ADDR(0x0700)
|
||||
#define IOP3XX_ESR (volatile u32 *)IOP3XX_REG_ADDR(0x0704)
|
||||
#define IOP3XX_EMISR (volatile u32 *)IOP3XX_REG_ADDR(0x0708)
|
||||
#define IOP3XX_GTSR (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
|
||||
/* PERCR0 DOESN'T EXIST - index from 1! */
|
||||
#define IOP3XX_PERCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x0710)
|
||||
|
||||
/* General Purpose I/O */
|
||||
#define IOP3XX_GPOE (volatile u32 *)IOP3XX_GPIO_REG(0x0004)
|
||||
#define IOP3XX_GPID (volatile u32 *)IOP3XX_GPIO_REG(0x0008)
|
||||
#define IOP3XX_GPOD (volatile u32 *)IOP3XX_GPIO_REG(0x000c)
|
||||
|
||||
/* Timers */
|
||||
#define IOP3XX_TU_TMR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0000)
|
||||
#define IOP3XX_TU_TMR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0004)
|
||||
#define IOP3XX_TU_TCR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0008)
|
||||
#define IOP3XX_TU_TCR1 (volatile u32 *)IOP3XX_TIMER_REG(0x000c)
|
||||
#define IOP3XX_TU_TRR0 (volatile u32 *)IOP3XX_TIMER_REG(0x0010)
|
||||
#define IOP3XX_TU_TRR1 (volatile u32 *)IOP3XX_TIMER_REG(0x0014)
|
||||
#define IOP3XX_TU_TISR (volatile u32 *)IOP3XX_TIMER_REG(0x0018)
|
||||
#define IOP3XX_TU_WDTCR (volatile u32 *)IOP3XX_TIMER_REG(0x001c)
|
||||
#define IOP3XX_TMR_TC 0x01
|
||||
#define IOP3XX_TMR_EN 0x02
|
||||
#define IOP3XX_TMR_RELOAD 0x04
|
||||
#define IOP3XX_TMR_PRIVILEGED 0x09
|
||||
#define IOP3XX_TMR_RATIO_1_1 0x00
|
||||
#define IOP3XX_TMR_RATIO_4_1 0x10
|
||||
#define IOP3XX_TMR_RATIO_8_1 0x20
|
||||
#define IOP3XX_TMR_RATIO_16_1 0x30
|
||||
|
||||
/* Application accelerator unit */
|
||||
#define IOP3XX_AAU_ACR (volatile u32 *)IOP3XX_REG_ADDR(0x0800)
|
||||
#define IOP3XX_AAU_ASR (volatile u32 *)IOP3XX_REG_ADDR(0x0804)
|
||||
#define IOP3XX_AAU_ADAR (volatile u32 *)IOP3XX_REG_ADDR(0x0808)
|
||||
#define IOP3XX_AAU_ANDAR (volatile u32 *)IOP3XX_REG_ADDR(0x080c)
|
||||
#define IOP3XX_AAU_SAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0810)
|
||||
#define IOP3XX_AAU_SAR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0814)
|
||||
#define IOP3XX_AAU_SAR3 (volatile u32 *)IOP3XX_REG_ADDR(0x0818)
|
||||
#define IOP3XX_AAU_SAR4 (volatile u32 *)IOP3XX_REG_ADDR(0x081c)
|
||||
#define IOP3XX_AAU_DAR (volatile u32 *)IOP3XX_REG_ADDR(0x0820)
|
||||
#define IOP3XX_AAU_ABCR (volatile u32 *)IOP3XX_REG_ADDR(0x0824)
|
||||
#define IOP3XX_AAU_ADCR (volatile u32 *)IOP3XX_REG_ADDR(0x0828)
|
||||
#define IOP3XX_AAU_SAR5 (volatile u32 *)IOP3XX_REG_ADDR(0x082c)
|
||||
#define IOP3XX_AAU_SAR6 (volatile u32 *)IOP3XX_REG_ADDR(0x0830)
|
||||
#define IOP3XX_AAU_SAR7 (volatile u32 *)IOP3XX_REG_ADDR(0x0834)
|
||||
#define IOP3XX_AAU_SAR8 (volatile u32 *)IOP3XX_REG_ADDR(0x0838)
|
||||
#define IOP3XX_AAU_EDCR0 (volatile u32 *)IOP3XX_REG_ADDR(0x083c)
|
||||
#define IOP3XX_AAU_SAR9 (volatile u32 *)IOP3XX_REG_ADDR(0x0840)
|
||||
#define IOP3XX_AAU_SAR10 (volatile u32 *)IOP3XX_REG_ADDR(0x0844)
|
||||
#define IOP3XX_AAU_SAR11 (volatile u32 *)IOP3XX_REG_ADDR(0x0848)
|
||||
#define IOP3XX_AAU_SAR12 (volatile u32 *)IOP3XX_REG_ADDR(0x084c)
|
||||
#define IOP3XX_AAU_SAR13 (volatile u32 *)IOP3XX_REG_ADDR(0x0850)
|
||||
#define IOP3XX_AAU_SAR14 (volatile u32 *)IOP3XX_REG_ADDR(0x0854)
|
||||
#define IOP3XX_AAU_SAR15 (volatile u32 *)IOP3XX_REG_ADDR(0x0858)
|
||||
#define IOP3XX_AAU_SAR16 (volatile u32 *)IOP3XX_REG_ADDR(0x085c)
|
||||
#define IOP3XX_AAU_EDCR1 (volatile u32 *)IOP3XX_REG_ADDR(0x0860)
|
||||
#define IOP3XX_AAU_SAR17 (volatile u32 *)IOP3XX_REG_ADDR(0x0864)
|
||||
#define IOP3XX_AAU_SAR18 (volatile u32 *)IOP3XX_REG_ADDR(0x0868)
|
||||
#define IOP3XX_AAU_SAR19 (volatile u32 *)IOP3XX_REG_ADDR(0x086c)
|
||||
#define IOP3XX_AAU_SAR20 (volatile u32 *)IOP3XX_REG_ADDR(0x0870)
|
||||
#define IOP3XX_AAU_SAR21 (volatile u32 *)IOP3XX_REG_ADDR(0x0874)
|
||||
#define IOP3XX_AAU_SAR22 (volatile u32 *)IOP3XX_REG_ADDR(0x0878)
|
||||
#define IOP3XX_AAU_SAR23 (volatile u32 *)IOP3XX_REG_ADDR(0x087c)
|
||||
#define IOP3XX_AAU_SAR24 (volatile u32 *)IOP3XX_REG_ADDR(0x0880)
|
||||
#define IOP3XX_AAU_EDCR2 (volatile u32 *)IOP3XX_REG_ADDR(0x0884)
|
||||
#define IOP3XX_AAU_SAR25 (volatile u32 *)IOP3XX_REG_ADDR(0x0888)
|
||||
#define IOP3XX_AAU_SAR26 (volatile u32 *)IOP3XX_REG_ADDR(0x088c)
|
||||
#define IOP3XX_AAU_SAR27 (volatile u32 *)IOP3XX_REG_ADDR(0x0890)
|
||||
#define IOP3XX_AAU_SAR28 (volatile u32 *)IOP3XX_REG_ADDR(0x0894)
|
||||
#define IOP3XX_AAU_SAR29 (volatile u32 *)IOP3XX_REG_ADDR(0x0898)
|
||||
#define IOP3XX_AAU_SAR30 (volatile u32 *)IOP3XX_REG_ADDR(0x089c)
|
||||
#define IOP3XX_AAU_SAR31 (volatile u32 *)IOP3XX_REG_ADDR(0x08a0)
|
||||
#define IOP3XX_AAU_SAR32 (volatile u32 *)IOP3XX_REG_ADDR(0x08a4)
|
||||
|
||||
/* I2C bus interface unit */
|
||||
#define IOP3XX_ICR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1680)
|
||||
#define IOP3XX_ISR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1684)
|
||||
#define IOP3XX_ISAR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1688)
|
||||
#define IOP3XX_IDBR0 (volatile u32 *)IOP3XX_REG_ADDR(0x168c)
|
||||
#define IOP3XX_IBMR0 (volatile u32 *)IOP3XX_REG_ADDR(0x1694)
|
||||
#define IOP3XX_ICR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
|
||||
#define IOP3XX_ISR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
|
||||
#define IOP3XX_ISAR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
|
||||
#define IOP3XX_IDBR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
|
||||
#define IOP3XX_IBMR1 (volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
|
||||
|
||||
|
||||
/*
|
||||
* IOP3XX I/O and Mem space regions for PCI autoconfiguration
|
||||
*/
|
||||
#define IOP3XX_PCI_MEM_WINDOW_SIZE 0x04000000
|
||||
#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
|
||||
#define IOP3XX_PCI_LOWER_MEM_BA (*IOP3XX_OMWTVR0)
|
||||
|
||||
#define IOP3XX_PCI_IO_WINDOW_SIZE 0x00010000
|
||||
#define IOP3XX_PCI_LOWER_IO_PA 0x90000000
|
||||
#define IOP3XX_PCI_LOWER_IO_VA 0xfe000000
|
||||
#define IOP3XX_PCI_LOWER_IO_BA (*IOP3XX_OIOWTVR)
|
||||
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
void iop3xx_map_io(void);
|
||||
void iop3xx_init_time(unsigned long);
|
||||
unsigned long iop3xx_gettimeoffset(void);
|
||||
|
||||
extern struct platform_device iop3xx_i2c0_device;
|
||||
extern struct platform_device iop3xx_i2c1_device;
|
||||
|
||||
extern inline void iop3xx_cp6_enable(void)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
asm volatile (
|
||||
"mrc p15, 0, %0, c15, c1, 0\n\t"
|
||||
"orr %0, %0, #(1 << 6)\n\t"
|
||||
"mcr p15, 0, %0, c15, c1, 0\n\t"
|
||||
"mrc p15, 0, %0, c15, c1, 0\n\t"
|
||||
"mov %0, %0\n\t"
|
||||
"sub pc, pc, #4\n\t"
|
||||
: "=r" (temp) );
|
||||
}
|
||||
|
||||
extern inline void iop3xx_cp6_disable(void)
|
||||
{
|
||||
u32 temp;
|
||||
|
||||
asm volatile (
|
||||
"mrc p15, 0, %0, c15, c1, 0\n\t"
|
||||
"bic %0, %0, #(1 << 6)\n\t"
|
||||
"mcr p15, 0, %0, c15, c1, 0\n\t"
|
||||
"mrc p15, 0, %0, c15, c1, 0\n\t"
|
||||
"mov %0, %0\n\t"
|
||||
"sub pc, pc, #4\n\t"
|
||||
: "=r" (temp) );
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#endif
|
||||
@@ -54,17 +54,18 @@
|
||||
#define LOCOMO_DAC_SDAOEB 0x01 /* SDA pin output data */
|
||||
|
||||
/* SPI interface */
|
||||
#define LOCOMO_SPIMD 0x60 /* SPI mode setting */
|
||||
#define LOCOMO_SPICT 0x64 /* SPI mode control */
|
||||
#define LOCOMO_SPIST 0x68 /* SPI status */
|
||||
#define LOCOMO_SPIIS 0x70 /* SPI interrupt status */
|
||||
#define LOCOMO_SPIWE 0x74 /* SPI interrupt status write enable */
|
||||
#define LOCOMO_SPIIE 0x78 /* SPI interrupt enable */
|
||||
#define LOCOMO_SPIIR 0x7c /* SPI interrupt request */
|
||||
#define LOCOMO_SPITD 0x80 /* SPI transfer data write */
|
||||
#define LOCOMO_SPIRD 0x84 /* SPI receive data read */
|
||||
#define LOCOMO_SPITS 0x88 /* SPI transfer data shift */
|
||||
#define LOCOMO_SPIRS 0x8C /* SPI receive data shift */
|
||||
#define LOCOMO_SPI 0x60
|
||||
#define LOCOMO_SPIMD 0x00 /* SPI mode setting */
|
||||
#define LOCOMO_SPICT 0x04 /* SPI mode control */
|
||||
#define LOCOMO_SPIST 0x08 /* SPI status */
|
||||
#define LOCOMO_SPIIS 0x10 /* SPI interrupt status */
|
||||
#define LOCOMO_SPIWE 0x14 /* SPI interrupt status write enable */
|
||||
#define LOCOMO_SPIIE 0x18 /* SPI interrupt enable */
|
||||
#define LOCOMO_SPIIR 0x1c /* SPI interrupt request */
|
||||
#define LOCOMO_SPITD 0x20 /* SPI transfer data write */
|
||||
#define LOCOMO_SPIRD 0x24 /* SPI receive data read */
|
||||
#define LOCOMO_SPITS 0x28 /* SPI transfer data shift */
|
||||
#define LOCOMO_SPIRS 0x2C /* SPI receive data shift */
|
||||
#define LOCOMO_SPI_TEND (1 << 3) /* Transfer end bit */
|
||||
#define LOCOMO_SPI_OVRN (1 << 2) /* Over Run bit */
|
||||
#define LOCOMO_SPI_RFW (1 << 1) /* write buffer bit */
|
||||
@@ -161,6 +162,7 @@ extern struct bus_type locomo_bus_type;
|
||||
#define LOCOMO_DEVID_AUDIO 3
|
||||
#define LOCOMO_DEVID_LED 4
|
||||
#define LOCOMO_DEVID_UART 5
|
||||
#define LOCOMO_DEVID_SPI 6
|
||||
|
||||
struct locomo_dev {
|
||||
struct device dev;
|
||||
@@ -197,10 +199,11 @@ int locomo_driver_register(struct locomo_driver *);
|
||||
void locomo_driver_unregister(struct locomo_driver *);
|
||||
|
||||
/* GPIO control functions */
|
||||
void locomo_gpio_set_dir(struct locomo_dev *ldev, unsigned int bits, unsigned int dir);
|
||||
unsigned int locomo_gpio_read_level(struct locomo_dev *ldev, unsigned int bits);
|
||||
unsigned int locomo_gpio_read_output(struct locomo_dev *ldev, unsigned int bits);
|
||||
void locomo_gpio_write(struct locomo_dev *ldev, unsigned int bits, unsigned int set);
|
||||
void locomo_gpio_set_dir(struct device *dev, unsigned int bits, unsigned int dir);
|
||||
int locomo_gpio_read_level(struct device *dev, unsigned int bits);
|
||||
int locomo_gpio_read_output(struct device *dev, unsigned int bits);
|
||||
void locomo_gpio_write(struct device *dev, unsigned int bits, unsigned int set);
|
||||
|
||||
|
||||
/* M62332 control function */
|
||||
void locomo_m62332_senddata(struct locomo_dev *ldev, unsigned int dac_data, int channel);
|
||||
|
||||
@@ -25,6 +25,7 @@ struct sharpsl_charger_machinfo {
|
||||
void (*measure_temp)(int);
|
||||
void (*presuspend)(void);
|
||||
void (*postsuspend)(void);
|
||||
void (*earlyresume)(void);
|
||||
unsigned long (*read_devdata)(int);
|
||||
#define SHARPSL_BATT_VOLT 1
|
||||
#define SHARPSL_BATT_TEMP 2
|
||||
|
||||
@@ -280,6 +280,10 @@ extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
|
||||
#define BIOVEC_MERGEABLE(vec1, vec2) \
|
||||
((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
|
||||
|
||||
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
|
||||
extern int valid_phys_addr_range(unsigned long addr, size_t size);
|
||||
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
|
||||
|
||||
/*
|
||||
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
|
||||
* access
|
||||
|
||||
@@ -0,0 +1,132 @@
|
||||
#ifndef __ASM_ARM_IRQFLAGS_H
|
||||
#define __ASM_ARM_IRQFLAGS_H
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#include <asm/ptrace.h>
|
||||
|
||||
/*
|
||||
* CPU interrupt mask handling.
|
||||
*/
|
||||
#if __LINUX_ARM_ARCH__ >= 6
|
||||
|
||||
#define raw_local_irq_save(x) \
|
||||
({ \
|
||||
__asm__ __volatile__( \
|
||||
"mrs %0, cpsr @ local_irq_save\n" \
|
||||
"cpsid i" \
|
||||
: "=r" (x) : : "memory", "cc"); \
|
||||
})
|
||||
|
||||
#define raw_local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc")
|
||||
#define raw_local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc")
|
||||
#define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc")
|
||||
#define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc")
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* Save the current interrupt enable state & disable IRQs
|
||||
*/
|
||||
#define raw_local_irq_save(x) \
|
||||
({ \
|
||||
unsigned long temp; \
|
||||
(void) (&temp == &x); \
|
||||
__asm__ __volatile__( \
|
||||
"mrs %0, cpsr @ local_irq_save\n" \
|
||||
" orr %1, %0, #128\n" \
|
||||
" msr cpsr_c, %1" \
|
||||
: "=r" (x), "=r" (temp) \
|
||||
: \
|
||||
: "memory", "cc"); \
|
||||
})
|
||||
|
||||
/*
|
||||
* Enable IRQs
|
||||
*/
|
||||
#define raw_local_irq_enable() \
|
||||
({ \
|
||||
unsigned long temp; \
|
||||
__asm__ __volatile__( \
|
||||
"mrs %0, cpsr @ local_irq_enable\n" \
|
||||
" bic %0, %0, #128\n" \
|
||||
" msr cpsr_c, %0" \
|
||||
: "=r" (temp) \
|
||||
: \
|
||||
: "memory", "cc"); \
|
||||
})
|
||||
|
||||
/*
|
||||
* Disable IRQs
|
||||
*/
|
||||
#define raw_local_irq_disable() \
|
||||
({ \
|
||||
unsigned long temp; \
|
||||
__asm__ __volatile__( \
|
||||
"mrs %0, cpsr @ local_irq_disable\n" \
|
||||
" orr %0, %0, #128\n" \
|
||||
" msr cpsr_c, %0" \
|
||||
: "=r" (temp) \
|
||||
: \
|
||||
: "memory", "cc"); \
|
||||
})
|
||||
|
||||
/*
|
||||
* Enable FIQs
|
||||
*/
|
||||
#define local_fiq_enable() \
|
||||
({ \
|
||||
unsigned long temp; \
|
||||
__asm__ __volatile__( \
|
||||
"mrs %0, cpsr @ stf\n" \
|
||||
" bic %0, %0, #64\n" \
|
||||
" msr cpsr_c, %0" \
|
||||
: "=r" (temp) \
|
||||
: \
|
||||
: "memory", "cc"); \
|
||||
})
|
||||
|
||||
/*
|
||||
* Disable FIQs
|
||||
*/
|
||||
#define local_fiq_disable() \
|
||||
({ \
|
||||
unsigned long temp; \
|
||||
__asm__ __volatile__( \
|
||||
"mrs %0, cpsr @ clf\n" \
|
||||
" orr %0, %0, #64\n" \
|
||||
" msr cpsr_c, %0" \
|
||||
: "=r" (temp) \
|
||||
: \
|
||||
: "memory", "cc"); \
|
||||
})
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Save the current interrupt enable state.
|
||||
*/
|
||||
#define raw_local_save_flags(x) \
|
||||
({ \
|
||||
__asm__ __volatile__( \
|
||||
"mrs %0, cpsr @ local_save_flags" \
|
||||
: "=r" (x) : : "memory", "cc"); \
|
||||
})
|
||||
|
||||
/*
|
||||
* restore saved IRQ & FIQ state
|
||||
*/
|
||||
#define raw_local_irq_restore(x) \
|
||||
__asm__ __volatile__( \
|
||||
"msr cpsr_c, %0 @ local_irq_restore\n" \
|
||||
: \
|
||||
: "r" (x) \
|
||||
: "memory", "cc")
|
||||
|
||||
#define raw_irqs_disabled_flags(flags) \
|
||||
({ \
|
||||
(int)((flags) & PSR_I_BIT); \
|
||||
})
|
||||
|
||||
#endif
|
||||
#endif
|
||||
@@ -52,13 +52,9 @@ void pci_common_init(struct hw_pci *);
|
||||
/*
|
||||
* PCI controllers
|
||||
*/
|
||||
extern int iop321_setup(int nr, struct pci_sys_data *);
|
||||
extern struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *);
|
||||
extern void iop321_init(void);
|
||||
|
||||
extern int iop331_setup(int nr, struct pci_sys_data *);
|
||||
extern struct pci_bus *iop331_scan_bus(int nr, struct pci_sys_data *);
|
||||
extern void iop331_init(void);
|
||||
extern int iop3xx_pci_setup(int nr, struct pci_sys_data *);
|
||||
extern struct pci_bus *iop3xx_pci_scan_bus(int nr, struct pci_sys_data *);
|
||||
extern void iop3xx_pci_preinit(void);
|
||||
|
||||
extern int dc21285_setup(int nr, struct pci_sys_data *);
|
||||
extern struct pci_bus *dc21285_scan_bus(int nr, struct pci_sys_data *);
|
||||
|
||||
@@ -38,7 +38,9 @@ struct sys_timer {
|
||||
void (*init)(void);
|
||||
void (*suspend)(void);
|
||||
void (*resume)(void);
|
||||
#ifndef CONFIG_GENERIC_TIME
|
||||
unsigned long (*offset)(void);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_NO_IDLE_HZ
|
||||
struct dyn_tick_timer *dyn_tick;
|
||||
|
||||
@@ -174,9 +174,6 @@ typedef unsigned long pgprot_t;
|
||||
|
||||
#endif /* STRICT_MM_TYPECHECKS */
|
||||
|
||||
/* the upper-most page table pointer */
|
||||
extern pmd_t *top_pmd;
|
||||
|
||||
#endif /* CONFIG_MMU */
|
||||
|
||||
#include <asm/memory.h>
|
||||
|
||||
@@ -135,6 +135,13 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
|
||||
#define FIRST_USER_PGD_NR 1
|
||||
#define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR)
|
||||
|
||||
/*
|
||||
* section address mask and size definitions.
|
||||
*/
|
||||
#define SECTION_SHIFT 20
|
||||
#define SECTION_SIZE (1UL << SECTION_SHIFT)
|
||||
#define SECTION_MASK (~(SECTION_SIZE-1))
|
||||
|
||||
/*
|
||||
* ARMv6 supersection address mask and size definitions.
|
||||
*/
|
||||
|
||||
@@ -33,6 +33,14 @@
|
||||
# define CPU_NAME cpu_arm6
|
||||
# endif
|
||||
# endif
|
||||
# ifdef CONFIG_CPU_ARM7TDMI
|
||||
# ifdef CPU_NAME
|
||||
# undef MULTI_CPU
|
||||
# define MULTI_CPU
|
||||
# else
|
||||
# define CPU_NAME cpu_arm7tdmi
|
||||
# endif
|
||||
# endif
|
||||
# ifdef CONFIG_CPU_ARM710
|
||||
# ifdef CPU_NAME
|
||||
# undef MULTI_CPU
|
||||
@@ -49,6 +57,22 @@
|
||||
# define CPU_NAME cpu_arm720
|
||||
# endif
|
||||
# endif
|
||||
# ifdef CONFIG_CPU_ARM740T
|
||||
# ifdef CPU_NAME
|
||||
# undef MULTI_CPU
|
||||
# define MULTI_CPU
|
||||
# else
|
||||
# define CPU_NAME cpu_arm740
|
||||
# endif
|
||||
# endif
|
||||
# ifdef CONFIG_CPU_ARM9TDMI
|
||||
# ifdef CPU_NAME
|
||||
# undef MULTI_CPU
|
||||
# define MULTI_CPU
|
||||
# else
|
||||
# define CPU_NAME cpu_arm9tdmi
|
||||
# endif
|
||||
# endif
|
||||
# ifdef CONFIG_CPU_ARM920T
|
||||
# ifdef CPU_NAME
|
||||
# undef MULTI_CPU
|
||||
@@ -81,6 +105,22 @@
|
||||
# define CPU_NAME cpu_arm926
|
||||
# endif
|
||||
# endif
|
||||
# ifdef CONFIG_CPU_ARM940T
|
||||
# ifdef CPU_NAME
|
||||
# undef MULTI_CPU
|
||||
# define MULTI_CPU
|
||||
# else
|
||||
# define CPU_NAME cpu_arm940
|
||||
# endif
|
||||
# endif
|
||||
# ifdef CONFIG_CPU_ARM946E
|
||||
# ifdef CPU_NAME
|
||||
# undef MULTI_CPU
|
||||
# define MULTI_CPU
|
||||
# else
|
||||
# define CPU_NAME cpu_arm946
|
||||
# endif
|
||||
# endif
|
||||
# ifdef CONFIG_CPU_SA110
|
||||
# ifdef CPU_NAME
|
||||
# undef MULTI_CPU
|
||||
|
||||
@@ -194,13 +194,15 @@ static struct tagtable __tagtable_##fn __tag = { tag, fn }
|
||||
# define NR_BANKS 8
|
||||
#endif
|
||||
|
||||
struct membank {
|
||||
unsigned long start;
|
||||
unsigned long size;
|
||||
int node;
|
||||
};
|
||||
|
||||
struct meminfo {
|
||||
int nr_banks;
|
||||
struct {
|
||||
unsigned long start;
|
||||
unsigned long size;
|
||||
int node;
|
||||
} bank[NR_BANKS];
|
||||
struct membank bank[NR_BANKS];
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
+9
-128
@@ -46,6 +46,7 @@
|
||||
#define CPUID_TCM 2
|
||||
#define CPUID_TLBTYPE 3
|
||||
|
||||
#ifdef CONFIG_CPU_CP15
|
||||
#define read_cpuid(reg) \
|
||||
({ \
|
||||
unsigned int __val; \
|
||||
@@ -55,6 +56,9 @@
|
||||
: "cc"); \
|
||||
__val; \
|
||||
})
|
||||
#else
|
||||
#define read_cpuid(reg) (processor_id)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* This is used to ensure the compiler did actually allocate the register we
|
||||
@@ -207,130 +211,7 @@ static inline void sched_cacheflush(void)
|
||||
{
|
||||
}
|
||||
|
||||
/*
|
||||
* CPU interrupt mask handling.
|
||||
*/
|
||||
#if __LINUX_ARM_ARCH__ >= 6
|
||||
|
||||
#define local_irq_save(x) \
|
||||
({ \
|
||||
__asm__ __volatile__( \
|
||||
"mrs %0, cpsr @ local_irq_save\n" \
|
||||
"cpsid i" \
|
||||
: "=r" (x) : : "memory", "cc"); \
|
||||
})
|
||||
|
||||
#define local_irq_enable() __asm__("cpsie i @ __sti" : : : "memory", "cc")
|
||||
#define local_irq_disable() __asm__("cpsid i @ __cli" : : : "memory", "cc")
|
||||
#define local_fiq_enable() __asm__("cpsie f @ __stf" : : : "memory", "cc")
|
||||
#define local_fiq_disable() __asm__("cpsid f @ __clf" : : : "memory", "cc")
|
||||
|
||||
#else
|
||||
|
||||
/*
|
||||
* Save the current interrupt enable state & disable IRQs
|
||||
*/
|
||||
#define local_irq_save(x) \
|
||||
({ \
|
||||
unsigned long temp; \
|
||||
(void) (&temp == &x); \
|
||||
__asm__ __volatile__( \
|
||||
"mrs %0, cpsr @ local_irq_save\n" \
|
||||
" orr %1, %0, #128\n" \
|
||||
" msr cpsr_c, %1" \
|
||||
: "=r" (x), "=r" (temp) \
|
||||
: \
|
||||
: "memory", "cc"); \
|
||||
})
|
||||
|
||||
/*
|
||||
* Enable IRQs
|
||||
*/
|
||||
#define local_irq_enable() \
|
||||
({ \
|
||||
unsigned long temp; \
|
||||
__asm__ __volatile__( \
|
||||
"mrs %0, cpsr @ local_irq_enable\n" \
|
||||
" bic %0, %0, #128\n" \
|
||||
" msr cpsr_c, %0" \
|
||||
: "=r" (temp) \
|
||||
: \
|
||||
: "memory", "cc"); \
|
||||
})
|
||||
|
||||
/*
|
||||
* Disable IRQs
|
||||
*/
|
||||
#define local_irq_disable() \
|
||||
({ \
|
||||
unsigned long temp; \
|
||||
__asm__ __volatile__( \
|
||||
"mrs %0, cpsr @ local_irq_disable\n" \
|
||||
" orr %0, %0, #128\n" \
|
||||
" msr cpsr_c, %0" \
|
||||
: "=r" (temp) \
|
||||
: \
|
||||
: "memory", "cc"); \
|
||||
})
|
||||
|
||||
/*
|
||||
* Enable FIQs
|
||||
*/
|
||||
#define local_fiq_enable() \
|
||||
({ \
|
||||
unsigned long temp; \
|
||||
__asm__ __volatile__( \
|
||||
"mrs %0, cpsr @ stf\n" \
|
||||
" bic %0, %0, #64\n" \
|
||||
" msr cpsr_c, %0" \
|
||||
: "=r" (temp) \
|
||||
: \
|
||||
: "memory", "cc"); \
|
||||
})
|
||||
|
||||
/*
|
||||
* Disable FIQs
|
||||
*/
|
||||
#define local_fiq_disable() \
|
||||
({ \
|
||||
unsigned long temp; \
|
||||
__asm__ __volatile__( \
|
||||
"mrs %0, cpsr @ clf\n" \
|
||||
" orr %0, %0, #64\n" \
|
||||
" msr cpsr_c, %0" \
|
||||
: "=r" (temp) \
|
||||
: \
|
||||
: "memory", "cc"); \
|
||||
})
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Save the current interrupt enable state.
|
||||
*/
|
||||
#define local_save_flags(x) \
|
||||
({ \
|
||||
__asm__ __volatile__( \
|
||||
"mrs %0, cpsr @ local_save_flags" \
|
||||
: "=r" (x) : : "memory", "cc"); \
|
||||
})
|
||||
|
||||
/*
|
||||
* restore saved IRQ & FIQ state
|
||||
*/
|
||||
#define local_irq_restore(x) \
|
||||
__asm__ __volatile__( \
|
||||
"msr cpsr_c, %0 @ local_irq_restore\n" \
|
||||
: \
|
||||
: "r" (x) \
|
||||
: "memory", "cc")
|
||||
|
||||
#define irqs_disabled() \
|
||||
({ \
|
||||
unsigned long flags; \
|
||||
local_save_flags(flags); \
|
||||
(int)(flags & PSR_I_BIT); \
|
||||
})
|
||||
#include <linux/irqflags.h>
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
||||
@@ -405,17 +286,17 @@ static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size
|
||||
#error SMP is not supported on this platform
|
||||
#endif
|
||||
case 1:
|
||||
local_irq_save(flags);
|
||||
raw_local_irq_save(flags);
|
||||
ret = *(volatile unsigned char *)ptr;
|
||||
*(volatile unsigned char *)ptr = x;
|
||||
local_irq_restore(flags);
|
||||
raw_local_irq_restore(flags);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
local_irq_save(flags);
|
||||
raw_local_irq_save(flags);
|
||||
ret = *(volatile unsigned long *)ptr;
|
||||
*(volatile unsigned long *)ptr = x;
|
||||
local_irq_restore(flags);
|
||||
raw_local_irq_restore(flags);
|
||||
break;
|
||||
#else
|
||||
case 1:
|
||||
|
||||
@@ -0,0 +1,4 @@
|
||||
#ifndef _ASM_ARM_TIMEOFDAY_H
|
||||
#define _ASM_ARM_TIMEOFDAY_H
|
||||
#include <asm-generic/timeofday.h>
|
||||
#endif
|
||||
+38
-38
@@ -247,16 +247,16 @@ static inline void local_flush_tlb_all(void)
|
||||
const unsigned int __tlb_flag = __cpu_tlb_flags;
|
||||
|
||||
if (tlb_flag(TLB_WB))
|
||||
asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
|
||||
|
||||
if (tlb_flag(TLB_V3_FULL))
|
||||
asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
|
||||
if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
|
||||
asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
|
||||
if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
|
||||
asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
|
||||
if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
|
||||
asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
|
||||
}
|
||||
|
||||
static inline void local_flush_tlb_mm(struct mm_struct *mm)
|
||||
@@ -266,25 +266,25 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm)
|
||||
const unsigned int __tlb_flag = __cpu_tlb_flags;
|
||||
|
||||
if (tlb_flag(TLB_WB))
|
||||
asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
|
||||
|
||||
if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) {
|
||||
if (tlb_flag(TLB_V3_FULL))
|
||||
asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
|
||||
if (tlb_flag(TLB_V4_U_FULL))
|
||||
asm("mcr%? p15, 0, %0, c8, c7, 0" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
|
||||
if (tlb_flag(TLB_V4_D_FULL))
|
||||
asm("mcr%? p15, 0, %0, c8, c6, 0" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
|
||||
if (tlb_flag(TLB_V4_I_FULL))
|
||||
asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
|
||||
}
|
||||
|
||||
if (tlb_flag(TLB_V6_U_ASID))
|
||||
asm("mcr%? p15, 0, %0, c8, c7, 2" : : "r" (asid));
|
||||
asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
|
||||
if (tlb_flag(TLB_V6_D_ASID))
|
||||
asm("mcr%? p15, 0, %0, c8, c6, 2" : : "r" (asid));
|
||||
asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
|
||||
if (tlb_flag(TLB_V6_I_ASID))
|
||||
asm("mcr%? p15, 0, %0, c8, c5, 2" : : "r" (asid));
|
||||
asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
|
||||
}
|
||||
|
||||
static inline void
|
||||
@@ -296,27 +296,27 @@ local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
|
||||
uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
|
||||
|
||||
if (tlb_flag(TLB_WB))
|
||||
asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero));
|
||||
|
||||
if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
|
||||
if (tlb_flag(TLB_V3_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (uaddr));
|
||||
asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
|
||||
if (tlb_flag(TLB_V4_U_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr));
|
||||
asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
|
||||
if (tlb_flag(TLB_V4_D_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr));
|
||||
asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
|
||||
if (tlb_flag(TLB_V4_I_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
|
||||
asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
|
||||
if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
|
||||
asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
|
||||
}
|
||||
|
||||
if (tlb_flag(TLB_V6_U_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (uaddr));
|
||||
asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
|
||||
if (tlb_flag(TLB_V6_D_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (uaddr));
|
||||
asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
|
||||
if (tlb_flag(TLB_V6_I_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (uaddr));
|
||||
asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
|
||||
}
|
||||
|
||||
static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
|
||||
@@ -327,31 +327,31 @@ static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
|
||||
kaddr &= PAGE_MASK;
|
||||
|
||||
if (tlb_flag(TLB_WB))
|
||||
asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
|
||||
|
||||
if (tlb_flag(TLB_V3_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c6, c0, 0" : : "r" (kaddr));
|
||||
asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
|
||||
if (tlb_flag(TLB_V4_U_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr));
|
||||
asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
|
||||
if (tlb_flag(TLB_V4_D_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
|
||||
asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
|
||||
if (tlb_flag(TLB_V4_I_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
|
||||
asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
|
||||
if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
|
||||
asm("mcr%? p15, 0, %0, c8, c5, 0" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
|
||||
|
||||
if (tlb_flag(TLB_V6_U_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c8, c7, 1" : : "r" (kaddr));
|
||||
asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
|
||||
if (tlb_flag(TLB_V6_D_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c8, c6, 1" : : "r" (kaddr));
|
||||
asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
|
||||
if (tlb_flag(TLB_V6_I_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c8, c5, 1" : : "r" (kaddr));
|
||||
asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
|
||||
|
||||
/* The ARM ARM states that the completion of a TLB maintenance
|
||||
* operation is only guaranteed by a DSB instruction
|
||||
*/
|
||||
if (tlb_flag(TLB_V6_U_PAGE | TLB_V6_D_PAGE | TLB_V6_I_PAGE))
|
||||
asm("mcr%? p15, 0, %0, c7, c10, 4" : : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (zero) : "cc");
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -373,11 +373,11 @@ static inline void flush_pmd_entry(pmd_t *pmd)
|
||||
const unsigned int __tlb_flag = __cpu_tlb_flags;
|
||||
|
||||
if (tlb_flag(TLB_DCLEAN))
|
||||
asm("mcr%? p15, 0, %0, c7, c10, 1 @ flush_pmd"
|
||||
: : "r" (pmd));
|
||||
asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
|
||||
: : "r" (pmd) : "cc");
|
||||
if (tlb_flag(TLB_WB))
|
||||
asm("mcr%? p15, 0, %0, c7, c10, 4 @ flush_pmd"
|
||||
: : "r" (zero));
|
||||
asm("mcr p15, 0, %0, c7, c10, 4 @ flush_pmd"
|
||||
: : "r" (zero) : "cc");
|
||||
}
|
||||
|
||||
static inline void clean_pmd_entry(pmd_t *pmd)
|
||||
@@ -385,8 +385,8 @@ static inline void clean_pmd_entry(pmd_t *pmd)
|
||||
const unsigned int __tlb_flag = __cpu_tlb_flags;
|
||||
|
||||
if (tlb_flag(TLB_DCLEAN))
|
||||
asm("mcr%? p15, 0, %0, c7, c10, 1 @ flush_pmd"
|
||||
: : "r" (pmd));
|
||||
asm("mcr p15, 0, %0, c7, c10, 1 @ flush_pmd"
|
||||
: : "r" (pmd) : "cc");
|
||||
}
|
||||
|
||||
#undef tlb_flag
|
||||
|
||||
+25
-37
@@ -3,7 +3,7 @@
|
||||
|
||||
#include <asm/types.h>
|
||||
|
||||
extern int __bug_unaligned_x(void *ptr);
|
||||
extern int __bug_unaligned_x(const void *ptr);
|
||||
|
||||
/*
|
||||
* What is the most efficient way of loading/storing an unaligned value?
|
||||
@@ -51,44 +51,32 @@ extern int __bug_unaligned_x(void *ptr);
|
||||
#define __get_unaligned_4_be(__p) \
|
||||
(__p[0] << 24 | __p[1] << 16 | __p[2] << 8 | __p[3])
|
||||
|
||||
#define __get_unaligned_le(ptr) \
|
||||
({ \
|
||||
__typeof__(*(ptr)) __v; \
|
||||
__u8 *__p = (__u8 *)(ptr); \
|
||||
switch (sizeof(*(ptr))) { \
|
||||
case 1: __v = *(ptr); break; \
|
||||
case 2: __v = __get_unaligned_2_le(__p); break; \
|
||||
case 4: __v = __get_unaligned_4_le(__p); break; \
|
||||
case 8: { \
|
||||
unsigned int __v1, __v2; \
|
||||
__v2 = __get_unaligned_4_le((__p+4)); \
|
||||
__v1 = __get_unaligned_4_le(__p); \
|
||||
__v = ((unsigned long long)__v2 << 32 | __v1); \
|
||||
} \
|
||||
break; \
|
||||
default: __v = __bug_unaligned_x(__p); break; \
|
||||
} \
|
||||
__v; \
|
||||
#define __get_unaligned_8_le(__p) \
|
||||
((unsigned long long)__get_unaligned_4_le((__p+4)) << 32 | \
|
||||
__get_unaligned_4_le(__p))
|
||||
|
||||
#define __get_unaligned_8_be(__p) \
|
||||
((unsigned long long)__get_unaligned_4_be(__p) << 32 | \
|
||||
__get_unaligned_4_be((__p+4)))
|
||||
|
||||
#define __get_unaligned_le(ptr) \
|
||||
({ \
|
||||
const __u8 *__p = (const __u8 *)(ptr); \
|
||||
__builtin_choose_expr(sizeof(*(ptr)) == 1, *__p, \
|
||||
__builtin_choose_expr(sizeof(*(ptr)) == 2, __get_unaligned_2_le(__p), \
|
||||
__builtin_choose_expr(sizeof(*(ptr)) == 4, __get_unaligned_4_le(__p), \
|
||||
__builtin_choose_expr(sizeof(*(ptr)) == 8, __get_unaligned_8_le(__p), \
|
||||
(void)__bug_unaligned_x(__p))))); \
|
||||
})
|
||||
|
||||
#define __get_unaligned_be(ptr) \
|
||||
({ \
|
||||
__typeof__(*(ptr)) __v; \
|
||||
__u8 *__p = (__u8 *)(ptr); \
|
||||
switch (sizeof(*(ptr))) { \
|
||||
case 1: __v = *(ptr); break; \
|
||||
case 2: __v = __get_unaligned_2_be(__p); break; \
|
||||
case 4: __v = __get_unaligned_4_be(__p); break; \
|
||||
case 8: { \
|
||||
unsigned int __v1, __v2; \
|
||||
__v2 = __get_unaligned_4_be(__p); \
|
||||
__v1 = __get_unaligned_4_be((__p+4)); \
|
||||
__v = ((unsigned long long)__v2 << 32 | __v1); \
|
||||
} \
|
||||
break; \
|
||||
default: __v = __bug_unaligned_x(__p); break; \
|
||||
} \
|
||||
__v; \
|
||||
#define __get_unaligned_be(ptr) \
|
||||
({ \
|
||||
const __u8 *__p = (const __u8 *)(ptr); \
|
||||
__builtin_choose_expr(sizeof(*(ptr)) == 1, *__p, \
|
||||
__builtin_choose_expr(sizeof(*(ptr)) == 2, __get_unaligned_2_be(__p), \
|
||||
__builtin_choose_expr(sizeof(*(ptr)) == 4, __get_unaligned_4_be(__p), \
|
||||
__builtin_choose_expr(sizeof(*(ptr)) == 8, __get_unaligned_8_be(__p), \
|
||||
(void)__bug_unaligned_x(__p))))); \
|
||||
})
|
||||
|
||||
|
||||
|
||||
Reference in New Issue
Block a user