[IA64] multi-core/multi-thread identification
Version 3 - rediffed to apply on top of Ashok's hotplug cpu patch. /proc/cpuinfo output in step with x86. This is an updated MC/MT identification patch based on the previous discussions on list. Add the Multi-core and Multi-threading detection for IPF. - Add new core and threading related fields in /proc/cpuinfo. Physical id Core id Thread id Siblings - setup the cpu_core_map and cpu_sibling_map appropriately - Handles Hot plug CPU Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Gordon Jin <gordon.jin@intel.com> Signed-off-by: Rohit Seth <rohit.seth@intel.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Suresh Siddha
Tony Luck
@@ -67,6 +67,7 @@
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#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
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#define PAL_SHUTDOWN 40 /* enter processor shutdown state */
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#define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
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#define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */
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#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
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#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
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@@ -1559,6 +1560,73 @@ ia64_pal_prefetch_visibility (s64 trans_type)
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return iprv.status;
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}
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/* data structure for getting information on logical to physical mappings */
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typedef union pal_log_overview_u {
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struct {
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u64 num_log :16, /* Total number of logical
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* processors on this die
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*/
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tpc :8, /* Threads per core */
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reserved3 :8, /* Reserved */
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cpp :8, /* Cores per processor */
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reserved2 :8, /* Reserved */
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ppid :8, /* Physical processor ID */
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reserved1 :8; /* Reserved */
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} overview_bits;
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u64 overview_data;
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} pal_log_overview_t;
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typedef union pal_proc_n_log_info1_u{
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struct {
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u64 tid :16, /* Thread id */
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reserved2 :16, /* Reserved */
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cid :16, /* Core id */
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reserved1 :16; /* Reserved */
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} ppli1_bits;
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u64 ppli1_data;
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} pal_proc_n_log_info1_t;
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typedef union pal_proc_n_log_info2_u {
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struct {
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u64 la :16, /* Logical address */
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reserved :48; /* Reserved */
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} ppli2_bits;
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u64 ppli2_data;
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} pal_proc_n_log_info2_t;
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typedef struct pal_logical_to_physical_s
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{
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pal_log_overview_t overview;
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pal_proc_n_log_info1_t ppli1;
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pal_proc_n_log_info2_t ppli2;
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} pal_logical_to_physical_t;
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#define overview_num_log overview.overview_bits.num_log
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#define overview_tpc overview.overview_bits.tpc
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#define overview_cpp overview.overview_bits.cpp
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#define overview_ppid overview.overview_bits.ppid
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#define log1_tid ppli1.ppli1_bits.tid
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#define log1_cid ppli1.ppli1_bits.cid
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#define log2_la ppli2.ppli2_bits.la
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/* Get information on logical to physical processor mappings. */
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static inline s64
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ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
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{
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struct ia64_pal_retval iprv;
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PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
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if (iprv.status == PAL_STATUS_SUCCESS)
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{
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if (proc_number == 0)
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mapping->overview.overview_data = iprv.v0;
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mapping->ppli1.ppli1_data = iprv.v1;
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mapping->ppli2.ppli2_data = iprv.v2;
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}
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return iprv.status;
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_IA64_PAL_H */
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@@ -148,6 +148,13 @@ struct cpuinfo_ia64 {
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#ifdef CONFIG_SMP
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__u64 loops_per_jiffy;
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int cpu;
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__u32 socket_id; /* physical processor socket id */
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__u16 core_id; /* core id */
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__u16 thread_id; /* thread id */
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__u16 num_log; /* Total number of logical processors on
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* this socket that were successfully booted */
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__u8 cores_per_socket; /* Cores per processor socket */
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__u8 threads_per_core; /* Threads per core */
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#endif
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/* CPUID-derived information: */
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@@ -91,6 +91,7 @@ extern spinlock_t sal_lock;
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#define SAL_PCI_CONFIG_READ 0x01000010
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#define SAL_PCI_CONFIG_WRITE 0x01000011
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#define SAL_FREQ_BASE 0x01000012
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#define SAL_PHYSICAL_ID_INFO 0x01000013
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#define SAL_UPDATE_PAL 0x01000020
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@@ -815,6 +816,17 @@ ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
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return isrv.status;
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}
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/* Get physical processor die mapping in the platform. */
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static inline s64
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ia64_sal_physical_id_info(u16 *splid)
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{
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struct ia64_sal_retval isrv;
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SAL_CALL(isrv, SAL_PHYSICAL_ID_INFO, 0, 0, 0, 0, 0, 0, 0);
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if (splid)
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*splid = isrv.v0;
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return isrv.status;
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}
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extern unsigned long sal_platform_features;
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extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *);
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@@ -56,6 +56,10 @@ extern struct smp_boot_data {
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extern char no_int_routing __devinitdata;
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extern cpumask_t cpu_online_map;
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extern cpumask_t cpu_core_map[NR_CPUS];
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extern cpumask_t cpu_sibling_map[NR_CPUS];
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extern int smp_num_siblings;
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extern int smp_num_cpucores;
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extern void __iomem *ipi_base_addr;
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extern unsigned char smp_int_redirect;
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@@ -124,6 +128,7 @@ extern int smp_call_function_single (int cpuid, void (*func) (void *info), void
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extern void smp_send_reschedule (int cpu);
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extern void lock_ipi_calllock(void);
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extern void unlock_ipi_calllock(void);
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extern void identify_siblings (struct cpuinfo_ia64 *);
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#else
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