From d8a2ae8d16e81a756eb848033e9b38e507921540 Mon Sep 17 00:00:00 2001 From: Narayan Reddy Date: Wed, 13 Apr 2022 07:15:18 +0000 Subject: [PATCH] NVIDIA: SAUCE: net: phy: aqr: add phy_mode support BugLink: https://bugs.launchpad.net/bugs/2072591 Provide phy_mode support in PHY DT. read phy_mode from DT and apply the configuration accordingly as per the platform requirement. If phy_mode not specified AQR operates in 10G XFI mode http://nvbugs/3599876 Signed-off-by: Narayan Reddy Signed-off-by: Revanth Kumar Uppala Tested-by: Abhilash G Reviewed-by: Abhilash G Signed-off-by: Laxman Dewangan Acked-by: Jacob Martin Acked-by: Noah Wager Signed-off-by: Noah Wager --- drivers/net/phy/aquantia/aquantia_main.c | 25 +++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/net/phy/aquantia/aquantia_main.c b/drivers/net/phy/aquantia/aquantia_main.c index b169ed124663..5c85d4504867 100644 --- a/drivers/net/phy/aquantia/aquantia_main.c +++ b/drivers/net/phy/aquantia/aquantia_main.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include "aquantia.h" @@ -178,6 +179,9 @@ #define AQR107_OP_IN_PROG_SLEEP 1000 #define AQR107_OP_IN_PROG_TIMEOUT 100000 +#define VEND1_GLOBAL_MDIO_PHYXS_PROV2 0xC441 +#define VEND1_GLOBAL_MDIO_PHYXS_PROV2_USX_AN BIT(3) + #define VEND1_SEC_INGRESS_CNTRL_REG1 0x7001 #define VEND1_GLOBAL_SYS_CONFIG_100M 0x31b #define VEND1_GLOBAL_SYS_CONFIG_1G 0x31c @@ -280,9 +284,11 @@ static void aqr107_get_stats(struct phy_device *phydev, static int aqr_config_aneg(struct phy_device *phydev) { + struct device_node *node = phydev->mdio.dev.of_node; bool changed = false; u16 reg; - int ret; + int ret, err; + int phy_mode; if (phydev->autoneg == AUTONEG_DISABLE) return genphy_c45_pma_setup_forced(phydev); @@ -324,6 +330,23 @@ static int aqr_config_aneg(struct phy_device *phydev) if (ret > 0) changed = true; + err = of_property_read_u32(node, "aquantia,phy_mode", &phy_mode); + if (!err) { + if (phy_mode == 1) { + phydev_info(phydev, "Configuring AQR PHY to 5G Mode\n"); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_2_5G, 0x0106); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_5G, 0x0106); + phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CFG_10G, 0x0000); + /* Disable 10G advertizement and restart autoneg */ + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, 0x01E1); + /* restart auto-negotiation */ + genphy_c45_restart_aneg(phydev); + phy_write_mmd(phydev, MDIO_MMD_PHYXS, VEND1_GLOBAL_MDIO_PHYXS_PROV2, 0x8); + } + } else { + phydev_info(phydev, "No AQR phy_mode setting in DT\n"); + } + return genphy_c45_check_and_restart_aneg(phydev, changed); }