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Merge branch 'master' of /home/trondmy/kernel/linux-2.6/

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This commit is contained in:
Trond Myklebust
2006-06-20 08:59:45 -04:00
parent 28df955a2a 25f42b6af0
commit d59bf96cdd
711 changed files with 41791 additions and 18080 deletions
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include/asm-arm/arch-pxa/ohci.h
+2
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@@ -11,6 +11,8 @@ struct pxaohci_platform_data {
#define PMM_NPS_MODE 1
#define PMM_GLOBAL_MODE 2
#define PMM_PERPORT_MODE 3
int power_budget;
};
extern void pxa_set_ohci_info(struct pxaohci_platform_data *info);
include/asm-mips/addrspace.h
-35
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@@ -133,57 +133,22 @@
|| defined (CONFIG_CPU_NEVADA) \
|| defined (CONFIG_CPU_TX49XX) \
|| defined (CONFIG_CPU_MIPS64)
#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K0SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */
#define K1SIZE _LLCONST_(0x0000001000000000) /* 2^^36 */
#define K2SIZE _LLCONST_(0x000000ff80000000)
#define KSEGSIZE _LLCONST_(0x000000ff80000000) /* max syssegsz */
#define TO_PHYS_MASK _LLCONST_(0x0000000fffffffff) /* 2^^36 - 1 */
#endif
#if defined (CONFIG_CPU_R8000)
/* We keep KUSIZE consistent with R4000 for now (2^^40) instead of (2^^48) */
#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K0SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K1SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K2SIZE _LLCONST_(0x0001000000000000)
#define KSEGSIZE _LLCONST_(0x0000010000000000) /* max syssegsz */
#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */
#endif
#if defined (CONFIG_CPU_R10000)
#define KUSIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define KUSIZE_64 _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K0SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K1SIZE _LLCONST_(0x0000010000000000) /* 2^^40 */
#define K2SIZE _LLCONST_(0x00000fff80000000)
#define KSEGSIZE _LLCONST_(0x00000fff80000000) /* max syssegsz */
#define TO_PHYS_MASK _LLCONST_(0x000000ffffffffff) /* 2^^40 - 1 */
#endif
#if defined(CONFIG_CPU_SB1) || defined(CONFIG_CPU_SB1A)
#define KUSIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
#define KUSIZE_64 _LLCONST_(0x0000100000000000) /* 2^^44 */
#define K0SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
#define K1SIZE _LLCONST_(0x0000100000000000) /* 2^^44 */
#define K2SIZE _LLCONST_(0x0000ffff80000000)
#define KSEGSIZE _LLCONST_(0x0000ffff80000000) /* max syssegsz */
#define TO_PHYS_MASK _LLCONST_(0x00000fffffffffff) /* 2^^44 - 1 */
#endif
/*
* Further names for SGI source compatibility. These are stolen from
* IRIX's <sys/mips_addrspace.h>.
*/
#define KUBASE _LLCONST_(0)
#define KUSIZE_32 _LLCONST_(0x0000000080000000) /* KUSIZE
for a 32 bit proc */
#define K0BASE_EXL_WR _LLCONST_(0xa800000000000000) /* exclusive on write */
#define K0BASE_NONCOH _LLCONST_(0x9800000000000000) /* noncoherent */
#define K0BASE_EXL _LLCONST_(0xa000000000000000) /* exclusive */
#ifndef CONFIG_CPU_R8000
/*
include/asm-mips/apm.h
+65
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@@ -0,0 +1,65 @@
/* -*- linux-c -*-
*
* (C) 2003 zecke@handhelds.org
*
* GPL version 2
*
* based on arch/arm/kernel/apm.c
* factor out the information needed by architectures to provide
* apm status
*
*
*/
#ifndef MIPS_ASM_SA1100_APM_H
#define MIPS_ASM_SA1100_APM_H
#include <linux/config.h>
#include <linux/apm_bios.h>
/*
* This structure gets filled in by the machine specific 'get_power_status'
* implementation. Any fields which are not set default to a safe value.
*/
struct apm_power_info {
unsigned char ac_line_status;
#define APM_AC_OFFLINE 0
#define APM_AC_ONLINE 1
#define APM_AC_BACKUP 2
#define APM_AC_UNKNOWN 0xff
unsigned char battery_status;
#define APM_BATTERY_STATUS_HIGH 0
#define APM_BATTERY_STATUS_LOW 1
#define APM_BATTERY_STATUS_CRITICAL 2
#define APM_BATTERY_STATUS_CHARGING 3
#define APM_BATTERY_STATUS_NOT_PRESENT 4
#define APM_BATTERY_STATUS_UNKNOWN 0xff
unsigned char battery_flag;
#define APM_BATTERY_FLAG_HIGH (1 << 0)
#define APM_BATTERY_FLAG_LOW (1 << 1)
#define APM_BATTERY_FLAG_CRITICAL (1 << 2)
#define APM_BATTERY_FLAG_CHARGING (1 << 3)
#define APM_BATTERY_FLAG_NOT_PRESENT (1 << 7)
#define APM_BATTERY_FLAG_UNKNOWN 0xff
int battery_life;
int time;
int units;
#define APM_UNITS_MINS 0
#define APM_UNITS_SECS 1
#define APM_UNITS_UNKNOWN -1
};
/*
* This allows machines to provide their own "apm get power status" function.
*/
extern void (*apm_get_power_status)(struct apm_power_info *);
/*
* Queue an event (APM_SYS_SUSPEND or APM_CRITICAL_SUSPEND)
*/
void apm_queue_event(apm_event_t event);
#endif
include/asm-mips/asmmacro-32.h
+2 -2
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@@ -12,7 +12,7 @@
#include <asm/fpregdef.h>
#include <asm/mipsregs.h>
.macro fpu_save_double thread status tmp1=t0 tmp2
.macro fpu_save_double thread status tmp1=t0
cfc1 \tmp1, fcr31
sdc1 $f0, THREAD_FPR0(\thread)
sdc1 $f2, THREAD_FPR2(\thread)
@@ -70,7 +70,7 @@
sw \tmp, THREAD_FCR31(\thread)
.endm
.macro fpu_restore_double thread tmp=t0
.macro fpu_restore_double thread status tmp=t0
lw \tmp, THREAD_FCR31(\thread)
ldc1 $f0, THREAD_FPR0(\thread)
ldc1 $f2, THREAD_FPR2(\thread)
include/asm-mips/asmmacro-64.h
+9 -10
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@@ -53,12 +53,12 @@
sdc1 $f31, THREAD_FPR31(\thread)
.endm
.macro fpu_save_double thread status tmp1 tmp2
sll \tmp2, \tmp1, 5
bgez \tmp2, 2f
.macro fpu_save_double thread status tmp
sll \tmp, \status, 5
bgez \tmp, 2f
fpu_save_16odd \thread
2:
fpu_save_16even \thread \tmp1 # clobbers t1
fpu_save_16even \thread \tmp
.endm
.macro fpu_restore_16even thread tmp=t0
@@ -101,13 +101,12 @@
ldc1 $f31, THREAD_FPR31(\thread)
.endm
.macro fpu_restore_double thread tmp
mfc0 t0, CP0_STATUS
sll t1, t0, 5
bgez t1, 1f # 16 register mode?
.macro fpu_restore_double thread status tmp
sll \tmp, \status, 5
bgez \tmp, 1f # 16 register mode?
fpu_restore_16odd a0
1: fpu_restore_16even a0, t0 # clobbers t0
fpu_restore_16odd \thread
1: fpu_restore_16even \thread \tmp
.endm
.macro cpu_save_nonscratch thread
include/asm-mips/bootinfo.h
+13
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@@ -217,6 +217,13 @@
*/
#define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
#define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
#define MACH_TITAN_EXCITE 2 /* Basler eXcite */
/*
* Valid machtype for group NEC EMMA2RH
*/
#define MACH_GROUP_NEC_EMMA2RH 25 /* NEC EMMA2RH (was 23) */
#define MACH_NEC_MARKEINS 0 /* NEC EMMA2RH Mark-eins */
#define CL_SIZE COMMAND_LINE_SIZE
@@ -258,4 +265,10 @@ extern char arcs_cmdline[CL_SIZE];
* Registers a0, a1, a3 and a4 as passed to the kenrel entry by firmware
*/
extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
/*
* Platform memory detection hook called by setup_arch
*/
extern void plat_mem_setup(void);
#endif /* _ASM_BOOTINFO_H */
include/asm-mips/ddb5074.h
-11
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@@ -1,11 +0,0 @@
/*
* include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
extern void ddb5074_led_hex(int hex);
extern void ddb5074_led_d2(int on);
extern void ddb5074_led_d3(int on);
include/asm-mips/ddb5xxx/ddb5074.h
-38
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@@ -1,38 +0,0 @@
/*
* include/asm-mips/ddb5074.h -- NEC DDB Vrc-5074 definitions
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
#ifndef _ASM_DDB5XXX_DDB5074_H
#define _ASM_DDB5XXX_DDB5074_H
#include <asm/nile4.h>
#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
#define DDB_PCI_IO_BASE 0x06000000
#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
#define DDB_PCI_MEM_BASE 0x08000000
#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
#define NILE4_PCI_IO_BASE 0xa6000000
#define NILE4_PCI_MEM_BASE 0xa8000000
#define NILE4_PCI_CFG_BASE NILE4_PCI_MEM_BASE
#define DDB_PCI_IACK_BASE NILE4_PCI_IO_BASE
#define NILE4_IRQ_BASE NUM_I8259_INTERRUPTS
#define CPU_IRQ_BASE (NUM_NILE4_INTERRUPTS + NILE4_IRQ_BASE)
#define CPU_NILE4_CASCADE 2
extern void ddb5074_led_hex(int hex);
extern void ddb5074_led_d2(int on);
extern void ddb5074_led_d3(int on);
extern void nile4_irq_setup(u32 base);
#endif
include/asm-mips/ddb5xxx/ddb5476.h
-157
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@@ -1,157 +0,0 @@
/*
* header file specific for ddb5476
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
/*
* Memory map (physical address)
*
* Note most of the following address must be properly aligned by the
* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
* PCI_IO_BASE must be aligned along 16MB boundary.
*/
#define DDB_SDRAM_BASE 0x00000000
#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
#define DDB_DCS3_BASE 0x04000000 /* flash 1 */
#define DDB_DCS3_SIZE 0x01000000 /* 16MB */
#define DDB_DCS2_BASE 0x05000000 /* flash 2 */
#define DDB_DCS2_SIZE 0x01000000 /* 16MB */
#define DDB_PCI_IO_BASE 0x06000000
#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
#define DDB_PCI_MEM_BASE 0x08000000
#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_DCS5_BASE 0x13000000 /* DDB status regs */
#define DDB_DCS5_SIZE 0x00200000 /* 2MB, 8-bit */
#define DDB_DCS4_BASE 0x14000000 /* DDB control regs */
#define DDB_DCS4_SIZE 0x00200000 /* 2MB, 8-bit */
#define DDB_INTCS_BASE 0x1fa00000 /* VRC5476 control regs */
#define DDB_INTCS_SIZE 0x00200000 /* 2MB */
#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
/* aliases */
#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
/* PCI intr ack share PCIW0 with PCI IO */
#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
/*
* Interrupt mapping
*
* We have three interrupt controllers:
*
* . CPU itself - 8 sources
* . i8259 - 16 sources
* . vrc5476 - 16 sources
*
* They connected as follows:
* all vrc5476 interrupts are routed to cpu IP2 (by software setting)
* all i2869 are routed to INTC in vrc5476 (by hardware connection)
*
* All VRC5476 PCI interrupts are level-triggered (no ack needed).
* All PCI irq but INTC are active low.
*/
/*
* irq number block assignment
*/
#define NUM_CPU_IRQ 8
#define NUM_I8259_IRQ 16
#define NUM_VRC5476_IRQ 16
#define DDB_IRQ_BASE 0
#define I8259_IRQ_BASE DDB_IRQ_BASE
#define VRC5476_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
#define CPU_IRQ_BASE (VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)
/*
* vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
*/
#define VRC5476_IRQ_CPCE 0 /* cpu parity error */
#define VRC5476_IRQ_CNTD 1 /* cpu no target */
#define VRC5476_IRQ_MCE 2 /* memory check error */
#define VRC5476_IRQ_DMA 3 /* DMA */
#define VRC5476_IRQ_UART 4 /* vrc5476 builtin UART, not used */
#define VRC5476_IRQ_WDOG 5 /* watchdog timer */
#define VRC5476_IRQ_GPT 6 /* general purpose timer */
#define VRC5476_IRQ_LBRT 7 /* local bus read timeout */
#define VRC5476_IRQ_INTA 8 /* PCI INT #A */
#define VRC5476_IRQ_INTB 9 /* PCI INT #B */
#define VRC5476_IRQ_INTC 10 /* PCI INT #C */
#define VRC5476_IRQ_INTD 11 /* PCI INT #D */
#define VRC5476_IRQ_INTE 12 /* PCI INT #E */
#define VRC5476_IRQ_RESERVED_13 13 /* reserved */
#define VRC5476_IRQ_PCIS 14 /* PCI SERR # */
#define VRC5476_IRQ_PCI 15 /* PCI internal error */
/*
* i2859 irq assignment
*/
#define I8259_IRQ_RESERVED_0 0
#define I8259_IRQ_KEYBOARD 1 /* M1543 default */
#define I8259_IRQ_CASCADE 2
#define I8259_IRQ_UART_B 3 /* M1543 default, may conflict with RTC according to schematic diagram */
#define I8259_IRQ_UART_A 4 /* M1543 default */
#define I8259_IRQ_PARALLEL 5 /* M1543 default */
#define I8259_IRQ_RESERVED_6 6
#define I8259_IRQ_RESERVED_7 7
#define I8259_IRQ_RTC 8 /* who set this? */
#define I8259_IRQ_USB 9 /* ddb_setup */
#define I8259_IRQ_PMU 10 /* ddb_setup */
#define I8259_IRQ_RESERVED_11 11
#define I8259_IRQ_RESERVED_12 12 /* m1543_irq_setup */
#define I8259_IRQ_RESERVED_13 13
#define I8259_IRQ_HDC1 14 /* default and ddb_setup */
#define I8259_IRQ_HDC2 15 /* default */
/*
* misc
*/
#define VRC5476_I8259_CASCADE VRC5476_IRQ_INTC
#define CPU_VRC5476_CASCADE 2
#define is_i8259_irq(irq) ((irq) < NUM_I8259_IRQ)
#define nile4_to_irq(n) ((n)+NUM_I8259_IRQ)
#define irq_to_nile4(n) ((n)-NUM_I8259_IRQ)
/*
* low-level irq functions
*/
#ifndef __ASSEMBLY__
extern void nile4_map_irq(int nile4_irq, int cpu_irq);
extern void nile4_map_irq_all(int cpu_irq);
extern void nile4_enable_irq(int nile4_irq);
extern void nile4_disable_irq(int nile4_irq);
extern void nile4_disable_irq_all(void);
extern u16 nile4_get_irq_stat(int cpu_irq);
extern void nile4_enable_irq_output(int cpu_irq);
extern void nile4_disable_irq_output(int cpu_irq);
extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
extern void nile4_clear_irq(int nile4_irq);
extern void nile4_clear_irq_mask(u32 mask);
extern u8 nile4_i8259_iack(void);
extern void nile4_dump_irq_status(void); /* Debug */
#endif /* !__ASSEMBLY__ */
include/asm-mips/ddb5xxx/ddb5xxx.h
+1 -10
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@@ -174,13 +174,8 @@
static inline void ddb_sync(void)
{
/* The DDB5074 doesn't seem to like these accesses. They kill the board on
* interrupt load
*/
#ifndef CONFIG_DDB5074
volatile u32 *p = (volatile u32 *)0xbfc00000;
(void)(*p);
#endif
}
static inline void ddb_out32(u32 offset, u32 val)
@@ -260,11 +255,7 @@ extern void ddb_pci_reset_bus(void);
/*
* include the board dependent part
*/
#if defined(CONFIG_DDB5074)
#include <asm/ddb5xxx/ddb5074.h>
#elif defined(CONFIG_DDB5476)
#include <asm/ddb5xxx/ddb5476.h>
#elif defined(CONFIG_DDB5477)
#if defined(CONFIG_DDB5477)
#include <asm/ddb5xxx/ddb5477.h>
#else
#error "Unknown DDB board!"
include/asm-mips/emma2rh/emma2rh.h
+330
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@@ -0,0 +1,330 @@
/*
* include/asm-mips/emma2rh/emma2rh.h
* This file is EMMA2RH common header.
*
* Copyright (C) NEC Electronics Corporation 2005-2006
*
* This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef __ASM_EMMA2RH_EMMA2RH_H
#define __ASM_EMMA2RH_EMMA2RH_H
/*
* EMMA2RH registers
*/
#define REGBASE 0x10000000
#define EMMA2RH_BHIF_STRAP_0 (0x000010+REGBASE)
#define EMMA2RH_BHIF_INT_ST_0 (0x000030+REGBASE)
#define EMMA2RH_BHIF_INT_ST_1 (0x000034+REGBASE)
#define EMMA2RH_BHIF_INT_ST_2 (0x000038+REGBASE)
#define EMMA2RH_BHIF_INT_EN_0 (0x000040+REGBASE)
#define EMMA2RH_BHIF_INT_EN_1 (0x000044+REGBASE)
#define EMMA2RH_BHIF_INT_EN_2 (0x000048+REGBASE)
#define EMMA2RH_BHIF_INT1_EN_0 (0x000050+REGBASE)
#define EMMA2RH_BHIF_INT1_EN_1 (0x000054+REGBASE)
#define EMMA2RH_BHIF_INT1_EN_2 (0x000058+REGBASE)
#define EMMA2RH_BHIF_SW_INT (0x000070+REGBASE)
#define EMMA2RH_BHIF_SW_INT_EN (0x000080+REGBASE)
#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE)
#define EMMA2RH_BHIF_MAIN_CTRL (0x0000b4+REGBASE)
#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS (0x0000c0+REGBASE)
#define EMMA2RH_GPIO_DIR (0x110d20+REGBASE)
#define EMMA2RH_GPIO_INT_ST (0x110d30+REGBASE)
#define EMMA2RH_GPIO_INT_MASK (0x110d3c+REGBASE)
#define EMMA2RH_GPIO_INT_MODE (0x110d48+REGBASE)
#define EMMA2RH_GPIO_INT_CND_A (0x110d54+REGBASE)
#define EMMA2RH_GPIO_INT_CND_B (0x110d60+REGBASE)
#define EMMA2RH_PBRD_INT_EN (0x100010+REGBASE)
#define EMMA2RH_PBRD_CLKSEL (0x100028+REGBASE)
#define EMMA2RH_PFUR0_BASE (0x101000+REGBASE)
#define EMMA2RH_PFUR1_BASE (0x102000+REGBASE)
#define EMMA2RH_PFUR2_BASE (0x103000+REGBASE)
#define EMMA2RH_PIIC0_BASE (0x107000+REGBASE)
#define EMMA2RH_PIIC1_BASE (0x108000+REGBASE)
#define EMMA2RH_PIIC2_BASE (0x109000+REGBASE)
#define EMMA2RH_PCI_CONTROL (0x200000+REGBASE)
#define EMMA2RH_PCI_ARBIT_CTR (0x200004+REGBASE)
#define EMMA2RH_PCI_IWIN0_CTR (0x200010+REGBASE)
#define EMMA2RH_PCI_IWIN1_CTR (0x200014+REGBASE)
#define EMMA2RH_PCI_INIT_ESWP (0x200018+REGBASE)
#define EMMA2RH_PCI_INT (0x200020+REGBASE)
#define EMMA2RH_PCI_INT_EN (0x200024+REGBASE)
#define EMMA2RH_PCI_TWIN_CTR (0x200030+REGBASE)
#define EMMA2RH_PCI_TWIN_BADR (0x200034+REGBASE)
#define EMMA2RH_PCI_TWIN0_DADR (0x200038+REGBASE)
#define EMMA2RH_PCI_TWIN1_DADR (0x20003c+REGBASE)
/*
* Memory map (physical address)
*
* Note most of the following address must be properly aligned by the
* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
* PCI_IO_BASE must be aligned along 16MB boundary.
*/
/* the actual ram size is detected at run-time */
#define EMMA2RH_RAM_BASE 0x00000000
#define EMMA2RH_RAM_SIZE 0x10000000 /* less than 256MB */
#define EMMA2RH_IO_BASE 0x10000000
#define EMMA2RH_IO_SIZE 0x01000000 /* 16 MB */
#define EMMA2RH_GENERALIO_BASE 0x11000000
#define EMMA2RH_GENERALIO_SIZE 0x01000000 /* 16 MB */
#define EMMA2RH_PCI_IO_BASE 0x12000000
#define EMMA2RH_PCI_IO_SIZE 0x02000000 /* 32 MB */
#define EMMA2RH_PCI_MEM_BASE 0x14000000
#define EMMA2RH_PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define EMMA2RH_ROM_BASE 0x1c000000
#define EMMA2RH_ROM_SIZE 0x04000000 /* 64 MB */
#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
#define NUM_CPU_IRQ 8
#define NUM_EMMA2RH_IRQ 96
#define CPU_EMMA2RH_CASCADE 2
#define EMMA2RH_IRQ_BASE 0
/*
* emma2rh irq defs
*/
#define EMMA2RH_IRQ_INT0 (0 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT1 (1 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT2 (2 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT3 (3 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT4 (4 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT5 (5 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT6 (6 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT7 (7 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT8 (8 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT9 (9 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT10 (10 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT11 (11 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT12 (12 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT13 (13 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT14 (14 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT15 (15 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT16 (16 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT17 (17 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT18 (18 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT19 (19 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT20 (20 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT21 (21 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT22 (22 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT23 (23 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT24 (24 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT25 (25 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT26 (26 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT27 (27 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT28 (28 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT29 (29 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT30 (30 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT31 (31 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT32 (32 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT33 (33 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT34 (34 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT35 (35 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT36 (36 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT37 (37 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT38 (38 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT39 (39 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT40 (40 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT41 (41 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT42 (42 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT43 (43 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT44 (44 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT45 (45 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT46 (46 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT47 (47 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT48 (48 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT49 (49 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT50 (50 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT51 (51 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT52 (52 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT53 (53 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT54 (54 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT55 (55 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT56 (56 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT57 (57 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT58 (58 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT59 (59 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT60 (60 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT61 (61 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT62 (62 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_INT63 (63 + EMMA2RH_IRQ_BASE)
#define EMMA2RH_IRQ_PFUR0 EMMA2RH_IRQ_INT49
#define EMMA2RH_IRQ_PFUR1 EMMA2RH_IRQ_INT50
#define EMMA2RH_IRQ_PFUR2 EMMA2RH_IRQ_INT51
#define EMMA2RH_IRQ_PIIC0 EMMA2RH_IRQ_INT56
#define EMMA2RH_IRQ_PIIC1 EMMA2RH_IRQ_INT57
#define EMMA2RH_IRQ_PIIC2 EMMA2RH_IRQ_INT58
/*
* EMMA2RH Register Access
*/
#define EMMA2RH_BASE (0xa0000000)
static inline void emma2rh_sync(void)
{
volatile u32 *p = (volatile u32 *)0xbfc00000;
(void)(*p);
}
static inline void emma2rh_out32(u32 offset, u32 val)
{
*(volatile u32 *)(EMMA2RH_BASE | offset) = val;
emma2rh_sync();
}
static inline u32 emma2rh_in32(u32 offset)
{
u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
emma2rh_sync();
return val;
}
static inline void emma2rh_out16(u32 offset, u16 val)
{
*(volatile u16 *)(EMMA2RH_BASE | offset) = val;
emma2rh_sync();
}
static inline u16 emma2rh_in16(u32 offset)
{
u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
emma2rh_sync();
return val;
}
static inline void emma2rh_out8(u32 offset, u8 val)
{
*(volatile u8 *)(EMMA2RH_BASE | offset) = val;
emma2rh_sync();
}
static inline u8 emma2rh_in8(u32 offset)
{
u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
emma2rh_sync();
return val;
}
/**
* IIC registers map
**/
/*---------------------------------------------------------------------------*/
/* CNT - Control register (00H R/W) */
/*---------------------------------------------------------------------------*/
#define SPT 0x00000001
#define STT 0x00000002
#define ACKE 0x00000004
#define WTIM 0x00000008
#define SPIE 0x00000010
#define WREL 0x00000020
#define LREL 0x00000040
#define IICE 0x00000080
#define CNT_RESERVED 0x000000ff /* reserved bit 0 */
#define I2C_EMMA_START (IICE | STT)
#define I2C_EMMA_STOP (IICE | SPT)
#define I2C_EMMA_REPSTART I2C_EMMA_START
/*---------------------------------------------------------------------------*/
/* STA - Status register (10H Read) */
/*---------------------------------------------------------------------------*/
#define MSTS 0x00000080
#define ALD 0x00000040
#define EXC 0x00000020
#define COI 0x00000010
#define TRC 0x00000008
#define ACKD 0x00000004
#define STD 0x00000002
#define SPD 0x00000001
/*---------------------------------------------------------------------------*/
/* CSEL - Clock select register (20H R/W) */
/*---------------------------------------------------------------------------*/
#define FCL 0x00000080
#define ND50 0x00000040
#define CLD 0x00000020
#define DAD 0x00000010
#define SMC 0x00000008
#define DFC 0x00000004
#define CL 0x00000003
#define CSEL_RESERVED 0x000000ff /* reserved bit 0 */
#define FAST397 0x0000008b
#define FAST297 0x0000008a
#define FAST347 0x0000000b
#define FAST260 0x0000000a
#define FAST130 0x00000008
#define STANDARD108 0x00000083
#define STANDARD83 0x00000082
#define STANDARD95 0x00000003
#define STANDARD73 0x00000002
#define STANDARD36 0x00000001
#define STANDARD71 0x00000000
/*---------------------------------------------------------------------------*/
/* SVA - Slave address register (30H R/W) */
/*---------------------------------------------------------------------------*/
#define SVA 0x000000fe
/*---------------------------------------------------------------------------*/
/* SHR - Shift register (40H R/W) */
/*---------------------------------------------------------------------------*/
#define SR 0x000000ff
/*---------------------------------------------------------------------------*/
/* INT - Interrupt register (50H R/W) */
/* INTM - Interrupt mask register (60H R/W) */
/*---------------------------------------------------------------------------*/
#define INTE0 0x00000001
/***********************************************************************
* I2C registers
***********************************************************************
*/
#define I2C_EMMA_CNT 0x00
#define I2C_EMMA_STA 0x10
#define I2C_EMMA_CSEL 0x20
#define I2C_EMMA_SVA 0x30
#define I2C_EMMA_SHR 0x40
#define I2C_EMMA_INT 0x50
#define I2C_EMMA_INTM 0x60
/*
* include the board dependent part
*/
#if defined(CONFIG_MARKEINS)
#include <asm/emma2rh/markeins.h>
#else
#error "Unknown EMMA2RH board!"
#endif
#endif /* __ASM_EMMA2RH_EMMA2RH_H */
include/asm-mips/emma2rh/markeins.h
+76
View File
@@ -0,0 +1,76 @@
/*
* include/asm-mips/emma2rh/markeins.h
* This file is EMMA2RH board depended header.
*
* Copyright (C) NEC Electronics Corporation 2005-2006
*
* This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
* Copyright 2001 MontaVista Software Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#ifndef MARKEINS_H
#define MARKEINS_H
#define NUM_EMMA2RH_IRQ_SW 32
#define NUM_EMMA2RH_IRQ_GPIO 32
#define EMMA2RH_SW_CASCADE (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
#define EMMA2RH_GPIO_CASCADE (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
#define EMMA2RH_SW_IRQ_BASE (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
#define EMMA2RH_GPIO_IRQ_BASE (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
#define CPU_IRQ_BASE (EMMA2RH_GPIO_IRQ_BASE + NUM_EMMA2RH_IRQ_GPIO)
#define EMMA2RH_SW_IRQ_INT0 (0+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT1 (1+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT2 (2+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT3 (3+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT4 (4+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT5 (5+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT6 (6+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT7 (7+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT8 (8+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT9 (9+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT10 (10+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT11 (11+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT12 (12+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT13 (13+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT14 (14+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT15 (15+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT16 (16+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT17 (17+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT18 (18+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT19 (19+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT20 (20+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT21 (21+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT22 (22+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT23 (23+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT24 (24+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT25 (25+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT26 (26+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT27 (27+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT28 (28+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT29 (29+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT30 (30+EMMA2RH_SW_IRQ_BASE)
#define EMMA2RH_SW_IRQ_INT31 (31+EMMA2RH_SW_IRQ_BASE)
#define MARKEINS_PCI_IRQ_INTA EMMA2RH_GPIO_IRQ_BASE+15
#define MARKEINS_PCI_IRQ_INTB EMMA2RH_GPIO_IRQ_BASE+16
#define MARKEINS_PCI_IRQ_INTC EMMA2RH_GPIO_IRQ_BASE+17
#define MARKEINS_PCI_IRQ_INTD EMMA2RH_GPIO_IRQ_BASE+18
#endif /* CONFIG_MARKEINS */
include/asm-mips/fpu.h
+1 -2
View File
@@ -138,10 +138,9 @@ static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
if (cpu_has_fpu) {
if ((tsk == current) && __is_fpu_owner())
_save_fp(current);
return tsk->thread.fpu.hard.fpr;
}
return tsk->thread.fpu.soft.fpr;
return tsk->thread.fpu.fpr;
}
#endif /* _ASM_FPU_H */
include/asm-mips/fpu_emulator.h
+2 -2
View File
@@ -12,8 +12,8 @@
* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
*
* Further private data for which no space exists in mips_fpu_soft_struct.
* This should be subsumed into the mips_fpu_soft_struct structure as
* Further private data for which no space exists in mips_fpu_struct.
* This should be subsumed into the mips_fpu_struct structure as
* defined in processor.h as soon as the absurd wired absolute assembler
* offsets become dynamic at compile time.
*
include/asm-mips/futex.h
+17 -15
View File
@@ -22,51 +22,53 @@
" .set push \n" \
" .set noat \n" \
" .set mips3 \n" \
"1: ll %1, (%3) # __futex_atomic_op \n" \
"1: ll %1, %4 # __futex_atomic_op \n" \
" .set mips0 \n" \
" " insn " \n" \
" .set mips3 \n" \
"2: sc $1, (%3) \n" \
"2: sc $1, %2 \n" \
" beqzl $1, 1b \n" \
__FUTEX_SMP_SYNC \
"3: \n" \
" .set pop \n" \
" .set mips0 \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %5 \n" \
"4: li %0, %6 \n" \
" j 2b \n" \
" .previous \n" \
" .section __ex_table,\"a\" \n" \
" "__UA_ADDR "\t1b, 4b \n" \
" "__UA_ADDR "\t2b, 4b \n" \
" .previous \n" \
: "=r" (ret), "=r" (oldval) \
: "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \
: "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
: "memory"); \
} else if (cpu_has_llsc) { \
__asm__ __volatile__( \
" .set push \n" \
" .set noat \n" \
" .set mips3 \n" \
"1: ll %1, (%3) # __futex_atomic_op \n" \
"1: ll %1, %4 # __futex_atomic_op \n" \
" .set mips0 \n" \
" " insn " \n" \
" .set mips3 \n" \
"2: sc $1, (%3) \n" \
"2: sc $1, %2 \n" \
" beqz $1, 1b \n" \
__FUTEX_SMP_SYNC \
"3: \n" \
" .set pop \n" \
" .set mips0 \n" \
" .section .fixup,\"ax\" \n" \
"4: li %0, %5 \n" \
"4: li %0, %6 \n" \
" j 2b \n" \
" .previous \n" \
" .section __ex_table,\"a\" \n" \
" "__UA_ADDR "\t1b, 4b \n" \
" "__UA_ADDR "\t2b, 4b \n" \
" .previous \n" \
: "=r" (ret), "=r" (oldval) \
: "0" (0), "r" (uaddr), "Jr" (oparg), "i" (-EFAULT)); \
: "=r" (ret), "=&r" (oldval), "=R" (*uaddr) \
: "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT) \
: "memory"); \
} else \
ret = -ENOSYS; \
}
@@ -89,23 +91,23 @@ futex_atomic_op_inuser (int encoded_op, int __user *uaddr)
switch (op) {
case FUTEX_OP_SET:
__futex_atomic_op("move $1, %z4", ret, oldval, uaddr, oparg);
__futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
break;
case FUTEX_OP_ADD:
__futex_atomic_op("addu $1, %1, %z4",
__futex_atomic_op("addu $1, %1, %z5",
ret, oldval, uaddr, oparg);
break;
case FUTEX_OP_OR:
__futex_atomic_op("or $1, %1, %z4",
__futex_atomic_op("or $1, %1, %z5",
ret, oldval, uaddr, oparg);
break;
case FUTEX_OP_ANDN:
__futex_atomic_op("and $1, %1, %z4",
__futex_atomic_op("and $1, %1, %z5",
ret, oldval, uaddr, ~oparg);
break;
case FUTEX_OP_XOR:
__futex_atomic_op("xor $1, %1, %z4",
__futex_atomic_op("xor $1, %1, %z5",
ret, oldval, uaddr, oparg);
break;
default:
include/asm-mips/mach-ddb5074/mc146818rtc.h
-31
View File
@@ -1,31 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1998, 2001, 03 by Ralf Baechle
*
* RTC routines for PC style attached Dallas chip.
*/
#ifndef __ASM_MACH_DDB5074_MC146818RTC_H
#define __ASM_MACH_DDB5074_MC146818RTC_H
#include <asm/ddb5xxx/ddb5074.h>
#include <asm/ddb5xxx/ddb5xxx.h>
#define RTC_PORT(x) (0x70 + (x))
#define RTC_IRQ 8
static inline unsigned char CMOS_READ(unsigned long addr)
{
return *(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr);
}
static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
{
*(volatile unsigned char *)(KSEG1ADDR(DDB_PCI_MEM_BASE)+addr) = data;
}
#define RTC_ALWAYS_BCD 1
#endif /* __ASM_MACH_DDB5074_MC146818RTC_H */
include/asm-mips/mach-dec/param.h
-18
View File
@@ -1,18 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 by Ralf Baechle
*/
#ifndef __ASM_MACH_DEC_PARAM_H
#define __ASM_MACH_DEC_PARAM_H
/*
* log2(HZ), change this here if you want another HZ value. This is also
* used in dec_time_init. Minimum is 1, Maximum is 15.
*/
#define LOG_2_HZ 7
#define HZ (1 << LOG_2_HZ)
#endif /* __ASM_MACH_DEC_PARAM_H */
include/asm-mips/mach-mips/param.h → include/asm-mips/mach-emma2rh/irq.h
+4 -4
View File
@@ -5,9 +5,9 @@
*
* Copyright (C) 2003 by Ralf Baechle
*/
#ifndef __ASM_MACH_MIPS_PARAM_H
#define __ASM_MACH_MIPS_PARAM_H
#ifndef __ASM_MACH_EMMA2RH_IRQ_H
#define __ASM_MACH_EMMA2RH_IRQ_H
#define HZ 100 /* Internal kernel timer frequency */
#define NR_IRQS 256
#endif /* __ASM_MACH_MIPS_PARAM_H */
#endif /* __ASM_MACH_EMMA2RH_IRQ_H */
include/asm-mips/mach-excite/cpu-feature-overrides.h
+40
View File
@@ -0,0 +1,40 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
*/
#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
/*
* Basler eXcite has an RM9122 processor.
*/
#define cpu_has_watch 1
#define cpu_has_mips16 0
#define cpu_has_divec 0
#define cpu_has_vce 0
#define cpu_has_cache_cdex_p 0
#define cpu_has_cache_cdex_s 0
#define cpu_has_prefetch 1
#define cpu_has_mcheck 0
#define cpu_has_ejtag 0
#define cpu_has_llsc 1
#define cpu_has_vtag_icache 0
#define cpu_has_dc_aliases 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_icache_snoops_remote_store 0
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_subset_pcaches 0
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 32
#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
include/asm-mips/mach-excite/excite.h
+155
View File
@@ -0,0 +1,155 @@
#ifndef __EXCITE_H__
#define __EXCITE_H__
#include <linux/config.h>
#include <linux/init.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#define EXCITE_CPU_EXT_CLOCK 100000000
#if !defined(__ASSEMBLER__)
void __init excite_kgdb_init(void);
void excite_procfs_init(void);
extern unsigned long memsize;
extern char modetty[];
extern u32 unit_id;
#endif
/* Base name for XICAP devices */
#define XICAP_NAME "xicap_gpi"
/* OCD register offsets */
#define LKB0 0x0038
#define LKB5 0x0128
#define LKM5 0x012C
#define LKB7 0x0138
#define LKM7 0x013c
#define LKB8 0x0140
#define LKM8 0x0144
#define LKB9 0x0148
#define LKM9 0x014c
#define LKB10 0x0150
#define LKM10 0x0154
#define LKB11 0x0158
#define LKM11 0x015c
#define LKB12 0x0160
#define LKM12 0x0164
#define LKB13 0x0168
#define LKM13 0x016c
#define LDP0 0x0200
#define LDP1 0x0210
#define LDP2 0x0220
#define LDP3 0x0230
#define INTPIN0 0x0A40
#define INTPIN1 0x0A44
#define INTPIN2 0x0A48
#define INTPIN3 0x0A4C
#define INTPIN4 0x0A50
#define INTPIN5 0x0A54
#define INTPIN6 0x0A58
#define INTPIN7 0x0A5C
/* TITAN register offsets */
#define CPRR 0x0004
#define CPDSR 0x0008
#define CPTC0R 0x000c
#define CPTC1R 0x0010
#define CPCFG0 0x0020
#define CPCFG1 0x0024
#define CPDST0A 0x0028
#define CPDST0B 0x002c
#define CPDST1A 0x0030
#define CPDST1B 0x0034
#define CPXDSTA 0x0038
#define CPXDSTB 0x003c
#define CPXCISRA 0x0048
#define CPXCISRB 0x004c
#define CPGIG0ER 0x0050
#define CPGIG1ER 0x0054
#define CPGRWL 0x0068
#define CPURSLMT 0x00f8
#define UACFG 0x0200
#define UAINTS 0x0204
#define SDRXFCIE 0x4828
#define SDTXFCIE 0x4928
#define INTP0Status0 0x1B00
#define INTP0Mask0 0x1B04
#define INTP0Set0 0x1B08
#define INTP0Clear0 0x1B0C
#define GXCFG 0x5000
#define GXDMADRPFX 0x5018
#define GXDMA_DESCADR 0x501c
#define GXCH0TDESSTRT 0x5054
/* IRQ definitions */
#define NMICONFIG 0xac0
#define TITAN_MSGINT 0xc4
#define TITAN_IRQ ((TITAN_MSGINT / 0x20) + 2)
#define FPGA0_MSGINT 0x5a
#define FPGA0_IRQ ((FPGA0_MSGINT / 0x20) + 2)
#define FPGA1_MSGINT 0x7b
#define FPGA1_IRQ ((FPGA1_MSGINT / 0x20) + 2)
#define PHY_MSGINT 0x9c
#define PHY_IRQ ((PHY_MSGINT / 0x20) + 2)
#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
/* Pre-release units used interrupt pin #9 */
#define USB_IRQ 11
#else
/* Re-designed units use interrupt pin #1 */
#define USB_MSGINT 0x39
#define USB_IRQ ((USB_MSGINT / 0x20) + 2)
#endif
#define TIMER_IRQ 12
/* Device address ranges */
#define EXCITE_OFFS_OCD 0x1fffc000
#define EXCITE_SIZE_OCD (16 * 1024)
#define EXCITE_PHYS_OCD CPHYSADDR(EXCITE_OFFS_OCD)
#define EXCITE_ADDR_OCD CKSEG1ADDR(EXCITE_OFFS_OCD)
#define EXCITE_OFFS_SCRAM 0x1fffa000
#define EXCITE_SIZE_SCRAM (8 << 10)
#define EXCITE_PHYS_SCRAM CPHYSADDR(EXCITE_OFFS_SCRAM)
#define EXCITE_ADDR_SCRAM CKSEG1ADDR(EXCITE_OFFS_SCRAM)
#define EXCITE_OFFS_PCI_IO 0x1fff8000
#define EXCITE_SIZE_PCI_IO (8 << 10)
#define EXCITE_PHYS_PCI_IO CPHYSADDR(EXCITE_OFFS_PCI_IO)
#define EXCITE_ADDR_PCI_IO CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
#define EXCITE_OFFS_TITAN 0x1fff0000
#define EXCITE_SIZE_TITAN (32 << 10)
#define EXCITE_PHYS_TITAN CPHYSADDR(EXCITE_OFFS_TITAN)
#define EXCITE_ADDR_TITAN CKSEG1ADDR(EXCITE_OFFS_TITAN)
#define EXCITE_OFFS_PCI_MEM 0x1ffe0000
#define EXCITE_SIZE_PCI_MEM (64 << 10)
#define EXCITE_PHYS_PCI_MEM CPHYSADDR(EXCITE_OFFS_PCI_MEM)
#define EXCITE_ADDR_PCI_MEM CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
#define EXCITE_OFFS_FPGA 0x1ffdc000
#define EXCITE_SIZE_FPGA (16 << 10)
#define EXCITE_PHYS_FPGA CPHYSADDR(EXCITE_OFFS_FPGA)
#define EXCITE_ADDR_FPGA CKSEG1ADDR(EXCITE_OFFS_FPGA)
#define EXCITE_OFFS_NAND 0x1ffd8000
#define EXCITE_SIZE_NAND (16 << 10)
#define EXCITE_PHYS_NAND CPHYSADDR(EXCITE_OFFS_NAND)
#define EXCITE_ADDR_NAND CKSEG1ADDR(EXCITE_OFFS_NAND)
#define EXCITE_OFFS_BOOTROM 0x1f000000
#define EXCITE_SIZE_BOOTROM (8 << 20)
#define EXCITE_PHYS_BOOTROM CPHYSADDR(EXCITE_OFFS_BOOTROM)
#define EXCITE_ADDR_BOOTROM CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
/* FPGA address offsets */
#define EXCITE_FPGA_DPR 0x0104 /* dual-ported ram */
#define EXCITE_FPGA_SYSCTL 0x0200 /* system control register block */
#endif /* __EXCITE_H__ */
include/asm-mips/mach-excite/excite_nandflash.h
+7
View File
@@ -0,0 +1,7 @@
#ifndef __EXCITE_NANDFLASH_H__
#define __EXCITE_NANDFLASH_H__
/* Resource names */
#define EXCITE_NANDFLASH_RESOURCE_REGS "excite_nandflash_regs"
#endif /* __EXCITE_NANDFLASH_H__ */
include/asm-mips/mach-excite/rm9k_eth.h
+23
View File
@@ -0,0 +1,23 @@
#if !defined(__RM9K_ETH_H__)
#define __RM9K_ETH_H__
#define RM9K_GE_NAME "rm9k_ge"
/* Resource names */
#define RM9K_GE_RESOURCE_MAC "rm9k_ge_mac"
#define RM9K_GE_RESOURCE_MSTAT "rm9k_ge_mstat"
#define RM9K_GE_RESOURCE_PKTPROC "rm9k_ge_pktproc"
#define RM9K_GE_RESOURCE_XDMA "rm9k_ge_xdma"
#define RM9K_GE_RESOURCE_FIFO_RX "rm9k_ge_fifo_rx"
#define RM9K_GE_RESOURCE_FIFO_TX "rm9k_ge_fifo_tx"
#define RM9K_GE_RESOURCE_FIFOMEM_RX "rm9k_ge_fifo_memory_rx"
#define RM9K_GE_RESOURCE_FIFOMEM_TX "rm9k_ge_fifo_memory_tx"
#define RM9K_GE_RESOURCE_PHY "rm9k_ge_phy"
#define RM9K_GE_RESOURCE_DMADESC_RX "rm9k_ge_dmadesc_rx"
#define RM9K_GE_RESOURCE_DMADESC_TX "rm9k_ge_dmadesc_tx"
#define RM9K_GE_RESOURCE_IRQ_MAIN "rm9k_ge_irq_main"
#define RM9K_GE_RESOURCE_IRQ_PHY "rm9k_ge_irq_phy"
#define RM9K_GE_RESOURCE_GPI_SLICE "rm9k_ge_gpi_slice"
#define RM9K_GE_RESOURCE_MDIO_CHANNEL "rm9k_ge_mdio_channel"
#endif /* !defined(__RM9K_ETH_H__) */
include/asm-mips/mach-excite/rm9k_wdt.h
+12
View File
@@ -0,0 +1,12 @@
#ifndef __RM9K_WDT_H__
#define __RM9K_WDT_H__
/* Device name */
#define WDT_NAME "wdt_gpi"
/* Resource names */
#define WDT_RESOURCE_REGS "excite_watchdog_regs"
#define WDT_RESOURCE_IRQ "excite_watchdog_irq"
#define WDT_RESOURCE_COUNTER "excite_watchdog_counter"
#endif /* __RM9K_WDT_H__ */
include/asm-mips/mach-excite/rm9k_xicap.h
+16
View File
@@ -0,0 +1,16 @@
#ifndef __EXCITE_XICAP_H__
#define __EXCITE_XICAP_H__
/* Resource names */
#define XICAP_RESOURCE_FIFO_RX "xicap_fifo_rx"
#define XICAP_RESOURCE_FIFO_TX "xicap_fifo_tx"
#define XICAP_RESOURCE_XDMA "xicap_xdma"
#define XICAP_RESOURCE_DMADESC "xicap_dmadesc"
#define XICAP_RESOURCE_PKTPROC "xicap_pktproc"
#define XICAP_RESOURCE_IRQ "xicap_irq"
#define XICAP_RESOURCE_GPI_SLICE "xicap_gpi_slice"
#define XICAP_RESOURCE_FIFO_BLK "xicap_fifo_blocks"
#define XICAP_RESOURCE_PKT_STREAM "xicap_pkt_stream"
#endif /* __EXCITE_XICAP_H__ */
include/asm-mips/mach-generic/param.h
-13
View File
@@ -1,13 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 by Ralf Baechle
*/
#ifndef __ASM_MACH_GENERIC_PARAM_H
#define __ASM_MACH_GENERIC_PARAM_H
#define HZ 1000 /* Internal kernel timer frequency */
#endif /* __ASM_MACH_GENERIC_PARAM_H */
include/asm-mips/mach-ip22/cpu-feature-overrides.h
+1 -1
View File
@@ -13,7 +13,7 @@
*/
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kcache 1
#define cpu_has_4k_cache 1
#define cpu_has_fpu 1
#define cpu_has_32fpr 1
#define cpu_has_counter 1
include/asm-mips/mach-ip27/cpu-feature-overrides.h
+3
View File
@@ -31,6 +31,9 @@
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_4kex 1
#define cpu_has_4k_cache 1
#define cpu_has_subset_pcaches 1
#define cpu_dcache_line_size() 32
include/asm-mips/mach-ip32/cpu-feature-overrides.h
+2
View File
@@ -38,6 +38,8 @@
#define cpu_has_vtag_icache 0
#define cpu_has_ic_fills_f_dc 0
#define cpu_has_dsp 0
#define cpu_has_4k_cache 1
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
include/asm-mips/mach-jazz/param.h
-16
View File
@@ -1,16 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003 by Ralf Baechle
*/
#ifndef __ASM_MACH_JAZZ_PARAM_H
#define __ASM_MACH_JAZZ_PARAM_H
/*
* Jazz is currently using the internal 100Hz timer of the R4030
*/
#define HZ 100 /* Internal kernel timer frequency */
#endif /* __ASM_MACH_JAZZ_PARAM_H */
include/asm-mips/mach-mips/cpu-feature-overrides.h
+2 -2
View File
@@ -17,7 +17,7 @@
#ifdef CONFIG_CPU_MIPS32
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kcache 1
#define cpu_has_4k_cache 1
/* #define cpu_has_fpu ? */
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
@@ -47,7 +47,7 @@
#ifdef CONFIG_CPU_MIPS64
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kcache 1
#define cpu_has_4k_cache 1
/* #define cpu_has_fpu ? */
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
include/asm-mips/mach-qemu/param.h
-13
View File
@@ -1,13 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2005 by Ralf Baechle
*/
#ifndef __ASM_MACH_QEMU_PARAM_H
#define __ASM_MACH_QEMU_PARAM_H
#define HZ 100 /* Internal kernel timer frequency */
#endif /* __ASM_MACH_QEMU_PARAM_H */
include/asm-mips/mach-rm200/cpu-feature-overrides.h
+1 -3
View File
@@ -14,7 +14,7 @@
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kcache 1
#define cpu_has_4k_cache 1
#define cpu_has_fpu 1
#define cpu_has_32fpr 1
#define cpu_has_counter 1
@@ -35,10 +35,8 @@
#define cpu_has_nofpuex 0
#define cpu_has_64bits 1
#define cpu_has_subset_pcaches 0 /* No S-cache on R5000 I think ... */
#define cpu_dcache_line_size() 32
#define cpu_icache_line_size() 32
#define cpu_scache_line_size() 0 /* No S-cache on R5000 I think ... */
#define cpu_has_mips32r1 0
#define cpu_has_mips32r2 0
include/asm-mips/mach-sim/cpu-feature-overrides.h
+2 -2
View File
@@ -16,7 +16,7 @@
#ifdef CONFIG_CPU_MIPS32
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kcache 1
#define cpu_has_4k_cache 1
#define cpu_has_fpu 0
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
@@ -41,7 +41,7 @@
#ifdef CONFIG_CPU_MIPS64
#define cpu_has_tlb 1
#define cpu_has_4kex 1
#define cpu_has_4kcache 1
#define cpu_has_4k_cache 1
/* #define cpu_has_fpu ? */
/* #define cpu_has_32fpr ? */
#define cpu_has_counter 1
include/asm-mips/mach-wrppmc/mach-gt64120.h
+84
View File
@@ -0,0 +1,84 @@
/*
* This is a direct copy of the ev96100.h file, with a global
* search and replace. The numbers are the same.
*
* The reason I'm duplicating this is so that the 64120/96100
* defines won't be confusing in the source code.
*/
#ifndef __ASM_MIPS_GT64120_H
#define __ASM_MIPS_GT64120_H
/*
* This is the CPU physical memory map of PPMC Board:
*
* 0x00000000-0x03FFFFFF - 64MB SDRAM (SCS[0]#)
* 0x1C000000-0x1C000000 - LED (CS0)
* 0x1C800000-0x1C800007 - UART 16550 port (CS1)
* 0x1F000000-0x1F000000 - MailBox (CS3)
* 0x1FC00000-0x20000000 - 4MB Flash (BOOT CS)
*/
#define WRPPMC_SDRAM_SCS0_BASE 0x00000000
#define WRPPMC_SDRAM_SCS0_SIZE 0x04000000
#define WRPPMC_UART16550_BASE 0x1C800000
#define WRPPMC_UART16550_CLOCK 3686400 /* 3.68MHZ */
#define WRPPMC_LED_BASE 0x1C000000
#define WRPPMC_MBOX_BASE 0x1F000000
#define WRPPMC_BOOTROM_BASE 0x1FC00000
#define WRPPMC_BOOTROM_SIZE 0x00400000 /* 4M Flash */
#define WRPPMC_MIPS_TIMER_IRQ 7 /* MIPS compare/count timer interrupt */
#define WRPPMC_UART16550_IRQ 6
#define WRPPMC_PCI_INTA_IRQ 3
/*
* PCI Bus I/O and Memory resources allocation
*
* NOTE: We only have PCI_0 hose interface
*/
#define GT_PCI_MEM_BASE 0x13000000UL
#define GT_PCI_MEM_SIZE 0x02000000UL
#define GT_PCI_IO_BASE 0x11000000UL
#define GT_PCI_IO_SIZE 0x02000000UL
#define GT_ISA_IO_BASE PCI_IO_BASE
/*
* PCI interrupts will come in on either the INTA or INTD interrups lines,
* which are mapped to the #2 and #5 interrupt pins of the MIPS. On our
* boards, they all either come in on IntD or they all come in on IntA, they
* aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
* "requested" interrupt numbers and go through the list whenever we get an
* IntA/D.
*
* Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
* INTD is 11.
*/
#define GT_TIMER 4
#define GT_INTA 2
#define GT_INTD 5
#ifndef __ASSEMBLY__
/*
* GT64120 internal register space base address
*/
extern unsigned long gt64120_base;
#define GT64120_BASE (gt64120_base)
/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
#undef WRPPMC_EARLY_DEBUG
#ifdef WRPPMC_EARLY_DEBUG
extern void wrppmc_led_on(int mask);
extern void wrppmc_led_off(int mask);
extern void wrppmc_early_printk(const char *fmt, ...);
#else
#define wrppmc_early_printk(fmt, ...) do {} while (0)
#endif /* WRPPMC_EARLY_DEBUG */
#endif /* __ASSEMBLY__ */
#endif /* __ASM_MIPS_GT64120_H */
include/asm-mips/mipsregs.h
+1 -3
View File
@@ -1451,12 +1451,10 @@ static inline void __emt(unsigned int previous)
{
if ((previous & __EMT_ENABLE))
__asm__ __volatile__(
" .set noreorder \n"
" .set mips32r2 \n"
" .word 0x41600be1 # emt \n"
" ehb \n"
" .set mips0 \n"
" .set reorder \n");
" .set mips0 \n");
}
static inline void __ehb(void)
include/asm-mips/mmzone.h
-11
View File
@@ -14,17 +14,6 @@
#define kvaddr_to_nid(kvaddr) pa_to_nid(__pa(kvaddr))
#define pfn_to_nid(pfn) pa_to_nid((pfn) << PAGE_SHIFT)
#define pfn_valid(pfn) \
({ \
unsigned long __pfn = (pfn); \
int __n = pfn_to_nid(__pfn); \
((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn + \
NODE_DATA(__n)->node_spanned_pages) : 0);\
})
/* XXX: FIXME -- wli */
#define kern_addr_valid(addr) (0)
#endif /* CONFIG_DISCONTIGMEM */
#endif /* _ASM_MMZONE_H_ */
include/asm-mips/page.h
+19
View File
@@ -145,6 +145,25 @@ typedef struct { unsigned long pgprot; } pgprot_t;
#endif
#endif
#ifdef CONFIG_FLATMEM
#define pfn_valid(pfn) ((pfn) < max_mapnr)
#elif defined(CONFIG_NEED_MULTIPLE_NODES)
#define pfn_valid(pfn) \
({ \
unsigned long __pfn = (pfn); \
int __n = pfn_to_nid(__pfn); \
((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn + \
NODE_DATA(__n)->node_spanned_pages) \
: 0); \
})
#else
#error Provide a definition of pfn_valid
#endif
#define virt_to_page(kaddr) pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
include/asm-mips/param.h
+1 -1
View File
@@ -11,7 +11,7 @@
#ifdef __KERNEL__
# include <param.h> /* Internal kernel timer frequency */
# define HZ CONFIG_HZ /* Internal kernel timer frequency */
# define USER_HZ 100 /* .. some user interfaces are in "ticks" */
# define CLOCKS_PER_SEC (USER_HZ) /* like times() */
#endif
include/asm-mips/pci/bridge.h
+3
View File
@@ -15,6 +15,7 @@
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/xtalk/xwidget.h> /* generic widget header */
#include <asm/sn/types.h>
/* I/O page size */
@@ -848,4 +849,6 @@ struct bridge_controller {
extern void register_bridge_irq(unsigned int irq);
extern int request_bridge_irq(struct bridge_controller *bc);
extern struct pci_ops bridge_pci_ops;
#endif /* _ASM_PCI_BRIDGE_H */
include/asm-mips/pgtable.h
-2
View File
@@ -379,9 +379,7 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
__update_cache(vma, address, pte);
}
#ifndef CONFIG_NEED_MULTIPLE_NODES
#define kern_addr_valid(addr) (1)
#endif
#ifdef CONFIG_64BIT_PHYS_ADDR
extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
include/asm-mips/processor.h
+3 -13
View File
@@ -71,11 +71,6 @@ extern unsigned int vced_count, vcei_count;
typedef __u64 fpureg_t;
struct mips_fpu_hard_struct {
fpureg_t fpr[NUM_FPU_REGS];
unsigned int fcr31;
};
/*
* It would be nice to add some more fields for emulator statistics, but there
* are a number of fixed offsets in offset.h and elsewhere that would have to
@@ -83,18 +78,13 @@ struct mips_fpu_hard_struct {
* the FPU emulator for now. See asm-mips/fpu_emulator.h.
*/
struct mips_fpu_soft_struct {
struct mips_fpu_struct {
fpureg_t fpr[NUM_FPU_REGS];
unsigned int fcr31;
};
union mips_fpu_union {
struct mips_fpu_hard_struct hard;
struct mips_fpu_soft_struct soft;
};
#define INIT_FPU { \
{{0,},} \
{0,} \
}
#define NUM_DSP_REGS 6
@@ -133,7 +123,7 @@ struct thread_struct {
unsigned long cp0_status;
/* Saved fpu/fpu emulator stuff. */
union mips_fpu_union fpu;
struct mips_fpu_struct fpu;
#ifdef CONFIG_MIPS_MT_FPAFF
/* Emulated instruction count */
unsigned long emulated_fp;
include/asm-mips/qemu.h
+6
View File
@@ -21,4 +21,10 @@
*/
#define QEMU_C0_COUNTER_CLOCK 100000000
/*
* Magic qemu system control location.
*/
#define QEMU_RESTART_REG 0xBFBF0000
#define QEMU_HALT_REG 0xBFBF0004
#endif /* __ASM_QEMU_H */
include/asm-mips/rm9k-ocd.h
+56
View File
@@ -0,0 +1,56 @@
/*
* Copyright (C) 2004 by Basler Vision Technologies AG
* Author: Thomas Koeller <thomas.koeller@baslerweb.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
#if !defined(_ASM_RM9K_OCD_H)
#define _ASM_RM9K_OCD_H
#include <linux/types.h>
#include <linux/spinlock.h>
#include <asm/io.h>
extern volatile void __iomem * const ocd_base;
extern volatile void __iomem * const titan_base;
#define ocd_addr(__x__) (ocd_base + (__x__))
#define titan_addr(__x__) (titan_base + (__x__))
#define scram_addr(__x__) (scram_base + (__x__))
/* OCD register access */
#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__))
#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__))
#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__))
#define ocd_writel(__val__, __offs__) \
__raw_writel((__val__), ocd_addr(__offs__))
#define ocd_writew(__val__, __offs__) \
__raw_writew((__val__), ocd_addr(__offs__))
#define ocd_writeb(__val__, __offs__) \
__raw_writeb((__val__), ocd_addr(__offs__))
/* TITAN register access - 32 bit-wide only */
#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__))
#define titan_writel(__val__, __offs__) \
__raw_writel((__val__), titan_addr(__offs__))
/* Protect access to shared TITAN registers */
extern spinlock_t titan_lock;
extern int titan_irqflags;
#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags)
#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags)
#endif /* !defined(_ASM_RM9K_OCD_H) */
include/asm-mips/sn/addrs.h
-27
View File
@@ -27,13 +27,8 @@
#ifndef __ASSEMBLY__
#if defined(CONFIG_SGI_IO) /* FIXME */
#define PS_UINT_CAST (__psunsigned_t)
#define UINT64_CAST (__uint64_t)
#else /* CONFIG_SGI_IO */
#define PS_UINT_CAST (unsigned long)
#define UINT64_CAST (unsigned long)
#endif /* CONFIG_SGI_IO */
#define HUBREG_CAST (volatile hubreg_t *)
@@ -253,14 +248,6 @@
* for _x.
*/
#ifdef _STANDALONE
/* DO NOT USE THESE DIRECTLY IN THE KERNEL. SEE BELOW. */
#define LOCAL_HUB(_x) (HUBREG_CAST (IALIAS_BASE + (_x)))
#define REMOTE_HUB(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) + \
0x800000 + (_x)))
#endif /* _STANDALONE */
/*
* WARNING:
* When certain Hub chip workaround are defined, it's not sufficient
@@ -327,20 +314,6 @@
PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET)
#define ARCS_SPB_SIZE 0x0400
#ifdef _STANDALONE
#define ARCS_TVECTOR_OFFSET 0x2800
#define ARCS_PVECTOR_OFFSET 0x2c00
/*
* These addresses are used by the master CPU to install the transfer
* and private vectors. All others use the SPB to find them.
*/
#define TVADDR (NODE_CAC_BASE(get_nasid()) + ARCS_TVECTOR_OFFSET)
#define PVADDR (NODE_CAC_BASE(get_nasid()) + ARCS_PVECTOR_OFFSET)
#endif /* _STANDALONE */
#define KLDIR_OFFSET 0x2000
#define KLDIR_ADDR(nasid) \
TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
include/asm-mips/sn/sn0/sn0_fru.h → include/asm-mips/sn/fru.h
+4 -4
View File
@@ -6,10 +6,10 @@
* Derived from IRIX <sys/SN/SN0/sn0_fru.h>
*
* Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
* Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
* Copyright (C) 1999, 2006 Ralf Baechle (ralf@linux-mips)
*/
#ifndef _ASM_SN_SN0_SN0_FRU_H
#define _ASM_SN_SN0_SN0_FRU_H
#ifndef __ASM_SN_FRU_H
#define __ASM_SN_FRU_H
#define MAX_DIMMS 8 /* max # of dimm banks */
#define MAX_PCIDEV 8 /* max # of pci devices on a pci bus */
@@ -41,4 +41,4 @@ typedef struct kf_pci_bus_s {
/* confidence level that the pci dev is bad */
} kf_pci_bus_t;
#endif /* _ASM_SN_SN0_SN0_FRU_H */
#endif /* __ASM_SN_FRU_H */
include/asm-mips/sn/klconfig.h
+3 -86
View File
@@ -37,7 +37,7 @@
//#include <sys/SN/router.h>
// XXX Stolen from <sys/SN/router.h>:
#define MAX_ROUTER_PORTS (6) /* Max. number of ports on a router */
#include <asm/sn/sn0/sn0_fru.h>
#include <asm/sn/fru.h>
//#include <sys/graph.h>
//#include <sys/xtalk/xbow.h>
@@ -54,32 +54,21 @@
#include <asm/sn/agent.h>
#include <asm/arc/types.h>
#include <asm/arc/hinv.h>
#if defined(CONFIG_SGI_IO) || defined(CONFIG_SGI_IP35)
#if defined(CONFIG_SGI_IP35)
// The hack file has to be before vector and after sn0_fru....
#include <asm/hack.h>
#include <asm/sn/vector.h>
#include <asm/xtalk/xtalk.h>
#endif /* CONFIG_SGI_IO || CONFIG_SGI_IP35 */
#endif /* CONFIG_SGI_IP35 */
#endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */
#define KLCFGINFO_MAGIC 0xbeedbabe
#ifdef FRUTEST
typedef u64 klconf_off_t;
#else
typedef s32 klconf_off_t;
#endif
/*
* Some IMPORTANT OFFSETS. These are the offsets on all NODES.
*/
#if 0
#define RAMBASE 0
#define ARCSSPB_OFF 0x1000 /* shift it to sys/arcs/spb.h */
#define OFF_HWGRAPH 0
#endif
#define MAX_MODULE_ID 255
#define SIZE_PAD 4096 /* 4k padding for structures */
/*
@@ -134,15 +123,9 @@ typedef s32 klconf_off_t;
typedef struct console_s {
#if defined(CONFIG_SGI_IO) /* FIXME */
__psunsigned_t uart_base;
__psunsigned_t config_base;
__psunsigned_t memory_base;
#else
unsigned long uart_base;
unsigned long config_base;
unsigned long memory_base;
#endif
short baud;
short flag;
int type;
@@ -174,10 +157,6 @@ typedef struct kl_config_hdr {
#define KL_CONFIG_HDR(_nasid) ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
#if 0
#define KL_CONFIG_MALLOC_HDR(_nasid) \
(KL_CONFIG_HDR(_nasid)->ch_malloc_hdr)
#endif
#define KL_CONFIG_INFO_OFFSET(_nasid) \
(KL_CONFIG_HDR(_nasid)->ch_board_info)
#define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off) \
@@ -197,23 +176,13 @@ typedef struct kl_config_hdr {
/* --- New Macros for the changed kl_config_hdr_t structure --- */
#if defined(CONFIG_SGI_IO)
#define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\
((__psunsigned_t)_k + (_k->ch_malloc_hdr_off)))
#else
#define PTR_CH_MALLOC_HDR(_k) ((klc_malloc_hdr_t *)\
(unsigned long)_k + (_k->ch_malloc_hdr_off)))
#endif
#define KL_CONFIG_CH_MALLOC_HDR(_n) PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
#if defined(CONFIG_SGI_IO)
#define PTR_CH_CONS_INFO(_k) ((console_t *)\
((__psunsigned_t)_k + (_k->ch_cons_off)))
#else
#define PTR_CH_CONS_INFO(_k) ((console_t *)\
((unsigned long)_k + (_k->ch_cons_off)))
#endif
#define KL_CONFIG_CH_CONS_INFO(_n) PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n))
@@ -490,14 +459,6 @@ typedef struct lboard_s {
#define KLCF_NUM_COMPS(_brd) ((_brd)->brd_numcompts)
#define KLCF_MODULE_ID(_brd) ((_brd)->brd_module)
#ifdef FRUTEST
#define KLCF_NEXT(_brd) ((_brd)->brd_next ? (lboard_t *)((_brd)->brd_next): NULL)
#define KLCF_COMP(_brd, _ndx) (klinfo_t *)((_brd)->brd_compts[(_ndx)])
#define KLCF_COMP_ERROR(_brd, _comp) (_brd = _brd , (_comp)->errinfo)
#else
#define KLCF_NEXT(_brd) \
((_brd)->brd_next ? \
(lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\
@@ -509,8 +470,6 @@ typedef struct lboard_s {
#define KLCF_COMP_ERROR(_brd, _comp) \
(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))
#endif
#define KLCF_COMP_TYPE(_comp) ((_comp)->struct_type)
#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid) /* Widget ID */
@@ -631,18 +590,6 @@ typedef struct klport_s {
klconf_off_t port_offset;
} klport_t;
#if 0
/*
* This is very similar to the klport_s but instead of having a componant
* offset it has a board offset.
*/
typedef struct klxbow_port_s {
nasid_t port_nasid;
unsigned char port_flag;
klconf_off_t board_offset;
} klxbow_port_t;
#endif
typedef struct klcpu_s { /* CPU */
klinfo_t cpu_info;
unsigned short cpu_prid; /* Processor PRID value */
@@ -945,36 +892,6 @@ extern klcpu_t *nasid_slice_to_cpuinfo(nasid_t, int);
extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class);
#if defined(CONFIG_SGI_IO)
extern xwidgetnum_t nodevertex_widgetnum_get(vertex_hdl_t node_vtx);
extern vertex_hdl_t nodevertex_xbow_peer_get(vertex_hdl_t node_vtx);
extern lboard_t *find_gfxpipe(int pipenum);
extern void setup_gfxpipe_link(vertex_hdl_t vhdl,int pipenum);
extern lboard_t *find_lboard_module_class(lboard_t *start, moduleid_t mod,
unsigned char brd_class);
extern lboard_t *find_nic_lboard(lboard_t *, nic_t);
extern lboard_t *find_nic_type_lboard(nasid_t, unsigned char, nic_t);
extern lboard_t *find_lboard_modslot(lboard_t *start, moduleid_t mod, slotid_t slot);
extern lboard_t *find_lboard_module(lboard_t *start, moduleid_t mod);
extern lboard_t *get_board_name(nasid_t nasid, moduleid_t mod, slotid_t slot, char *name);
extern int config_find_nic_router(nasid_t, nic_t, lboard_t **, klrou_t**);
extern int config_find_nic_hub(nasid_t, nic_t, lboard_t **, klhub_t**);
extern int config_find_xbow(nasid_t, lboard_t **, klxbow_t**);
extern klcpu_t *get_cpuinfo(cpuid_t cpu);
extern int update_klcfg_cpuinfo(nasid_t, int);
extern void board_to_path(lboard_t *brd, char *path);
extern moduleid_t get_module_id(nasid_t nasid);
extern void nic_name_convert(char *old_name, char *new_name);
extern int module_brds(nasid_t nasid, lboard_t **module_brds, int n);
extern lboard_t *brd_from_key(ulong_t key);
extern void device_component_canonical_name_get(lboard_t *,klinfo_t *,
char *);
extern int board_serial_number_get(lboard_t *,char *);
extern int is_master_baseio(nasid_t,moduleid_t,slotid_t);
extern nasid_t get_actual_nasid(lboard_t *brd) ;
extern net_vec_t klcfg_discover_route(lboard_t *, lboard_t *, int);
#else /* CONFIG_SGI_IO */
extern klcpu_t *sn_get_cpuinfo(cpuid_t cpu);
#endif /* CONFIG_SGI_IO */
#endif /* _ASM_SN_KLCONFIG_H */
include/asm-mips/sn/kldir.h
+2 -32
View File
@@ -13,10 +13,6 @@
#include <linux/config.h>
#if defined(CONFIG_SGI_IO)
#include <asm/hack.h>
#endif
/*
* The kldir memory area resides at a fixed place in each node's memory and
* provides pointers to most other IP27 memory areas. This allows us to
@@ -136,8 +132,6 @@
#define KLDIR_OFF_STRIDE 0x28
#endif /* __ASSEMBLY__ */
#if !defined(CONFIG_SGI_IO)
/*
* This is defined here because IP27_SYMMON_STK_SIZE must be at least what
* we define here. Since it's set up in the prom. We can't redefine it later
@@ -147,7 +141,7 @@
*/
#define SYMMON_STACK_SIZE 0x8000
#if defined (PROM) || defined (SABLE)
#if defined (PROM)
/*
* These defines are prom version dependent. No code other than the IP27
@@ -184,7 +178,7 @@
#define IP27_FREEMEM_COUNT 1
#define IP27_FREEMEM_STRIDE 0
#endif /* PROM || SABLE*/
#endif /* PROM */
/*
* There will be only one of these in a partition so the IO6 must set it up.
*/
@@ -207,17 +201,11 @@
#define KLDIR_ENT_SIZE 0x40
#define KLDIR_MAX_ENTRIES (0x400 / 0x40)
#endif /* !CONFIG_SGI_IO */
#ifndef __ASSEMBLY__
typedef struct kldir_ent_s {
u64 magic; /* Indicates validity of entry */
off_t offset; /* Offset from start of node space */
#if defined(CONFIG_SGI_IO) /* FIXME */
__psunsigned_t pointer; /* Pointer to area in some cases */
#else
unsigned long pointer; /* Pointer to area in some cases */
#endif
size_t size; /* Size in bytes */
u64 count; /* Repeat count if array, 1 if not */
size_t stride; /* Stride if array, 0 if not */
@@ -227,22 +215,4 @@ typedef struct kldir_ent_s {
} kldir_ent_t;
#endif /* !__ASSEMBLY__ */
#if defined(CONFIG_SGI_IO)
#define KLDIR_ENT_SIZE 0x40
#define KLDIR_MAX_ENTRIES (0x400 / 0x40)
/*
* The actual offsets of each memory area are machine-dependent
*/
#ifdef CONFIG_SGI_IP27
// Not yet #include <asm/sn/sn0/kldir.h>
#elif defined(CONFIG_SGI_IP35)
#include <asm/sn/sn1/kldir.h>
#else
#error "kldir.h is currently defined for IP27 and IP35 platforms only"
#endif
#endif /* CONFIG_SGI_IO */
#endif /* _ASM_SN_KLDIR_H */
include/asm-mips/sn/sn0/addrs.h
+6 -81
View File
@@ -49,7 +49,7 @@
* so for now we just use defines bracketed by an ifdef.
*/
#ifdef CONFIG_SGI_SN0_N_MODE
#ifdef CONFIG_SGI_SN_N_MODE
#define NODE_SIZE_BITS 31
#define BWIN_SIZE_BITS 28
@@ -63,7 +63,7 @@
#define BDDIR_UPPER_MASK (UINT64_CAST 0x7ffff << 10)
#define BDECC_UPPER_MASK (UINT64_CAST 0x3ffffff << 3)
#else /* !defined(CONFIG_SGI_SN0_N_MODE), assume that M-mode is desired */
#else /* !defined(CONFIG_SGI_SN_N_MODE), assume that M-mode is desired */
#define NODE_SIZE_BITS 32
#define BWIN_SIZE_BITS 29
@@ -77,7 +77,7 @@
#define BDDIR_UPPER_MASK (UINT64_CAST 0xfffff << 10)
#define BDECC_UPPER_MASK (UINT64_CAST 0x7ffffff << 3)
#endif /* !defined(CONFIG_SGI_SN0_N_MODE) */
#endif /* !defined(CONFIG_SGI_SN_N_MODE) */
#define NODE_ADDRSPACE_SIZE (UINT64_CAST 1 << NODE_SIZE_BITS)
@@ -85,15 +85,15 @@
#define NASID_GET(_pa) (int) ((UINT64_CAST (_pa) >> \
NASID_SHFT) & NASID_BITMASK)
#if !defined(__ASSEMBLY__) && !defined(_STANDALONE)
#if !defined(__ASSEMBLY__)
#define NODE_SWIN_BASE(nasid, widget) \
((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN) \
: RAW_NODE_SWIN_BASE(nasid, widget))
#else /* __ASSEMBLY__ || _STANDALONE */
#else /* __ASSEMBLY__ */
#define NODE_SWIN_BASE(nasid, widget) \
(NODE_IO_BASE(nasid) + (UINT64_CAST (widget) << SWIN_SIZE_BITS))
#endif /* __ASSEMBLY__ || _STANDALONE */
#endif /* __ASSEMBLY__ */
/*
* The following definitions pertain to the IO special address
@@ -143,12 +143,7 @@
#define SN0_WIDGET_BASE(_nasid, _wid) (NODE_SWIN_BASE((_nasid), (_wid)))
/* Turn on sable logging for the processors whose bits are set. */
#ifdef SABLE
#define SABLE_LOG_TRIGGER(_map) \
*((volatile hubreg_t *)(IO_BASE + 0x17ffff0)) = (_map)
#else
#define SABLE_LOG_TRIGGER(_map)
#endif /* SABLE */
#ifndef __ASSEMBLY__
#define KERN_NMI_ADDR(nasid, slice) \
@@ -281,76 +276,6 @@
#define _ARCSPROM
#ifdef _STANDALONE
/*
* The PROM needs to pass the device base address and the
* device pci cfg space address to the device drivers during
* install. The COMPONENT->Key field is used for this purpose.
* Macros needed by SN0 device drivers to convert the
* COMPONENT->Key field to the respective base address.
* Key field looks as follows:
*
* +----------------------------------------------------+
* |devnasid | widget |pciid |hubwidid|hstnasid | adap |
* | 2 | 1 | 1 | 1 | 2 | 1 |
* +----------------------------------------------------+
* | | | | | | |
* 64 48 40 32 24 8 0
*
* These are used by standalone drivers till the io infrastructure
* is in place.
*/
#ifndef __ASSEMBLY__
#define uchar unsigned char
#define KEY_DEVNASID_SHFT 48
#define KEY_WIDID_SHFT 40
#define KEY_PCIID_SHFT 32
#define KEY_HUBWID_SHFT 24
#define KEY_HSTNASID_SHFT 8
#define MK_SN0_KEY(nasid, widid, pciid) \
((((__psunsigned_t)nasid)<< KEY_DEVNASID_SHFT |\
((__psunsigned_t)widid) << KEY_WIDID_SHFT) |\
((__psunsigned_t)pciid) << KEY_PCIID_SHFT)
#define ADD_HUBWID_KEY(key,hubwid)\
(key|=((__psunsigned_t)hubwid << KEY_HUBWID_SHFT))
#define ADD_HSTNASID_KEY(key,hstnasid)\
(key|=((__psunsigned_t)hstnasid << KEY_HSTNASID_SHFT))
#define GET_DEVNASID_FROM_KEY(key) ((short)(key >> KEY_DEVNASID_SHFT))
#define GET_WIDID_FROM_KEY(key) ((uchar)(key >> KEY_WIDID_SHFT))
#define GET_PCIID_FROM_KEY(key) ((uchar)(key >> KEY_PCIID_SHFT))
#define GET_HUBWID_FROM_KEY(key) ((uchar)(key >> KEY_HUBWID_SHFT))
#define GET_HSTNASID_FROM_KEY(key) ((short)(key >> KEY_HSTNASID_SHFT))
#define PCI_64_TARGID_SHFT 60
#define GET_PCIBASE_FROM_KEY(key) (NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
GET_WIDID_FROM_KEY(key))\
| BRIDGE_DEVIO(GET_PCIID_FROM_KEY(key)))
#define GET_PCICFGBASE_FROM_KEY(key) \
(NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
GET_WIDID_FROM_KEY(key))\
| BRIDGE_TYPE0_CFG_DEV(GET_PCIID_FROM_KEY(key)))
#define GET_WIDBASE_FROM_KEY(key) \
(NODE_SWIN_BASE(GET_DEVNASID_FROM_KEY(key),\
GET_WIDID_FROM_KEY(key)))
#define PUT_INSTALL_STATUS(c,s) c->Revision = s
#define GET_INSTALL_STATUS(c) c->Revision
#endif /* !__ASSEMBLY__ */
#endif /* _STANDALONE */
#if defined (HUB_ERR_STS_WAR)
#define ERR_STS_WAR_REGISTER IIO_IIBUSERR
include/asm-mips/sn/sn0/arch.h
+3 -14
View File
@@ -13,8 +13,6 @@
#include <linux/config.h>
#ifndef SABLE
#ifndef SN0XXL /* 128 cpu SMP max */
/*
* This is the maximum number of nodes that can be part of a kernel.
@@ -54,25 +52,16 @@
*/
#define MAX_PARTITIONS MAX_REGIONS
#else
#define MAX_COMPACT_NODES 4
#define MAX_NASIDS 4
#define MAXCPUS 8
#endif
#define NASID_MASK_BYTES ((MAX_NASIDS + 7) / 8)
/*
* Slot constants for SN0
*/
#ifdef CONFIG_SGI_SN0_N_MODE
#ifdef CONFIG_SGI_SN_N_MODE
#define MAX_MEM_SLOTS 16 /* max slots per node */
#else /* !CONFIG_SGI_SN0_N_MODE, assume M_MODE */
#else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */
#define MAX_MEM_SLOTS 32 /* max slots per node */
#endif /* defined(N_MODE) */
#endif /* CONFIG_SGI_SN_M_MODE */
#define SLOT_SHIFT (27)
#define SLOT_MIN_MEM_SIZE (32*1024*1024)
include/asm-mips/sn/sn0/hub.h
-4
View File
@@ -31,10 +31,6 @@
#include <asm/sn/sn0/hubni.h>
//#include <asm/sn/sn0/hubcore.h>
#ifdef SABLE
#define IP27_NO_HUBUART_INT 1
#endif
/* Translation of uncached attributes */
#define UATTR_HSPEC 0
#define UATTR_IO 1
include/asm-mips/sn/sn0/hubio.h
-16
View File
@@ -486,22 +486,6 @@ typedef union h1_icrba_u {
#define ICRBN_A_CERR_SHFT 54
#define ICRBN_A_ERR_MASK 0x3ff
#if 0 /* Disabled, this causes namespace polution and break allmodconfig */
/*
* Easy access macros.
*/
#define a_error icrba_fields_s.error
#define a_ecode icrba_fields_s.ecode
#define a_lnetuce icrba_fields_s.lnetuce
#define a_mark icrba_fields_s.mark
#define a_xerr icrba_fields_s.xerr
#define a_sidn icrba_fields_s.sidn
#define a_tnum icrba_fields_s.tnum
#define a_addr icrba_fields_s.addr
#define a_valid icrba_fields_s.valid
#define a_iow icrba_fields_s.iow
#endif
#endif /* !__ASSEMBLY__ */
#define IIO_ICRB_ADDR_SHFT 2 /* Shift to get proper address */
include/asm-mips/sn/sn0/hubmd.h
+1 -1
View File
@@ -92,7 +92,7 @@
#define MD_UREG1_14 0x2200f0 /* uController/UART 1 register */
#define MD_UREG1_15 0x2200f8 /* uController/UART 1 register */
#ifdef CONFIG_SGI_SN0_N_MODE
#ifdef CONFIG_SGI_SN_N_MODE
#define MD_MEM_BANKS 4 /* 4 banks of memory max in N mode */
#else
#define MD_MEM_BANKS 8 /* 8 banks of memory max in M mode */
include/asm-mips/sn/sn0/hubpi.h
-18
View File
@@ -398,24 +398,6 @@ typedef u64 rtc_time_t;
/* PI_RT_FILTER_CTRL mask and shift definitions */
#if 0
/*
* XXX - This register's definition has changed, but it's only implemented
* in Hub 2.
*/
#define PRFC_DROP_COUNT_SHFT 27
#define PRFC_DROP_COUNT_MASK (UINT64_CAST 0x3ff << 27)
#define PRFC_DROP_CTR_SHFT 18
#define PRFC_DROP_CTR_MASK (UINT64_CAST 0x1ff << 18)
#define PRFC_MASK_ENABLE_SHFT 10
#define PRFC_MASK_ENABLE_MASK (UINT64_CAST 0x7f << 10)
#define PRFC_MASK_CTR_SHFT 2
#define PRFC_MASK_CTR_MASK (UINT64_CAST 0xff << 2)
#define PRFC_OFFSET_SHFT 0
#define PRFC_OFFSET_MASK (UINT64_CAST 3)
#endif /* 0 */
/*
* Bits for NACK_CNT_A/B and NACK_CMP
*/
include/asm-mips/sn/sn0/ip27.h
+1 -8
View File
@@ -6,7 +6,7 @@
* Derived from IRIX <sys/SN/SN0/IP27.h>.
*
* Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
* Copyright (C) 1999 by Ralf Baechle
* Copyright (C) 1999, 2006 by Ralf Baechle
*/
#ifndef _ASM_SN_SN0_IP27_H
#define _ASM_SN_SN0_IP27_H
@@ -82,11 +82,4 @@
#define SEND_NMI(_nasid, _slice) \
REMOTE_HUB_S((_nasid), (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
/* Sanity hazzard ... Below all the Origin hacks are following. */
#define SN00_BRIDGE 0x9200000008000000
#define SN00I_BRIDGE0 0x920000000b000000
#define SN00I_BRIDGE1 0x920000000e000000
#define SN00I_BRIDGE2 0x920000000f000000
#endif /* _ASM_SN_SN0_IP27_H */
include/asm-mips/sni.h
+2 -5
View File
@@ -15,9 +15,6 @@
/*
* ASIC PCI registers for little endian configuration.
*/
#ifndef __MIPSEL__
#error "Fix me for big endian"
#endif
#define PCIMT_UCONF 0xbfff0000
#define PCIMT_IOADTIMEOUT2 0xbfff0008
#define PCIMT_IOMEMCONF 0xbfff0010
@@ -51,9 +48,9 @@
#define PCIMT_PCI_CONF 0xbfff0100
/*
* Data port for the PCI bus.
* Data port for the PCI bus in IO space
*/
#define PCIMT_CONFIG_DATA 0xb4000cfc
#define PCIMT_CONFIG_DATA 0x0cfc
/*
* Board specific registers
include/asm-mips/war.h
+3 -2
View File
@@ -172,7 +172,8 @@
* On the RM9000 there is a problem which makes the CreateDirtyExclusive
* cache operation unusable on SMP systems.
*/
#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE)
#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_PMC_YOSEMITE) || \
defined(CONFIG_BASLER_EXCITE)
#define RM9000_CDEX_SMP_WAR 1
#endif
@@ -182,7 +183,7 @@
* being fetched may case spurious exceptions.
*/
#if defined(CONFIG_MOMENCO_JAGUAR_ATX) || defined(CONFIG_MOMENCO_OCELOT_3) || \
defined(CONFIG_PMC_YOSEMITE)
defined(CONFIG_PMC_YOSEMITE) || defined(CONFIG_BASLER_EXCITE)
#define ICACHE_REFILLS_WORKAROUND_WAR 1
#endif
include/asm-powerpc/cputable.h
+1 -1
View File
@@ -329,7 +329,7 @@ extern void do_cpu_ftr_fixups(unsigned long offset);
#define CPU_FTRS_CELL (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO)
CPU_FTR_CTRL | CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE)
#define CPU_FTRS_COMPATIBLE (CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB | \
CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
#endif
include/linux/console.h
+4
View File
@@ -117,6 +117,10 @@ extern void console_stop(struct console *);
extern void console_start(struct console *);
extern int is_console_locked(void);
/* Suspend and resume console messages over PM events */
extern void suspend_console(void);
extern void resume_console(void);
/* Some debug stub to catch some of the obvious races in the VT code */
#if 1
#define WARN_CONSOLE_UNLOCKED() WARN_ON(!is_console_locked() && !oops_in_progress)
include/linux/dmaengine.h
+359
View File
@@ -0,0 +1,359 @@
/*
* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* The full GNU General Public License is included in this distribution in the
* file called COPYING.
*/
#ifndef DMAENGINE_H
#define DMAENGINE_H
#include <linux/config.h>
#ifdef CONFIG_DMA_ENGINE
#include <linux/device.h>
#include <linux/uio.h>
#include <linux/kref.h>
#include <linux/completion.h>
#include <linux/rcupdate.h>
/**
* enum dma_event - resource PNP/power managment events
* @DMA_RESOURCE_SUSPEND: DMA device going into low power state
* @DMA_RESOURCE_RESUME: DMA device returning to full power
* @DMA_RESOURCE_ADDED: DMA device added to the system
* @DMA_RESOURCE_REMOVED: DMA device removed from the system
*/
enum dma_event {
DMA_RESOURCE_SUSPEND,
DMA_RESOURCE_RESUME,
DMA_RESOURCE_ADDED,
DMA_RESOURCE_REMOVED,
};
/**
* typedef dma_cookie_t
*
* if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
*/
typedef s32 dma_cookie_t;
#define dma_submit_error(cookie) ((cookie) < 0 ? 1 : 0)
/**
* enum dma_status - DMA transaction status
* @DMA_SUCCESS: transaction completed successfully
* @DMA_IN_PROGRESS: transaction not yet processed
* @DMA_ERROR: transaction failed
*/
enum dma_status {
DMA_SUCCESS,
DMA_IN_PROGRESS,
DMA_ERROR,
};
/**
* struct dma_chan_percpu - the per-CPU part of struct dma_chan
* @refcount: local_t used for open-coded "bigref" counting
* @memcpy_count: transaction counter
* @bytes_transferred: byte counter
*/
struct dma_chan_percpu {
local_t refcount;
/* stats */
unsigned long memcpy_count;
unsigned long bytes_transferred;
};
/**
* struct dma_chan - devices supply DMA channels, clients use them
* @client: ptr to the client user of this chan, will be NULL when unused
* @device: ptr to the dma device who supplies this channel, always !NULL
* @cookie: last cookie value returned to client
* @chan_id:
* @class_dev:
* @refcount: kref, used in "bigref" slow-mode
* @slow_ref:
* @rcu:
* @client_node: used to add this to the client chan list
* @device_node: used to add this to the device chan list
* @local: per-cpu pointer to a struct dma_chan_percpu
*/
struct dma_chan {
struct dma_client *client;
struct dma_device *device;
dma_cookie_t cookie;
/* sysfs */
int chan_id;
struct class_device class_dev;
struct kref refcount;
int slow_ref;
struct rcu_head rcu;
struct list_head client_node;
struct list_head device_node;
struct dma_chan_percpu *local;
};
void dma_chan_cleanup(struct kref *kref);
static inline void dma_chan_get(struct dma_chan *chan)
{
if (unlikely(chan->slow_ref))
kref_get(&chan->refcount);
else {
local_inc(&(per_cpu_ptr(chan->local, get_cpu())->refcount));
put_cpu();
}
}
static inline void dma_chan_put(struct dma_chan *chan)
{
if (unlikely(chan->slow_ref))
kref_put(&chan->refcount, dma_chan_cleanup);
else {
local_dec(&(per_cpu_ptr(chan->local, get_cpu())->refcount));
put_cpu();
}
}
/*
* typedef dma_event_callback - function pointer to a DMA event callback
*/
typedef void (*dma_event_callback) (struct dma_client *client,
struct dma_chan *chan, enum dma_event event);
/**
* struct dma_client - info on the entity making use of DMA services
* @event_callback: func ptr to call when something happens
* @chan_count: number of chans allocated
* @chans_desired: number of chans requested. Can be +/- chan_count
* @lock: protects access to the channels list
* @channels: the list of DMA channels allocated
* @global_node: list_head for global dma_client_list
*/
struct dma_client {
dma_event_callback event_callback;
unsigned int chan_count;
unsigned int chans_desired;
spinlock_t lock;
struct list_head channels;
struct list_head global_node;
};
/**
* struct dma_device - info on the entity supplying DMA services
* @chancnt: how many DMA channels are supported
* @channels: the list of struct dma_chan
* @global_node: list_head for global dma_device_list
* @refcount:
* @done:
* @dev_id:
* Other func ptrs: used to make use of this device's capabilities
*/
struct dma_device {
unsigned int chancnt;
struct list_head channels;
struct list_head global_node;
struct kref refcount;
struct completion done;
int dev_id;
int (*device_alloc_chan_resources)(struct dma_chan *chan);
void (*device_free_chan_resources)(struct dma_chan *chan);
dma_cookie_t (*device_memcpy_buf_to_buf)(struct dma_chan *chan,
void *dest, void *src, size_t len);
dma_cookie_t (*device_memcpy_buf_to_pg)(struct dma_chan *chan,
struct page *page, unsigned int offset, void *kdata,
size_t len);
dma_cookie_t (*device_memcpy_pg_to_pg)(struct dma_chan *chan,
struct page *dest_pg, unsigned int dest_off,
struct page *src_pg, unsigned int src_off, size_t len);
enum dma_status (*device_memcpy_complete)(struct dma_chan *chan,
dma_cookie_t cookie, dma_cookie_t *last,
dma_cookie_t *used);
void (*device_memcpy_issue_pending)(struct dma_chan *chan);
};
/* --- public DMA engine API --- */
struct dma_client *dma_async_client_register(dma_event_callback event_callback);
void dma_async_client_unregister(struct dma_client *client);
void dma_async_client_chan_request(struct dma_client *client,
unsigned int number);
/**
* dma_async_memcpy_buf_to_buf - offloaded copy between virtual addresses
* @chan: DMA channel to offload copy to
* @dest: destination address (virtual)
* @src: source address (virtual)
* @len: length
*
* Both @dest and @src must be mappable to a bus address according to the
* DMA mapping API rules for streaming mappings.
* Both @dest and @src must stay memory resident (kernel memory or locked
* user space pages)
*/
static inline dma_cookie_t dma_async_memcpy_buf_to_buf(struct dma_chan *chan,
void *dest, void *src, size_t len)
{
int cpu = get_cpu();
per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
per_cpu_ptr(chan->local, cpu)->memcpy_count++;
put_cpu();
return chan->device->device_memcpy_buf_to_buf(chan, dest, src, len);
}
/**
* dma_async_memcpy_buf_to_pg - offloaded copy
* @chan: DMA channel to offload copy to
* @page: destination page
* @offset: offset in page to copy to
* @kdata: source address (virtual)
* @len: length
*
* Both @page/@offset and @kdata must be mappable to a bus address according
* to the DMA mapping API rules for streaming mappings.
* Both @page/@offset and @kdata must stay memory resident (kernel memory or
* locked user space pages)
*/
static inline dma_cookie_t dma_async_memcpy_buf_to_pg(struct dma_chan *chan,
struct page *page, unsigned int offset, void *kdata, size_t len)
{
int cpu = get_cpu();
per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
per_cpu_ptr(chan->local, cpu)->memcpy_count++;
put_cpu();
return chan->device->device_memcpy_buf_to_pg(chan, page, offset,
kdata, len);
}
/**
* dma_async_memcpy_buf_to_pg - offloaded copy
* @chan: DMA channel to offload copy to
* @dest_page: destination page
* @dest_off: offset in page to copy to
* @src_page: source page
* @src_off: offset in page to copy from
* @len: length
*
* Both @dest_page/@dest_off and @src_page/@src_off must be mappable to a bus
* address according to the DMA mapping API rules for streaming mappings.
* Both @dest_page/@dest_off and @src_page/@src_off must stay memory resident
* (kernel memory or locked user space pages)
*/
static inline dma_cookie_t dma_async_memcpy_pg_to_pg(struct dma_chan *chan,
struct page *dest_pg, unsigned int dest_off, struct page *src_pg,
unsigned int src_off, size_t len)
{
int cpu = get_cpu();
per_cpu_ptr(chan->local, cpu)->bytes_transferred += len;
per_cpu_ptr(chan->local, cpu)->memcpy_count++;
put_cpu();
return chan->device->device_memcpy_pg_to_pg(chan, dest_pg, dest_off,
src_pg, src_off, len);
}
/**
* dma_async_memcpy_issue_pending - flush pending copies to HW
* @chan:
*
* This allows drivers to push copies to HW in batches,
* reducing MMIO writes where possible.
*/
static inline void dma_async_memcpy_issue_pending(struct dma_chan *chan)
{
return chan->device->device_memcpy_issue_pending(chan);
}
/**
* dma_async_memcpy_complete - poll for transaction completion
* @chan: DMA channel
* @cookie: transaction identifier to check status of
* @last: returns last completed cookie, can be NULL
* @used: returns last issued cookie, can be NULL
*
* If @last and @used are passed in, upon return they reflect the driver
* internal state and can be used with dma_async_is_complete() to check
* the status of multiple cookies without re-checking hardware state.
*/
static inline enum dma_status dma_async_memcpy_complete(struct dma_chan *chan,
dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
{
return chan->device->device_memcpy_complete(chan, cookie, last, used);
}
/**
* dma_async_is_complete - test a cookie against chan state
* @cookie: transaction identifier to test status of
* @last_complete: last know completed transaction
* @last_used: last cookie value handed out
*
* dma_async_is_complete() is used in dma_async_memcpy_complete()
* the test logic is seperated for lightweight testing of multiple cookies
*/
static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
dma_cookie_t last_complete, dma_cookie_t last_used)
{
if (last_complete <= last_used) {
if ((cookie <= last_complete) || (cookie > last_used))
return DMA_SUCCESS;
} else {
if ((cookie <= last_complete) && (cookie > last_used))
return DMA_SUCCESS;
}
return DMA_IN_PROGRESS;
}
/* --- DMA device --- */
int dma_async_device_register(struct dma_device *device);
void dma_async_device_unregister(struct dma_device *device);
/* --- Helper iov-locking functions --- */
struct dma_page_list {
char *base_address;
int nr_pages;
struct page **pages;
};
struct dma_pinned_list {
int nr_iovecs;
struct dma_page_list page_list[0];
};
struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
struct dma_pinned_list *pinned_list, struct page *page,
unsigned int offset, size_t len);
#endif /* CONFIG_DMA_ENGINE */
#endif /* DMAENGINE_H */
include/linux/i2o.h
+4 -1
View File
@@ -1114,8 +1114,11 @@ static inline struct i2o_message *i2o_msg_get(struct i2o_controller *c)
mmsg->mfa = readl(c->in_port);
if (unlikely(mmsg->mfa >= c->in_queue.len)) {
u32 mfa = mmsg->mfa;
mempool_free(mmsg, c->in_msg.mempool);
if(mmsg->mfa == I2O_QUEUE_EMPTY)
if (mfa == I2O_QUEUE_EMPTY)
return ERR_PTR(-EBUSY);
return ERR_PTR(-EFAULT);
}
include/linux/igmp.h
+1 -1
View File
@@ -169,7 +169,7 @@ struct ip_sf_list
struct ip_mc_list
{
struct in_device *interface;
unsigned long multiaddr;
__be32 multiaddr;
struct ip_sf_list *sources;
struct ip_sf_list *tomb;
unsigned int sfmode;
include/linux/netdevice.h
+42 -3
View File
@@ -37,6 +37,7 @@
#include <linux/config.h>
#include <linux/device.h>
#include <linux/percpu.h>
#include <linux/dmaengine.h>
struct divert_blk;
struct vlan_group;
@@ -311,6 +312,9 @@ struct net_device
#define NETIF_F_LLTX 4096 /* LockLess TX */
#define NETIF_F_UFO 8192 /* Can offload UDP Large Send*/
#define NETIF_F_GEN_CSUM (NETIF_F_NO_CSUM | NETIF_F_HW_CSUM)
#define NETIF_F_ALL_CSUM (NETIF_F_IP_CSUM | NETIF_F_GEN_CSUM)
struct net_device *next_sched;
/* Interface index. Unique device identifier */
@@ -406,7 +410,7 @@ struct net_device
* One part is mostly used on xmit path (device)
*/
/* hard_start_xmit synchronizer */
spinlock_t xmit_lock ____cacheline_aligned_in_smp;
spinlock_t _xmit_lock ____cacheline_aligned_in_smp;
/* cpu id of processor entered to hard_start_xmit or -1,
if nobody entered there.
*/
@@ -593,6 +597,9 @@ struct softnet_data
struct sk_buff *completion_queue;
struct net_device backlog_dev; /* Sorry. 8) */
#ifdef CONFIG_NET_DMA
struct dma_chan *net_dma;
#endif
};
DECLARE_PER_CPU(struct softnet_data,softnet_data);
@@ -889,11 +896,43 @@ static inline void __netif_rx_complete(struct net_device *dev)
clear_bit(__LINK_STATE_RX_SCHED, &dev->state);
}
static inline void netif_tx_lock(struct net_device *dev)
{
spin_lock(&dev->_xmit_lock);
dev->xmit_lock_owner = smp_processor_id();
}
static inline void netif_tx_lock_bh(struct net_device *dev)
{
spin_lock_bh(&dev->_xmit_lock);
dev->xmit_lock_owner = smp_processor_id();
}
static inline int netif_tx_trylock(struct net_device *dev)
{
int err = spin_trylock(&dev->_xmit_lock);
if (!err)
dev->xmit_lock_owner = smp_processor_id();
return err;
}
static inline void netif_tx_unlock(struct net_device *dev)
{
dev->xmit_lock_owner = -1;
spin_unlock(&dev->_xmit_lock);
}
static inline void netif_tx_unlock_bh(struct net_device *dev)
{
dev->xmit_lock_owner = -1;
spin_unlock_bh(&dev->_xmit_lock);
}
static inline void netif_tx_disable(struct net_device *dev)
{
spin_lock_bh(&dev->xmit_lock);
netif_tx_lock_bh(dev);
netif_stop_queue(dev);
spin_unlock_bh(&dev->xmit_lock);
netif_tx_unlock_bh(dev);
}
/* These functions live elsewhere (drivers/net/net_init.c, but related) */
include/linux/netfilter/nf_conntrack_common.h
+4
View File
@@ -69,6 +69,10 @@ enum ip_conntrack_status {
/* Connection is dying (removed from lists), can not be unset. */
IPS_DYING_BIT = 9,
IPS_DYING = (1 << IPS_DYING_BIT),
/* Connection has fixed timeout. */
IPS_FIXED_TIMEOUT_BIT = 10,
IPS_FIXED_TIMEOUT = (1 << IPS_FIXED_TIMEOUT_BIT),
};
/* Connection tracking event bits */
include/linux/netfilter/nfnetlink_conntrack.h
+3 -1
View File
@@ -27,13 +27,15 @@ enum ctattr_type {
CTA_STATUS,
CTA_PROTOINFO,
CTA_HELP,
CTA_NAT,
CTA_NAT_SRC,
#define CTA_NAT CTA_NAT_SRC /* backwards compatibility */
CTA_TIMEOUT,
CTA_MARK,
CTA_COUNTERS_ORIG,
CTA_COUNTERS_REPLY,
CTA_USE,
CTA_ID,
CTA_NAT_DST,
__CTA_MAX
};
#define CTA_MAX (__CTA_MAX - 1)
include/linux/netfilter/xt_CONNSECMARK.h
+13
View File
@@ -0,0 +1,13 @@
#ifndef _XT_CONNSECMARK_H_target
#define _XT_CONNSECMARK_H_target
enum {
CONNSECMARK_SAVE = 1,
CONNSECMARK_RESTORE,
};
struct xt_connsecmark_target_info {
u_int8_t mode;
};
#endif /*_XT_CONNSECMARK_H_target */
include/linux/netfilter/xt_SECMARK.h
+26
View File
@@ -0,0 +1,26 @@
#ifndef _XT_SECMARK_H_target
#define _XT_SECMARK_H_target
/*
* This is intended for use by various security subsystems (but not
* at the same time).
*
* 'mode' refers to the specific security subsystem which the
* packets are being marked for.
*/
#define SECMARK_MODE_SEL 0x01 /* SELinux */
#define SECMARK_SELCTX_MAX 256
struct xt_secmark_target_selinux_info {
u_int32_t selsid;
char selctx[SECMARK_SELCTX_MAX];
};
struct xt_secmark_target_info {
u_int8_t mode;
union {
struct xt_secmark_target_selinux_info sel;
} u;
};
#endif /*_XT_SECMARK_H_target */
include/linux/netfilter/xt_quota.h
+16
View File
@@ -0,0 +1,16 @@
#ifndef _XT_QUOTA_H
#define _XT_QUOTA_H
enum xt_quota_flags {
XT_QUOTA_INVERT = 0x1,
};
#define XT_QUOTA_MASK 0x1
struct xt_quota_info {
u_int32_t flags;
u_int32_t pad;
aligned_u64 quota;
struct xt_quota_info *master;
};
#endif /* _XT_QUOTA_H */
include/linux/netfilter/xt_statistic.h
+32
View File
@@ -0,0 +1,32 @@
#ifndef _XT_STATISTIC_H
#define _XT_STATISTIC_H
enum xt_statistic_mode {
XT_STATISTIC_MODE_RANDOM,
XT_STATISTIC_MODE_NTH,
__XT_STATISTIC_MODE_MAX
};
#define XT_STATISTIC_MODE_MAX (__XT_STATISTIC_MODE_MAX - 1)
enum xt_statistic_flags {
XT_STATISTIC_INVERT = 0x1,
};
#define XT_STATISTIC_MASK 0x1
struct xt_statistic_info {
u_int16_t mode;
u_int16_t flags;
union {
struct {
u_int32_t probability;
} random;
struct {
u_int32_t every;
u_int32_t packet;
u_int32_t count;
} nth;
} u;
struct xt_statistic_info *master __attribute__((aligned(8)));
};
#endif /* _XT_STATISTIC_H */
include/linux/netfilter_ipv4/ip_conntrack.h
+6
View File
@@ -121,6 +121,10 @@ struct ip_conntrack
u_int32_t mark;
#endif
#ifdef CONFIG_IP_NF_CONNTRACK_SECMARK
u_int32_t secmark;
#endif
/* Traversed often, so hopefully in different cacheline to top */
/* These are my tuples; original and reply */
struct ip_conntrack_tuple_hash tuplehash[IP_CT_DIR_MAX];
@@ -154,6 +158,7 @@ struct ip_conntrack_expect
unsigned int flags;
#ifdef CONFIG_IP_NF_NAT_NEEDED
u_int32_t saved_ip;
/* This is the original per-proto part, used to map the
* expected connection the way the recipient expects. */
union ip_conntrack_manip_proto saved_proto;
@@ -293,6 +298,7 @@ static inline int is_dying(struct ip_conntrack *ct)
}
extern unsigned int ip_conntrack_htable_size;
extern int ip_conntrack_checksum;
#define CONNTRACK_STAT_INC(count) (__get_cpu_var(ip_conntrack_stat).count++)
include/linux/netfilter_ipv4/ip_conntrack_h323.h
+7
View File
@@ -71,6 +71,13 @@ extern int (*nat_h245_hook) (struct sk_buff ** pskb, struct ip_conntrack * ct,
unsigned char **data, int dataoff,
TransportAddress * addr, u_int16_t port,
struct ip_conntrack_expect * exp);
extern int (*nat_callforwarding_hook) (struct sk_buff ** pskb,
struct ip_conntrack * ct,
enum ip_conntrack_info ctinfo,
unsigned char **data, int dataoff,
TransportAddress * addr,
u_int16_t port,
struct ip_conntrack_expect * exp);
extern int (*nat_q931_hook) (struct sk_buff ** pskb, struct ip_conntrack * ct,
enum ip_conntrack_info ctinfo,
unsigned char **data, TransportAddress * addr,
include/linux/netfilter_ipv4/ip_conntrack_helper_h323_types.h
+2 -1
View File
@@ -1,4 +1,4 @@
/* Generated by Jing Min Zhao's ASN.1 parser, Mar 15 2006
/* Generated by Jing Min Zhao's ASN.1 parser, Apr 20 2006
*
* Copyright (c) 2006 Jing Min Zhao <zhaojingmin@users.sourceforge.net>
*
@@ -412,6 +412,7 @@ typedef struct Facility_UUIE { /* SEQUENCE */
eFacility_UUIE_destinationInfo = (1 << 14),
eFacility_UUIE_h245SecurityMode = (1 << 13),
} options;
TransportAddress alternativeAddress;
FacilityReason reason;
TransportAddress h245Address;
Facility_UUIE_fastStart fastStart;
include/linux/netfilter_ipv4/ip_conntrack_sip.h
+44
View File
@@ -0,0 +1,44 @@
#ifndef __IP_CONNTRACK_SIP_H__
#define __IP_CONNTRACK_SIP_H__
#ifdef __KERNEL__
#define SIP_PORT 5060
#define SIP_TIMEOUT 3600
#define POS_VIA 0
#define POS_CONTACT 1
#define POS_CONTENT 2
#define POS_MEDIA 3
#define POS_OWNER 4
#define POS_CONNECTION 5
#define POS_REQ_HEADER 6
#define POS_SDP_HEADER 7
struct sip_header_nfo {
const char *lname;
const char *sname;
const char *ln_str;
size_t lnlen;
size_t snlen;
size_t ln_strlen;
int (*match_len)(const char *, const char *, int *);
};
extern unsigned int (*ip_nat_sip_hook)(struct sk_buff **pskb,
enum ip_conntrack_info ctinfo,
struct ip_conntrack *ct,
const char **dptr);
extern unsigned int (*ip_nat_sdp_hook)(struct sk_buff **pskb,
enum ip_conntrack_info ctinfo,
struct ip_conntrack_expect *exp,
const char *dptr);
extern int ct_sip_get_info(const char *dptr, size_t dlen,
unsigned int *matchoff,
unsigned int *matchlen,
struct sip_header_nfo *hnfo);
extern int ct_sip_lnlen(const char *line, const char *limit);
extern const char *ct_sip_search(const char *needle, const char *haystack,
size_t needle_len, size_t haystack_len);
#endif /* __KERNEL__ */
#endif /* __IP_CONNTRACK_SIP_H__ */
include/linux/pci-acpi.h
+1 -1
View File
@@ -50,7 +50,7 @@
extern acpi_status pci_osc_control_set(acpi_handle handle, u32 flags);
extern acpi_status pci_osc_support_set(u32 flags);
#else
#if !defined(acpi_status)
#if !defined(AE_ERROR)
typedef u32 acpi_status;
#define AE_ERROR (acpi_status) (0x0001)
#endif
include/linux/pci.h
+2
View File
@@ -442,6 +442,7 @@ struct pci_dev *pci_find_device_reverse (unsigned int vendor, unsigned int devic
struct pci_dev *pci_find_slot (unsigned int bus, unsigned int devfn);
int pci_find_capability (struct pci_dev *dev, int cap);
int pci_find_next_capability (struct pci_dev *dev, u8 pos, int cap);
int pci_find_ext_capability (struct pci_dev *dev, int cap);
struct pci_bus * pci_find_next_bus(const struct pci_bus *from);
struct pci_dev *pci_get_device (unsigned int vendor, unsigned int device, struct pci_dev *from);
@@ -662,6 +663,7 @@ static inline int pci_register_driver(struct pci_driver *drv) { return 0;}
static inline void pci_unregister_driver(struct pci_driver *drv) { }
static inline int pci_find_capability (struct pci_dev *dev, int cap) {return 0; }
static inline int pci_find_next_capability (struct pci_dev *dev, u8 post, int cap) { return 0; }
static inline int pci_find_ext_capability (struct pci_dev *dev, int cap) {return 0; }
static inline const struct pci_device_id *pci_match_device(const struct pci_device_id *ids, const struct pci_dev *dev) { return NULL; }
/* Power management related routines */
include/linux/pci_ids.h
+12
View File
@@ -935,6 +935,7 @@
#define PCI_DEVICE_ID_PLX_DJINN_ITOO 0x1151
#define PCI_DEVICE_ID_PLX_R753 0x1152
#define PCI_DEVICE_ID_PLX_OLITEC 0x1187
#define PCI_DEVICE_ID_PLX_PCI200SYN 0x3196
#define PCI_DEVICE_ID_PLX_9050 0x9050
#define PCI_DEVICE_ID_PLX_9080 0x9080
#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2 0xa001
@@ -1182,6 +1183,14 @@
#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100 0x034E
#define PCI_DEVICE_ID_NVIDIA_NVENET_14 0x0372
#define PCI_DEVICE_ID_NVIDIA_NVENET_15 0x0373
#define PCI_DEVICE_ID_NVIDIA_NVENET_16 0x03E5
#define PCI_DEVICE_ID_NVIDIA_NVENET_17 0x03E6
#define PCI_DEVICE_ID_NVIDIA_NVENET_18 0x03EE
#define PCI_DEVICE_ID_NVIDIA_NVENET_19 0x03EF
#define PCI_DEVICE_ID_NVIDIA_NVENET_20 0x0450
#define PCI_DEVICE_ID_NVIDIA_NVENET_21 0x0451
#define PCI_DEVICE_ID_NVIDIA_NVENET_22 0x0452
#define PCI_DEVICE_ID_NVIDIA_NVENET_23 0x0453
#define PCI_VENDOR_ID_IMS 0x10e0
#define PCI_DEVICE_ID_IMS_TT128 0x9128
@@ -1827,6 +1836,7 @@
#define PCI_VENDOR_ID_SAMSUNG 0x144d
#define PCI_VENDOR_ID_MYRICOM 0x14c1
#define PCI_VENDOR_ID_TITAN 0x14D2
#define PCI_DEVICE_ID_TITAN_010L 0x8001
@@ -1887,6 +1897,7 @@
#define PCI_DEVICE_ID_TIGON3_5751F 0x167e
#define PCI_DEVICE_ID_TIGON3_5787M 0x1693
#define PCI_DEVICE_ID_TIGON3_5782 0x1696
#define PCI_DEVICE_ID_TIGON3_5786 0x169a
#define PCI_DEVICE_ID_TIGON3_5787 0x169b
#define PCI_DEVICE_ID_TIGON3_5788 0x169c
#define PCI_DEVICE_ID_TIGON3_5789 0x169d
@@ -2043,6 +2054,7 @@
#define PCI_DEVICE_ID_INTEL_80960_RP 0x1960
#define PCI_DEVICE_ID_INTEL_82840_HB 0x1a21
#define PCI_DEVICE_ID_INTEL_82845_HB 0x1a30
#define PCI_DEVICE_ID_INTEL_IOAT 0x1a38
#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410
#define PCI_DEVICE_ID_INTEL_82801AA_1 0x2411
#define PCI_DEVICE_ID_INTEL_82801AA_3 0x2413
include/linux/pfkeyv2.h
+1 -1
View File
@@ -159,7 +159,7 @@ struct sadb_spirange {
struct sadb_x_kmprivate {
uint16_t sadb_x_kmprivate_len;
uint16_t sadb_x_kmprivate_exttype;
u_int32_t sadb_x_kmprivate_reserved;
uint32_t sadb_x_kmprivate_reserved;
} __attribute__((packed));
/* sizeof(struct sadb_x_kmprivate) == 8 */
include/linux/security.h
+34 -6
View File
@@ -805,31 +805,37 @@ struct swap_info_struct;
* used by the XFRM system.
* @sec_ctx contains the security context information being provided by
* the user-level policy update program (e.g., setkey).
* Allocate a security structure to the xp->selector.security field.
* Allocate a security structure to the xp->security field.
* The security field is initialized to NULL when the xfrm_policy is
* allocated.
* Return 0 if operation was successful (memory to allocate, legal context)
* @xfrm_policy_clone_security:
* @old contains an existing xfrm_policy in the SPD.
* @new contains a new xfrm_policy being cloned from old.
* Allocate a security structure to the new->selector.security field
* that contains the information from the old->selector.security field.
* Allocate a security structure to the new->security field
* that contains the information from the old->security field.
* Return 0 if operation was successful (memory to allocate).
* @xfrm_policy_free_security:
* @xp contains the xfrm_policy
* Deallocate xp->selector.security.
* Deallocate xp->security.
* @xfrm_policy_delete_security:
* @xp contains the xfrm_policy.
* Authorize deletion of xp->security.
* @xfrm_state_alloc_security:
* @x contains the xfrm_state being added to the Security Association
* Database by the XFRM system.
* @sec_ctx contains the security context information being provided by
* the user-level SA generation program (e.g., setkey or racoon).
* Allocate a security structure to the x->sel.security field. The
* Allocate a security structure to the x->security field. The
* security field is initialized to NULL when the xfrm_state is
* allocated.
* Return 0 if operation was successful (memory to allocate, legal context).
* @xfrm_state_free_security:
* @x contains the xfrm_state.
* Deallocate x>sel.security.
* Deallocate x->security.
* @xfrm_state_delete_security:
* @x contains the xfrm_state.
* Authorize deletion of x->security.
* @xfrm_policy_lookup:
* @xp contains the xfrm_policy for which the access control is being
* checked.
@@ -1298,8 +1304,10 @@ struct security_operations {
int (*xfrm_policy_alloc_security) (struct xfrm_policy *xp, struct xfrm_user_sec_ctx *sec_ctx);
int (*xfrm_policy_clone_security) (struct xfrm_policy *old, struct xfrm_policy *new);
void (*xfrm_policy_free_security) (struct xfrm_policy *xp);
int (*xfrm_policy_delete_security) (struct xfrm_policy *xp);
int (*xfrm_state_alloc_security) (struct xfrm_state *x, struct xfrm_user_sec_ctx *sec_ctx);
void (*xfrm_state_free_security) (struct xfrm_state *x);
int (*xfrm_state_delete_security) (struct xfrm_state *x);
int (*xfrm_policy_lookup)(struct xfrm_policy *xp, u32 sk_sid, u8 dir);
#endif /* CONFIG_SECURITY_NETWORK_XFRM */
@@ -2934,11 +2942,21 @@ static inline void security_xfrm_policy_free(struct xfrm_policy *xp)
security_ops->xfrm_policy_free_security(xp);
}
static inline int security_xfrm_policy_delete(struct xfrm_policy *xp)
{
return security_ops->xfrm_policy_delete_security(xp);
}
static inline int security_xfrm_state_alloc(struct xfrm_state *x, struct xfrm_user_sec_ctx *sec_ctx)
{
return security_ops->xfrm_state_alloc_security(x, sec_ctx);
}
static inline int security_xfrm_state_delete(struct xfrm_state *x)
{
return security_ops->xfrm_state_delete_security(x);
}
static inline void security_xfrm_state_free(struct xfrm_state *x)
{
security_ops->xfrm_state_free_security(x);
@@ -2963,6 +2981,11 @@ static inline void security_xfrm_policy_free(struct xfrm_policy *xp)
{
}
static inline int security_xfrm_policy_delete(struct xfrm_policy *xp)
{
return 0;
}
static inline int security_xfrm_state_alloc(struct xfrm_state *x, struct xfrm_user_sec_ctx *sec_ctx)
{
return 0;
@@ -2972,6 +2995,11 @@ static inline void security_xfrm_state_free(struct xfrm_state *x)
{
}
static inline int security_xfrm_state_delete(struct xfrm_state *x)
{
return 0;
}
static inline int security_xfrm_policy_lookup(struct xfrm_policy *xp, u32 sk_sid, u8 dir)
{
return 0;
include/linux/selinux.h
+32
View File
@@ -118,6 +118,27 @@ void selinux_get_ipc_sid(const struct kern_ipc_perm *ipcp, u32 *sid);
*/
void selinux_get_task_sid(struct task_struct *tsk, u32 *sid);
/**
* selinux_string_to_sid - map a security context string to a security ID
* @str: the security context string to be mapped
* @sid: ID value returned via this.
*
* Returns 0 if successful, with the SID stored in sid. A value
* of zero for sid indicates no SID could be determined (but no error
* occurred).
*/
int selinux_string_to_sid(char *str, u32 *sid);
/**
* selinux_relabel_packet_permission - check permission to relabel a packet
* @sid: ID value to be applied to network packet (via SECMARK, most likely)
*
* Returns 0 if the current task is allowed to label packets with the
* supplied security ID. Note that it is implicit that the packet is always
* being relabeled from the default unlabled value, and that the access
* control decision is made in the AVC.
*/
int selinux_relabel_packet_permission(u32 sid);
#else
@@ -172,6 +193,17 @@ static inline void selinux_get_task_sid(struct task_struct *tsk, u32 *sid)
*sid = 0;
}
static inline int selinux_string_to_sid(const char *str, u32 *sid)
{
*sid = 0;
return 0;
}
static inline int selinux_relabel_packet_permission(u32 sid)
{
return 0;
}
#endif /* CONFIG_SECURITY_SELINUX */
#endif /* _LINUX_SELINUX_H */
include/linux/skbuff.h
+58 -16
View File
@@ -29,6 +29,7 @@
#include <linux/net.h>
#include <linux/textsearch.h>
#include <net/checksum.h>
#include <linux/dmaengine.h>
#define HAVE_ALLOC_SKB /* For the drivers to know */
#define HAVE_ALIGNABLE_SKB /* Ditto 8) */
@@ -209,6 +210,7 @@ enum {
* @nf_bridge: Saved data about a bridged frame - see br_netfilter.c
* @tc_index: Traffic control index
* @tc_verd: traffic control verdict
* @secmark: security marking
*/
struct sk_buff {
@@ -285,6 +287,12 @@ struct sk_buff {
__u16 tc_verd; /* traffic control verdict */
#endif
#endif
#ifdef CONFIG_NET_DMA
dma_cookie_t dma_cookie;
#endif
#ifdef CONFIG_NETWORK_SECMARK
__u32 secmark;
#endif
/* These elements must be at the end, see alloc_skb() for details. */
@@ -967,15 +975,16 @@ static inline void skb_reserve(struct sk_buff *skb, int len)
#define NET_SKB_PAD 16
#endif
extern int ___pskb_trim(struct sk_buff *skb, unsigned int len, int realloc);
extern int ___pskb_trim(struct sk_buff *skb, unsigned int len);
static inline void __skb_trim(struct sk_buff *skb, unsigned int len)
{
if (!skb->data_len) {
skb->len = len;
skb->tail = skb->data + len;
} else
___pskb_trim(skb, len, 0);
if (unlikely(skb->data_len)) {
WARN_ON(1);
return;
}
skb->len = len;
skb->tail = skb->data + len;
}
/**
@@ -985,6 +994,7 @@ static inline void __skb_trim(struct sk_buff *skb, unsigned int len)
*
* Cut the length of a buffer down by removing data from the tail. If
* the buffer is already under the length specified it is not modified.
* The skb must be linear.
*/
static inline void skb_trim(struct sk_buff *skb, unsigned int len)
{
@@ -995,12 +1005,10 @@ static inline void skb_trim(struct sk_buff *skb, unsigned int len)
static inline int __pskb_trim(struct sk_buff *skb, unsigned int len)
{
if (!skb->data_len) {
skb->len = len;
skb->tail = skb->data+len;
return 0;
}
return ___pskb_trim(skb, len, 1);
if (skb->data_len)
return ___pskb_trim(skb, len);
__skb_trim(skb, len);
return 0;
}
static inline int pskb_trim(struct sk_buff *skb, unsigned int len)
@@ -1161,18 +1169,34 @@ static inline int skb_can_coalesce(struct sk_buff *skb, int i,
return 0;
}
static inline int __skb_linearize(struct sk_buff *skb)
{
return __pskb_pull_tail(skb, skb->data_len) ? 0 : -ENOMEM;
}
/**
* skb_linearize - convert paged skb to linear one
* @skb: buffer to linarize
* @gfp: allocation mode
*
* If there is no free memory -ENOMEM is returned, otherwise zero
* is returned and the old skb data released.
*/
extern int __skb_linearize(struct sk_buff *skb, gfp_t gfp);
static inline int skb_linearize(struct sk_buff *skb, gfp_t gfp)
static inline int skb_linearize(struct sk_buff *skb)
{
return __skb_linearize(skb, gfp);
return skb_is_nonlinear(skb) ? __skb_linearize(skb) : 0;
}
/**
* skb_linearize_cow - make sure skb is linear and writable
* @skb: buffer to process
*
* If there is no free memory -ENOMEM is returned, otherwise zero
* is returned and the old skb data released.
*/
static inline int skb_linearize_cow(struct sk_buff *skb)
{
return skb_is_nonlinear(skb) || skb_cloned(skb) ?
__skb_linearize(skb) : 0;
}
/**
@@ -1396,5 +1420,23 @@ static inline void nf_reset(struct sk_buff *skb)
static inline void nf_reset(struct sk_buff *skb) {}
#endif /* CONFIG_NETFILTER */
#ifdef CONFIG_NETWORK_SECMARK
static inline void skb_copy_secmark(struct sk_buff *to, const struct sk_buff *from)
{
to->secmark = from->secmark;
}
static inline void skb_init_secmark(struct sk_buff *skb)
{
skb->secmark = 0;
}
#else
static inline void skb_copy_secmark(struct sk_buff *to, const struct sk_buff *from)
{ }
static inline void skb_init_secmark(struct sk_buff *skb)
{ }
#endif
#endif /* __KERNEL__ */
#endif /* _LINUX_SKBUFF_H */
include/linux/sysctl.h
+4
View File
@@ -313,6 +313,7 @@ enum
NET_NF_CONNTRACK_FRAG6_TIMEOUT=29,
NET_NF_CONNTRACK_FRAG6_LOW_THRESH=30,
NET_NF_CONNTRACK_FRAG6_HIGH_THRESH=31,
NET_NF_CONNTRACK_CHECKSUM=32,
};
/* /proc/sys/net/ipv4 */
@@ -403,6 +404,8 @@ enum
NET_TCP_MTU_PROBING=113,
NET_TCP_BASE_MSS=114,
NET_IPV4_TCP_WORKAROUND_SIGNED_WINDOWS=115,
NET_TCP_DMA_COPYBREAK=116,
NET_TCP_SLOW_START_AFTER_IDLE=117,
};
enum {
@@ -491,6 +494,7 @@ enum
NET_IPV4_NF_CONNTRACK_SCTP_TIMEOUT_SHUTDOWN_RECD=25,
NET_IPV4_NF_CONNTRACK_SCTP_TIMEOUT_SHUTDOWN_ACK_SENT=26,
NET_IPV4_NF_CONNTRACK_COUNT=27,
NET_IPV4_NF_CONNTRACK_CHECKSUM=28,
};
/* /proc/sys/net/ipv6 */
include/linux/tcp.h
+8
View File
@@ -18,6 +18,7 @@
#define _LINUX_TCP_H
#include <linux/types.h>
#include <linux/dmaengine.h>
#include <asm/byteorder.h>
struct tcphdr {
@@ -233,6 +234,13 @@ struct tcp_sock {
struct iovec *iov;
int memory;
int len;
#ifdef CONFIG_NET_DMA
/* members for async copy */
struct dma_chan *dma_chan;
int wakeup;
struct dma_pinned_list *pinned_list;
dma_cookie_t dma_cookie;
#endif
} ucopy;
__u32 snd_wl1; /* Sequence for window update */
include/linux/xfrm.h
+4
View File
@@ -118,6 +118,10 @@ enum
XFRM_SHARE_UNIQUE /* Use once */
};
#define XFRM_MODE_TRANSPORT 0
#define XFRM_MODE_TUNNEL 1
#define XFRM_MODE_MAX 2
/* Netlink configuration messages. */
enum {
XFRM_MSG_BASE = 0x10,
include/net/ieee80211.h
+7 -2
View File
@@ -29,7 +29,7 @@
#include <linux/kernel.h> /* ARRAY_SIZE */
#include <linux/wireless.h>
#define IEEE80211_VERSION "git-1.1.7"
#define IEEE80211_VERSION "git-1.1.13"
#define IEEE80211_DATA_LEN 2304
/* Maximum size for the MA-UNITDATA primitive, 802.11 standard section
@@ -104,6 +104,9 @@
#define IEEE80211_SCTL_FRAG 0x000F
#define IEEE80211_SCTL_SEQ 0xFFF0
/* QOS control */
#define IEEE80211_QCTL_TID 0x000F
/* debug macros */
#ifdef CONFIG_IEEE80211_DEBUG
@@ -1075,6 +1078,7 @@ struct ieee80211_device {
int (*handle_management) (struct net_device * dev,
struct ieee80211_network * network, u16 type);
int (*is_qos_active) (struct net_device *dev, struct sk_buff *skb);
/* Typical STA methods */
int (*handle_auth) (struct net_device * dev,
@@ -1243,7 +1247,8 @@ extern int ieee80211_set_encryption(struct ieee80211_device *ieee);
extern int ieee80211_xmit(struct sk_buff *skb, struct net_device *dev);
extern void ieee80211_txb_free(struct ieee80211_txb *);
extern int ieee80211_tx_frame(struct ieee80211_device *ieee,
struct ieee80211_hdr *frame, int len);
struct ieee80211_hdr *frame, int hdr_len,
int total_len, int encrypt_mpdu);
/* ieee80211_rx.c */
extern int ieee80211_rx(struct ieee80211_device *ieee, struct sk_buff *skb,
include/net/ieee80211softmac.h
+34 -6
View File
@@ -86,6 +86,9 @@ struct ieee80211softmac_assoc_info {
/* BSSID we're trying to associate to */
char bssid[ETH_ALEN];
/* Rates supported by the network */
struct ieee80211softmac_ratesinfo supported_rates;
/* some flags.
* static_essid is valid if the essid is constant,
@@ -132,23 +135,26 @@ enum {
struct ieee80211softmac_txrates {
/* The Bit-Rate to be used for multicast frames. */
u8 mcast_rate;
/* The Bit-Rate to be used for multicast fallback
* (If the device supports fallback and hardware-retry)
*/
u8 mcast_fallback;
/* The Bit-Rate to be used for multicast management frames. */
u8 mgt_mcast_rate;
/* The Bit-Rate to be used for any other (normal) data packet. */
u8 default_rate;
/* The Bit-Rate to be used for default fallback
* (If the device supports fallback and hardware-retry)
*/
u8 default_fallback;
/* This is the rate that the user asked for */
u8 user_rate;
};
/* Bits for txrates_change callback. */
#define IEEE80211SOFTMAC_TXRATECHG_DEFAULT (1 << 0) /* default_rate */
#define IEEE80211SOFTMAC_TXRATECHG_DEFAULT_FBACK (1 << 1) /* default_fallback */
#define IEEE80211SOFTMAC_TXRATECHG_MCAST (1 << 2) /* mcast_rate */
#define IEEE80211SOFTMAC_TXRATECHG_MCAST_FBACK (1 << 3) /* mcast_fallback */
#define IEEE80211SOFTMAC_TXRATECHG_MGT_MCAST (1 << 3) /* mgt_mcast_rate */
struct ieee80211softmac_device {
/* 802.11 structure for data stuff */
@@ -250,6 +256,28 @@ extern void ieee80211softmac_fragment_lost(struct net_device *dev,
* Note that the rates need to be sorted. */
extern void ieee80211softmac_set_rates(struct net_device *dev, u8 count, u8 *rates);
/* Helper function which advises you the rate at which a frame should be
* transmitted at. */
static inline u8 ieee80211softmac_suggest_txrate(struct ieee80211softmac_device *mac,
int is_multicast,
int is_mgt)
{
struct ieee80211softmac_txrates *txrates = &mac->txrates;
if (!mac->associated)
return txrates->mgt_mcast_rate;
/* We are associated, sending unicast frame */
if (!is_multicast)
return txrates->default_rate;
/* We are associated, sending multicast frame */
if (is_mgt)
return txrates->mgt_mcast_rate;
else
return txrates->mcast_rate;
}
/* Start the SoftMAC. Call this after you initialized the device
* and it is ready to run.
*/
@@ -282,7 +310,7 @@ extern void ieee80211softmac_stop(struct net_device *dev);
* - context set to the context data you want passed
* The return value is 0, or an error.
*/
typedef void (*notify_function_ptr)(struct net_device *dev, void *context);
typedef void (*notify_function_ptr)(struct net_device *dev, int event_type, void *context);
#define ieee80211softmac_notify(dev, event, fun, context) ieee80211softmac_notify_gfp(dev, event, fun, context, GFP_KERNEL);
#define ieee80211softmac_notify_atomic(dev, event, fun, context) ieee80211softmac_notify_gfp(dev, event, fun, context, GFP_ATOMIC);
include/net/ieee80211softmac_wx.h
+5
View File
@@ -91,4 +91,9 @@ ieee80211softmac_wx_get_genie(struct net_device *dev,
struct iw_request_info *info,
union iwreq_data *wrqu,
char *extra);
extern int
ieee80211softmac_wx_set_mlme(struct net_device *dev,
struct iw_request_info *info,
union iwreq_data *wrqu,
char *extra);
#endif /* _IEEE80211SOFTMAC_WX */
include/net/ip.h
-1
View File
@@ -147,7 +147,6 @@ void ip_send_reply(struct sock *sk, struct sk_buff *skb, struct ip_reply_arg *ar
struct ipv4_config
{
int log_martians;
int autoconfig;
int no_pmtu_disc;
};
include/net/llc_if.h
+10 -7
View File
@@ -16,6 +16,7 @@
#include <linux/if.h>
#include <linux/if_arp.h>
#include <linux/llc.h>
#include <linux/etherdevice.h>
#include <net/llc.h>
#define LLC_DATAUNIT_PRIM 1
@@ -61,8 +62,6 @@
#define LLC_STATUS_CONFLICT 7 /* disconnect conn */
#define LLC_STATUS_RESET_DONE 8 /* */
extern u8 llc_mac_null_var[IFHWADDRLEN];
/**
* llc_mac_null - determines if a address is a null mac address
* @mac: Mac address to test if null.
@@ -70,16 +69,20 @@ extern u8 llc_mac_null_var[IFHWADDRLEN];
* Determines if a given address is a null mac address. Returns 0 if the
* address is not a null mac, 1 if the address is a null mac.
*/
static __inline__ int llc_mac_null(u8 *mac)
static inline int llc_mac_null(const u8 *mac)
{
return !memcmp(mac, llc_mac_null_var, IFHWADDRLEN);
return is_zero_ether_addr(mac);
}
static __inline__ int llc_addrany(struct llc_addr *addr)
static inline int llc_addrany(const struct llc_addr *addr)
{
return llc_mac_null(addr->mac) && !addr->lsap;
}
static inline int llc_mac_multicast(const u8 *mac)
{
return is_multicast_ether_addr(mac);
}
/**
* llc_mac_match - determines if two mac addresses are the same
* @mac1: First mac address to compare.
@@ -89,9 +92,9 @@ static __inline__ int llc_addrany(struct llc_addr *addr)
* is not a complete match up to len, 1 if a complete match up to len is
* found.
*/
static __inline__ int llc_mac_match(u8 *mac1, u8 *mac2)
static inline int llc_mac_match(const u8 *mac1, const u8 *mac2)
{
return !memcmp(mac1, mac2, IFHWADDRLEN);
return !compare_ether_addr(mac1, mac2);
}
extern int llc_establish_connection(struct sock *sk, u8 *lmac,
include/net/netdma.h
+44
View File
@@ -0,0 +1,44 @@
/*
* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free
* Software Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59
* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* The full GNU General Public License is included in this distribution in the
* file called COPYING.
*/
#ifndef NETDMA_H
#define NETDMA_H
#include <linux/config.h>
#ifdef CONFIG_NET_DMA
#include <linux/dmaengine.h>
#include <linux/skbuff.h>
static inline struct dma_chan *get_softnet_dma(void)
{
struct dma_chan *chan;
rcu_read_lock();
chan = rcu_dereference(__get_cpu_var(softnet_data.net_dma));
if (chan)
dma_chan_get(chan);
rcu_read_unlock();
return chan;
}
int dma_skb_copy_datagram_iovec(struct dma_chan* chan,
const struct sk_buff *skb, int offset, struct iovec *to,
size_t len, struct dma_pinned_list *pinned_list);
#endif /* CONFIG_NET_DMA */
#endif /* NETDMA_H */
include/net/netfilter/nf_conntrack.h
+5
View File
@@ -114,6 +114,10 @@ struct nf_conn
u_int32_t mark;
#endif
#ifdef CONFIG_NF_CONNTRACK_SECMARK
u_int32_t secmark;
#endif
/* Storage reserved for other modules: */
union nf_conntrack_proto proto;
@@ -285,6 +289,7 @@ static inline int nf_ct_is_dying(struct nf_conn *ct)
}
extern unsigned int nf_conntrack_htable_size;
extern int nf_conntrack_checksum;
#define NF_CT_STAT_INC(count) (__get_cpu_var(nf_conntrack_stat).count++)
include/net/netfilter/nf_conntrack_compat.h
+26
View File
@@ -20,6 +20,19 @@ static inline u_int32_t *nf_ct_get_mark(const struct sk_buff *skb,
}
#endif /* CONFIG_IP_NF_CONNTRACK_MARK */
#ifdef CONFIG_IP_NF_CONNTRACK_SECMARK
static inline u_int32_t *nf_ct_get_secmark(const struct sk_buff *skb,
u_int32_t *ctinfo)
{
struct ip_conntrack *ct = ip_conntrack_get(skb, ctinfo);
if (ct)
return &ct->secmark;
else
return NULL;
}
#endif /* CONFIG_IP_NF_CONNTRACK_SECMARK */
#ifdef CONFIG_IP_NF_CT_ACCT
static inline struct ip_conntrack_counter *
nf_ct_get_counters(const struct sk_buff *skb)
@@ -70,6 +83,19 @@ static inline u_int32_t *nf_ct_get_mark(const struct sk_buff *skb,
}
#endif /* CONFIG_NF_CONNTRACK_MARK */
#ifdef CONFIG_NF_CONNTRACK_SECMARK
static inline u_int32_t *nf_ct_get_secmark(const struct sk_buff *skb,
u_int32_t *ctinfo)
{
struct nf_conn *ct = nf_ct_get(skb, ctinfo);
if (ct)
return &ct->secmark;
else
return NULL;
}
#endif /* CONFIG_NF_CONNTRACK_MARK */
#ifdef CONFIG_NF_CT_ACCT
static inline struct ip_conntrack_counter *
nf_ct_get_counters(const struct sk_buff *skb)
include/net/raw.h
+1 -1
View File
@@ -36,7 +36,7 @@ extern rwlock_t raw_v4_lock;
extern struct sock *__raw_v4_lookup(struct sock *sk, unsigned short num,
unsigned long raddr, unsigned long laddr,
__be32 raddr, __be32 laddr,
int dif);
extern int raw_v4_input(struct sk_buff *skb, struct iphdr *iph, int hash);
include/net/sctp/sctp.h
+1 -1
View File
@@ -255,7 +255,7 @@ extern int sctp_debug_flag;
#define SCTP_DEBUG_PRINTK_IPADDR(whatever...)
#define SCTP_ENABLE_DEBUG
#define SCTP_DISABLE_DEBUG
#define SCTP_ASSERT(expr, str, func)
#define SCTP_ASSERT(expr, str, func) BUG_ON(!(expr))
#endif /* SCTP_DEBUG */
include/net/sctp/structs.h
+2 -1
View File
@@ -555,7 +555,8 @@ struct sctp_af {
int (*to_addr_param) (const union sctp_addr *,
union sctp_addr_param *);
int (*addr_valid) (union sctp_addr *,
struct sctp_sock *);
struct sctp_sock *,
const struct sk_buff *);
sctp_scope_t (*scope) (union sctp_addr *);
void (*inaddr_any) (union sctp_addr *, unsigned short);
int (*is_any) (const union sctp_addr *);
include/net/sock.h
+15 -5
View File
@@ -132,6 +132,7 @@ struct sock_common {
* @sk_receive_queue: incoming packets
* @sk_wmem_alloc: transmit queue bytes committed
* @sk_write_queue: Packet sending queue
* @sk_async_wait_queue: DMA copied packets
* @sk_omem_alloc: "o" is "option" or "other"
* @sk_wmem_queued: persistent queue size
* @sk_forward_alloc: space allocated forward
@@ -205,6 +206,7 @@ struct sock {
atomic_t sk_omem_alloc;
struct sk_buff_head sk_receive_queue;
struct sk_buff_head sk_write_queue;
struct sk_buff_head sk_async_wait_queue;
int sk_wmem_queued;
int sk_forward_alloc;
gfp_t sk_allocation;
@@ -871,10 +873,7 @@ static inline int sk_filter(struct sock *sk, struct sk_buff *skb, int needlock)
if (filter) {
unsigned int pkt_len = sk_run_filter(skb, filter->insns,
filter->len);
if (!pkt_len)
err = -EPERM;
else
skb_trim(skb, pkt_len);
err = pkt_len ? pskb_trim(skb, pkt_len) : -EPERM;
}
if (needlock)
@@ -1271,11 +1270,22 @@ sock_recv_timestamp(struct msghdr *msg, struct sock *sk, struct sk_buff *skb)
* This routine must be called with interrupts disabled or with the socket
* locked so that the sk_buff queue operation is ok.
*/
static inline void sk_eat_skb(struct sock *sk, struct sk_buff *skb)
#ifdef CONFIG_NET_DMA
static inline void sk_eat_skb(struct sock *sk, struct sk_buff *skb, int copied_early)
{
__skb_unlink(skb, &sk->sk_receive_queue);
if (!copied_early)
__kfree_skb(skb);
else
__skb_queue_tail(&sk->sk_async_wait_queue, skb);
}
#else
static inline void sk_eat_skb(struct sock *sk, struct sk_buff *skb, int copied_early)
{
__skb_unlink(skb, &sk->sk_receive_queue);
__kfree_skb(skb);
}
#endif
extern void sock_enable_timestamp(struct sock *sk);
extern int sock_get_timestamp(struct sock *, struct timeval __user *);
include/net/tcp.h
+13 -2
View File
@@ -28,6 +28,7 @@
#include <linux/cache.h>
#include <linux/percpu.h>
#include <linux/skbuff.h>
#include <linux/dmaengine.h>
#include <net/inet_connection_sock.h>
#include <net/inet_timewait_sock.h>
@@ -218,6 +219,7 @@ extern int sysctl_tcp_adv_win_scale;
extern int sysctl_tcp_tw_reuse;
extern int sysctl_tcp_frto;
extern int sysctl_tcp_low_latency;
extern int sysctl_tcp_dma_copybreak;
extern int sysctl_tcp_nometrics_save;
extern int sysctl_tcp_moderate_rcvbuf;
extern int sysctl_tcp_tso_win_divisor;
@@ -225,6 +227,7 @@ extern int sysctl_tcp_abc;
extern int sysctl_tcp_mtu_probing;
extern int sysctl_tcp_base_mss;
extern int sysctl_tcp_workaround_signed_windows;
extern int sysctl_tcp_slow_start_after_idle;
extern atomic_t tcp_memory_allocated;
extern atomic_t tcp_sockets_allocated;
@@ -293,6 +296,8 @@ extern int tcp_rcv_established(struct sock *sk,
extern void tcp_rcv_space_adjust(struct sock *sk);
extern void tcp_cleanup_rbuf(struct sock *sk, int copied);
extern int tcp_twsk_unique(struct sock *sk,
struct sock *sktw, void *twp);
@@ -628,7 +633,7 @@ struct tcp_congestion_ops {
/* return slow start threshold (required) */
u32 (*ssthresh)(struct sock *sk);
/* lower bound for congestion window (optional) */
u32 (*min_cwnd)(struct sock *sk);
u32 (*min_cwnd)(const struct sock *sk);
/* do new cwnd calculation (required) */
void (*cong_avoid)(struct sock *sk, u32 ack,
u32 rtt, u32 in_flight, int good_ack);
@@ -663,7 +668,7 @@ extern struct tcp_congestion_ops tcp_init_congestion_ops;
extern u32 tcp_reno_ssthresh(struct sock *sk);
extern void tcp_reno_cong_avoid(struct sock *sk, u32 ack,
u32 rtt, u32 in_flight, int flag);
extern u32 tcp_reno_min_cwnd(struct sock *sk);
extern u32 tcp_reno_min_cwnd(const struct sock *sk);
extern struct tcp_congestion_ops tcp_reno;
static inline void tcp_set_ca_state(struct sock *sk, const u8 ca_state)
@@ -817,6 +822,12 @@ static inline void tcp_prequeue_init(struct tcp_sock *tp)
tp->ucopy.len = 0;
tp->ucopy.memory = 0;
skb_queue_head_init(&tp->ucopy.prequeue);
#ifdef CONFIG_NET_DMA
tp->ucopy.dma_chan = NULL;
tp->ucopy.wakeup = 0;
tp->ucopy.pinned_list = NULL;
tp->ucopy.dma_cookie = 0;
#endif
}
/* Packet is added to VJ-style prequeue for processing in process
include/net/xfrm.h
+18 -8
View File
@@ -20,6 +20,8 @@
#include <net/ip6_fib.h>
#define XFRM_ALIGN8(len) (((len) + 7) & ~7)
#define MODULE_ALIAS_XFRM_MODE(family, encap) \
MODULE_ALIAS("xfrm-mode-" __stringify(family) "-" __stringify(encap))
extern struct sock *xfrm_nl;
extern u32 sysctl_xfrm_aevent_etime;
@@ -164,6 +166,7 @@ struct xfrm_state
/* Reference to data common to all the instances of this
* transformer. */
struct xfrm_type *type;
struct xfrm_mode *mode;
/* Security context */
struct xfrm_sec_ctx *security;
@@ -204,8 +207,8 @@ struct xfrm_type;
struct xfrm_dst;
struct xfrm_policy_afinfo {
unsigned short family;
rwlock_t lock;
struct xfrm_type_map *type_map;
struct xfrm_type *type_map[IPPROTO_MAX];
struct xfrm_mode *mode_map[XFRM_MODE_MAX];
struct dst_ops *dst_ops;
void (*garbage_collect)(void);
int (*dst_lookup)(struct xfrm_dst **dst, struct flowi *fl);
@@ -232,7 +235,6 @@ extern int __xfrm_state_delete(struct xfrm_state *x);
struct xfrm_state_afinfo {
unsigned short family;
rwlock_t lock;
struct list_head *state_bydst;
struct list_head *state_byspi;
int (*init_flags)(struct xfrm_state *x);
@@ -264,16 +266,24 @@ struct xfrm_type
u32 (*get_max_size)(struct xfrm_state *, int size);
};
struct xfrm_type_map {
rwlock_t lock;
struct xfrm_type *map[256];
};
extern int xfrm_register_type(struct xfrm_type *type, unsigned short family);
extern int xfrm_unregister_type(struct xfrm_type *type, unsigned short family);
extern struct xfrm_type *xfrm_get_type(u8 proto, unsigned short family);
extern void xfrm_put_type(struct xfrm_type *type);
struct xfrm_mode {
int (*input)(struct xfrm_state *x, struct sk_buff *skb);
int (*output)(struct sk_buff *skb);
struct module *owner;
unsigned int encap;
};
extern int xfrm_register_mode(struct xfrm_mode *mode, int family);
extern int xfrm_unregister_mode(struct xfrm_mode *mode, int family);
extern struct xfrm_mode *xfrm_get_mode(unsigned int encap, int family);
extern void xfrm_put_mode(struct xfrm_mode *mode);
struct xfrm_tmpl
{
/* id in template is interpreted as:
include/rdma/ib_addr.h
+114
View File
@@ -0,0 +1,114 @@
/*
* Copyright (c) 2005 Voltaire Inc. All rights reserved.
* Copyright (c) 2005 Intel Corporation. All rights reserved.
*
* This Software is licensed under one of the following licenses:
*
* 1) under the terms of the "Common Public License 1.0" a copy of which is
* available from the Open Source Initiative, see
* http://www.opensource.org/licenses/cpl.php.
*
* 2) under the terms of the "The BSD License" a copy of which is
* available from the Open Source Initiative, see
* http://www.opensource.org/licenses/bsd-license.php.
*
* 3) under the terms of the "GNU General Public License (GPL) Version 2" a
* copy of which is available from the Open Source Initiative, see
* http://www.opensource.org/licenses/gpl-license.php.
*
* Licensee has the right to choose one of the above licenses.
*
* Redistributions of source code must retain the above copyright
* notice and one of the license notices.
*
* Redistributions in binary form must reproduce both the above copyright
* notice, one of the license notices in the documentation
* and/or other materials provided with the distribution.
*
*/
#if !defined(IB_ADDR_H)
#define IB_ADDR_H
#include <linux/in.h>
#include <linux/in6.h>
#include <linux/netdevice.h>
#include <linux/socket.h>
#include <rdma/ib_verbs.h>
struct rdma_dev_addr {
unsigned char src_dev_addr[MAX_ADDR_LEN];
unsigned char dst_dev_addr[MAX_ADDR_LEN];
unsigned char broadcast[MAX_ADDR_LEN];
enum ib_node_type dev_type;
};
/**
* rdma_translate_ip - Translate a local IP address to an RDMA hardware
* address.
*/
int rdma_translate_ip(struct sockaddr *addr, struct rdma_dev_addr *dev_addr);
/**
* rdma_resolve_ip - Resolve source and destination IP addresses to
* RDMA hardware addresses.
* @src_addr: An optional source address to use in the resolution. If a
* source address is not provided, a usable address will be returned via
* the callback.
* @dst_addr: The destination address to resolve.
* @addr: A reference to a data location that will receive the resolved
* addresses. The data location must remain valid until the callback has
* been invoked.
* @timeout_ms: Amount of time to wait for the address resolution to complete.
* @callback: Call invoked once address resolution has completed, timed out,
* or been canceled. A status of 0 indicates success.
* @context: User-specified context associated with the call.
*/
int rdma_resolve_ip(struct sockaddr *src_addr, struct sockaddr *dst_addr,
struct rdma_dev_addr *addr, int timeout_ms,
void (*callback)(int status, struct sockaddr *src_addr,
struct rdma_dev_addr *addr, void *context),
void *context);
void rdma_addr_cancel(struct rdma_dev_addr *addr);
static inline int ip_addr_size(struct sockaddr *addr)
{
return addr->sa_family == AF_INET6 ?
sizeof(struct sockaddr_in6) : sizeof(struct sockaddr_in);
}
static inline u16 ib_addr_get_pkey(struct rdma_dev_addr *dev_addr)
{
return ((u16)dev_addr->broadcast[8] << 8) | (u16)dev_addr->broadcast[9];
}
static inline void ib_addr_set_pkey(struct rdma_dev_addr *dev_addr, u16 pkey)
{
dev_addr->broadcast[8] = pkey >> 8;
dev_addr->broadcast[9] = (unsigned char) pkey;
}
static inline union ib_gid *ib_addr_get_sgid(struct rdma_dev_addr *dev_addr)
{
return (union ib_gid *) (dev_addr->src_dev_addr + 4);
}
static inline void ib_addr_set_sgid(struct rdma_dev_addr *dev_addr,
union ib_gid *gid)
{
memcpy(dev_addr->src_dev_addr + 4, gid, sizeof *gid);
}
static inline union ib_gid *ib_addr_get_dgid(struct rdma_dev_addr *dev_addr)
{
return (union ib_gid *) (dev_addr->dst_dev_addr + 4);
}
static inline void ib_addr_set_dgid(struct rdma_dev_addr *dev_addr,
union ib_gid *gid)
{
memcpy(dev_addr->dst_dev_addr + 4, gid, sizeof *gid);
}
#endif /* IB_ADDR_H */
include/rdma/ib_cache.h
+13
View File
@@ -102,4 +102,17 @@ int ib_find_cached_pkey(struct ib_device *device,
u16 pkey,
u16 *index);
/**
* ib_get_cached_lmc - Returns a cached lmc table entry
* @device: The device to query.
* @port_num: The port number of the device to query.
* @lmc: The lmc value for the specified port for that device.
*
* ib_get_cached_lmc() fetches the specified lmc table entry stored in
* the local software cache.
*/
int ib_get_cached_lmc(struct ib_device *device,
u8 port_num,
u8 *lmc);
#endif /* _IB_CACHE_H */
include/rdma/ib_cm.h
+18 -8
View File
@@ -32,7 +32,7 @@
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* $Id: ib_cm.h 2730 2005-06-28 16:43:03Z sean.hefty $
* $Id: ib_cm.h 4311 2005-12-05 18:42:01Z sean.hefty $
*/
#if !defined(IB_CM_H)
#define IB_CM_H
@@ -102,7 +102,8 @@ enum ib_cm_data_size {
IB_CM_APR_INFO_LENGTH = 72,
IB_CM_SIDR_REQ_PRIVATE_DATA_SIZE = 216,
IB_CM_SIDR_REP_PRIVATE_DATA_SIZE = 136,
IB_CM_SIDR_REP_INFO_LENGTH = 72
IB_CM_SIDR_REP_INFO_LENGTH = 72,
IB_CM_COMPARE_SIZE = 64
};
struct ib_cm_id;
@@ -238,7 +239,6 @@ struct ib_cm_sidr_rep_event_param {
u32 qpn;
void *info;
u8 info_len;
};
struct ib_cm_event {
@@ -317,6 +317,15 @@ void ib_destroy_cm_id(struct ib_cm_id *cm_id);
#define IB_SERVICE_ID_AGN_MASK __constant_cpu_to_be64(0xFF00000000000000ULL)
#define IB_CM_ASSIGN_SERVICE_ID __constant_cpu_to_be64(0x0200000000000000ULL)
#define IB_CMA_SERVICE_ID __constant_cpu_to_be64(0x0000000001000000ULL)
#define IB_CMA_SERVICE_ID_MASK __constant_cpu_to_be64(0xFFFFFFFFFF000000ULL)
#define IB_SDP_SERVICE_ID __constant_cpu_to_be64(0x0000000000010000ULL)
#define IB_SDP_SERVICE_ID_MASK __constant_cpu_to_be64(0xFFFFFFFFFFFF0000ULL)
struct ib_cm_compare_data {
u8 data[IB_CM_COMPARE_SIZE];
u8 mask[IB_CM_COMPARE_SIZE];
};
/**
* ib_cm_listen - Initiates listening on the specified service ID for
@@ -330,10 +339,12 @@ void ib_destroy_cm_id(struct ib_cm_id *cm_id);
* range of service IDs. If set to 0, the service ID is matched
* exactly. This parameter is ignored if %service_id is set to
* IB_CM_ASSIGN_SERVICE_ID.
* @compare_data: This parameter is optional. It specifies data that must
* appear in the private data of a connection request for the specified
* listen request.
*/
int ib_cm_listen(struct ib_cm_id *cm_id,
__be64 service_id,
__be64 service_mask);
int ib_cm_listen(struct ib_cm_id *cm_id, __be64 service_id, __be64 service_mask,
struct ib_cm_compare_data *compare_data);
struct ib_cm_req_param {
struct ib_sa_path_rec *primary_path;
@@ -535,7 +546,6 @@ struct ib_cm_sidr_req_param {
const void *private_data;
u8 private_data_len;
u8 max_cm_retries;
u16 pkey;
};
/**
@@ -559,7 +569,7 @@ struct ib_cm_sidr_rep_param {
};
/**
* ib_send_cm_sidr_rep - Sends a service ID resolution request to the
* ib_send_cm_sidr_rep - Sends a service ID resolution reply to the
* remote node.
* @cm_id: Communication identifier associated with the received service ID
* resolution request.
include/rdma/ib_marshall.h
+50
View File
@@ -0,0 +1,50 @@
/*
* Copyright (c) 2005 Intel Corporation. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#if !defined(IB_USER_MARSHALL_H)
#define IB_USER_MARSHALL_H
#include <rdma/ib_verbs.h>
#include <rdma/ib_sa.h>
#include <rdma/ib_user_verbs.h>
#include <rdma/ib_user_sa.h>
void ib_copy_qp_attr_to_user(struct ib_uverbs_qp_attr *dst,
struct ib_qp_attr *src);
void ib_copy_path_rec_to_user(struct ib_user_path_rec *dst,
struct ib_sa_path_rec *src);
void ib_copy_path_rec_from_user(struct ib_sa_path_rec *dst,
struct ib_user_path_rec *src);
#endif /* IB_USER_MARSHALL_H */

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