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Merge branch 'master' into upstream

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This commit is contained in:
Jeff Garzik
2006-05-20 00:03:38 -04:00
parent 753a6c4ff4 2f880b65fd
commit badc48e660
386 changed files with 7459 additions and 3242 deletions
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include/asm-arm/arch-aaec2000/debug-macro.S
+1
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@@ -9,6 +9,7 @@
* published by the Free Software Foundation.
*/
#include "hardware.h"
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ MMU enabled?
include/asm-arm/arch-aaec2000/entry-macro.S
+1
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@@ -10,6 +10,7 @@
* published by the Free Software Foundation.
*
*/
#include <asm/arch/irqs.h>
.macro disable_fiq
.endm
include/asm-arm/arch-imx/debug-macro.S
+1 -1
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@@ -16,7 +16,7 @@
tst \rx, #1 @ MMU enabled?
moveq \rx, #0x00000000 @ physical
movne \rx, #0xe0000000 @ virtual
orr \rx, \rx, #0x00200000
orreq \rx, \rx, #0x00200000 @ physical
orr \rx, \rx, #0x00006000 @ UART1 offset
.endm
include/asm-arm/arch-imx/imx-uart.h
+10
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@@ -0,0 +1,10 @@
#ifndef ASMARM_ARCH_UART_H
#define ASMARM_ARCH_UART_H
#define IMXUART_HAVE_RTSCTS (1<<0)
struct imxuart_platform_data {
unsigned int flags;
};
#endif
include/asm-arm/arch-ixp4xx/io.h
+7
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@@ -260,6 +260,12 @@ out:
#endif
#ifndef CONFIG_PCI
#define __io(v) v
#else
/*
* IXP4xx does not have a transparent cpu -> PCI I/O translation
* window. Instead, it has a set of registers that must be tweaked
@@ -578,6 +584,7 @@ __ixp4xx_iowrite32_rep(void __iomem *addr, const void *vaddr, u32 count)
#define ioport_map(port, nr) ((void __iomem*)(port + PIO_OFFSET))
#define ioport_unmap(addr)
#endif // !CONFIG_PCI
#endif // __ASM_ARM_ARCH_IO_H
include/asm-arm/arch-ixp4xx/memory.h
+1 -1
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@@ -14,7 +14,7 @@
*/
#define PHYS_OFFSET UL(0x00000000)
#ifndef __ASSEMBLY__
#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
void ixp4xx_adjust_zones(int node, unsigned long *size, unsigned long *holes);
include/asm-arm/arch-pxa/dma.h
+14 -12
View File
@@ -24,27 +24,29 @@ typedef struct pxa_dma_desc {
volatile u32 dcmd; /* DCMD value for the current transfer */
} pxa_dma_desc;
typedef enum {
DMA_PRIO_HIGH = 0,
DMA_PRIO_MEDIUM = 1,
DMA_PRIO_LOW = 2
} pxa_dma_prio;
#if defined(CONFIG_PXA27x)
#define PXA_DMA_CHANNELS 32
#define PXA_DMA_NBCH(prio) ((prio == DMA_PRIO_LOW) ? 16 : 8)
typedef enum {
DMA_PRIO_HIGH = 0,
DMA_PRIO_MEDIUM = 8,
DMA_PRIO_LOW = 16
} pxa_dma_prio;
#define pxa_for_each_dma_prio(ch, prio) \
for ( \
ch = prio * 4; \
ch != (4 << prio) + 16; \
ch = (ch + 1 == (4 << prio)) ? (prio * 4 + 16) : (ch + 1) \
)
#elif defined(CONFIG_PXA25x)
#define PXA_DMA_CHANNELS 16
#define PXA_DMA_NBCH(prio) ((prio == DMA_PRIO_LOW) ? 8 : 4)
typedef enum {
DMA_PRIO_HIGH = 0,
DMA_PRIO_MEDIUM = 4,
DMA_PRIO_LOW = 8
} pxa_dma_prio;
#define pxa_for_each_dma_prio(ch, prio) \
for (ch = prio * 4; ch != (4 << prio); ch++)
#endif
include/asm-arm/arch-pxa/pxa2xx_spi.h
+68
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@@ -0,0 +1,68 @@
/*
* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef PXA2XX_SPI_H_
#define PXA2XX_SPI_H_
#define PXA2XX_CS_ASSERT (0x01)
#define PXA2XX_CS_DEASSERT (0x02)
#if defined(CONFIG_PXA25x)
#define CLOCK_SPEED_HZ 3686400
#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/2/(x+1))<<8)&0x0000ff00)
#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#elif defined(CONFIG_PXA27x)
#define CLOCK_SPEED_HZ 13000000
#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
#endif
#define SSP1_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(1)))))
#define SSP2_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(2)))))
#define SSP3_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(3)))))
enum pxa_ssp_type {
SSP_UNDEFINED = 0,
PXA25x_SSP, /* pxa 210, 250, 255, 26x */
PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
PXA27x_SSP,
};
/* device.platform_data for SSP controller devices */
struct pxa2xx_spi_master {
enum pxa_ssp_type ssp_type;
u32 clock_enable;
u16 num_chipselect;
u8 enable_dma;
};
/* spi_board_info.controller_data for SPI slave devices,
* copied to spi_device.platform_data ... mostly for dma tuning
*/
struct pxa2xx_spi_chip {
u8 tx_threshold;
u8 rx_threshold;
u8 dma_burst_size;
u32 timeout_microsecs;
u8 enable_loopback;
void (*cs_control)(u32 command);
};
#endif /*PXA2XX_SPI_H_*/
include/asm-arm/bug.h
+1
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@@ -2,6 +2,7 @@
#define _ASMARM_BUG_H
#include <linux/config.h>
#include <linux/stddef.h>
#ifdef CONFIG_BUG
#ifdef CONFIG_DEBUG_BUGVERBOSE
include/asm-arm/procinfo.h
-2
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@@ -45,8 +45,6 @@ extern unsigned int elf_hwcap;
#endif /* __ASSEMBLY__ */
#define PROC_INFO_SZ 48
#define HWCAP_SWP 1
#define HWCAP_HALF 2
#define HWCAP_THUMB 4
include/asm-arm/spinlock.h
+6
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@@ -142,6 +142,9 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
: "cc");
}
/* write_can_lock - would write_trylock() succeed? */
#define __raw_write_can_lock(x) ((x)->lock == 0x80000000)
/*
* Read locks are a bit more hairy:
* - Exclusively load the lock value.
@@ -198,4 +201,7 @@ static inline void __raw_read_unlock(raw_rwlock_t *rw)
#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
/* read_can_lock - would read_trylock() succeed? */
#define __raw_read_can_lock(x) ((x)->lock < 0x80000000)
#endif /* __ASM_SPINLOCK_H */
include/asm-arm/unistd.h
+15 -8
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@@ -363,7 +363,7 @@
/*
* The following syscalls are obsolete and no longer available for EABI.
*/
#if defined(__ARM_EABI__)
#if defined(__ARM_EABI__) && !defined(__KERNEL__)
#undef __NR_time
#undef __NR_umount
#undef __NR_stime
@@ -410,7 +410,8 @@ type name(void) { \
__asm__ __volatile__ ( \
__syscall(name) \
: "=r" (__res_r0) \
: __SYS_REG_LIST() ); \
: __SYS_REG_LIST() \
: "memory" ); \
__res = __res_r0; \
__syscall_return(type,__res); \
}
@@ -424,7 +425,8 @@ type name(type1 arg1) { \
__asm__ __volatile__ ( \
__syscall(name) \
: "=r" (__res_r0) \
: __SYS_REG_LIST( "0" (__r0) ) ); \
: __SYS_REG_LIST( "0" (__r0) ) \
: "memory" ); \
__res = __res_r0; \
__syscall_return(type,__res); \
}
@@ -439,7 +441,8 @@ type name(type1 arg1,type2 arg2) { \
__asm__ __volatile__ ( \
__syscall(name) \
: "=r" (__res_r0) \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1) ) ); \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1) ) \
: "memory" ); \
__res = __res_r0; \
__syscall_return(type,__res); \
}
@@ -456,7 +459,8 @@ type name(type1 arg1,type2 arg2,type3 arg3) { \
__asm__ __volatile__ ( \
__syscall(name) \
: "=r" (__res_r0) \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2) ) ); \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2) ) \
: "memory" ); \
__res = __res_r0; \
__syscall_return(type,__res); \
}
@@ -474,7 +478,8 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4) { \
__asm__ __volatile__ ( \
__syscall(name) \
: "=r" (__res_r0) \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) ) ); \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2), "r" (__r3) ) \
: "memory" ); \
__res = __res_r0; \
__syscall_return(type,__res); \
}
@@ -494,7 +499,8 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5) { \
__syscall(name) \
: "=r" (__res_r0) \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2), \
"r" (__r3), "r" (__r4) ) ); \
"r" (__r3), "r" (__r4) ) \
: "memory" ); \
__res = __res_r0; \
__syscall_return(type,__res); \
}
@@ -514,7 +520,8 @@ type name(type1 arg1, type2 arg2, type3 arg3, type4 arg4, type5 arg5, type6 arg6
__syscall(name) \
: "=r" (__res_r0) \
: __SYS_REG_LIST( "0" (__r0), "r" (__r1), "r" (__r2), \
"r" (__r3), "r" (__r4), "r" (__r5) ) ); \
"r" (__r3), "r" (__r4), "r" (__r5) ) \
: "memory" ); \
__res = __res_r0; \
__syscall_return(type,__res); \
}
include/asm-i386/io_apic.h
+1
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@@ -200,6 +200,7 @@ extern int io_apic_get_unique_id (int ioapic, int apic_id);
extern int io_apic_get_version (int ioapic);
extern int io_apic_get_redir_entries (int ioapic);
extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low);
extern int timer_uses_ioapic_pin_0;
#endif /* CONFIG_ACPI */
extern int (*ioapic_renumber_irq)(int ioapic, int irq);
include/asm-ia64/bitops.h
-1
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@@ -11,7 +11,6 @@
#include <linux/compiler.h>
#include <linux/types.h>
#include <asm/bitops.h>
#include <asm/intrinsics.h>
/**
include/asm-powerpc/uaccess.h
+13 -6
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@@ -7,6 +7,7 @@
#include <linux/sched.h>
#include <linux/errno.h>
#include <asm/processor.h>
#include <asm/page.h>
#define VERIFY_READ 0
#define VERIFY_WRITE 1
@@ -179,9 +180,11 @@ do { \
#define __put_user_nocheck(x, ptr, size) \
({ \
long __pu_err; \
might_sleep(); \
__typeof__(*(ptr)) __user *__pu_addr = (ptr); \
if (!is_kernel_addr((unsigned long)__pu_addr)) \
might_sleep(); \
__chk_user_ptr(ptr); \
__put_user_size((x), (ptr), (size), __pu_err); \
__put_user_size((x), __pu_addr, (size), __pu_err); \
__pu_err; \
})
@@ -258,9 +261,11 @@ do { \
({ \
long __gu_err; \
unsigned long __gu_val; \
const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
__chk_user_ptr(ptr); \
might_sleep(); \
__get_user_size(__gu_val, (ptr), (size), __gu_err); \
if (!is_kernel_addr((unsigned long)__gu_addr)) \
might_sleep(); \
__get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
(x) = (__typeof__(*(ptr)))__gu_val; \
__gu_err; \
})
@@ -270,9 +275,11 @@ do { \
({ \
long __gu_err; \
long long __gu_val; \
const __typeof__(*(ptr)) __user *__gu_addr = (ptr); \
__chk_user_ptr(ptr); \
might_sleep(); \
__get_user_size(__gu_val, (ptr), (size), __gu_err); \
if (!is_kernel_addr((unsigned long)__gu_addr)) \
might_sleep(); \
__get_user_size(__gu_val, __gu_addr, (size), __gu_err); \
(x) = (__typeof__(*(ptr)))__gu_val; \
__gu_err; \
})
include/asm-ppc/commproc.h
+1
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@@ -35,6 +35,7 @@
#define CPM_CR_INIT_TX ((ushort)0x0002)
#define CPM_CR_HUNT_MODE ((ushort)0x0003)
#define CPM_CR_STOP_TX ((ushort)0x0004)
#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
include/asm-ppc/cpm2.h
+1 -1
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@@ -69,7 +69,7 @@
#define CPM_CR_INIT_TX ((ushort)0x0002)
#define CPM_CR_HUNT_MODE ((ushort)0x0003)
#define CPM_CR_STOP_TX ((ushort)0x0004)
#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
#define CPM_CR_RESTART_TX ((ushort)0x0006)
#define CPM_CR_SET_GADDR ((ushort)0x0008)
#define CPM_CR_START_IDMA ((ushort)0x0009)
include/asm-ppc/page.h
+1
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@@ -20,6 +20,7 @@
/* This must match what is in arch/ppc/Makefile */
#define PAGE_OFFSET CONFIG_KERNEL_START
#define KERNELBASE PAGE_OFFSET
#define is_kernel_addr(x) ((x) >= PAGE_OFFSET)
#ifndef __ASSEMBLY__
include/asm-s390/unistd.h
+7 -1
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@@ -296,8 +296,14 @@
#define __NR_pselect6 301
#define __NR_ppoll 302
#define __NR_unshare 303
#define __NR_set_robust_list 304
#define __NR_get_robust_list 305
#define __NR_splice 306
#define __NR_sync_file_range 307
#define __NR_tee 308
#define __NR_vmsplice 309
#define NR_syscalls 304
#define NR_syscalls 310
/*
* There are some system calls that are not present on 64 bit, some
include/asm-sparc/unistd.h
+1 -1
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@@ -41,7 +41,7 @@
#define __NR_capset 22 /* Linux Specific */
#define __NR_setuid 23 /* Implemented via setreuid in SunOS */
#define __NR_getuid 24 /* Common */
/* #define __NR_time alias 25 ENOSYS under SunOS */
#define __NR_vmsplice 25 /* ENOSYS under SunOS */
#define __NR_ptrace 26 /* Common */
#define __NR_alarm 27 /* Implemented via setitimer in SunOS */
#define __NR_sigaltstack 28 /* Common */
include/asm-sparc64/unistd.h
+1 -1
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@@ -41,7 +41,7 @@
#define __NR_capset 22 /* Linux Specific */
#define __NR_setuid 23 /* Implemented via setreuid in SunOS */
#define __NR_getuid 24 /* Common */
/* #define __NR_time alias 25 ENOSYS under SunOS */
#define __NR_vmsplice 25 /* ENOSYS under SunOS */
#define __NR_ptrace 26 /* Common */
#define __NR_alarm 27 /* Implemented via setitimer in SunOS */
#define __NR_sigaltstack 28 /* Common */
include/asm-x86_64/e820.h
+2
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@@ -59,6 +59,8 @@ extern void __init parse_memopt(char *p, char **end);
extern void __init parse_memmapopt(char *p, char **end);
extern struct e820map e820;
extern unsigned ebda_addr, ebda_size;
#endif/*!__ASSEMBLY__*/
#endif/*__E820_HEADER*/
include/asm-x86_64/io_apic.h
+1
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@@ -205,6 +205,7 @@ extern int skip_ioapic_setup;
extern int io_apic_get_version (int ioapic);
extern int io_apic_get_redir_entries (int ioapic);
extern int io_apic_set_pci_routing (int ioapic, int pin, int irq, int, int);
extern int timer_uses_ioapic_pin_0;
#endif
extern int sis_apic_bug; /* dummy */
include/linux/device.h
+2
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@@ -200,6 +200,7 @@ extern int class_device_create_file(struct class_device *,
* @node: for internal use by the driver core only.
* @kobj: for internal use by the driver core only.
* @devt_attr: for internal use by the driver core only.
* @groups: optional additional groups to be created
* @dev: if set, a symlink to the struct device is created in the sysfs
* directory for this struct class device.
* @class_data: pointer to whatever you want to store here for this struct
@@ -228,6 +229,7 @@ struct class_device {
struct device * dev; /* not necessary, but nice to have */
void * class_data; /* class-specific data */
struct class_device *parent; /* parent of this child device, if there is one */
struct attribute_group ** groups; /* optional groups */
void (*release)(struct class_device *dev);
int (*uevent)(struct class_device *dev, char **envp,
include/linux/dma-mapping.h
+1
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@@ -14,6 +14,7 @@ enum dma_data_direction {
};
#define DMA_64BIT_MASK 0xffffffffffffffffULL
#define DMA_48BIT_MASK 0x0000ffffffffffffULL
#define DMA_40BIT_MASK 0x000000ffffffffffULL
#define DMA_39BIT_MASK 0x0000007fffffffffULL
#define DMA_32BIT_MASK 0x00000000ffffffffULL
include/linux/fs_uart_pd.h
+60
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@@ -0,0 +1,60 @@
/*
* Platform information definitions for the CPM Uart driver.
*
* 2006 (c) MontaVista Software, Inc.
* Vitaly Bordug <vbordug@ru.mvista.com>
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
#ifndef FS_UART_PD_H
#define FS_UART_PD_H
#include <linux/version.h>
#include <asm/types.h>
enum fs_uart_id {
fsid_smc1_uart,
fsid_smc2_uart,
fsid_scc1_uart,
fsid_scc2_uart,
fsid_scc3_uart,
fsid_scc4_uart,
fs_uart_nr,
};
static inline int fs_uart_id_scc2fsid(int id)
{
return fsid_scc1_uart + id - 1;
}
static inline int fs_uart_id_fsid2scc(int id)
{
return id - fsid_scc1_uart + 1;
}
static inline int fs_uart_id_smc2fsid(int id)
{
return fsid_smc1_uart + id - 1;
}
static inline int fs_uart_id_fsid2smc(int id)
{
return id - fsid_smc1_uart + 1;
}
struct fs_uart_platform_info {
void(*init_ioports)(void);
/* device specific information */
int fs_no; /* controller index */
u32 uart_clk;
u8 tx_num_fifo;
u8 tx_buf_size;
u8 rx_num_fifo;
u8 rx_buf_size;
u8 brg;
};
#endif
include/linux/kernel.h
+1
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@@ -124,6 +124,7 @@ extern int get_option(char **str, int *pint);
extern char *get_options(const char *str, int nints, int *ints);
extern unsigned long long memparse(char *ptr, char **retptr);
extern int core_kernel_text(unsigned long addr);
extern int __kernel_text_address(unsigned long addr);
extern int kernel_text_address(unsigned long addr);
extern int session_of_pgrp(int pgrp);
include/linux/mmc/card.h
+1
View File
@@ -28,6 +28,7 @@ struct mmc_csd {
unsigned short cmdclass;
unsigned short tacc_clks;
unsigned int tacc_ns;
unsigned int r2w_factor;
unsigned int max_dtr;
unsigned int read_blkbits;
unsigned int write_blkbits;
include/linux/mmc/mmc.h
+1
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@@ -69,6 +69,7 @@ struct mmc_data {
unsigned int timeout_ns; /* data timeout (in ns, max 80ms) */
unsigned int timeout_clks; /* data timeout (in clocks) */
unsigned int blksz_bits; /* data block size */
unsigned int blksz; /* data block size */
unsigned int blocks; /* number of blocks */
unsigned int error; /* data error */
unsigned int flags;
include/linux/netdevice.h
+11 -12
View File
@@ -433,8 +433,7 @@ struct net_device
/* register/unregister state machine */
enum { NETREG_UNINITIALIZED=0,
NETREG_REGISTERING, /* called register_netdevice */
NETREG_REGISTERED, /* completed register todo */
NETREG_REGISTERED, /* completed register_netdevice */
NETREG_UNREGISTERING, /* called unregister_netdevice */
NETREG_UNREGISTERED, /* completed unregister todo */
NETREG_RELEASED, /* called free_netdev */
@@ -506,6 +505,8 @@ struct net_device
/* class/net/name entry */
struct class_device class_dev;
/* space for optional statistics and wireless sysfs groups */
struct attribute_group *sysfs_groups[3];
};
#define NETDEV_ALIGN 32
@@ -829,21 +830,19 @@ static inline void netif_rx_schedule(struct net_device *dev)
__netif_rx_schedule(dev);
}
static inline void __netif_rx_reschedule(struct net_device *dev, int undo)
{
dev->quota += undo;
list_add_tail(&dev->poll_list, &__get_cpu_var(softnet_data).poll_list);
__raise_softirq_irqoff(NET_RX_SOFTIRQ);
}
/* Try to reschedule poll. Called by dev->poll() after netif_rx_complete(). */
/* Try to reschedule poll. Called by dev->poll() after netif_rx_complete().
* Do not inline this?
*/
static inline int netif_rx_reschedule(struct net_device *dev, int undo)
{
if (netif_rx_schedule_prep(dev)) {
unsigned long flags;
dev->quota += undo;
local_irq_save(flags);
__netif_rx_reschedule(dev, undo);
list_add_tail(&dev->poll_list, &__get_cpu_var(softnet_data).poll_list);
__raise_softirq_irqoff(NET_RX_SOFTIRQ);
local_irq_restore(flags);
return 1;
}
include/linux/netfilter_ipv4/ip_conntrack_helper_h323_asn1.h
+1 -1
View File
@@ -2,7 +2,7 @@
* ip_conntrack_helper_h323_asn1.h - BER and PER decoding library for H.323
* conntrack/NAT module.
*
* Copyright (c) 2006 by Jing Min Zhao <zhaojingmin@hotmail.com>
* Copyright (c) 2006 by Jing Min Zhao <zhaojingmin@users.sourceforge.net>
*
* This source code is licensed under General Public License version 2.
*
include/linux/pipe_fs_i.h
+3 -2
View File
@@ -5,8 +5,9 @@
#define PIPE_BUFFERS (16)
#define PIPE_BUF_FLAG_ATOMIC 0x01 /* was atomically mapped */
#define PIPE_BUF_FLAG_GIFT 0x02 /* page is a gift */
#define PIPE_BUF_FLAG_LRU 0x01 /* page is on the LRU */
#define PIPE_BUF_FLAG_ATOMIC 0x02 /* was atomically mapped */
#define PIPE_BUF_FLAG_GIFT 0x04 /* page is a gift */
struct pipe_buffer {
struct page *page;
include/linux/rcupdate.h
+1
View File
@@ -132,6 +132,7 @@ static inline void rcu_bh_qsctr_inc(int cpu)
}
extern int rcu_pending(int cpu);
extern int rcu_needs_cpu(int cpu);
/**
* rcu_read_lock - mark the beginning of an RCU read-side critical section.
include/linux/serial_core.h
+1
View File
@@ -254,6 +254,7 @@ struct uart_port {
#define UPF_CONS_FLOW ((__force upf_t) (1 << 23))
#define UPF_SHARE_IRQ ((__force upf_t) (1 << 24))
#define UPF_BOOT_AUTOCONF ((__force upf_t) (1 << 28))
#define UPF_DEAD ((__force upf_t) (1 << 30))
#define UPF_IOREMAP ((__force upf_t) (1 << 31))
#define UPF_CHANGE_MASK ((__force upf_t) (0x17fff))
include/linux/slab.h
+1
View File
@@ -150,6 +150,7 @@ static inline void *kcalloc(size_t n, size_t size, gfp_t flags)
extern void kfree(const void *);
extern unsigned int ksize(const void *);
extern int slab_is_available(void);
#ifdef CONFIG_NUMA
extern void *kmem_cache_alloc_node(kmem_cache_t *, gfp_t flags, int node);
include/linux/spi/spi.h
+28 -17
View File
@@ -31,18 +31,23 @@ extern struct bus_type spi_bus_type;
* @master: SPI controller used with the device.
* @max_speed_hz: Maximum clock rate to be used with this chip
* (on this board); may be changed by the device's driver.
* The spi_transfer.speed_hz can override this for each transfer.
* @chip-select: Chipselect, distinguishing chips handled by "master".
* @mode: The spi mode defines how data is clocked out and in.
* This may be changed by the device's driver.
* The "active low" default for chipselect mode can be overridden,
* as can the "MSB first" default for each word in a transfer.
* @bits_per_word: Data transfers involve one or more words; word sizes
* like eight or 12 bits are common. In-memory wordsizes are
* like eight or 12 bits are common. In-memory wordsizes are
* powers of two bytes (e.g. 20 bit samples use 32 bits).
* This may be changed by the device's driver.
* This may be changed by the device's driver, or left at the
* default (0) indicating protocol words are eight bit bytes.
* The spi_transfer.bits_per_word can override this for each transfer.
* @irq: Negative, or the number passed to request_irq() to receive
* interrupts from this device.
* interrupts from this device.
* @controller_state: Controller's runtime state
* @controller_data: Board-specific definitions for controller, such as
* FIFO initialization parameters; from board_info.controller_data
* FIFO initialization parameters; from board_info.controller_data
*
* An spi_device is used to interchange data between an SPI slave
* (usually a discrete chip) and CPU memory.
@@ -65,6 +70,7 @@ struct spi_device {
#define SPI_MODE_2 (SPI_CPOL|0)
#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA)
#define SPI_CS_HIGH 0x04 /* chipselect active high? */
#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */
u8 bits_per_word;
int irq;
void *controller_state;
@@ -73,7 +79,6 @@ struct spi_device {
// likely need more hooks for more protocol options affecting how
// the controller talks to each chip, like:
// - bit order (default is wordwise msb-first)
// - memory packing (12 bit samples into low bits, others zeroed)
// - priority
// - drop chipselect after each word
@@ -143,13 +148,13 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
* struct spi_master - interface to SPI master controller
* @cdev: class interface to this driver
* @bus_num: board-specific (and often SOC-specific) identifier for a
* given SPI controller.
* given SPI controller.
* @num_chipselect: chipselects are used to distinguish individual
* SPI slaves, and are numbered from zero to num_chipselects.
* each slave has a chipselect signal, but it's common that not
* every chipselect is connected to a slave.
* SPI slaves, and are numbered from zero to num_chipselects.
* each slave has a chipselect signal, but it's common that not
* every chipselect is connected to a slave.
* @setup: updates the device mode and clocking records used by a
* device's SPI controller; protocol code may call this.
* device's SPI controller; protocol code may call this.
* @transfer: adds a message to the controller's transfer queue.
* @cleanup: frees controller-specific state
*
@@ -167,13 +172,13 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
struct spi_master {
struct class_device cdev;
/* other than zero (== assign one dynamically), bus_num is fully
/* other than negative (== assign one dynamically), bus_num is fully
* board-specific. usually that simplifies to being SOC-specific.
* example: one SOC has three SPI controllers, numbered 1..3,
* example: one SOC has three SPI controllers, numbered 0..2,
* and one board's schematics might show it using SPI-2. software
* would normally use bus_num=2 for that controller.
*/
u16 bus_num;
s16 bus_num;
/* chipselects will be integral to many controllers; some others
* might use board-specific GPIOs.
@@ -268,10 +273,14 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
* @tx_dma: DMA address of tx_buf, if spi_message.is_dma_mapped
* @rx_dma: DMA address of rx_buf, if spi_message.is_dma_mapped
* @len: size of rx and tx buffers (in bytes)
* @speed_hz: Select a speed other then the device default for this
* transfer. If 0 the default (from spi_device) is used.
* @bits_per_word: select a bits_per_word other then the device default
* for this transfer. If 0 the default (from spi_device) is used.
* @cs_change: affects chipselect after this transfer completes
* @delay_usecs: microseconds to delay after this transfer before
* (optionally) changing the chipselect status, then starting
* the next transfer or completing this spi_message.
* (optionally) changing the chipselect status, then starting
* the next transfer or completing this spi_message.
* @transfer_list: transfers are sequenced through spi_message.transfers
*
* SPI transfers always write the same number of bytes as they read.
@@ -322,7 +331,9 @@ struct spi_transfer {
dma_addr_t rx_dma;
unsigned cs_change:1;
u8 bits_per_word;
u16 delay_usecs;
u32 speed_hz;
struct list_head transfer_list;
};
@@ -356,7 +367,7 @@ struct spi_transfer {
* and its transfers, ignore them until its completion callback.
*/
struct spi_message {
struct list_head transfers;
struct list_head transfers;
struct spi_device *spi;
@@ -374,7 +385,7 @@ struct spi_message {
*/
/* completion is reported through a callback */
void (*complete)(void *context);
void (*complete)(void *context);
void *context;
unsigned actual_length;
int status;
include/linux/spi/spi_bitbang.h
+8
View File
@@ -30,6 +30,12 @@ struct spi_bitbang {
struct spi_master *master;
/* setup_transfer() changes clock and/or wordsize to match settings
* for this transfer; zeroes restore defaults from spi_device.
*/
int (*setup_transfer)(struct spi_device *spi,
struct spi_transfer *t);
void (*chipselect)(struct spi_device *spi, int is_on);
#define BITBANG_CS_ACTIVE 1 /* normally nCS, active low */
#define BITBANG_CS_INACTIVE 0
@@ -51,6 +57,8 @@ struct spi_bitbang {
extern int spi_bitbang_setup(struct spi_device *spi);
extern void spi_bitbang_cleanup(const struct spi_device *spi);
extern int spi_bitbang_transfer(struct spi_device *spi, struct spi_message *m);
extern int spi_bitbang_setup_transfer(struct spi_device *spi,
struct spi_transfer *t);
/* start or stop queue processing */
extern int spi_bitbang_start(struct spi_bitbang *spi);
include/linux/swap.h
+1 -1
View File
@@ -296,7 +296,7 @@ static inline void disable_swap_token(void)
#define read_swap_cache_async(swp,vma,addr) NULL
#define lookup_swap_cache(swp) NULL
#define valid_swaphandles(swp, off) 0
#define can_share_swap_page(p) 0
#define can_share_swap_page(p) (page_mapcount(p) == 1)
#define move_to_swap_cache(p, swp) 1
#define move_from_swap_cache(p, i, m) 1
#define __delete_from_swap_cache(p) /*NOTHING*/
include/net/ax25.h
+5 -5
View File
@@ -145,14 +145,14 @@ enum {
#define AX25_DEF_CONMODE 2 /* Connected mode allowed */
#define AX25_DEF_WINDOW 2 /* Window=2 */
#define AX25_DEF_EWINDOW 32 /* Module-128 Window=32 */
#define AX25_DEF_T1 (10 * HZ) /* T1=10s */
#define AX25_DEF_T2 (3 * HZ) /* T2=3s */
#define AX25_DEF_T3 (300 * HZ) /* T3=300s */
#define AX25_DEF_T1 10000 /* T1=10s */
#define AX25_DEF_T2 3000 /* T2=3s */
#define AX25_DEF_T3 300000 /* T3=300s */
#define AX25_DEF_N2 10 /* N2=10 */
#define AX25_DEF_IDLE (0 * 60 * HZ) /* Idle=None */
#define AX25_DEF_IDLE 0 /* Idle=None */
#define AX25_DEF_PACLEN 256 /* Paclen=256 */
#define AX25_DEF_PROTOCOL AX25_PROTO_STD_SIMPLEX /* Standard AX.25 */
#define AX25_DEF_DS_TIMEOUT (3 * 60 * HZ) /* DAMA timeout 3 minutes */
#define AX25_DEF_DS_TIMEOUT 180000 /* DAMA timeout 3 minutes */
typedef struct ax25_uid_assoc {
struct hlist_node uid_node;
include/net/ieee80211.h
+4 -2
View File
@@ -958,11 +958,13 @@ enum ieee80211_state {
#define IEEE80211_24GHZ_MIN_CHANNEL 1
#define IEEE80211_24GHZ_MAX_CHANNEL 14
#define IEEE80211_24GHZ_CHANNELS 14
#define IEEE80211_24GHZ_CHANNELS (IEEE80211_24GHZ_MAX_CHANNEL - \
IEEE80211_24GHZ_MIN_CHANNEL + 1)
#define IEEE80211_52GHZ_MIN_CHANNEL 34
#define IEEE80211_52GHZ_MAX_CHANNEL 165
#define IEEE80211_52GHZ_CHANNELS 131
#define IEEE80211_52GHZ_CHANNELS (IEEE80211_52GHZ_MAX_CHANNEL - \
IEEE80211_52GHZ_MIN_CHANNEL + 1)
enum {
IEEE80211_CH_PASSIVE_ONLY = (1 << 0),
include/net/ieee80211softmac.h
+2 -1
View File
@@ -204,7 +204,8 @@ struct ieee80211softmac_device {
/* couple of flags */
u8 scanning:1, /* protects scanning from being done multiple times at once */
associated:1;
associated:1,
running:1;
struct ieee80211softmac_scaninfo *scaninfo;
struct ieee80211softmac_assoc_info associnfo;
include/net/neighbour.h
+1
View File
@@ -211,6 +211,7 @@ struct neigh_table
#define NEIGH_UPDATE_F_ADMIN 0x80000000
extern void neigh_table_init(struct neigh_table *tbl);
extern void neigh_table_init_no_netlink(struct neigh_table *tbl);
extern int neigh_table_clear(struct neigh_table *tbl);
extern struct neighbour * neigh_lookup(struct neigh_table *tbl,
const void *pkey,
include/net/netrom.h
+4 -4
View File
@@ -42,11 +42,11 @@ enum {
#define NR_COND_PEER_RX_BUSY 0x04
#define NR_COND_OWN_RX_BUSY 0x08
#define NR_DEFAULT_T1 (120 * HZ) /* Outstanding frames - 120 seconds */
#define NR_DEFAULT_T2 (5 * HZ) /* Response delay - 5 seconds */
#define NR_DEFAULT_T1 120000 /* Outstanding frames - 120 seconds */
#define NR_DEFAULT_T2 5000 /* Response delay - 5 seconds */
#define NR_DEFAULT_N2 3 /* Number of Retries - 3 */
#define NR_DEFAULT_T4 (180 * HZ) /* Busy Delay - 180 seconds */
#define NR_DEFAULT_IDLE (0 * 60 * HZ) /* No Activity Timeout - none */
#define NR_DEFAULT_T4 180000 /* Busy Delay - 180 seconds */
#define NR_DEFAULT_IDLE 0 /* No Activity Timeout - none */
#define NR_DEFAULT_WINDOW 4 /* Default Window Size - 4 */
#define NR_DEFAULT_OBS 6 /* Default Obsolescence Count - 6 */
#define NR_DEFAULT_QUAL 10 /* Default Neighbour Quality - 10 */
include/net/rose.h
+7 -7
View File
@@ -49,14 +49,14 @@ enum {
ROSE_STATE_5 /* Deferred Call Acceptance */
};
#define ROSE_DEFAULT_T0 (180 * HZ) /* Default T10 T20 value */
#define ROSE_DEFAULT_T1 (200 * HZ) /* Default T11 T21 value */
#define ROSE_DEFAULT_T2 (180 * HZ) /* Default T12 T22 value */
#define ROSE_DEFAULT_T3 (180 * HZ) /* Default T13 T23 value */
#define ROSE_DEFAULT_HB (5 * HZ) /* Default Holdback value */
#define ROSE_DEFAULT_IDLE (0 * 60 * HZ) /* No Activity Timeout - none */
#define ROSE_DEFAULT_T0 180000 /* Default T10 T20 value */
#define ROSE_DEFAULT_T1 200000 /* Default T11 T21 value */
#define ROSE_DEFAULT_T2 180000 /* Default T12 T22 value */
#define ROSE_DEFAULT_T3 180000 /* Default T13 T23 value */
#define ROSE_DEFAULT_HB 5000 /* Default Holdback value */
#define ROSE_DEFAULT_IDLE 0 /* No Activity Timeout - none */
#define ROSE_DEFAULT_ROUTING 1 /* Default routing flag */
#define ROSE_DEFAULT_FAIL_TIMEOUT (120 * HZ) /* Time until link considered usable */
#define ROSE_DEFAULT_FAIL_TIMEOUT 120000 /* Time until link considered usable */
#define ROSE_DEFAULT_MAXVC 50 /* Maximum number of VCs per neighbour */
#define ROSE_DEFAULT_WINDOW_SIZE 7 /* Default window size */
include/net/sctp/command.h
+1
View File
@@ -99,6 +99,7 @@ typedef enum {
SCTP_CMD_DEL_NON_PRIMARY, /* Removes non-primary peer transports. */
SCTP_CMD_T3_RTX_TIMERS_STOP, /* Stops T3-rtx pending timers */
SCTP_CMD_FORCE_PRIM_RETRAN, /* Forces retrans. over primary path. */
SCTP_CMD_SET_SK_ERR, /* Set sk_err */
SCTP_CMD_LAST
} sctp_verb_t;
include/net/sctp/sctp.h
+3 -3
View File
@@ -461,12 +461,12 @@ static inline int sctp_frag_point(const struct sctp_sock *sp, int pmtu)
* there is room for a param header too.
*/
#define sctp_walk_params(pos, chunk, member)\
_sctp_walk_params((pos), (chunk), WORD_ROUND(ntohs((chunk)->chunk_hdr.length)), member)
_sctp_walk_params((pos), (chunk), ntohs((chunk)->chunk_hdr.length), member)
#define _sctp_walk_params(pos, chunk, end, member)\
for (pos.v = chunk->member;\
pos.v <= (void *)chunk + end - sizeof(sctp_paramhdr_t) &&\
pos.v <= (void *)chunk + end - WORD_ROUND(ntohs(pos.p->length)) &&\
pos.v <= (void *)chunk + end - ntohs(pos.p->length) &&\
ntohs(pos.p->length) >= sizeof(sctp_paramhdr_t);\
pos.v += WORD_ROUND(ntohs(pos.p->length)))
@@ -477,7 +477,7 @@ _sctp_walk_errors((err), (chunk_hdr), ntohs((chunk_hdr)->length))
for (err = (sctp_errhdr_t *)((void *)chunk_hdr + \
sizeof(sctp_chunkhdr_t));\
(void *)err <= (void *)chunk_hdr + end - sizeof(sctp_errhdr_t) &&\
(void *)err <= (void *)chunk_hdr + end - WORD_ROUND(ntohs(err->length)) &&\
(void *)err <= (void *)chunk_hdr + end - ntohs(err->length) &&\
ntohs(err->length) >= sizeof(sctp_errhdr_t); \
err = (sctp_errhdr_t *)((void *)err + WORD_ROUND(ntohs(err->length))))
include/net/sctp/structs.h
+1
View File
@@ -712,6 +712,7 @@ struct sctp_chunk {
__u8 tsn_gap_acked; /* Is this chunk acked by a GAP ACK? */
__s8 fast_retransmit; /* Is this chunk fast retransmitted? */
__u8 tsn_missing_report; /* Data chunk missing counter. */
__u8 data_accepted; /* At least 1 chunk in this packet accepted */
};
void sctp_chunk_hold(struct sctp_chunk *);
include/scsi/srp.h
+17 -6
View File
@@ -95,14 +95,15 @@ struct srp_direct_buf {
/*
* We need the packed attribute because the SRP spec puts the list of
* descriptors at an offset of 20, which is not aligned to the size
* of struct srp_direct_buf.
* descriptors at an offset of 20, which is not aligned to the size of
* struct srp_direct_buf. The whole structure must be packed to avoid
* having the 20-byte structure padded to 24 bytes on 64-bit architectures.
*/
struct srp_indirect_buf {
struct srp_direct_buf table_desc;
__be32 len;
struct srp_direct_buf desc_list[0] __attribute__((packed));
};
struct srp_direct_buf desc_list[0];
} __attribute__((packed));
enum {
SRP_MULTICHAN_SINGLE = 0,
@@ -122,6 +123,11 @@ struct srp_login_req {
u8 target_port_id[16];
};
/*
* The SRP spec defines the size of the LOGIN_RSP structure to be 52
* bytes, so it needs to be packed to avoid having it padded to 56
* bytes on 64-bit architectures.
*/
struct srp_login_rsp {
u8 opcode;
u8 reserved1[3];
@@ -132,7 +138,7 @@ struct srp_login_rsp {
__be16 buf_fmt;
u8 rsp_flags;
u8 reserved2[25];
};
} __attribute__((packed));
struct srp_login_rej {
u8 opcode;
@@ -207,6 +213,11 @@ enum {
SRP_RSP_FLAG_DIUNDER = 1 << 5
};
/*
* The SRP spec defines the size of the RSP structure to be 36 bytes,
* so it needs to be packed to avoid having it padded to 40 bytes on
* 64-bit architectures.
*/
struct srp_rsp {
u8 opcode;
u8 sol_not;
@@ -221,6 +232,6 @@ struct srp_rsp {
__be32 sense_data_len;
__be32 resp_data_len;
u8 data[0];
};
} __attribute__((packed));
#endif /* SCSI_SRP_H */