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Merge tag 'mips_6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

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Pull MIPS updates from Thomas Bogendoerfer:

 - add support for TP-Link HC220 G5 v1

 - add support for Wifi/Bluetooth on CI20

 - rework Ralink clock and reset handling

 - cleanups and fixes

* tag 'mips_6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (58 commits)
  MIPS: Loongson64: DTS: Add RTC support to Loongson-2K1000
  MIPS: Loongson64: DTS: Add RTC support to LS7A PCH
  MIPS: OCTEON: octeon-usb: cleanup divider calculation
  MIPS: OCTEON: octeon-usb: introduce dwc3_octeon_{read,write}q
  MIPS: OCTEON: octeon-usb: move gpio config to separate function
  MIPS: OCTEON: octeon-usb: use bitfields for shim register
  MIPS: OCTEON: octeon-usb: use bitfields for host config register
  MIPS: OCTEON: octeon-usb: use bitfields for control register
  MIPS: OCTEON: octeon-usb: add all register offsets
  mips: ralink: match all supported system controller compatible strings
  MIPS: dec: prom: Address -Warray-bounds warning
  MIPS: DTS: CI20: Raise VDDCORE voltage to 1.125 volts
  clk: ralink: mtmips: Fix uninitialized use of ret in mtmips_register_{fixed,factor}_clocks()
  mips: ralink: introduce commonly used remap node function
  mips: pci-mt7620: use dev_info() to log PCIe device detection result
  mips: pci-mt7620: do not print NFTS register value as error log
  MAINTAINERS: add Mediatek MTMIPS Clock maintainer
  mips: ralink: get cpu rate from new driver code
  mips: ralink: remove reset related code
  mips: ralink: mt7620: remove clock related code
  ...
This commit is contained in:
Linus Torvalds
2023-06-29 15:01:51 -07:00
parent 18f38fedfa e47084e116
commit b775d6c585
56 changed files with 2092 additions and 1136 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/mips/include/uapi/asm/inst.h
+33
View File
@@ -272,6 +272,27 @@ enum lx_func {
lbx_op = 0x16,
};
/*
* func field for special2 MXU opcodes (Ingenic XBurst MXU).
*/
enum mxu_func {
/* TODO, other MXU funcs */
mxu_lx_op = 0x28,
};
/*
* op field for special2 MXU LX opcodes (Ingenic XBurst MXU).
*/
enum lx_ingenic_func {
mxu_lxb_op,
mxu_lxh_op,
/* reserved */
mxu_lxw_op = 3,
mxu_lxbu_op,
mxu_lxhu_op,
/* more reserved */
};
/*
* BSHFL opcodes
*/
@@ -774,6 +795,17 @@ struct dsp_format { /* SPEC3 DSP format instructions */
;))))))
};
struct mxu_lx_format { /* SPEC2 MXU LX format instructions */
__BITFIELD_FIELD(unsigned int opcode : 6,
__BITFIELD_FIELD(unsigned int rs : 5,
__BITFIELD_FIELD(unsigned int rt : 5,
__BITFIELD_FIELD(unsigned int rd : 5,
__BITFIELD_FIELD(unsigned int strd : 2,
__BITFIELD_FIELD(unsigned int op : 3,
__BITFIELD_FIELD(unsigned int func : 6,
;)))))))
};
struct spec3_format { /* SPEC3 */
__BITFIELD_FIELD(unsigned int opcode:6,
__BITFIELD_FIELD(unsigned int rs:5,
@@ -1125,6 +1157,7 @@ union mips_instruction {
struct loongson3_lswc2_format loongson3_lswc2_format;
struct loongson3_lsdc2_format loongson3_lsdc2_format;
struct loongson3_lscsr_format loongson3_lscsr_format;
struct mxu_lx_format mxu_lx_format;
};
union mips16e_instruction {