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merge by hand - fix up rejections in Documentation/DocBook/Makefile

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This commit is contained in:
James Bottomley
2005-05-20 15:27:44 -05:00
parent 90356ac319 88d7bd8cb9
commit ad34ea2cc3
1282 changed files with 32304 additions and 15748 deletions
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include/asm-alpha/bug.h
+3
View File
@@ -1,6 +1,7 @@
#ifndef _ALPHA_BUG_H
#define _ALPHA_BUG_H
#ifdef CONFIG_BUG
#include <asm/pal.h>
/* ??? Would be nice to use .gprel32 here, but we can't be sure that the
@@ -10,6 +11,8 @@
: : "i" (PAL_bugchk), "i"(__LINE__), "i"(__FILE__))
#define HAVE_ARCH_BUG
#endif
#include <asm-generic/bug.h>
#endif
include/asm-alpha/errno.h
+4
View File
@@ -116,4 +116,8 @@
#define EKEYREVOKED 134 /* Key has been revoked */
#define EKEYREJECTED 135 /* Key was rejected by service */
/* for robust mutexes */
#define EOWNERDEAD 136 /* Owner died */
#define ENOTRECOVERABLE 137 /* State not recoverable */
#endif
include/asm-alpha/siginfo.h
-2
View File
@@ -4,8 +4,6 @@
#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
#define __ARCH_SI_TRAPNO
#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 4)
#include <asm-generic/siginfo.h>
#endif
include/asm-alpha/signal.h
+1 -24
View File
@@ -109,34 +109,11 @@ typedef unsigned long sigset_t;
#define MINSIGSTKSZ 4096
#define SIGSTKSZ 16384
#ifdef __KERNEL__
/*
* These values of sa_flags are used only by the kernel as part of the
* irq handling routines.
*
* SA_INTERRUPT is also used by the irq handling routines.
* SA_SHIRQ is for shared interrupt support on PCI and EISA.
*/
#define SA_PROBE SA_ONESHOT
#define SA_SAMPLE_RANDOM SA_RESTART
#define SA_SHIRQ 0x40000000
#endif
#define SIG_BLOCK 1 /* for blocking signals */
#define SIG_UNBLOCK 2 /* for unblocking signals */
#define SIG_SETMASK 3 /* for setting the signal mask */
/* Type of a signal handler. */
typedef void __signalfn_t(int);
typedef __signalfn_t __user *__sighandler_t;
typedef void __restorefn_t(void);
typedef __restorefn_t __user *__sigrestore_t;
#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
#include <asm-generic/signal.h>
#ifdef __KERNEL__
struct osf_sigaction {
include/asm-arm/arch-cl7500/vmalloc.h
-11
View File
@@ -1,15 +1,4 @@
/*
* linux/include/asm-arm/arch-cl7500/vmalloc.h
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_END (PAGE_OFFSET + 0x1c000000)
include/asm-arm/arch-clps711x/vmalloc.h
-11
View File
@@ -17,15 +17,4 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
include/asm-arm/arch-ebsa110/vmalloc.h
-11
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@@ -7,15 +7,4 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_END (PAGE_OFFSET + 0x1f000000)
include/asm-arm/arch-ebsa285/vmalloc.h
-11
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@@ -8,17 +8,6 @@
#include <linux/config.h>
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#ifdef CONFIG_ARCH_FOOTBRIDGE
#define VMALLOC_END (PAGE_OFFSET + 0x30000000)
#else
include/asm-arm/arch-epxa10db/vmalloc.h
-11
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@@ -17,15 +17,4 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
include/asm-arm/arch-h720x/vmalloc.h
-11
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@@ -5,17 +5,6 @@
#ifndef __ARCH_ARM_VMALLOC_H
#define __ARCH_ARM_VMALLOC_H
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
#endif
include/asm-arm/arch-imx/imxfb.h
+35
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@@ -0,0 +1,35 @@
/*
* This structure describes the machine which we are running on.
*/
struct imxfb_mach_info {
u_long pixclock;
u_short xres;
u_short yres;
u_char bpp;
u_char hsync_len;
u_char left_margin;
u_char right_margin;
u_char vsync_len;
u_char upper_margin;
u_char lower_margin;
u_char sync;
u_int cmap_greyscale:1,
cmap_inverse:1,
cmap_static:1,
unused:29;
u_int pcr;
u_int pwmr;
u_int lscr1;
u_char * fixed_screen_cpu;
dma_addr_t fixed_screen_dma;
void (*lcd_power)(int);
void (*backlight_power)(int);
};
void set_imx_fb_info(struct imxfb_mach_info *hard_imx_fb_info);
include/asm-arm/arch-imx/vmalloc.h
-12
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@@ -17,16 +17,4 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
include/asm-arm/arch-integrator/cm.h
+3 -3
View File
@@ -24,9 +24,9 @@ void cm_control(u32, u32);
#define CM_CTRL_LCDBIASDN (1 << 10)
#define CM_CTRL_LCDMUXSEL_MASK (7 << 11)
#define CM_CTRL_LCDMUXSEL_GENLCD (1 << 11)
#define CM_CTRL_LCDMUXSEL_SHARPLCD1 (3 << 11)
#define CM_CTRL_LCDMUXSEL_SHARPLCD2 (4 << 11)
#define CM_CTRL_LCDMUXSEL_VGA (7 << 11)
#define CM_CTRL_LCDMUXSEL_VGA_16BPP (2 << 11)
#define CM_CTRL_LCDMUXSEL_SHARPLCD (3 << 11)
#define CM_CTRL_LCDMUXSEL_VGA_8421BPP (4 << 11)
#define CM_CTRL_LCDEN0 (1 << 14)
#define CM_CTRL_LCDEN1 (1 << 15)
#define CM_CTRL_STATIC1 (1 << 16)
include/asm-arm/arch-integrator/platform.h
+54 -54
View File
@@ -20,14 +20,14 @@
* * Copyright © ARM Limited 1998. All rights reserved.
* ***********************************************************************/
/* ************************************************************************
*
*
* Integrator address map
*
*
* NOTE: This is a multi-hosted header file for use with uHAL and
* supported debuggers.
*
*
* $Id: platform.s,v 1.32 2000/02/18 10:51:39 asims Exp $
*
*
* ***********************************************************************/
#ifndef __address_h
@@ -40,22 +40,22 @@
* Memory definitions
* ------------------------------------------------------------------------
* Integrator memory map
*
*
*/
#define INTEGRATOR_BOOT_ROM_LO 0x00000000
#define INTEGRATOR_BOOT_ROM_HI 0x20000000
#define INTEGRATOR_BOOT_ROM_BASE INTEGRATOR_BOOT_ROM_HI /* Normal position */
#define INTEGRATOR_BOOT_ROM_SIZE SZ_512K
/*
/*
* New Core Modules have different amounts of SSRAM, the amount of SSRAM
* fitted can be found in HDR_STAT.
*
*
* The symbol INTEGRATOR_SSRAM_SIZE is kept, however this now refers to
* the minimum amount of SSRAM fitted on any core module.
*
*
* New Core Modules also alias the SSRAM.
*
*
*/
#define INTEGRATOR_SSRAM_BASE 0x00000000
#define INTEGRATOR_SSRAM_ALIAS_BASE 0x10800000
@@ -67,9 +67,9 @@
#define INTEGRATOR_MBRD_SSRAM_BASE 0x28000000
#define INTEGRATOR_MBRD_SSRAM_SIZE SZ_512K
/*
/*
* SDRAM is a SIMM therefore the size is not known.
*
*
*/
#define INTEGRATOR_SDRAM_BASE 0x00040000
@@ -79,9 +79,9 @@
#define INTEGRATOR_HDR2_SDRAM_BASE 0xA0000000
#define INTEGRATOR_HDR3_SDRAM_BASE 0xB0000000
/*
/*
* Logic expansion modules
*
*
*/
#define INTEGRATOR_LOGIC_MODULES_BASE 0xC0000000
#define INTEGRATOR_LOGIC_MODULE0_BASE 0xC0000000
@@ -92,7 +92,7 @@
/* ------------------------------------------------------------------------
* Integrator header card registers
* ------------------------------------------------------------------------
*
*
*/
#define INTEGRATOR_HDR_ID_OFFSET 0x00
#define INTEGRATOR_HDR_PROC_OFFSET 0x04
@@ -185,12 +185,12 @@
/* ------------------------------------------------------------------------
* Integrator system registers
* ------------------------------------------------------------------------
*
*
*/
/*
/*
* System Controller
*
*
*/
#define INTEGRATOR_SC_ID_OFFSET 0x00
#define INTEGRATOR_SC_OSC_OFFSET 0x04
@@ -230,11 +230,11 @@
#define INTEGRATOR_SC_CTRL_URTS1 (1 << 6)
#define INTEGRATOR_SC_CTRL_UDTR1 (1 << 7)
/*
/*
* External Bus Interface
*
*
*/
#define INTEGRATOR_EBI_BASE 0x12000000
#define INTEGRATOR_EBI_BASE 0x12000000
#define INTEGRATOR_EBI_CSR0_OFFSET 0x00
#define INTEGRATOR_EBI_CSR1_OFFSET 0x04
@@ -279,9 +279,9 @@
#define INTEGRATOR_KBD_BASE 0x18000000 /* Keyboard */
#define INTEGRATOR_MOUSE_BASE 0x19000000 /* Mouse */
/*
/*
* LED's & Switches
*
*
*/
#define INTEGRATOR_DBG_ALPHA_OFFSET 0x00
#define INTEGRATOR_DBG_LEDS_OFFSET 0x04
@@ -300,7 +300,7 @@
* ------------------------------------------------------------------------
*/
/* PS2 Keyboard interface */
#define KMI0_BASE INTEGRATOR_KBD_BASE
#define KMI0_BASE INTEGRATOR_KBD_BASE
/* PS2 Mouse interface */
#define KMI1_BASE INTEGRATOR_MOUSE_BASE
@@ -313,7 +313,7 @@
* This represents a fairly liberal usage of address space. Even though
* the V3 only has two windows (therefore we need to map stuff on the fly),
* we maintain the same addresses, even if they're not mapped.
*
*
*/
#define PHYS_PCI_MEM_BASE 0x40000000 /* 512M to xxx */
/* unused 256M from A0000000-AFFFFFFF might be used for I2O ???
@@ -326,7 +326,7 @@
*/
#define PHYS_PCI_V3_BASE 0x62000000
#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE
#define PCI_DRAMSIZE INTEGRATOR_SSRAM_SIZE
/* 'export' these to UHAL */
#define UHAL_PCI_IO PCI_IO_BASE
@@ -334,7 +334,7 @@
#define UHAL_PCI_ALLOC_IO_BASE 0x00004000
#define UHAL_PCI_ALLOC_MEM_BASE PCI_MEM_BASE
#define UHAL_PCI_MAX_SLOT 20
/* ========================================================================
* Start of uHAL definitions
* ========================================================================
@@ -343,17 +343,17 @@
/* ------------------------------------------------------------------------
* Integrator Interrupt Controllers
* ------------------------------------------------------------------------
*
* Offsets from interrupt controller base
*
*
* Offsets from interrupt controller base
*
* System Controller interrupt controller base is
*
*
* INTEGRATOR_IC_BASE + (header_number << 6)
*
*
* Core Module interrupt controller base is
*
* INTEGRATOR_HDR_IC
*
*
* INTEGRATOR_HDR_IC
*
*/
#define IRQ_STATUS 0
#define IRQ_RAW_STATUS 0x04
@@ -374,22 +374,22 @@
/* ------------------------------------------------------------------------
* Interrupts
* ------------------------------------------------------------------------
*
*
*
*
* Each Core Module has two interrupts controllers, one on the core module
* itself and one in the system controller on the motherboard. The
* READ_INT macro in target.s reads both interrupt controllers and returns
* a 32 bit bitmask, bits 0 to 23 are interrupts from the system controller
* and bits 24 to 31 are from the core module.
*
*
* The following definitions relate to the bitmask returned by READ_INT.
*
*
*/
/* ------------------------------------------------------------------------
* LED's - The header LED is not accessible via the uHAL API
* ------------------------------------------------------------------------
*
*
*/
#define GREEN_LED 0x01
#define YELLOW_LED 0x02
@@ -399,44 +399,44 @@
#define LED_BANK INTEGRATOR_DBG_LEDS
/*
/*
* Memory definitions - run uHAL out of SSRAM.
*
*
*/
#define uHAL_MEMORY_SIZE INTEGRATOR_SSRAM_SIZE
/*
/*
* Application Flash
*
*
*/
#define FLASH_BASE INTEGRATOR_FLASH_BASE
#define FLASH_SIZE INTEGRATOR_FLASH_SIZE
#define FLASH_END (FLASH_BASE + FLASH_SIZE - 1)
#define FLASH_BLOCK_SIZE SZ_128K
/*
/*
* Boot Flash
*
*
*/
#define EPROM_BASE INTEGRATOR_BOOT_ROM_HI
#define EPROM_SIZE INTEGRATOR_BOOT_ROM_SIZE
#define EPROM_END (EPROM_BASE + EPROM_SIZE - 1)
/*
/*
* Clean base - dummy
*
*
*/
#define CLEAN_BASE EPROM_BASE
/*
/*
* Timer definitions
*
*
* Only use timer 1 & 2
* (both run at 24MHz and will need the clock divider set to 16).
*
*
* Timer 0 runs at bus frequency and therefore could vary and currently
* uHAL can't handle that.
*
*
*/
#define INTEGRATOR_TIMER0_BASE INTEGRATOR_CT_BASE
@@ -447,9 +447,9 @@
#define MAX_PERIOD 699050
#define TICKS_PER_uSEC 24
/*
* These are useconds NOT ticks.
*
/*
* These are useconds NOT ticks.
*
*/
#define mSEC_1 1000
#define mSEC_5 (mSEC_1 * 5)
include/asm-arm/arch-integrator/vmalloc.h
-11
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@@ -17,15 +17,4 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
include/asm-arm/arch-iop3xx/vmalloc.h
-3
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@@ -10,9 +10,6 @@
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
//#define VMALLOC_END (0xe8000000)
/* increase usable physical RAM to ~992M per RMK */
#define VMALLOC_END (0xfe000000)
include/asm-arm/arch-ixp2000/platform.h
+1
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@@ -121,6 +121,7 @@ unsigned long ixp2000_gettimeoffset(void);
struct pci_sys_data;
u32 *ixp2000_pci_config_addr(unsigned int bus, unsigned int devfn, int where);
void ixp2000_pci_preinit(void);
int ixp2000_pci_setup(int, struct pci_sys_data*);
struct pci_bus* ixp2000_pci_scan_bus(int, struct pci_sys_data*);
include/asm-arm/arch-ixp2000/vmalloc.h
-3
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@@ -17,7 +17,4 @@
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END 0xfaffefff
include/asm-arm/arch-ixp4xx/vmalloc.h
-12
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@@ -1,17 +1,5 @@
/*
* linux/include/asm-arm/arch-ixp4xx/vmalloc.h
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END (0xFF000000)
include/asm-arm/arch-l7200/vmalloc.h
-11
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@@ -1,15 +1,4 @@
/*
* linux/include/asm-arm/arch-l7200/vmalloc.h
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
include/asm-arm/arch-lh7a40x/vmalloc.h
-11
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@@ -7,15 +7,4 @@
* version 2 as published by the Free Software Foundation.
*
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after
* the physical memory until the kernel virtual memory starts. That
* means that any out-of-bounds memory accesses will hopefully be
* caught. The vmalloc() routines leaves a hole of 4kB (one page)
* between each vmalloced area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_END (0xe8000000)
include/asm-arm/arch-omap/vmalloc.h
-12
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@@ -17,17 +17,5 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
include/asm-arm/arch-pxa/vmalloc.h
-11
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@@ -8,15 +8,4 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_END (0xe8000000)
include/asm-arm/arch-rpc/vmalloc.h
-11
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@@ -7,15 +7,4 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_END (PAGE_OFFSET + 0x1c000000)
include/asm-arm/arch-s3c2410/regs-iis.h
+10
View File
@@ -14,6 +14,7 @@
* 26-06-2003 BJD Finished off definitions for register addresses
* 12-03-2004 BJD Updated include protection
* 07-03-2005 BJD Added FIFO size flags and S3C2440 MPLL
* 05-04-2005 LCVR Added IISFCON definitions for the S3C2400
*/
#ifndef __ASM_ARCH_REGS_IIS_H
@@ -68,5 +69,14 @@
#define S3C2410_IISFCON_RXMASK (0x3f)
#define S3C2410_IISFCON_RXSHIFT (0)
#define S3C2400_IISFCON_TXDMA (1<<11)
#define S3C2400_IISFCON_RXDMA (1<<10)
#define S3C2400_IISFCON_TXENABLE (1<<9)
#define S3C2400_IISFCON_RXENABLE (1<<8)
#define S3C2400_IISFCON_TXMASK (0x07 << 4)
#define S3C2400_IISFCON_TXSHIFT (4)
#define S3C2400_IISFCON_RXMASK (0x07)
#define S3C2400_IISFCON_RXSHIFT (0)
#define S3C2410_IISFIFO (0x10)
#endif /* __ASM_ARCH_REGS_IIS_H */
include/asm-arm/arch-s3c2410/regs-mem.h
+8
View File
@@ -12,6 +12,7 @@
* Changelog:
* 29-Sep-2004 BJD Initial include for Linux
* 10-Mar-2005 LCVR Changed S3C2410_VA to S3C24XX_VA
* 04-Apr-2005 LCVR Added S3C2400 DRAM/BANKSIZE_MASK definitions
*
*/
@@ -183,6 +184,12 @@
#define S3C2410_REFRESH_TRP_3clk (1<<20)
#define S3C2410_REFRESH_TRP_4clk (2<<20)
#define S3C2400_REFRESH_DRAM_TRP_MASK (3<<20)
#define S3C2400_REFRESH_DRAM_TRP_1_5clk (0<<20)
#define S3C2400_REFRESH_DRAM_TRP_2_5clk (1<<20)
#define S3C2400_REFRESH_DRAM_TRP_3_5clk (2<<20)
#define S3C2400_REFRESH_DRAM_TRP_4_5clk (3<<20)
#define S3C2410_REFRESH_TSRC_MASK (3<<18)
#define S3C2410_REFRESH_TSRC_4clk (0<<18)
#define S3C2410_REFRESH_TSRC_5clk (1<<18)
@@ -205,6 +212,7 @@
#define S3C2410_BANKSIZE_4M (0x5 << 0)
#define S3C2410_BANKSIZE_2M (0x4 << 0)
#define S3C2410_BANKSIZE_MASK (0x7 << 0)
#define S3C2400_BANKSIZE_MASK (0x4 << 0)
#define S3C2410_BANKSIZE_SCLK_EN (1<<4)
#define S3C2410_BANKSIZE_SCKE_EN (1<<5)
#define S3C2410_BANKSIZE_BURST (1<<7)
include/asm-arm/arch-s3c2410/regs-spi.h
+2
View File
@@ -12,6 +12,7 @@
* 20-04-2004 KF Created file
* 04-10-2004 BJD Removed VA address (no longer mapped)
* tidied file for submission
* 03-04-2005 LCVR Added S3C2400_SPPIN_nCS definition
*/
#ifndef __ASM_ARCH_REGS_SPI_H
@@ -46,6 +47,7 @@
#define S3C2410_SPPIN_ENMUL (1<<2) /* Multi Master Error detect */
#define S3C2410_SPPIN_RESERVED (1<<1)
#define S3C2400_SPPIN_nCS (1<<1) /* SPI Card Select */
#define S3C2410_SPPIN_KEEP (1<<0) /* Master Out keep */
include/asm-arm/arch-s3c2410/uncompress.h
+5 -1
View File
@@ -16,6 +16,7 @@
* 12-Oct-2004 BJD Take account of debug uart configuration
* 15-Nov-2004 BJD Fixed uart configuration
* 22-Feb-2005 BJD Added watchdog to uncompress
* 04-Apr-2005 LCVR Added support to S3C2400 (no cpuid at GSTATUS1)
*/
#ifndef __ASM_ARCH_UNCOMPRESS_H
@@ -69,9 +70,12 @@ uart_rd(unsigned int reg)
static void
putc(char ch)
{
int cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
int cpuid = S3C2410_GSTATUS1_2410;
#ifndef CONFIG_CPU_S3C2400
cpuid = *((volatile unsigned int *)S3C2410_GSTATUS1);
cpuid &= S3C2410_GSTATUS1_IDMASK;
#endif
if (ch == '\n')
putc('\r'); /* expand newline to \r\n */
include/asm-arm/arch-s3c2410/vmalloc.h
-12
View File
@@ -19,18 +19,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END (0xE0000000)
#endif /* __ASM_ARCH_VMALLOC_H */
include/asm-arm/arch-sa1100/vmalloc.h
-11
View File
@@ -1,15 +1,4 @@
/*
* linux/include/asm-arm/arch-sa1100/vmalloc.h
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_END (0xe8000000)
include/asm-arm/arch-shark/vmalloc.h
-11
View File
@@ -1,15 +1,4 @@
/*
* linux/include/asm-arm/arch-rpc/vmalloc.h
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_END (PAGE_OFFSET + 0x10000000)
include/asm-arm/arch-versatile/vmalloc.h
-12
View File
@@ -18,16 +18,4 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*/
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#define VMALLOC_VMADDR(x) ((unsigned long)(x))
#define VMALLOC_END (PAGE_OFFSET + 0x18000000)
include/asm-arm/bug.h
+3
View File
@@ -3,6 +3,7 @@
#include <linux/config.h>
#ifdef CONFIG_BUG
#ifdef CONFIG_DEBUG_BUGVERBOSE
extern volatile void __bug(const char *file, int line, void *data);
@@ -17,6 +18,8 @@ extern volatile void __bug(const char *file, int line, void *data);
#endif
#define HAVE_ARCH_BUG
#endif
#include <asm-generic/bug.h>
#endif
include/asm-arm/hardware/amba_clcd.h
+19 -12
View File
@@ -153,7 +153,7 @@ struct clcd_fb {
static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
{
u32 val;
u32 val, cpl;
/*
* Program the CLCD controller registers and start the CLCD
@@ -164,7 +164,10 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
val |= (fb->fb.var.left_margin - 1) << 24;
regs->tim0 = val;
val = fb->fb.var.yres - 1;
val = fb->fb.var.yres;
if (fb->panel->cntl & CNTL_LCDDUAL)
val /= 2;
val -= 1;
val |= (fb->fb.var.vsync_len - 1) << 10;
val |= fb->fb.var.lower_margin << 16;
val |= fb->fb.var.upper_margin << 24;
@@ -174,13 +177,17 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
val |= fb->fb.var.sync & FB_SYNC_HOR_HIGH_ACT ? 0 : TIM2_IHS;
val |= fb->fb.var.sync & FB_SYNC_VERT_HIGH_ACT ? 0 : TIM2_IVS;
if (fb->panel->cntl & CNTL_LCDTFT)
val |= (fb->fb.var.xres_virtual - 1) << 16;
else if (fb->panel->cntl & CNTL_LCDBW)
printk("what value for CPL for stnmono panels?");
else
val |= ((fb->fb.var.xres_virtual * 8 / 3) - 1) << 16;
regs->tim2 = val;
cpl = fb->fb.var.xres_virtual;
if (fb->panel->cntl & CNTL_LCDTFT) /* TFT */
/* / 1 */;
else if (!fb->fb.var.grayscale) /* STN color */
cpl = cpl * 8 / 3;
else if (fb->panel->cntl & CNTL_LCDMONO8) /* STN monochrome, 8bit */
cpl /= 8;
else /* STN monochrome, 4bit */
cpl /= 4;
regs->tim2 = val | ((cpl - 1) << 16);
regs->tim3 = fb->panel->tim3;
@@ -204,7 +211,7 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
case 16:
val |= CNTL_LCDBPP16;
break;
case 24:
case 32:
val |= CNTL_LCDBPP24;
break;
}
@@ -215,8 +222,8 @@ static inline void clcdfb_decode(struct clcd_fb *fb, struct clcd_regs *regs)
static inline int clcdfb_check(struct clcd_fb *fb, struct fb_var_screeninfo *var)
{
var->xres_virtual = var->xres = (var->xres + 7) & ~7;
var->yres_virtual = var->yres;
var->xres_virtual = var->xres = (var->xres + 15) & ~15;
var->yres_virtual = var->yres = (var->yres + 1) & ~1;
#define CHECK(e,l,h) (var->e < l || var->e > h)
if (CHECK(right_margin, (5+1), 256) || /* back porch */
include/asm-arm/hardware/clock.h
+5 -2
View File
@@ -26,10 +26,13 @@ struct clk;
/**
* clk_get - lookup and obtain a reference to a clock producer.
* @dev: device for clock "consumer"
* @id: device ID
* @id: clock comsumer ID
*
* Returns a struct clk corresponding to the clock producer, or
* valid IS_ERR() condition containing errno.
* valid IS_ERR() condition containing errno. The implementation
* uses @dev and @id to determine the clock consumer, and thereby
* the clock producer. (IOW, @id may be identical strings, but
* clk_get may return different clock producers depending on @dev.)
*/
struct clk *clk_get(struct device *dev, const char *id);
include/asm-arm/io.h
+18 -10
View File
@@ -99,12 +99,16 @@ extern void __readwrite_bug(const char *fn);
*/
#ifdef __io
#define outb(v,p) __raw_writeb(v,__io(p))
#define outw(v,p) __raw_writew(cpu_to_le16(v),__io(p))
#define outl(v,p) __raw_writel(cpu_to_le32(v),__io(p))
#define outw(v,p) __raw_writew((__force __u16) \
cpu_to_le16(v),__io(p))
#define outl(v,p) __raw_writel((__force __u32) \
cpu_to_le32(v),__io(p))
#define inb(p) ({ unsigned int __v = __raw_readb(__io(p)); __v; })
#define inw(p) ({ unsigned int __v = le16_to_cpu(__raw_readw(__io(p))); __v; })
#define inl(p) ({ unsigned int __v = le32_to_cpu(__raw_readl(__io(p))); __v; })
#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __v; })
#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
__raw_readw(__io(p))); __v; })
#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
__raw_readl(__io(p))); __v; })
#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
@@ -149,9 +153,11 @@ extern void _memset_io(void __iomem *, int, size_t);
* IO port primitives for more information.
*/
#ifdef __mem_pci
#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; })
#define readw(c) ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; })
#define readl(c) ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; })
#define readb(c) ({ __u8 __v = __raw_readb(__mem_pci(c)); __v; })
#define readw(c) ({ __u16 __v = le16_to_cpu((__force __le16) \
__raw_readw(__mem_pci(c))); __v; })
#define readl(c) ({ __u32 __v = le32_to_cpu((__force __le32) \
__raw_readl(__mem_pci(c))); __v; })
#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)
@@ -161,8 +167,10 @@ extern void _memset_io(void __iomem *, int, size_t);
#define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l)
#define writeb(v,c) __raw_writeb(v,__mem_pci(c))
#define writew(v,c) __raw_writew(cpu_to_le16(v),__mem_pci(c))
#define writel(v,c) __raw_writel(cpu_to_le32(v),__mem_pci(c))
#define writew(v,c) __raw_writew((__force __u16) \
cpu_to_le16(v),__mem_pci(c))
#define writel(v,c) __raw_writel((__force __u32) \
cpu_to_le32(v),__mem_pci(c))
#define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l)
#define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l)
include/asm-arm/pgtable.h
+17
View File
@@ -16,6 +16,23 @@
#include <asm/proc-fns.h>
#include <asm/arch/vmalloc.h>
/*
* Just any arbitrary offset to the start of the vmalloc VM area: the
* current 8MB value just means that there will be a 8MB "hole" after the
* physical memory until the kernel virtual memory starts. That means that
* any out-of-bounds memory accesses will hopefully be caught.
* The vmalloc() routines leaves a hole of 4kB between each vmalloced
* area for the same reason. ;)
*
* Note that platforms may override VMALLOC_START, but they must provide
* VMALLOC_END. VMALLOC_END defines the (exclusive) limit of this space,
* which may not overlap IO space.
*/
#ifndef VMALLOC_START
#define VMALLOC_OFFSET (8*1024*1024)
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#endif
/*
* Hardware-wise, we have a two level page table structure, where the first
* level has 4096 entries, and the second level has 256 entries. Each entry
include/asm-arm/processor.h
+3 -4
View File
@@ -23,8 +23,6 @@
#include <asm/procinfo.h>
#include <asm/types.h>
#define KERNEL_STACK_SIZE PAGE_SIZE
union debug_insn {
u32 arm;
u16 thumb;
@@ -87,8 +85,9 @@ unsigned long get_wchan(struct task_struct *p);
*/
extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
#define KSTK_EIP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)->thread_info))[1019])
#define KSTK_ESP(tsk) (((unsigned long *)(4096+(unsigned long)(tsk)->thread_info))[1017])
#define KSTK_REGS(tsk) (((struct pt_regs *)(THREAD_START_SP + (unsigned long)(tsk)->thread_info)) - 1)
#define KSTK_EIP(tsk) KSTK_REGS(tsk)->ARM_pc
#define KSTK_ESP(tsk) KSTK_REGS(tsk)->ARM_sp
/*
* Prefetching support - only ARMv5.
include/asm-arm/rtc.h
+2 -2
View File
@@ -18,9 +18,9 @@ struct rtc_ops {
void (*release)(void);
int (*ioctl)(unsigned int, unsigned long);
void (*read_time)(struct rtc_time *);
int (*read_time)(struct rtc_time *);
int (*set_time)(struct rtc_time *);
void (*read_alarm)(struct rtc_wkalrm *);
int (*read_alarm)(struct rtc_wkalrm *);
int (*set_alarm)(struct rtc_wkalrm *);
int (*proc)(char *buf);
};
include/asm-arm/signal.h
+1 -25
View File
@@ -114,34 +114,10 @@ typedef unsigned long sigset_t;
#define SIGSTKSZ 8192
#ifdef __KERNEL__
/*
* These values of sa_flags are used only by the kernel as part of the
* irq handling routines.
*
* SA_INTERRUPT is also used by the irq handling routines.
* SA_SHIRQ is for shared interrupt support on PCI and EISA.
*/
#define SA_PROBE 0x80000000
#define SA_SAMPLE_RANDOM 0x10000000
#define SA_IRQNOMASK 0x08000000
#define SA_SHIRQ 0x04000000
#endif
#define SIG_BLOCK 0 /* for blocking signals */
#define SIG_UNBLOCK 1 /* for unblocking signals */
#define SIG_SETMASK 2 /* for setting the signal mask */
/* Type of a signal handler. */
typedef void __signalfn_t(int);
typedef __signalfn_t __user *__sighandler_t;
typedef void __restorefn_t(void);
typedef __restorefn_t __user *__sigrestore_t;
#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
#include <asm-generic/signal.h>
#ifdef __KERNEL__
struct old_sigaction {
include/asm-arm/string.h
+12 -5
View File
@@ -29,15 +29,22 @@ extern void __memzero(void *ptr, __kernel_size_t n);
#define memset(p,v,n) \
({ \
if ((n) != 0) { \
void *__p = (p); size_t __n = n; \
if ((__n) != 0) { \
if (__builtin_constant_p((v)) && (v) == 0) \
__memzero((p),(n)); \
__memzero((__p),(__n)); \
else \
memset((p),(v),(n)); \
memset((__p),(v),(__n)); \
} \
(p); \
(__p); \
})
#define memzero(p,n) ({ if ((n) != 0) __memzero((p),(n)); (p); })
#define memzero(p,n) \
({ \
void *__p = (p); size_t __n = n; \
if ((__n) != 0) \
__memzero((__p),(__n)); \
(__p); \
})
#endif
include/asm-arm/thread_info.h
+4 -2
View File
@@ -14,6 +14,10 @@
#include <asm/fpstate.h>
#define THREAD_SIZE_ORDER 1
#define THREAD_SIZE 8192
#define THREAD_START_SP (THREAD_SIZE - 8)
#ifndef __ASSEMBLY__
struct task_struct;
@@ -77,8 +81,6 @@ struct thread_info {
#define init_thread_info (init_thread_union.thread_info)
#define init_stack (init_thread_union.stack)
#define THREAD_SIZE 8192
/*
* how to get the thread information struct from C
*/
include/asm-arm/unistd.h
+1 -2
View File
@@ -359,8 +359,7 @@
#define __ARM_NR_cacheflush (__ARM_NR_BASE+2)
#define __ARM_NR_usr26 (__ARM_NR_BASE+3)
#define __ARM_NR_usr32 (__ARM_NR_BASE+4)
#define __ARM_NR_set_tls (__ARM_NR_BASE+0x800)
#define __ARM_NR_set_tls (__ARM_NR_BASE+5)
#define __sys2(x) #x
#define __sys1(x) __sys2(x)
include/asm-arm26/bug.h
+3
View File
@@ -3,6 +3,7 @@
#include <linux/config.h>
#ifdef CONFIG_BUG
#ifdef CONFIG_DEBUG_BUGVERBOSE
extern volatile void __bug(const char *file, int line, void *data);
/* give file/line information */
@@ -12,6 +13,8 @@ extern volatile void __bug(const char *file, int line, void *data);
#endif
#define HAVE_ARCH_BUG
#endif
#include <asm-generic/bug.h>
#endif
include/asm-arm26/signal.h
+1 -21
View File
@@ -114,30 +114,10 @@ typedef unsigned long sigset_t;
#define SIGSTKSZ 8192
#ifdef __KERNEL__
/*
* These values of sa_flags are used only by the kernel as part of the
* irq handling routines.
*
* SA_INTERRUPT is also used by the irq handling routines.
* SA_SHIRQ is for shared interrupt support on PCI and EISA.
*/
#define SA_PROBE 0x80000000
#define SA_SAMPLE_RANDOM 0x10000000
#define SA_IRQNOMASK 0x08000000
#define SA_SHIRQ 0x04000000
#endif
#define SIG_BLOCK 0 /* for blocking signals */
#define SIG_UNBLOCK 1 /* for unblocking signals */
#define SIG_SETMASK 2 /* for setting the signal mask */
/* Type of a signal handler. */
typedef void (*__sighandler_t)(int);
#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
#include <asm-generic/signal.h>
#ifdef __KERNEL__
struct old_sigaction {
include/asm-cris/page.h
-4
View File
@@ -77,10 +77,6 @@ typedef struct { unsigned long pgprot; } pgprot_t;
printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
} while (0)
#define PAGE_BUG(page) do { \
BUG(); \
} while (0)
/* Pure 2^n version of get_order */
static inline int get_order(unsigned long size)
{
include/asm-cris/signal.h
+1 -24
View File
@@ -108,30 +108,7 @@ typedef unsigned long sigset_t;
#define MINSIGSTKSZ 2048
#define SIGSTKSZ 8192
#ifdef __KERNEL__
/*
* These values of sa_flags are used only by the kernel as part of the
* irq handling routines.
*
* SA_INTERRUPT is also used by the irq handling routines.
* SA_SHIRQ is for shared interrupt support
*/
#define SA_PROBE SA_ONESHOT
#define SA_SAMPLE_RANDOM SA_RESTART
#define SA_SHIRQ 0x04000000
#endif
#define SIG_BLOCK 0 /* for blocking signals */
#define SIG_UNBLOCK 1 /* for unblocking signals */
#define SIG_SETMASK 2 /* for setting the signal mask */
/* Type of a signal handler. */
typedef void (*__sighandler_t)(int);
#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
#include <asm-generic/signal.h>
#ifdef __KERNEL__
struct old_sigaction {
include/asm-frv/bug.h
+2
View File
@@ -13,6 +13,7 @@
#include <linux/config.h>
#ifdef CONFIG_BUG
/*
* Tell the user there is some problem.
*/
@@ -45,6 +46,7 @@ do { \
#define HAVE_ARCH_KGDB_BAD_PAGE
#define kgdb_bad_page(page) do { kgdb_raise(SIGABRT); } while(0)
#endif
#endif
#include <asm-generic/bug.h>
include/asm-frv/pgtable.h
+2 -2
View File
@@ -349,9 +349,9 @@ static inline pmd_t *pmd_offset(pud_t *dir, unsigned long address)
/*
* Define this to warn about kernel memory accesses that are
* done without a 'verify_area(VERIFY_WRITE,..)'
* done without a 'access_ok(VERIFY_WRITE,..)'
*/
#undef TEST_VERIFY_AREA
#undef TEST_ACCESS_OK
#define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
#define pte_clear(mm,addr,xp) do { set_pte_at(mm, addr, xp, __pte(0)); } while (0)
include/asm-frv/signal.h
+1 -24
View File
@@ -107,30 +107,7 @@ typedef unsigned long sigset_t;
#define MINSIGSTKSZ 2048
#define SIGSTKSZ 8192
#ifdef __KERNEL__
/*
* These values of sa_flags are used only by the kernel as part of the
* irq handling routines.
*
* SA_INTERRUPT is also used by the irq handling routines.
* SA_SHIRQ is for shared interrupt support on PCI and EISA.
*/
#define SA_PROBE SA_ONESHOT
#define SA_SAMPLE_RANDOM SA_RESTART
#define SA_SHIRQ 0x04000000
#endif
#define SIG_BLOCK 0 /* for blocking signals */
#define SIG_UNBLOCK 1 /* for unblocking signals */
#define SIG_SETMASK 2 /* for setting the signal mask */
/* Type of a signal handler. */
typedef void (*__sighandler_t)(int);
#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
#include <asm-generic/signal.h>
#ifdef __KERNEL__
struct old_sigaction {
include/asm-generic/bug.h
+15 -7
View File
@@ -4,6 +4,7 @@
#include <linux/compiler.h>
#include <linux/config.h>
#ifdef CONFIG_BUG
#ifndef HAVE_ARCH_BUG
#define BUG() do { \
printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); \
@@ -11,13 +12,6 @@
} while (0)
#endif
#ifndef HAVE_ARCH_PAGE_BUG
#define PAGE_BUG(page) do { \
printk("page BUG for page at %p\n", page); \
BUG(); \
} while (0)
#endif
#ifndef HAVE_ARCH_BUG_ON
#define BUG_ON(condition) do { if (unlikely((condition)!=0)) BUG(); } while(0)
#endif
@@ -31,4 +25,18 @@
} while (0)
#endif
#else /* !CONFIG_BUG */
#ifndef HAVE_ARCH_BUG
#define BUG()
#endif
#ifndef HAVE_ARCH_BUG_ON
#define BUG_ON(condition) do { if (condition) ; } while(0)
#endif
#ifndef HAVE_ARCH_WARN_ON
#define WARN_ON(condition) do { if (condition) ; } while(0)
#endif
#endif
#endif
include/asm-generic/errno.h
+4
View File
@@ -102,4 +102,8 @@
#define EKEYREVOKED 128 /* Key has been revoked */
#define EKEYREJECTED 129 /* Key was rejected by service */
/* for robust mutexes */
#define EOWNERDEAD 130 /* Owner died */
#define ENOTRECOVERABLE 131 /* State not recoverable */
#endif
include/asm-generic/resource.h
+6 -1
View File
@@ -41,8 +41,11 @@
#define RLIMIT_LOCKS 10 /* maximum file locks held */
#define RLIMIT_SIGPENDING 11 /* max number of pending signals */
#define RLIMIT_MSGQUEUE 12 /* maximum bytes in POSIX mqueues */
#define RLIMIT_NICE 13 /* max nice prio allowed to raise to
0-39 for nice level 19 .. -20 */
#define RLIMIT_RTPRIO 14 /* maximum realtime priority */
#define RLIM_NLIMITS 13
#define RLIM_NLIMITS 15
/*
* SuS says limits have to be unsigned.
@@ -81,6 +84,8 @@
[RLIMIT_LOCKS] = { RLIM_INFINITY, RLIM_INFINITY }, \
[RLIMIT_SIGPENDING] = { 0, 0 }, \
[RLIMIT_MSGQUEUE] = { MQ_BYTES_MAX, MQ_BYTES_MAX }, \
[RLIMIT_NICE] = { 0, 0 }, \
[RLIMIT_RTPRIO] = { 0, 0 }, \
}
#endif /* __KERNEL__ */
include/asm-generic/sections.h
+2
View File
@@ -8,6 +8,8 @@ extern char _data[], _sdata[], _edata[];
extern char __bss_start[], __bss_stop[];
extern char __init_begin[], __init_end[];
extern char _sinittext[], _einittext[];
extern char _sextratext[] __attribute__((weak));
extern char _eextratext[] __attribute__((weak));
extern char _end[];
#endif /* _ASM_GENERIC_SECTIONS_H_ */
include/asm-generic/siginfo.h
+10 -3
View File
@@ -236,11 +236,18 @@ typedef struct siginfo {
#define SIGEV_THREAD 2 /* deliver via thread creation */
#define SIGEV_THREAD_ID 4 /* deliver to thread */
#define SIGEV_MAX_SIZE 64
#ifndef SIGEV_PAD_SIZE
#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 3)
/*
* This works because the alignment is ok on all current architectures
* but we leave open this being overridden in the future
*/
#ifndef __ARCH_SIGEV_PREAMBLE_SIZE
#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(int) * 2 + sizeof(sigval_t))
#endif
#define SIGEV_MAX_SIZE 64
#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE - __ARCH_SIGEV_PREAMBLE_SIZE) \
/ sizeof(int))
typedef struct sigevent {
sigval_t sigev_value;
int sigev_signo;
include/asm-generic/signal.h
+21
View File
@@ -0,0 +1,21 @@
#ifndef SIG_BLOCK
#define SIG_BLOCK 0 /* for blocking signals */
#endif
#ifndef SIG_UNBLOCK
#define SIG_UNBLOCK 1 /* for unblocking signals */
#endif
#ifndef SIG_SETMASK
#define SIG_SETMASK 2 /* for setting the signal mask */
#endif
#ifndef __ASSEMBLY__
typedef void __signalfn_t(int);
typedef __signalfn_t __user *__sighandler_t;
typedef void __restorefn_t(void);
typedef __restorefn_t __user *__sigrestore_t;
#define SIG_DFL ((__force __sighandler_t)0) /* default signal handling */
#define SIG_IGN ((__force __sighandler_t)1) /* ignore signal */
#define SIG_ERR ((__force __sighandler_t)-1) /* error return from signal */
#endif
include/asm-generic/unaligned.h
+41 -40
View File
@@ -76,46 +76,47 @@ static inline void __ustw(__u16 val, __u16 *addr)
ptr->x = val;
}
static inline unsigned long __get_unaligned(const void *ptr, size_t size)
{
unsigned long val;
switch (size) {
case 1:
val = *(const __u8 *)ptr;
break;
case 2:
val = __uldw((const __u16 *)ptr);
break;
case 4:
val = __uldl((const __u32 *)ptr);
break;
case 8:
val = __uldq((const __u64 *)ptr);
break;
default:
bad_unaligned_access_length();
};
return val;
}
#define __get_unaligned(ptr, size) ({ \
const void *__gu_p = ptr; \
unsigned long val; \
switch (size) { \
case 1: \
val = *(const __u8 *)__gu_p; \
break; \
case 2: \
val = __uldw(__gu_p); \
break; \
case 4: \
val = __uldl(__gu_p); \
break; \
case 8: \
val = __uldq(__gu_p); \
break; \
default: \
bad_unaligned_access_length(); \
}; \
val; \
})
static inline void __put_unaligned(unsigned long val, void *ptr, size_t size)
{
switch (size) {
case 1:
*(__u8 *)ptr = val;
break;
case 2:
__ustw(val, (__u16 *)ptr);
break;
case 4:
__ustl(val, (__u32 *)ptr);
break;
case 8:
__ustq(val, (__u64 *)ptr);
break;
default:
bad_unaligned_access_length();
};
}
#define __put_unaligned(val, ptr, size) \
do { \
void *__gu_p = ptr; \
switch (size) { \
case 1: \
*(__u8 *)__gu_p = val; \
break; \
case 2: \
__ustw(val, __gu_p); \
break; \
case 4: \
__ustl(val, __gu_p); \
break; \
case 8: \
__ustq(val, __gu_p); \
break; \
default: \
bad_unaligned_access_length(); \
}; \
} while(0)
#endif /* _ASM_GENERIC_UNALIGNED_H */
include/asm-h8300/signal.h
+1 -23
View File
@@ -107,29 +107,7 @@ typedef unsigned long sigset_t;
#define MINSIGSTKSZ 2048
#define SIGSTKSZ 8192
#ifdef __KERNEL__
/*
* These values of sa_flags are used only by the kernel as part of the
* irq handling routines.
*
* SA_INTERRUPT is also used by the irq handling routines.
* SA_SHIRQ is for shared interrupt support on PCI and EISA.
*/
#define SA_PROBE SA_ONESHOT
#define SA_SAMPLE_RANDOM SA_RESTART
#define SA_SHIRQ 0x04000000
#endif
#define SIG_BLOCK 0 /* for blocking signals */
#define SIG_UNBLOCK 1 /* for unblocking signals */
#define SIG_SETMASK 2 /* for setting the signal mask */
/* Type of a signal handler. */
typedef void (*__sighandler_t)(int);
#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
#include <asm-generic/signal.h>
#ifdef __KERNEL__
struct old_sigaction {
include/asm-i386/apic.h
-1
View File
@@ -109,7 +109,6 @@ extern int APIC_init_uniprocessor (void);
extern void disable_APIC_timer(void);
extern void enable_APIC_timer(void);
extern int check_nmi_watchdog (void);
extern void enable_NMI_through_LVT0 (void * dummy);
extern unsigned int nmi_watchdog;
include/asm-i386/bug.h
+5 -4
View File
@@ -9,6 +9,8 @@
* undefined" opcode for parsing in the trap handler.
*/
#ifdef CONFIG_BUG
#define HAVE_ARCH_BUG
#ifdef CONFIG_DEBUG_BUGVERBOSE
#define BUG() \
__asm__ __volatile__( "ud2\n" \
@@ -18,8 +20,7 @@
#else
#define BUG() __asm__ __volatile__("ud2\n")
#endif
#define HAVE_ARCH_BUG
#include <asm-generic/bug.h>
#endif
#include <asm-generic/bug.h>
#endif
include/asm-i386/checksum.h
+1 -1
View File
@@ -33,7 +33,7 @@ asmlinkage unsigned int csum_partial_copy_generic(const unsigned char *src, unsi
* passed in an incorrect kernel address to one of these functions.
*
* If you use these functions directly please don't forget the
* verify_area().
* access_ok().
*/
static __inline__
unsigned int csum_partial_copy_nocheck (const unsigned char *src, unsigned char *dst,
include/asm-i386/cpufeature.h
+2 -2
View File
@@ -87,8 +87,8 @@
#define X86_FEATURE_XCRYPT_EN (5*32+ 7) /* on-CPU crypto enabled */
/* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
#define X86_FEATURE_LAHF_LM (5*32+ 0) /* LAHF/SAHF in long mode */
#define X86_FEATURE_CMP_LEGACY (5*32+ 1) /* If yes HyperThreading not valid */
#define X86_FEATURE_LAHF_LM (6*32+ 0) /* LAHF/SAHF in long mode */
#define X86_FEATURE_CMP_LEGACY (6*32+ 1) /* If yes HyperThreading not valid */
#define cpu_has(c, bit) test_bit(bit, (c)->x86_capability)
#define boot_cpu_has(bit) test_bit(bit, boot_cpu_data.x86_capability)
include/asm-i386/e820.h
+1 -1
View File
@@ -13,7 +13,7 @@
#define __E820_HEADER
#define E820MAP 0x2d0 /* our map */
#define E820MAX 32 /* number of entries in E820MAP */
#define E820MAX 128 /* number of entries in E820MAP */
#define E820NR 0x1e8 /* # entries in E820MAP */
#define E820_RAM 1
include/asm-i386/floppy.h
+1 -1
View File
@@ -257,7 +257,7 @@ static int hard_dma_setup(char *addr, unsigned long size, int mode, int io)
return 0;
}
struct fd_routine_l {
static struct fd_routine_l {
int (*_request_dma)(unsigned int dmanr, const char * device_id);
void (*_free_dma)(unsigned int dmanr);
int (*_get_dma_residue)(unsigned int dummy);
include/asm-i386/hpet.h
+1
View File
@@ -92,6 +92,7 @@
extern unsigned long hpet_tick; /* hpet clks count per tick */
extern unsigned long hpet_address; /* hpet memory map physical address */
extern int hpet_use_timer;
extern int hpet_rtc_timer_init(void);
extern int hpet_enable(void);
include/asm-i386/module.h
+2 -2
View File
@@ -52,8 +52,8 @@ struct mod_arch_specific
#define MODULE_PROC_FAMILY "CYRIXIII "
#elif defined CONFIG_MVIAC3_2
#define MODULE_PROC_FAMILY "VIAC3-2 "
#elif CONFIG_MGEODE
#define MODULE_PROC_FAMILY "GEODE "
#elif CONFIG_MGEODEGX1
#define MODULE_PROC_FAMILY "GEODEGX1 "
#else
#error unknown processor family
#endif
include/asm-i386/pgtable.h
+2 -2
View File
@@ -193,9 +193,9 @@ extern unsigned long long __PAGE_KERNEL, __PAGE_KERNEL_EXEC;
/*
* Define this if things work differently on an i386 and an i486:
* it will (on an i486) warn about kernel memory accesses that are
* done without a 'verify_area(VERIFY_WRITE,..)'
* done without a 'access_ok(VERIFY_WRITE,..)'
*/
#undef TEST_VERIFY_AREA
#undef TEST_ACCESS_OK
/* The boot page tables (all created as a single array) */
extern unsigned long pg0[];
include/asm-i386/setup.h
+1 -1
View File
@@ -16,7 +16,7 @@
#define MAXMEM_PFN PFN_DOWN(MAXMEM)
#define MAX_NONPAE_PFN (1 << 20)
#define PARAM_SIZE 2048
#define PARAM_SIZE 4096
#define COMMAND_LINE_SIZE 256
#define OLD_CL_MAGIC_ADDR 0x90020
include/asm-i386/signal.h
+1 -28
View File
@@ -110,34 +110,7 @@ typedef unsigned long sigset_t;
#define MINSIGSTKSZ 2048
#define SIGSTKSZ 8192
#ifdef __KERNEL__
/*
* These values of sa_flags are used only by the kernel as part of the
* irq handling routines.
*
* SA_INTERRUPT is also used by the irq handling routines.
* SA_SHIRQ is for shared interrupt support on PCI and EISA.
*/
#define SA_PROBE SA_ONESHOT
#define SA_SAMPLE_RANDOM SA_RESTART
#define SA_SHIRQ 0x04000000
#endif
#define SIG_BLOCK 0 /* for blocking signals */
#define SIG_UNBLOCK 1 /* for unblocking signals */
#define SIG_SETMASK 2 /* for setting the signal mask */
/* Type of a signal handler. */
typedef void __signalfn_t(int);
typedef __signalfn_t __user *__sighandler_t;
typedef void __restorefn_t(void);
typedef __restorefn_t __user *__sigrestore_t;
#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
#include <asm-generic/signal.h>
#ifdef __KERNEL__
struct old_sigaction {
include/asm-i386/string.h
+62 -29
View File
@@ -198,46 +198,79 @@ static inline void * __memcpy(void * to, const void * from, size_t n)
int d0, d1, d2;
__asm__ __volatile__(
"rep ; movsl\n\t"
"testb $2,%b4\n\t"
"je 1f\n\t"
"movsw\n"
"1:\ttestb $1,%b4\n\t"
"je 2f\n\t"
"movsb\n"
"2:"
"movl %4,%%ecx\n\t"
"andl $3,%%ecx\n\t"
#if 1 /* want to pay 2 byte penalty for a chance to skip microcoded rep? */
"jz 1f\n\t"
#endif
"rep ; movsb\n\t"
"1:"
: "=&c" (d0), "=&D" (d1), "=&S" (d2)
:"0" (n/4), "q" (n),"1" ((long) to),"2" ((long) from)
: "0" (n/4), "g" (n), "1" ((long) to), "2" ((long) from)
: "memory");
return (to);
}
/*
* This looks horribly ugly, but the compiler can optimize it totally,
* This looks ugly, but the compiler can optimize it totally,
* as the count is constant.
*/
static inline void * __constant_memcpy(void * to, const void * from, size_t n)
{
if (n <= 128)
return __builtin_memcpy(to, from, n);
#define COMMON(x) \
__asm__ __volatile__( \
"rep ; movsl" \
x \
: "=&c" (d0), "=&D" (d1), "=&S" (d2) \
: "0" (n/4),"1" ((long) to),"2" ((long) from) \
: "memory");
{
int d0, d1, d2;
switch (n % 4) {
case 0: COMMON(""); return to;
case 1: COMMON("\n\tmovsb"); return to;
case 2: COMMON("\n\tmovsw"); return to;
default: COMMON("\n\tmovsw\n\tmovsb"); return to;
long esi, edi;
if (!n) return to;
#if 1 /* want to do small copies with non-string ops? */
switch (n) {
case 1: *(char*)to = *(char*)from; return to;
case 2: *(short*)to = *(short*)from; return to;
case 4: *(int*)to = *(int*)from; return to;
#if 1 /* including those doable with two moves? */
case 3: *(short*)to = *(short*)from;
*((char*)to+2) = *((char*)from+2); return to;
case 5: *(int*)to = *(int*)from;
*((char*)to+4) = *((char*)from+4); return to;
case 6: *(int*)to = *(int*)from;
*((short*)to+2) = *((short*)from+2); return to;
case 8: *(int*)to = *(int*)from;
*((int*)to+1) = *((int*)from+1); return to;
#endif
}
#endif
esi = (long) from;
edi = (long) to;
if (n >= 5*4) {
/* large block: use rep prefix */
int ecx;
__asm__ __volatile__(
"rep ; movsl"
: "=&c" (ecx), "=&D" (edi), "=&S" (esi)
: "0" (n/4), "1" (edi),"2" (esi)
: "memory"
);
} else {
/* small block: don't clobber ecx + smaller code */
if (n >= 4*4) __asm__ __volatile__("movsl"
:"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory");
if (n >= 3*4) __asm__ __volatile__("movsl"
:"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory");
if (n >= 2*4) __asm__ __volatile__("movsl"
:"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory");
if (n >= 1*4) __asm__ __volatile__("movsl"
:"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory");
}
switch (n % 4) {
/* tail */
case 0: return to;
case 1: __asm__ __volatile__("movsb"
:"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory");
return to;
case 2: __asm__ __volatile__("movsw"
:"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory");
return to;
default: __asm__ __volatile__("movsw\n\tmovsb"
:"=&D"(edi),"=&S"(esi):"0"(edi),"1"(esi):"memory");
return to;
}
}
#undef COMMON
}
#define __HAVE_ARCH_MEMCPY
include/asm-i386/system.h
+3 -3
View File
@@ -81,7 +81,7 @@ static inline unsigned long _get_base(char * addr)
#define loadsegment(seg,value) \
asm volatile("\n" \
"1:\t" \
"movl %0,%%" #seg "\n" \
"mov %0,%%" #seg "\n" \
"2:\n" \
".section .fixup,\"ax\"\n" \
"3:\t" \
@@ -93,13 +93,13 @@ static inline unsigned long _get_base(char * addr)
".align 4\n\t" \
".long 1b,3b\n" \
".previous" \
: :"m" (*(unsigned int *)&(value)))
: :"m" (value))
/*
* Save a segment register away
*/
#define savesegment(seg, value) \
asm volatile("movl %%" #seg ",%0":"=m" (*(int *)&(value)))
asm volatile("mov %%" #seg ",%0":"=m" (value))
/*
* Clear and set 'TS' bit respectively
include/asm-ia64/bitops.h
+17 -4
View File
@@ -314,8 +314,8 @@ __ffs (unsigned long x)
#ifdef __KERNEL__
/*
* find_last_zero_bit - find the last zero bit in a 64 bit quantity
* @x: The value to search
* Return bit number of last (most-significant) bit set. Undefined
* for x==0. Bits are numbered from 0..63 (e.g., ia64_fls(9) == 3).
*/
static inline unsigned long
ia64_fls (unsigned long x)
@@ -327,10 +327,23 @@ ia64_fls (unsigned long x)
return exp - 0xffff;
}
/*
* Find the last (most significant) bit set. Returns 0 for x==0 and
* bits are numbered from 1..32 (e.g., fls(9) == 4).
*/
static inline int
fls (int x)
fls (int t)
{
return ia64_fls((unsigned int) x);
unsigned long x = t & 0xffffffffu;
if (!x)
return 0;
x |= x >> 1;
x |= x >> 2;
x |= x >> 4;
x |= x >> 8;
x |= x >> 16;
return ia64_popcnt(x);
}
/*
include/asm-ia64/bug.h
+4 -1
View File
@@ -1,6 +1,7 @@
#ifndef _ASM_IA64_BUG_H
#define _ASM_IA64_BUG_H
#ifdef CONFIG_BUG
#if (__GNUC__ > 3) || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1)
# define ia64_abort() __builtin_trap()
#else
@@ -8,8 +9,10 @@
#endif
#define BUG() do { printk("kernel BUG at %s:%d!\n", __FILE__, __LINE__); ia64_abort(); } while (0)
/* should this BUG should be made generic? */
/* should this BUG be made generic? */
#define HAVE_ARCH_BUG
#endif
#include <asm-generic/bug.h>
#endif
include/asm-ia64/gcc_intrin.h
+7 -3
View File
@@ -133,13 +133,17 @@ register unsigned long ia64_r13 asm ("r13") __attribute_used__;
ia64_intri_res; \
})
#define ia64_popcnt(x) \
({ \
#if __GNUC__ >= 4 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
# define ia64_popcnt(x) __builtin_popcountl(x)
#else
# define ia64_popcnt(x) \
({ \
__u64 ia64_intri_res; \
asm ("popcnt %0=%1" : "=r" (ia64_intri_res) : "r" (x)); \
\
ia64_intri_res; \
})
})
#endif
#define ia64_getf_exp(x) \
({ \
include/asm-ia64/hw_irq.h
+1
View File
@@ -81,6 +81,7 @@ extern __u8 isa_irq_to_vector_map[16];
extern struct hw_interrupt_type irq_type_ia64_lsapic; /* CPU-internal interrupt controller */
extern int assign_irq_vector_nopanic (int irq); /* allocate a free vector without panic */
extern int assign_irq_vector (int irq); /* allocate a free vector */
extern void free_irq_vector (int vector);
extern void ia64_send_ipi (int cpu, int vector, int delivery_mode, int redirect);
include/asm-ia64/pal.h
+68
View File
@@ -67,6 +67,7 @@
#define PAL_REGISTER_INFO 39 /* return AR and CR register information*/
#define PAL_SHUTDOWN 40 /* enter processor shutdown state */
#define PAL_PREFETCH_VISIBILITY 41 /* Make Processor Prefetches Visible */
#define PAL_LOGICAL_TO_PHYSICAL 42 /* returns information on logical to physical processor mapping */
#define PAL_COPY_PAL 256 /* relocate PAL procedures and PAL PMI */
#define PAL_HALT_INFO 257 /* return the low power capabilities of processor */
@@ -1559,6 +1560,73 @@ ia64_pal_prefetch_visibility (s64 trans_type)
return iprv.status;
}
/* data structure for getting information on logical to physical mappings */
typedef union pal_log_overview_u {
struct {
u64 num_log :16, /* Total number of logical
* processors on this die
*/
tpc :8, /* Threads per core */
reserved3 :8, /* Reserved */
cpp :8, /* Cores per processor */
reserved2 :8, /* Reserved */
ppid :8, /* Physical processor ID */
reserved1 :8; /* Reserved */
} overview_bits;
u64 overview_data;
} pal_log_overview_t;
typedef union pal_proc_n_log_info1_u{
struct {
u64 tid :16, /* Thread id */
reserved2 :16, /* Reserved */
cid :16, /* Core id */
reserved1 :16; /* Reserved */
} ppli1_bits;
u64 ppli1_data;
} pal_proc_n_log_info1_t;
typedef union pal_proc_n_log_info2_u {
struct {
u64 la :16, /* Logical address */
reserved :48; /* Reserved */
} ppli2_bits;
u64 ppli2_data;
} pal_proc_n_log_info2_t;
typedef struct pal_logical_to_physical_s
{
pal_log_overview_t overview;
pal_proc_n_log_info1_t ppli1;
pal_proc_n_log_info2_t ppli2;
} pal_logical_to_physical_t;
#define overview_num_log overview.overview_bits.num_log
#define overview_tpc overview.overview_bits.tpc
#define overview_cpp overview.overview_bits.cpp
#define overview_ppid overview.overview_bits.ppid
#define log1_tid ppli1.ppli1_bits.tid
#define log1_cid ppli1.ppli1_bits.cid
#define log2_la ppli2.ppli2_bits.la
/* Get information on logical to physical processor mappings. */
static inline s64
ia64_pal_logical_to_phys(u64 proc_number, pal_logical_to_physical_t *mapping)
{
struct ia64_pal_retval iprv;
PAL_CALL(iprv, PAL_LOGICAL_TO_PHYSICAL, proc_number, 0, 0);
if (iprv.status == PAL_STATUS_SUCCESS)
{
if (proc_number == 0)
mapping->overview.overview_data = iprv.v0;
mapping->ppli1.ppli1_data = iprv.v1;
mapping->ppli2.ppli2_data = iprv.v2;
}
return iprv.status;
}
#endif /* __ASSEMBLY__ */
#endif /* _ASM_IA64_PAL_H */
include/asm-ia64/perfmon.h
+12
View File
@@ -254,6 +254,18 @@ extern int pfm_mod_write_dbrs(struct task_struct *task, void *req, unsigned int
#define PFM_CPUINFO_DCR_PP 0x2 /* if set the system wide session has started */
#define PFM_CPUINFO_EXCL_IDLE 0x4 /* the system wide session excludes the idle task */
/*
* sysctl control structure. visible to sampling formats
*/
typedef struct {
int debug; /* turn on/off debugging via syslog */
int debug_ovfl; /* turn on/off debug printk in overflow handler */
int fastctxsw; /* turn on/off fast (unsecure) ctxsw */
int expert_mode; /* turn on/off value checking */
} pfm_sysctl_t;
extern pfm_sysctl_t pfm_sysctl;
#endif /* __KERNEL__ */
#endif /* _ASM_IA64_PERFMON_H */
include/asm-ia64/pgalloc.h
+68 -90
View File
@@ -22,146 +22,124 @@
#include <asm/mmu_context.h>
/*
* Very stupidly, we used to get new pgd's and pmd's, init their contents
* to point to the NULL versions of the next level page table, later on
* completely re-init them the same way, then free them up. This wasted
* a lot of work and caused unnecessary memory traffic. How broken...
* We fix this by caching them.
*/
#define pgd_quicklist (local_cpu_data->pgd_quick)
#define pmd_quicklist (local_cpu_data->pmd_quick)
#define pgtable_cache_size (local_cpu_data->pgtable_cache_sz)
DECLARE_PER_CPU(unsigned long *, __pgtable_quicklist);
#define pgtable_quicklist __ia64_per_cpu_var(__pgtable_quicklist)
DECLARE_PER_CPU(long, __pgtable_quicklist_size);
#define pgtable_quicklist_size __ia64_per_cpu_var(__pgtable_quicklist_size)
static inline pgd_t*
pgd_alloc_one_fast (struct mm_struct *mm)
static inline long pgtable_quicklist_total_size(void)
{
long ql_size = 0;
int cpuid;
for_each_online_cpu(cpuid) {
ql_size += per_cpu(__pgtable_quicklist_size, cpuid);
}
return ql_size;
}
static inline void *pgtable_quicklist_alloc(void)
{
unsigned long *ret = NULL;
preempt_disable();
ret = pgd_quicklist;
ret = pgtable_quicklist;
if (likely(ret != NULL)) {
pgd_quicklist = (unsigned long *)(*ret);
pgtable_quicklist = (unsigned long *)(*ret);
ret[0] = 0;
--pgtable_cache_size;
} else
ret = NULL;
preempt_enable();
return (pgd_t *) ret;
}
static inline pgd_t*
pgd_alloc (struct mm_struct *mm)
{
/* the VM system never calls pgd_alloc_one_fast(), so we do it here. */
pgd_t *pgd = pgd_alloc_one_fast(mm);
if (unlikely(pgd == NULL)) {
pgd = (pgd_t *)__get_free_page(GFP_KERNEL|__GFP_ZERO);
--pgtable_quicklist_size;
preempt_enable();
} else {
preempt_enable();
ret = (unsigned long *)__get_free_page(GFP_KERNEL | __GFP_ZERO);
}
return pgd;
return ret;
}
static inline void
pgd_free (pgd_t *pgd)
static inline void pgtable_quicklist_free(void *pgtable_entry)
{
#ifdef CONFIG_NUMA
unsigned long nid = page_to_nid(virt_to_page(pgtable_entry));
if (unlikely(nid != numa_node_id())) {
free_page((unsigned long)pgtable_entry);
return;
}
#endif
preempt_disable();
*(unsigned long *)pgd = (unsigned long) pgd_quicklist;
pgd_quicklist = (unsigned long *) pgd;
++pgtable_cache_size;
*(unsigned long *)pgtable_entry = (unsigned long)pgtable_quicklist;
pgtable_quicklist = (unsigned long *)pgtable_entry;
++pgtable_quicklist_size;
preempt_enable();
}
static inline pgd_t *pgd_alloc(struct mm_struct *mm)
{
return pgtable_quicklist_alloc();
}
static inline void pgd_free(pgd_t * pgd)
{
pgtable_quicklist_free(pgd);
}
static inline void
pud_populate (struct mm_struct *mm, pud_t *pud_entry, pmd_t *pmd)
pud_populate(struct mm_struct *mm, pud_t * pud_entry, pmd_t * pmd)
{
pud_val(*pud_entry) = __pa(pmd);
}
static inline pmd_t*
pmd_alloc_one_fast (struct mm_struct *mm, unsigned long addr)
static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
{
unsigned long *ret = NULL;
preempt_disable();
ret = (unsigned long *)pmd_quicklist;
if (likely(ret != NULL)) {
pmd_quicklist = (unsigned long *)(*ret);
ret[0] = 0;
--pgtable_cache_size;
}
preempt_enable();
return (pmd_t *)ret;
return pgtable_quicklist_alloc();
}
static inline pmd_t*
pmd_alloc_one (struct mm_struct *mm, unsigned long addr)
static inline void pmd_free(pmd_t * pmd)
{
pmd_t *pmd = (pmd_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
return pmd;
}
static inline void
pmd_free (pmd_t *pmd)
{
preempt_disable();
*(unsigned long *)pmd = (unsigned long) pmd_quicklist;
pmd_quicklist = (unsigned long *) pmd;
++pgtable_cache_size;
preempt_enable();
pgtable_quicklist_free(pmd);
}
#define __pmd_free_tlb(tlb, pmd) pmd_free(pmd)
static inline void
pmd_populate (struct mm_struct *mm, pmd_t *pmd_entry, struct page *pte)
pmd_populate(struct mm_struct *mm, pmd_t * pmd_entry, struct page *pte)
{
pmd_val(*pmd_entry) = page_to_phys(pte);
}
static inline void
pmd_populate_kernel (struct mm_struct *mm, pmd_t *pmd_entry, pte_t *pte)
pmd_populate_kernel(struct mm_struct *mm, pmd_t * pmd_entry, pte_t * pte)
{
pmd_val(*pmd_entry) = __pa(pte);
}
static inline struct page *
pte_alloc_one (struct mm_struct *mm, unsigned long addr)
static inline struct page *pte_alloc_one(struct mm_struct *mm,
unsigned long addr)
{
struct page *pte = alloc_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, 0);
return pte;
return virt_to_page(pgtable_quicklist_alloc());
}
static inline pte_t *
pte_alloc_one_kernel (struct mm_struct *mm, unsigned long addr)
static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
unsigned long addr)
{
pte_t *pte = (pte_t *)__get_free_page(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO);
return pte;
return pgtable_quicklist_alloc();
}
static inline void
pte_free (struct page *pte)
static inline void pte_free(struct page *pte)
{
__free_page(pte);
pgtable_quicklist_free(page_address(pte));
}
static inline void
pte_free_kernel (pte_t *pte)
static inline void pte_free_kernel(pte_t * pte)
{
free_page((unsigned long) pte);
pgtable_quicklist_free(pte);
}
#define __pte_free_tlb(tlb, pte) tlb_remove_page((tlb), (pte))
#define __pte_free_tlb(tlb, pte) pte_free(pte)
extern void check_pgt_cache (void);
extern void check_pgt_cache(void);
#endif /* _ASM_IA64_PGALLOC_H */
#endif /* _ASM_IA64_PGALLOC_H */
include/asm-ia64/processor.h
+7 -3
View File
@@ -137,9 +137,6 @@ struct cpuinfo_ia64 {
__u64 nsec_per_cyc; /* (1000000000<<IA64_NSEC_PER_CYC_SHIFT)/itc_freq */
__u64 unimpl_va_mask; /* mask of unimplemented virtual address bits (from PAL) */
__u64 unimpl_pa_mask; /* mask of unimplemented physical address bits (from PAL) */
__u64 *pgd_quick;
__u64 *pmd_quick;
__u64 pgtable_cache_sz;
__u64 itc_freq; /* frequency of ITC counter */
__u64 proc_freq; /* frequency of processor */
__u64 cyc_per_usec; /* itc_freq/1000000 */
@@ -151,6 +148,13 @@ struct cpuinfo_ia64 {
#ifdef CONFIG_SMP
__u64 loops_per_jiffy;
int cpu;
__u32 socket_id; /* physical processor socket id */
__u16 core_id; /* core id */
__u16 thread_id; /* thread id */
__u16 num_log; /* Total number of logical processors on
* this socket that were successfully booted */
__u8 cores_per_socket; /* Cores per processor socket */
__u8 threads_per_core; /* Threads per core */
#endif
/* CPUID-derived information: */
include/asm-ia64/sal.h
+50
View File
@@ -91,6 +91,7 @@ extern spinlock_t sal_lock;
#define SAL_PCI_CONFIG_READ 0x01000010
#define SAL_PCI_CONFIG_WRITE 0x01000011
#define SAL_FREQ_BASE 0x01000012
#define SAL_PHYSICAL_ID_INFO 0x01000013
#define SAL_UPDATE_PAL 0x01000020
@@ -815,6 +816,17 @@ ia64_sal_update_pal (u64 param_buf, u64 scratch_buf, u64 scratch_buf_size,
return isrv.status;
}
/* Get physical processor die mapping in the platform. */
static inline s64
ia64_sal_physical_id_info(u16 *splid)
{
struct ia64_sal_retval isrv;
SAL_CALL(isrv, SAL_PHYSICAL_ID_INFO, 0, 0, 0, 0, 0, 0, 0);
if (splid)
*splid = isrv.v0;
return isrv.status;
}
extern unsigned long sal_platform_features;
extern int (*salinfo_platform_oemdata)(const u8 *, u8 **, u64 *);
@@ -832,6 +844,44 @@ extern int ia64_sal_oemcall_nolock(struct ia64_sal_retval *, u64, u64, u64,
u64, u64, u64, u64, u64);
extern int ia64_sal_oemcall_reentrant(struct ia64_sal_retval *, u64, u64, u64,
u64, u64, u64, u64, u64);
#ifdef CONFIG_HOTPLUG_CPU
/*
* System Abstraction Layer Specification
* Section 3.2.5.1: OS_BOOT_RENDEZ to SAL return State.
* Note: region regs are stored first in head.S _start. Hence they must
* stay up front.
*/
struct sal_to_os_boot {
u64 rr[8]; /* Region Registers */
u64 br[6]; /* br0: return addr into SAL boot rendez routine */
u64 gr1; /* SAL:GP */
u64 gr12; /* SAL:SP */
u64 gr13; /* SAL: Task Pointer */
u64 fpsr;
u64 pfs;
u64 rnat;
u64 unat;
u64 bspstore;
u64 dcr; /* Default Control Register */
u64 iva;
u64 pta;
u64 itv;
u64 pmv;
u64 cmcv;
u64 lrr[2];
u64 gr[4];
u64 pr; /* Predicate registers */
u64 lc; /* Loop Count */
struct ia64_fpreg fp[20];
};
/*
* Global array allocated for NR_CPUS at boot time
*/
extern struct sal_to_os_boot sal_boot_rendez_state[NR_CPUS];
extern void ia64_jump_to_sal(struct sal_to_os_boot *);
#endif
extern void ia64_sal_handler_init(void *entry_point, void *gpval);
include/asm-ia64/siginfo.h
+1 -3
View File
@@ -8,9 +8,7 @@
* David Mosberger-Tang <davidm@hpl.hp.com>, Hewlett-Packard Co
*/
#define SI_PAD_SIZE ((SI_MAX_SIZE/sizeof(int)) - 4)
#define SIGEV_PAD_SIZE ((SIGEV_MAX_SIZE/sizeof(int)) - 4)
#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
#define HAVE_ARCH_SIGINFO_T
#define HAVE_ARCH_COPY_SIGINFO
include/asm-ia64/signal.h
+1 -20
View File
@@ -114,27 +114,11 @@
#define _NSIG_BPW 64
#define _NSIG_WORDS (_NSIG / _NSIG_BPW)
/*
* These values of sa_flags are used only by the kernel as part of the
* irq handling routines.
*
* SA_INTERRUPT is also used by the irq handling routines.
* SA_SHIRQ is for shared interrupt support on PCI and EISA.
*/
#define SA_PROBE SA_ONESHOT
#define SA_SAMPLE_RANDOM SA_RESTART
#define SA_SHIRQ 0x04000000
#define SA_PERCPU_IRQ 0x02000000
#endif /* __KERNEL__ */
#define SIG_BLOCK 0 /* for blocking signals */
#define SIG_UNBLOCK 1 /* for unblocking signals */
#define SIG_SETMASK 2 /* for setting the signal mask */
#define SIG_DFL ((__sighandler_t)0) /* default signal handling */
#define SIG_IGN ((__sighandler_t)1) /* ignore signal */
#define SIG_ERR ((__sighandler_t)-1) /* error return from signal */
#include <asm-generic/signal.h>
# ifndef __ASSEMBLY__
@@ -143,9 +127,6 @@
/* Avoid too many header ordering problems. */
struct siginfo;
/* Type of a signal handler. */
typedef void __user (*__sighandler_t)(int);
typedef struct sigaltstack {
void __user *ss_sp;
int ss_flags;
include/asm-ia64/smp.h
+5
View File
@@ -56,6 +56,10 @@ extern struct smp_boot_data {
extern char no_int_routing __devinitdata;
extern cpumask_t cpu_online_map;
extern cpumask_t cpu_core_map[NR_CPUS];
extern cpumask_t cpu_sibling_map[NR_CPUS];
extern int smp_num_siblings;
extern int smp_num_cpucores;
extern void __iomem *ipi_base_addr;
extern unsigned char smp_int_redirect;
@@ -124,6 +128,7 @@ extern int smp_call_function_single (int cpuid, void (*func) (void *info), void
extern void smp_send_reschedule (int cpu);
extern void lock_ipi_calllock(void);
extern void unlock_ipi_calllock(void);
extern void identify_siblings (struct cpuinfo_ia64 *);
#else
include/asm-ia64/sn/addrs.h
+13 -1
View File
@@ -136,6 +136,7 @@
*/
#define CAC_BASE (CACHED | AS_CAC_SPACE)
#define AMO_BASE (UNCACHED | AS_AMO_SPACE)
#define AMO_PHYS_BASE (UNCACHED_PHYS | AS_AMO_SPACE)
#define GET_BASE (CACHED | AS_GET_SPACE)
/*
@@ -154,11 +155,19 @@
* the chiplet id is zero. If we implement TIO-TIO dma, we might need
* to insert a chiplet id into this macro. However, it is our belief
* right now that this chiplet id will be ICE, which is also zero.
* Nasid starts on bit 40.
*/
#define PHYS_TO_TIODMA(x) ( (((u64)(x) & NASID_MASK) << 2) | NODE_OFFSET(x))
#define PHYS_TO_TIODMA(x) ( (((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
#define PHYS_TO_DMA(x) ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
/*
* Macros to test for address type.
*/
#define IS_AMO_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_BASE)
#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_PHYS_BASE)
/*
* The following definitions pertain to the IO special address
* space. They define the location of the big and little windows
@@ -168,7 +177,10 @@
#define TIO_BWIN_SIZE_BITS 30 /* big window size: 1G */
#define NODE_SWIN_BASE(n, w) ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
: RAW_NODE_SWIN_BASE(n, w))
#define TIO_SWIN_BASE(n, w) (TIO_IO_BASE(n) + \
((u64) (w) << TIO_SWIN_SIZE_BITS))
#define NODE_IO_BASE(n) (GLOBAL_MMR_SPACE | NASID_SPACE(n))
#define TIO_IO_BASE(n) (UNCACHED | NASID_SPACE(n))
#define BWIN_SIZE (1UL << BWIN_SIZE_BITS)
#define NODE_BWIN_BASE0(n) (NODE_IO_BASE(n) + BWIN_SIZE)
#define NODE_BWIN_BASE(n, w) (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
include/asm-ia64/sn/arch.h
+16 -1
View File
@@ -5,7 +5,7 @@
*
* SGI specific setup.
*
* Copyright (C) 1995-1997,1999,2001-2004 Silicon Graphics, Inc. All rights reserved.
* Copyright (C) 1995-1997,1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
* Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
*/
#ifndef _ASM_IA64_SN_ARCH_H
@@ -47,6 +47,21 @@ DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
#define MAX_COMPACT_NODES 2048
#define CPUS_PER_NODE 4
/*
* Compact node ID to nasid mappings kept in the per-cpu data areas of each
* cpu.
*/
DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_NUMNODES]);
#define sn_cnodeid_to_nasid (&__get_cpu_var(__sn_cnodeid_to_nasid[0]))
extern u8 sn_partition_id;
extern u8 sn_system_size;
extern u8 sn_sharing_domain_size;
extern u8 sn_region_size;
extern void sn_flush_all_caches(long addr, long bytes);
#endif /* _ASM_IA64_SN_ARCH_H */
include/asm-ia64/sn/bte.h
+47 -6
View File
@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 2000-2004 Silicon Graphics, Inc. All Rights Reserved.
* Copyright (c) 2000-2005 Silicon Graphics, Inc. All Rights Reserved.
*/
@@ -13,8 +13,12 @@
#include <linux/timer.h>
#include <linux/spinlock.h>
#include <linux/cache.h>
#include <asm/sn/pda.h>
#include <asm/sn/types.h>
#include <asm/sn/shub_mmr.h>
#define IBCT_NOTIFY (0x1UL << 4)
#define IBCT_ZFIL_MODE (0x1UL << 0)
/* #define BTE_DEBUG */
/* #define BTE_DEBUG_VERBOSE */
@@ -39,8 +43,36 @@
/* Define hardware */
#define BTES_PER_NODE 2
#define BTES_PER_NODE (is_shub2() ? 4 : 2)
#define MAX_BTES_PER_NODE 4
#define BTE2OFF_CTRL (0)
#define BTE2OFF_SRC (SH2_BT_ENG_SRC_ADDR_0 - SH2_BT_ENG_CSR_0)
#define BTE2OFF_DEST (SH2_BT_ENG_DEST_ADDR_0 - SH2_BT_ENG_CSR_0)
#define BTE2OFF_NOTIFY (SH2_BT_ENG_NOTIF_ADDR_0 - SH2_BT_ENG_CSR_0)
#define BTE_BASE_ADDR(interface) \
(is_shub2() ? (interface == 0) ? SH2_BT_ENG_CSR_0 : \
(interface == 1) ? SH2_BT_ENG_CSR_1 : \
(interface == 2) ? SH2_BT_ENG_CSR_2 : \
SH2_BT_ENG_CSR_3 \
: (interface == 0) ? IIO_IBLS0 : IIO_IBLS1)
#define BTE_SOURCE_ADDR(base) \
(is_shub2() ? base + (BTE2OFF_SRC/8) \
: base + (BTEOFF_SRC/8))
#define BTE_DEST_ADDR(base) \
(is_shub2() ? base + (BTE2OFF_DEST/8) \
: base + (BTEOFF_DEST/8))
#define BTE_CTRL_ADDR(base) \
(is_shub2() ? base + (BTE2OFF_CTRL/8) \
: base + (BTEOFF_CTRL/8))
#define BTE_NOTIF_ADDR(base) \
(is_shub2() ? base + (BTE2OFF_NOTIFY/8) \
: base + (BTEOFF_NOTIFY/8))
/* Define hardware modes */
#define BTE_NOTIFY (IBCT_NOTIFY)
@@ -68,14 +100,18 @@
#define BTE_LNSTAT_STORE(_bte, _x) \
HUB_S(_bte->bte_base_addr, (_x))
#define BTE_SRC_STORE(_bte, _x) \
HUB_S(_bte->bte_base_addr + (BTEOFF_SRC/8), (_x))
HUB_S(_bte->bte_source_addr, (_x))
#define BTE_DEST_STORE(_bte, _x) \
HUB_S(_bte->bte_base_addr + (BTEOFF_DEST/8), (_x))
HUB_S(_bte->bte_destination_addr, (_x))
#define BTE_CTRL_STORE(_bte, _x) \
HUB_S(_bte->bte_base_addr + (BTEOFF_CTRL/8), (_x))
HUB_S(_bte->bte_control_addr, (_x))
#define BTE_NOTIF_STORE(_bte, _x) \
HUB_S(_bte->bte_base_addr + (BTEOFF_NOTIFY/8), (_x))
HUB_S(_bte->bte_notify_addr, (_x))
#define BTE_START_TRANSFER(_bte, _len, _mode) \
is_shub2() ? BTE_CTRL_STORE(_bte, IBLS_BUSY | (_mode << 24) | _len) \
: BTE_LNSTAT_STORE(_bte, _len); \
BTE_CTRL_STORE(_bte, _mode)
/* Possible results from bte_copy and bte_unaligned_copy */
/* The following error codes map into the BTE hardware codes
@@ -110,6 +146,10 @@ typedef enum {
struct bteinfo_s {
volatile u64 notify ____cacheline_aligned;
u64 *bte_base_addr ____cacheline_aligned;
u64 *bte_source_addr;
u64 *bte_destination_addr;
u64 *bte_control_addr;
u64 *bte_notify_addr;
spinlock_t spinlock;
cnodeid_t bte_cnode; /* cnode */
int bte_error_count; /* Number of errors encountered */
@@ -117,6 +157,7 @@ struct bteinfo_s {
int cleanup_active; /* Interface is locked for cleanup */
volatile bte_result_t bh_error; /* error while processing */
volatile u64 *most_rcnt_na;
struct bteinfo_s *btes_to_try[MAX_BTES_PER_NODE];
};
include/asm-ia64/sn/fetchop.h
-85
View File
@@ -1,85 +0,0 @@
/*
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 2001-2004 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_IA64_SN_FETCHOP_H
#define _ASM_IA64_SN_FETCHOP_H
#include <linux/config.h>
#define FETCHOP_BASENAME "sgi_fetchop"
#define FETCHOP_FULLNAME "/dev/sgi_fetchop"
#define FETCHOP_VAR_SIZE 64 /* 64 byte per fetchop variable */
#define FETCHOP_LOAD 0
#define FETCHOP_INCREMENT 8
#define FETCHOP_DECREMENT 16
#define FETCHOP_CLEAR 24
#define FETCHOP_STORE 0
#define FETCHOP_AND 24
#define FETCHOP_OR 32
#define FETCHOP_CLEAR_CACHE 56
#define FETCHOP_LOAD_OP(addr, op) ( \
*(volatile long *)((char*) (addr) + (op)))
#define FETCHOP_STORE_OP(addr, op, x) ( \
*(volatile long *)((char*) (addr) + (op)) = (long) (x))
#ifdef __KERNEL__
/*
* Convert a region 6 (kaddr) address to the address of the fetchop variable
*/
#define FETCHOP_KADDR_TO_MSPEC_ADDR(kaddr) TO_MSPEC(kaddr)
/*
* Each Atomic Memory Operation (AMO formerly known as fetchop)
* variable is 64 bytes long. The first 8 bytes are used. The
* remaining 56 bytes are unaddressable due to the operation taking
* that portion of the address.
*
* NOTE: The AMO_t _MUST_ be placed in either the first or second half
* of the cache line. The cache line _MUST NOT_ be used for anything
* other than additional AMO_t entries. This is because there are two
* addresses which reference the same physical cache line. One will
* be a cached entry with the memory type bits all set. This address
* may be loaded into processor cache. The AMO_t will be referenced
* uncached via the memory special memory type. If any portion of the
* cached cache-line is modified, when that line is flushed, it will
* overwrite the uncached value in physical memory and lead to
* inconsistency.
*/
typedef struct {
u64 variable;
u64 unused[7];
} AMO_t;
/*
* The following APIs are externalized to the kernel to allocate/free pages of
* fetchop variables.
* fetchop_kalloc_page - Allocate/initialize 1 fetchop page on the
* specified cnode.
* fetchop_kfree_page - Free a previously allocated fetchop page
*/
unsigned long fetchop_kalloc_page(int nid);
void fetchop_kfree_page(unsigned long maddr);
#endif /* __KERNEL__ */
#endif /* _ASM_IA64_SN_FETCHOP_H */
include/asm-ia64/sn/geo.h
+27 -18
View File
@@ -18,32 +18,34 @@
#define GEOID_SIZE 8 /* Would 16 be better? The size can
be different on different platforms. */
#define MAX_SLABS 0xe /* slabs per module */
#define MAX_SLOTS 0xf /* slots per module */
#define MAX_SLABS 0xf /* slabs per slot */
typedef unsigned char geo_type_t;
/* Fields common to all substructures */
typedef struct geo_any_s {
typedef struct geo_common_s {
moduleid_t module; /* The module (box) this h/w lives in */
geo_type_t type; /* What type of h/w is named by this geoid_t */
slabid_t slab; /* The logical assembly within the module */
} geo_any_t;
slabid_t slab:4; /* slab (ASIC), 0 .. 15 within slot */
slotid_t slot:4; /* slot (Blade), 0 .. 15 within module */
} geo_common_t;
/* Additional fields for particular types of hardware */
typedef struct geo_node_s {
geo_any_t any; /* No additional fields needed */
geo_common_t common; /* No additional fields needed */
} geo_node_t;
typedef struct geo_rtr_s {
geo_any_t any; /* No additional fields needed */
geo_common_t common; /* No additional fields needed */
} geo_rtr_t;
typedef struct geo_iocntl_s {
geo_any_t any; /* No additional fields needed */
geo_common_t common; /* No additional fields needed */
} geo_iocntl_t;
typedef struct geo_pcicard_s {
geo_iocntl_t any;
geo_iocntl_t common;
char bus; /* Bus/widget number */
char slot; /* PCI slot number */
} geo_pcicard_t;
@@ -62,14 +64,14 @@ typedef struct geo_mem_s {
typedef union geoid_u {
geo_any_t any;
geo_node_t node;
geo_common_t common;
geo_node_t node;
geo_iocntl_t iocntl;
geo_pcicard_t pcicard;
geo_rtr_t rtr;
geo_cpu_t cpu;
geo_mem_t mem;
char padsize[GEOID_SIZE];
geo_rtr_t rtr;
geo_cpu_t cpu;
geo_mem_t mem;
char padsize[GEOID_SIZE];
} geoid_t;
@@ -104,19 +106,26 @@ typedef union geoid_u {
#define INVALID_CNODEID ((cnodeid_t)-1)
#define INVALID_PNODEID ((pnodeid_t)-1)
#define INVALID_SLAB (slabid_t)-1
#define INVALID_SLOT (slotid_t)-1
#define INVALID_MODULE ((moduleid_t)-1)
#define INVALID_PARTID ((partid_t)-1)
static inline slabid_t geo_slab(geoid_t g)
{
return (g.any.type == GEO_TYPE_INVALID) ?
INVALID_SLAB : g.any.slab;
return (g.common.type == GEO_TYPE_INVALID) ?
INVALID_SLAB : g.common.slab;
}
static inline slotid_t geo_slot(geoid_t g)
{
return (g.common.type == GEO_TYPE_INVALID) ?
INVALID_SLOT : g.common.slot;
}
static inline moduleid_t geo_module(geoid_t g)
{
return (g.any.type == GEO_TYPE_INVALID) ?
INVALID_MODULE : g.any.module;
return (g.common.type == GEO_TYPE_INVALID) ?
INVALID_MODULE : g.common.module;
}
extern geoid_t cnodeid_get_geoid(cnodeid_t cnode);
include/asm-ia64/sn/l1.h
+2 -1
View File
@@ -29,8 +29,9 @@
#define L1_BRICKTYPE_CHI_CG 0x76 /* v */
#define L1_BRICKTYPE_X 0x78 /* x */
#define L1_BRICKTYPE_X2 0x79 /* y */
#define L1_BRICKTYPE_SA 0x5e /* ^ */ /* TIO bringup brick */
#define L1_BRICKTYPE_SA 0x5e /* ^ */
#define L1_BRICKTYPE_PA 0x6a /* j */
#define L1_BRICKTYPE_IA 0x6b /* k */
#define L1_BRICKTYPE_ATHENA 0x2b /* + */
#endif /* _ASM_IA64_SN_L1_H */
include/asm-ia64/sn/nodepda.h
+8 -11
View File
@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
* Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_IA64_SN_NODEPDA_H
#define _ASM_IA64_SN_NODEPDA_H
@@ -13,7 +13,6 @@
#include <asm/irq.h>
#include <asm/sn/arch.h>
#include <asm/sn/intr.h>
#include <asm/sn/pda.h>
#include <asm/sn/bte.h>
/*
@@ -43,7 +42,7 @@ struct nodepda_s {
/*
* The BTEs on this node are shared by the local cpus
*/
struct bteinfo_s bte_if[BTES_PER_NODE]; /* Virtual Interface */
struct bteinfo_s bte_if[MAX_BTES_PER_NODE]; /* Virtual Interface */
struct timer_list bte_recovery_timer;
spinlock_t bte_recovery_lock;
@@ -67,20 +66,18 @@ typedef struct nodepda_s nodepda_t;
* The next set of definitions provides this.
* Routines are expected to use
*
* nodepda -> to access node PDA for the node on which code is running
* subnodepda -> to access subnode PDA for the subnode on which code is running
*
* NODEPDA(cnode) -> to access node PDA for cnodeid
* SUBNODEPDA(cnode,sn) -> to access subnode PDA for cnodeid/subnode
* sn_nodepda - to access node PDA for the node on which code is running
* NODEPDA(cnodeid) - to access node PDA for cnodeid
*/
#define nodepda pda->p_nodepda /* Ptr to this node's PDA */
#define NODEPDA(cnode) (nodepda->pernode_pdaindr[cnode])
DECLARE_PER_CPU(struct nodepda_s *, __sn_nodepda);
#define sn_nodepda (__get_cpu_var(__sn_nodepda))
#define NODEPDA(cnodeid) (sn_nodepda->pernode_pdaindr[cnodeid])
/*
* Check if given a compact node id the corresponding node has all the
* cpus disabled.
*/
#define is_headless_node(cnode) (nr_cpus_node(cnode) == 0)
#define is_headless_node(cnodeid) (nr_cpus_node(cnodeid) == 0)
#endif /* _ASM_IA64_SN_NODEPDA_H */
include/asm-ia64/sn/pcibus_provider_defs.h
+52
View File
@@ -0,0 +1,52 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
#define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
/*
* SN pci asic types. Do not ever renumber these or reuse values. The
* values must agree with what prom thinks they are.
*/
#define PCIIO_ASIC_TYPE_UNKNOWN 0
#define PCIIO_ASIC_TYPE_PPB 1
#define PCIIO_ASIC_TYPE_PIC 2
#define PCIIO_ASIC_TYPE_TIOCP 3
#define PCIIO_ASIC_TYPE_TIOCA 4
#define PCIIO_ASIC_MAX_TYPES 5
/*
* Common pciio bus provider data. There should be one of these as the
* first field in any pciio based provider soft structure (e.g. pcibr_soft
* tioca_soft, etc).
*/
struct pcibus_bussoft {
uint32_t bs_asic_type; /* chipset type */
uint32_t bs_xid; /* xwidget id */
uint64_t bs_persist_busnum; /* Persistent Bus Number */
uint64_t bs_legacy_io; /* legacy io pio addr */
uint64_t bs_legacy_mem; /* legacy mem pio addr */
uint64_t bs_base; /* widget base */
struct xwidget_info *bs_xwidget_info;
};
/*
* SN pci bus indirection
*/
struct sn_pcibus_provider {
dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t);
dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t);
void (*dma_unmap)(struct pci_dev *, dma_addr_t, int);
void * (*bus_fixup)(struct pcibus_bussoft *);
};
extern struct sn_pcibus_provider *sn_pci_provider[];
#endif /* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */
include/asm-ia64/sn/pcidev.h
+58
View File
@@ -0,0 +1,58 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_IA64_SN_PCI_PCIDEV_H
#define _ASM_IA64_SN_PCI_PCIDEV_H
#include <linux/pci.h>
extern struct sn_irq_info **sn_irq;
#define SN_PCIDEV_INFO(pci_dev) \
((struct pcidev_info *)(pci_dev)->sysdata)
/*
* Given a pci_bus, return the sn pcibus_bussoft struct. Note that
* this only works for root busses, not for busses represented by PPB's.
*/
#define SN_PCIBUS_BUSSOFT(pci_bus) \
((struct pcibus_bussoft *)(PCI_CONTROLLER((pci_bus))->platform_data))
/*
* Given a struct pci_dev, return the sn pcibus_bussoft struct. Note
* that this is not equivalent to SN_PCIBUS_BUSSOFT(pci_dev->bus) due
* due to possible PPB's in the path.
*/
#define SN_PCIDEV_BUSSOFT(pci_dev) \
(SN_PCIDEV_INFO(pci_dev)->pdi_host_pcidev_info->pdi_pcibus_info)
#define SN_PCIDEV_BUSPROVIDER(pci_dev) \
(SN_PCIDEV_INFO(pci_dev)->pdi_provider)
#define PCIIO_BUS_NONE 255 /* bus 255 reserved */
#define PCIIO_SLOT_NONE 255
#define PCIIO_FUNC_NONE 255
#define PCIIO_VENDOR_ID_NONE (-1)
struct pcidev_info {
uint64_t pdi_pio_mapped_addr[7]; /* 6 BARs PLUS 1 ROM */
uint64_t pdi_slot_host_handle; /* Bus and devfn Host pci_dev */
struct pcibus_bussoft *pdi_pcibus_info; /* Kernel common bus soft */
struct pcidev_info *pdi_host_pcidev_info; /* Kernel Host pci_dev */
struct pci_dev *pdi_linux_pcidev; /* Kernel pci_dev */
struct sn_irq_info *pdi_sn_irq_info;
struct sn_pcibus_provider *pdi_provider; /* sn pci ops */
};
extern void sn_irq_fixup(struct pci_dev *pci_dev,
struct sn_irq_info *sn_irq_info);
#endif /* _ASM_IA64_SN_PCI_PCIDEV_H */
include/asm-ia64/sn/pda.h
+1 -11
View File
@@ -3,7 +3,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
* Copyright (C) 1992 - 1997, 2000-2005 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_IA64_SN_PDA_H
#define _ASM_IA64_SN_PDA_H
@@ -11,7 +11,6 @@
#include <linux/cache.h>
#include <asm/percpu.h>
#include <asm/system.h>
#include <asm/sn/bte.h>
/*
@@ -25,14 +24,6 @@
typedef struct pda_s {
/* Having a pointer in the begining of PDA tends to increase
* the chance of having this pointer in cache. (Yes something
* else gets pushed out). Doing this reduces the number of memory
* access to all nodepda variables to be one
*/
struct nodepda_s *p_nodepda; /* Pointer to Per node PDA */
struct subnodepda_s *p_subnodepda; /* Pointer to CPU subnode PDA */
/*
* Support for SN LEDs
*/
@@ -50,7 +41,6 @@ typedef struct pda_s {
unsigned long sn_soft_irr[4];
unsigned long sn_in_service_ivecs[4];
short cnodeid_to_nasid_table[MAX_NUMNODES];
int sn_lb_int_war_ticks;
int sn_last_irq;
int sn_first_irq;
include/asm-ia64/sn/shub_mmr.h
+60 -1
View File
@@ -4,7 +4,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 2001-2004 Silicon Graphics, Inc. All rights reserved.
* Copyright (c) 2001-2005 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_IA64_SN_SHUB_MMR_H
@@ -129,6 +129,23 @@
#define SH_EVENT_OCCURRED_II_INT1_SHFT 30
#define SH_EVENT_OCCURRED_II_INT1_MASK 0x0000000040000000
/* SH2_EVENT_OCCURRED_EXTIO_INT2 */
/* Description: Pending SHUB 2 EXT IO INT2 */
#define SH2_EVENT_OCCURRED_EXTIO_INT2_SHFT 33
#define SH2_EVENT_OCCURRED_EXTIO_INT2_MASK 0x0000000200000000
/* SH2_EVENT_OCCURRED_EXTIO_INT3 */
/* Description: Pending SHUB 2 EXT IO INT3 */
#define SH2_EVENT_OCCURRED_EXTIO_INT3_SHFT 34
#define SH2_EVENT_OCCURRED_EXTIO_INT3_MASK 0x0000000400000000
#define SH_ALL_INT_MASK \
(SH_EVENT_OCCURRED_UART_INT_MASK | SH_EVENT_OCCURRED_IPI_INT_MASK | \
SH_EVENT_OCCURRED_II_INT0_MASK | SH_EVENT_OCCURRED_II_INT1_MASK | \
SH_EVENT_OCCURRED_II_INT1_MASK | SH2_EVENT_OCCURRED_EXTIO_INT2_MASK | \
SH2_EVENT_OCCURRED_EXTIO_INT3_MASK)
/* ==================================================================== */
/* LEDS */
/* ==================================================================== */
@@ -367,6 +384,17 @@
#define SH_EVENT_OCCURRED_RTC3_INT_SHFT 26
#define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000
/* ==================================================================== */
/* Register "SH_IPI_ACCESS" */
/* CPU interrupt Access Permission Bits */
/* ==================================================================== */
#define SH1_IPI_ACCESS 0x0000000110060480
#define SH2_IPI_ACCESS0 0x0000000010060c00
#define SH2_IPI_ACCESS1 0x0000000010060c80
#define SH2_IPI_ACCESS2 0x0000000010060d00
#define SH2_IPI_ACCESS3 0x0000000010060d80
/* ==================================================================== */
/* Register "SH_INT_CMPB" */
/* RTC Compare Value for Processor B */
@@ -412,6 +440,19 @@
#define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0
#define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff
/* ==================================================================== */
/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */
/* privilege vector for acc=0 */
/* ==================================================================== */
#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 0x0000000100030300
/* ==================================================================== */
/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */
/* privilege vector for acc=0 */
/* ==================================================================== */
#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 0x0000000100050300
/* ==================================================================== */
/* Some MMRs are functionally identical (or close enough) on both SHUB1 */
@@ -438,4 +479,22 @@
#define SH_INT_CMPC shubmmr(SH, INT_CMPC)
#define SH_INT_CMPD shubmmr(SH, INT_CMPD)
/* ========================================================================== */
/* Register "SH2_BT_ENG_CSR_0" */
/* Engine 0 Control and Status Register */
/* ========================================================================== */
#define SH2_BT_ENG_CSR_0 0x0000000030040000
#define SH2_BT_ENG_SRC_ADDR_0 0x0000000030040080
#define SH2_BT_ENG_DEST_ADDR_0 0x0000000030040100
#define SH2_BT_ENG_NOTIF_ADDR_0 0x0000000030040180
/* ========================================================================== */
/* BTE interfaces 1-3 */
/* ========================================================================== */
#define SH2_BT_ENG_CSR_1 0x0000000030050000
#define SH2_BT_ENG_CSR_2 0x0000000030060000
#define SH2_BT_ENG_CSR_3 0x0000000030070000
#endif /* _ASM_IA64_SN_SHUB_MMR_H */
include/asm-ia64/sn/shubio.h
+1462 -1580
View File
File diff suppressed because it is too large Load Diff
include/asm-ia64/sn/sn_cpuid.h
+11 -14
View File
@@ -4,7 +4,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2000-2004 Silicon Graphics, Inc. All rights reserved.
* Copyright (C) 2000-2005 Silicon Graphics, Inc. All rights reserved.
*/
@@ -92,24 +92,24 @@
* NOTE: on non-MP systems, only cpuid 0 exists
*/
extern short physical_node_map[]; /* indexed by nasid to get cnode */
extern short physical_node_map[]; /* indexed by nasid to get cnode */
/*
* Macros for retrieving info about current cpu
*/
#define get_nasid() (nodepda->phys_cpuid[smp_processor_id()].nasid)
#define get_subnode() (nodepda->phys_cpuid[smp_processor_id()].subnode)
#define get_slice() (nodepda->phys_cpuid[smp_processor_id()].slice)
#define get_cnode() (nodepda->phys_cpuid[smp_processor_id()].cnode)
#define get_sapicid() ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff)
#define get_nasid() (sn_nodepda->phys_cpuid[smp_processor_id()].nasid)
#define get_subnode() (sn_nodepda->phys_cpuid[smp_processor_id()].subnode)
#define get_slice() (sn_nodepda->phys_cpuid[smp_processor_id()].slice)
#define get_cnode() (sn_nodepda->phys_cpuid[smp_processor_id()].cnode)
#define get_sapicid() ((ia64_getreg(_IA64_REG_CR_LID) >> 16) & 0xffff)
/*
* Macros for retrieving info about an arbitrary cpu
* cpuid - logical cpu id
*/
#define cpuid_to_nasid(cpuid) (nodepda->phys_cpuid[cpuid].nasid)
#define cpuid_to_subnode(cpuid) (nodepda->phys_cpuid[cpuid].subnode)
#define cpuid_to_slice(cpuid) (nodepda->phys_cpuid[cpuid].slice)
#define cpuid_to_nasid(cpuid) (sn_nodepda->phys_cpuid[cpuid].nasid)
#define cpuid_to_subnode(cpuid) (sn_nodepda->phys_cpuid[cpuid].subnode)
#define cpuid_to_slice(cpuid) (sn_nodepda->phys_cpuid[cpuid].slice)
#define cpuid_to_cnodeid(cpuid) (physical_node_map[cpuid_to_nasid(cpuid)])
@@ -123,11 +123,8 @@ extern int nasid_slice_to_cpuid(int, int);
/*
* cnodeid_to_nasid - convert a cnodeid to a NASID
* Macro relies on pg_data for a node being on the node itself.
* Just extract the NASID from the pointer.
*
*/
#define cnodeid_to_nasid(cnodeid) pda->cnodeid_to_nasid_table[cnodeid]
#define cnodeid_to_nasid(cnodeid) (sn_cnodeid_to_nasid[cnodeid])
/*
* nasid_to_cnodeid - convert a NASID to a cnodeid
include/asm-ia64/sn/sn_fru.h
-44
View File
@@ -1,44 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1992-1997,1999-2004 Silicon Graphics, Inc. All rights reserved.
*/
#ifndef _ASM_IA64_SN_SN_FRU_H
#define _ASM_IA64_SN_SN_FRU_H
#define MAX_DIMMS 8 /* max # of dimm banks */
#define MAX_PCIDEV 8 /* max # of pci devices on a pci bus */
typedef unsigned char confidence_t;
typedef struct kf_mem_s {
confidence_t km_confidence; /* confidence level that the memory is bad
* is this necessary ?
*/
confidence_t km_dimm[MAX_DIMMS];
/* confidence level that dimm[i] is bad
*I think this is the right number
*/
} kf_mem_t;
typedef struct kf_cpu_s {
confidence_t kc_confidence; /* confidence level that cpu is bad */
confidence_t kc_icache; /* confidence level that instr. cache is bad */
confidence_t kc_dcache; /* confidence level that data cache is bad */
confidence_t kc_scache; /* confidence level that sec. cache is bad */
confidence_t kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
} kf_cpu_t;
typedef struct kf_pci_bus_s {
confidence_t kpb_belief; /* confidence level that the pci bus is bad */
confidence_t kpb_pcidev_belief[MAX_PCIDEV];
/* confidence level that the pci dev is bad */
} kf_pci_bus_t;
#endif /* _ASM_IA64_SN_SN_FRU_H */
include/asm-ia64/sn/sn_sal.h
+89 -22
View File
@@ -8,7 +8,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 2000-2004 Silicon Graphics, Inc. All rights reserved.
* Copyright (c) 2000-2005 Silicon Graphics, Inc. All rights reserved.
*/
@@ -35,8 +35,8 @@
#define SN_SAL_PRINT_ERROR 0x02000012
#define SN_SAL_SET_ERROR_HANDLING_FEATURES 0x0200001a // reentrant
#define SN_SAL_GET_FIT_COMPT 0x0200001b // reentrant
#define SN_SAL_GET_SN_INFO 0x0200001c
#define SN_SAL_GET_SAPIC_INFO 0x0200001d
#define SN_SAL_GET_SN_INFO 0x0200001e
#define SN_SAL_CONSOLE_PUTC 0x02000021
#define SN_SAL_CONSOLE_GETC 0x02000022
#define SN_SAL_CONSOLE_PUTS 0x02000023
@@ -64,6 +64,7 @@
#define SN_SAL_SYSCTL_IOBRICK_PCI_OP 0x02000042 // reentrant
#define SN_SAL_IROUTER_OP 0x02000043
#define SN_SAL_SYSCTL_EVENT 0x02000044
#define SN_SAL_IOIF_INTERRUPT 0x0200004a
#define SN_SAL_HWPERF_OP 0x02000050 // lock
#define SN_SAL_IOIF_ERROR_INTERRUPT 0x02000051
@@ -76,7 +77,8 @@
#define SN_SAL_IOIF_GET_WIDGET_DMAFLUSH_LIST 0x02000058
#define SN_SAL_HUB_ERROR_INTERRUPT 0x02000060
#define SN_SAL_BTE_RECOVER 0x02000061
#define SN_SAL_IOIF_GET_PCI_TOPOLOGY 0x02000062
/*
* Service-specific constants
@@ -555,7 +557,8 @@ static inline u64
ia64_sn_partition_serial_get(void)
{
struct ia64_sal_retval ret_stuff;
SAL_CALL(ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0, 0, 0, 0, 0, 0, 0);
ia64_sal_oemcall_reentrant(&ret_stuff, SN_SAL_PARTITION_SERIAL_GET, 0,
0, 0, 0, 0, 0, 0);
if (ret_stuff.status != 0)
return 0;
return ret_stuff.v0;
@@ -563,11 +566,10 @@ ia64_sn_partition_serial_get(void)
static inline u64
sn_partition_serial_number_val(void) {
if (sn_partition_serial_number) {
return(sn_partition_serial_number);
} else {
return(sn_partition_serial_number = ia64_sn_partition_serial_get());
if (unlikely(sn_partition_serial_number == 0)) {
sn_partition_serial_number = ia64_sn_partition_serial_get();
}
return sn_partition_serial_number;
}
/*
@@ -578,8 +580,8 @@ static inline partid_t
ia64_sn_sysctl_partition_get(nasid_t nasid)
{
struct ia64_sal_retval ret_stuff;
SAL_CALL(ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid,
0, 0, 0, 0, 0, 0);
ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_SYSCTL_PARTITION_GET, nasid,
0, 0, 0, 0, 0, 0);
if (ret_stuff.status != 0)
return INVALID_PARTID;
return ((partid_t)ret_stuff.v0);
@@ -593,11 +595,38 @@ extern partid_t sn_partid;
static inline partid_t
sn_local_partid(void) {
if (sn_partid < 0) {
return (sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id())));
} else {
return sn_partid;
if (unlikely(sn_partid < 0)) {
sn_partid = ia64_sn_sysctl_partition_get(cpuid_to_nasid(smp_processor_id()));
}
return sn_partid;
}
/*
* Returns the physical address of the partition's reserved page through
* an iterative number of calls.
*
* On first call, 'cookie' and 'len' should be set to 0, and 'addr'
* set to the nasid of the partition whose reserved page's address is
* being sought.
* On subsequent calls, pass the values, that were passed back on the
* previous call.
*
* While the return status equals SALRET_MORE_PASSES, keep calling
* this function after first copying 'len' bytes starting at 'addr'
* into 'buf'. Once the return status equals SALRET_OK, 'addr' will
* be the physical address of the partition's reserved page. If the
* return status equals neither of these, an error as occurred.
*/
static inline s64
sn_partition_reserved_page_pa(u64 buf, u64 *cookie, u64 *addr, u64 *len)
{
struct ia64_sal_retval rv;
ia64_sal_oemcall_reentrant(&rv, SN_SAL_GET_PARTITION_ADDR, *cookie,
*addr, buf, *len, 0, 0, 0);
*cookie = rv.v0;
*addr = rv.v1;
*len = rv.v2;
return rv.status;
}
/*
@@ -619,8 +648,8 @@ static inline int
sn_register_xp_addr_region(u64 paddr, u64 len, int operation)
{
struct ia64_sal_retval ret_stuff;
SAL_CALL(ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len, (u64)operation,
0, 0, 0, 0);
ia64_sal_oemcall(&ret_stuff, SN_SAL_XP_ADDR_REGION, paddr, len,
(u64)operation, 0, 0, 0, 0);
return ret_stuff.status;
}
@@ -644,8 +673,8 @@ sn_register_nofault_code(u64 start_addr, u64 end_addr, u64 return_addr,
} else {
call = SN_SAL_NO_FAULT_ZONE_PHYSICAL;
}
SAL_CALL(ret_stuff, call, start_addr, end_addr, return_addr, (u64)1,
0, 0, 0);
ia64_sal_oemcall(&ret_stuff, call, start_addr, end_addr, return_addr,
(u64)1, 0, 0, 0);
return ret_stuff.status;
}
@@ -666,8 +695,8 @@ static inline int
sn_change_coherence(u64 *new_domain, u64 *old_domain)
{
struct ia64_sal_retval ret_stuff;
SAL_CALL(ret_stuff, SN_SAL_COHERENCE, new_domain, old_domain, 0, 0,
0, 0, 0);
ia64_sal_oemcall(&ret_stuff, SN_SAL_COHERENCE, (u64)new_domain,
(u64)old_domain, 0, 0, 0, 0, 0);
return ret_stuff.status;
}
@@ -686,8 +715,8 @@ sn_change_memprotect(u64 paddr, u64 len, u64 perms, u64 *nasid_array)
cnodeid = nasid_to_cnodeid(get_node_number(paddr));
// spin_lock(&NODEPDA(cnodeid)->bist_lock);
local_irq_save(irq_flags);
SAL_CALL_NOLOCK(ret_stuff, SN_SAL_MEMPROTECT, paddr, len, nasid_array,
perms, 0, 0, 0);
ia64_sal_oemcall_nolock(&ret_stuff, SN_SAL_MEMPROTECT, paddr, len,
(u64)nasid_array, perms, 0, 0, 0);
local_irq_restore(irq_flags);
// spin_unlock(&NODEPDA(cnodeid)->bist_lock);
return ret_stuff.status;
@@ -849,6 +878,19 @@ ia64_sn_irtr_intr_disable(nasid_t nasid, int subch, u64 intr)
return (int) rv.v0;
}
/*
* Set up a node as the point of contact for system controller
* environmental event delivery.
*/
static inline int
ia64_sn_sysctl_event_init(nasid_t nasid)
{
struct ia64_sal_retval rv;
SAL_CALL_REENTRANT(rv, SN_SAL_SYSCTL_EVENT, (u64) nasid,
0, 0, 0, 0, 0, 0);
return (int) rv.v0;
}
/**
* ia64_sn_get_fit_compt - read a FIT entry from the PROM header
* @nasid: NASID of node to read
@@ -1012,4 +1054,29 @@ ia64_sn_hwperf_op(nasid_t nasid, u64 opcode, u64 a0, u64 a1, u64 a2,
return (int) rv.status;
}
static inline int
ia64_sn_ioif_get_pci_topology(u64 rack, u64 bay, u64 slot, u64 slab,
u64 buf, u64 len)
{
struct ia64_sal_retval rv;
SAL_CALL_NOLOCK(rv, SN_SAL_IOIF_GET_PCI_TOPOLOGY,
rack, bay, slot, slab, buf, len, 0);
return (int) rv.status;
}
/*
* BTE error recovery is implemented in SAL
*/
static inline int
ia64_sn_bte_recovery(nasid_t nasid)
{
struct ia64_sal_retval rv;
rv.status = 0;
SAL_CALL_NOLOCK(rv, SN_SAL_BTE_RECOVER, 0, 0, 0, 0, 0, 0, 0);
if (rv.status == SALRET_NOT_IMPLEMENTED)
return 0;
return (int) rv.status;
}
#endif /* _ASM_IA64_SN_SN_SAL_H */
include/asm-ia64/sn/sndrv.h
-47
View File
@@ -1,47 +0,0 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 2002-2004 Silicon Graphics, Inc. All Rights Reserved.
*/
#ifndef _ASM_IA64_SN_SNDRV_H
#define _ASM_IA64_SN_SNDRV_H
/* ioctl commands */
#define SNDRV_GET_ROUTERINFO 1
#define SNDRV_GET_INFOSIZE 2
#define SNDRV_GET_HUBINFO 3
#define SNDRV_GET_FLASHLOGSIZE 4
#define SNDRV_SET_FLASHSYNC 5
#define SNDRV_GET_FLASHLOGDATA 6
#define SNDRV_GET_FLASHLOGALL 7
#define SNDRV_SET_HISTOGRAM_TYPE 14
#define SNDRV_ELSC_COMMAND 19
#define SNDRV_CLEAR_LOG 20
#define SNDRV_INIT_LOG 21
#define SNDRV_GET_PIMM_PSC 22
#define SNDRV_SET_PARTITION 23
#define SNDRV_GET_PARTITION 24
/* see synergy_perf_ioctl() */
#define SNDRV_GET_SYNERGY_VERSION 30
#define SNDRV_GET_SYNERGY_STATUS 31
#define SNDRV_GET_SYNERGYINFO 32
#define SNDRV_SYNERGY_APPEND 33
#define SNDRV_SYNERGY_ENABLE 34
#define SNDRV_SYNERGY_FREQ 35
/* Devices */
#define SNDRV_UKNOWN_DEVICE -1
#define SNDRV_ROUTER_DEVICE 1
#define SNDRV_HUB_DEVICE 2
#define SNDRV_ELSC_NVRAM_DEVICE 3
#define SNDRV_ELSC_CONTROLLER_DEVICE 4
#define SNDRV_SYSCTL_SUBCH 5
#define SNDRV_SYNERGY_DEVICE 6
#endif /* _ASM_IA64_SN_SNDRV_H */
include/asm-ia64/sn/tioca.h
+596
View File
@@ -0,0 +1,596 @@
#ifndef _ASM_IA64_SN_TIO_TIOCA_H
#define _ASM_IA64_SN_TIO_TIOCA_H
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (c) 2003-2005 Silicon Graphics, Inc. All rights reserved.
*/
#define TIOCA_PART_NUM 0xE020
#define TIOCA_MFGR_NUM 0x24
#define TIOCA_REV_A 0x1
/*
* Register layout for TIO:CA. See below for bitmasks for each register.
*/
struct tioca {
uint64_t ca_id; /* 0x000000 */
uint64_t ca_control1; /* 0x000008 */
uint64_t ca_control2; /* 0x000010 */
uint64_t ca_status1; /* 0x000018 */
uint64_t ca_status2; /* 0x000020 */
uint64_t ca_gart_aperature; /* 0x000028 */
uint64_t ca_gfx_detach; /* 0x000030 */
uint64_t ca_inta_dest_addr; /* 0x000038 */
uint64_t ca_intb_dest_addr; /* 0x000040 */
uint64_t ca_err_int_dest_addr; /* 0x000048 */
uint64_t ca_int_status; /* 0x000050 */
uint64_t ca_int_status_alias; /* 0x000058 */
uint64_t ca_mult_error; /* 0x000060 */
uint64_t ca_mult_error_alias; /* 0x000068 */
uint64_t ca_first_error; /* 0x000070 */
uint64_t ca_int_mask; /* 0x000078 */
uint64_t ca_crm_pkterr_type; /* 0x000080 */
uint64_t ca_crm_pkterr_type_alias; /* 0x000088 */
uint64_t ca_crm_ct_error_detail_1; /* 0x000090 */
uint64_t ca_crm_ct_error_detail_2; /* 0x000098 */
uint64_t ca_crm_tnumto; /* 0x0000A0 */
uint64_t ca_gart_err; /* 0x0000A8 */
uint64_t ca_pcierr_type; /* 0x0000B0 */
uint64_t ca_pcierr_addr; /* 0x0000B8 */
uint64_t ca_pad_0000C0[3]; /* 0x0000{C0..D0} */
uint64_t ca_pci_rd_buf_flush; /* 0x0000D8 */
uint64_t ca_pci_dma_addr_extn; /* 0x0000E0 */
uint64_t ca_agp_dma_addr_extn; /* 0x0000E8 */
uint64_t ca_force_inta; /* 0x0000F0 */
uint64_t ca_force_intb; /* 0x0000F8 */
uint64_t ca_debug_vector_sel; /* 0x000100 */
uint64_t ca_debug_mux_core_sel; /* 0x000108 */
uint64_t ca_debug_mux_pci_sel; /* 0x000110 */
uint64_t ca_debug_domain_sel; /* 0x000118 */
uint64_t ca_pad_000120[28]; /* 0x0001{20..F8} */
uint64_t ca_gart_ptr_table; /* 0x200 */
uint64_t ca_gart_tlb_addr[8]; /* 0x2{08..40} */
};
/*
* Mask/shift definitions for TIO:CA registers. The convention here is
* to mainly use the names as they appear in the "TIO AEGIS Programmers'
* Reference" with a CA_ prefix added. Some exceptions were made to fix
* duplicate field names or to generalize fields that are common to
* different registers (ca_debug_mux_core_sel and ca_debug_mux_pci_sel for
* example).
*
* Fields consisting of a single bit have a single #define have a single
* macro declaration to mask the bit. Fields consisting of multiple bits
* have two declarations: one to mask the proper bits in a register, and
* a second with the suffix "_SHFT" to identify how far the mask needs to
* be shifted right to get its base value.
*/
/* ==== ca_control1 */
#define CA_SYS_BIG_END (1ull << 0)
#define CA_DMA_AGP_SWAP (1ull << 1)
#define CA_DMA_PCI_SWAP (1ull << 2)
#define CA_PIO_IO_SWAP (1ull << 3)
#define CA_PIO_MEM_SWAP (1ull << 4)
#define CA_GFX_WR_SWAP (1ull << 5)
#define CA_AGP_FW_ENABLE (1ull << 6)
#define CA_AGP_CAL_CYCLE (0x7ull << 7)
#define CA_AGP_CAL_CYCLE_SHFT 7
#define CA_AGP_CAL_PRSCL_BYP (1ull << 10)
#define CA_AGP_INIT_CAL_ENB (1ull << 11)
#define CA_INJ_ADDR_PERR (1ull << 12)
#define CA_INJ_DATA_PERR (1ull << 13)
/* bits 15:14 unused */
#define CA_PCIM_IO_NBE_AD (0x7ull << 16)
#define CA_PCIM_IO_NBE_AD_SHFT 16
#define CA_PCIM_FAST_BTB_ENB (1ull << 19)
/* bits 23:20 unused */
#define CA_PIO_ADDR_OFFSET (0xffull << 24)
#define CA_PIO_ADDR_OFFSET_SHFT 24
/* bits 35:32 unused */
#define CA_AGPDMA_OP_COMBDELAY (0x1full << 36)
#define CA_AGPDMA_OP_COMBDELAY_SHFT 36
/* bit 41 unused */
#define CA_AGPDMA_OP_ENB_COMBDELAY (1ull << 42)
#define CA_PCI_INT_LPCNT (0xffull << 44)
#define CA_PCI_INT_LPCNT_SHFT 44
/* bits 63:52 unused */
/* ==== ca_control2 */
#define CA_AGP_LATENCY_TO (0xffull << 0)
#define CA_AGP_LATENCY_TO_SHFT 0
#define CA_PCI_LATENCY_TO (0xffull << 8)
#define CA_PCI_LATENCY_TO_SHFT 8
#define CA_PCI_MAX_RETRY (0x3ffull << 16)
#define CA_PCI_MAX_RETRY_SHFT 16
/* bits 27:26 unused */
#define CA_RT_INT_EN (0x3ull << 28)
#define CA_RT_INT_EN_SHFT 28
#define CA_MSI_INT_ENB (1ull << 30)
#define CA_PCI_ARB_ERR_ENB (1ull << 31)
#define CA_GART_MEM_PARAM (0x3ull << 32)
#define CA_GART_MEM_PARAM_SHFT 32
#define CA_GART_RD_PREFETCH_ENB (1ull << 34)
#define CA_GART_WR_PREFETCH_ENB (1ull << 35)
#define CA_GART_FLUSH_TLB (1ull << 36)
/* bits 39:37 unused */
#define CA_CRM_TNUMTO_PERIOD (0x1fffull << 40)
#define CA_CRM_TNUMTO_PERIOD_SHFT 40
/* bits 55:53 unused */
#define CA_CRM_TNUMTO_ENB (1ull << 56)
#define CA_CRM_PRESCALER_BYP (1ull << 57)
/* bits 59:58 unused */
#define CA_CRM_MAX_CREDIT (0x7ull << 60)
#define CA_CRM_MAX_CREDIT_SHFT 60
/* bit 63 unused */
/* ==== ca_status1 */
#define CA_CORELET_ID (0x3ull << 0)
#define CA_CORELET_ID_SHFT 0
#define CA_INTA_N (1ull << 2)
#define CA_INTB_N (1ull << 3)
#define CA_CRM_CREDIT_AVAIL (0x7ull << 4)
#define CA_CRM_CREDIT_AVAIL_SHFT 4
/* bit 7 unused */
#define CA_CRM_SPACE_AVAIL (0x7full << 8)
#define CA_CRM_SPACE_AVAIL_SHFT 8
/* bit 15 unused */
#define CA_GART_TLB_VAL (0xffull << 16)
#define CA_GART_TLB_VAL_SHFT 16
/* bits 63:24 unused */
/* ==== ca_status2 */
#define CA_GFX_CREDIT_AVAIL (0xffull << 0)
#define CA_GFX_CREDIT_AVAIL_SHFT 0
#define CA_GFX_OPQ_AVAIL (0xffull << 8)
#define CA_GFX_OPQ_AVAIL_SHFT 8
#define CA_GFX_WRBUFF_AVAIL (0xffull << 16)
#define CA_GFX_WRBUFF_AVAIL_SHFT 16
#define CA_ADMA_OPQ_AVAIL (0xffull << 24)
#define CA_ADMA_OPQ_AVAIL_SHFT 24
#define CA_ADMA_WRBUFF_AVAIL (0xffull << 32)
#define CA_ADMA_WRBUFF_AVAIL_SHFT 32
#define CA_ADMA_RDBUFF_AVAIL (0x7full << 40)
#define CA_ADMA_RDBUFF_AVAIL_SHFT 40
#define CA_PCI_PIO_OP_STAT (1ull << 47)
#define CA_PDMA_OPQ_AVAIL (0xfull << 48)
#define CA_PDMA_OPQ_AVAIL_SHFT 48
#define CA_PDMA_WRBUFF_AVAIL (0xfull << 52)
#define CA_PDMA_WRBUFF_AVAIL_SHFT 52
#define CA_PDMA_RDBUFF_AVAIL (0x3ull << 56)
#define CA_PDMA_RDBUFF_AVAIL_SHFT 56
/* bits 63:58 unused */
/* ==== ca_gart_aperature */
#define CA_GART_AP_ENB_AGP (1ull << 0)
#define CA_GART_PAGE_SIZE (1ull << 1)
#define CA_GART_AP_ENB_PCI (1ull << 2)
/* bits 11:3 unused */
#define CA_GART_AP_SIZE (0x3ffull << 12)
#define CA_GART_AP_SIZE_SHFT 12
#define CA_GART_AP_BASE (0x3ffffffffffull << 22)
#define CA_GART_AP_BASE_SHFT 22
/* ==== ca_inta_dest_addr
==== ca_intb_dest_addr
==== ca_err_int_dest_addr */
/* bits 2:0 unused */
#define CA_INT_DEST_ADDR (0x7ffffffffffffull << 3)
#define CA_INT_DEST_ADDR_SHFT 3
/* bits 55:54 unused */
#define CA_INT_DEST_VECT (0xffull << 56)
#define CA_INT_DEST_VECT_SHFT 56
/* ==== ca_int_status */
/* ==== ca_int_status_alias */
/* ==== ca_mult_error */
/* ==== ca_mult_error_alias */
/* ==== ca_first_error */
/* ==== ca_int_mask */
#define CA_PCI_ERR (1ull << 0)
/* bits 3:1 unused */
#define CA_GART_FETCH_ERR (1ull << 4)
#define CA_GFX_WR_OVFLW (1ull << 5)
#define CA_PIO_REQ_OVFLW (1ull << 6)
#define CA_CRM_PKTERR (1ull << 7)
#define CA_CRM_DVERR (1ull << 8)
#define CA_TNUMTO (1ull << 9)
#define CA_CXM_RSP_CRED_OVFLW (1ull << 10)
#define CA_CXM_REQ_CRED_OVFLW (1ull << 11)
#define CA_PIO_INVALID_ADDR (1ull << 12)
#define CA_PCI_ARB_TO (1ull << 13)
#define CA_AGP_REQ_OFLOW (1ull << 14)
#define CA_SBA_TYPE1_ERR (1ull << 15)
/* bit 16 unused */
#define CA_INTA (1ull << 17)
#define CA_INTB (1ull << 18)
#define CA_MULT_INTA (1ull << 19)
#define CA_MULT_INTB (1ull << 20)
#define CA_GFX_CREDIT_OVFLW (1ull << 21)
/* bits 63:22 unused */
/* ==== ca_crm_pkterr_type */
/* ==== ca_crm_pkterr_type_alias */
#define CA_CRM_PKTERR_SBERR_HDR (1ull << 0)
#define CA_CRM_PKTERR_DIDN (1ull << 1)
#define CA_CRM_PKTERR_PACTYPE (1ull << 2)
#define CA_CRM_PKTERR_INV_TNUM (1ull << 3)
#define CA_CRM_PKTERR_ADDR_RNG (1ull << 4)
#define CA_CRM_PKTERR_ADDR_ALGN (1ull << 5)
#define CA_CRM_PKTERR_HDR_PARAM (1ull << 6)
#define CA_CRM_PKTERR_CW_ERR (1ull << 7)
#define CA_CRM_PKTERR_SBERR_NH (1ull << 8)
#define CA_CRM_PKTERR_EARLY_TERM (1ull << 9)
#define CA_CRM_PKTERR_EARLY_TAIL (1ull << 10)
#define CA_CRM_PKTERR_MSSNG_TAIL (1ull << 11)
#define CA_CRM_PKTERR_MSSNG_HDR (1ull << 12)
/* bits 15:13 unused */
#define CA_FIRST_CRM_PKTERR_SBERR_HDR (1ull << 16)
#define CA_FIRST_CRM_PKTERR_DIDN (1ull << 17)
#define CA_FIRST_CRM_PKTERR_PACTYPE (1ull << 18)
#define CA_FIRST_CRM_PKTERR_INV_TNUM (1ull << 19)
#define CA_FIRST_CRM_PKTERR_ADDR_RNG (1ull << 20)
#define CA_FIRST_CRM_PKTERR_ADDR_ALGN (1ull << 21)
#define CA_FIRST_CRM_PKTERR_HDR_PARAM (1ull << 22)
#define CA_FIRST_CRM_PKTERR_CW_ERR (1ull << 23)
#define CA_FIRST_CRM_PKTERR_SBERR_NH (1ull << 24)
#define CA_FIRST_CRM_PKTERR_EARLY_TERM (1ull << 25)
#define CA_FIRST_CRM_PKTERR_EARLY_TAIL (1ull << 26)
#define CA_FIRST_CRM_PKTERR_MSSNG_TAIL (1ull << 27)
#define CA_FIRST_CRM_PKTERR_MSSNG_HDR (1ull << 28)
/* bits 63:29 unused */
/* ==== ca_crm_ct_error_detail_1 */
#define CA_PKT_TYPE (0xfull << 0)
#define CA_PKT_TYPE_SHFT 0
#define CA_SRC_ID (0x3ull << 4)
#define CA_SRC_ID_SHFT 4
#define CA_DATA_SZ (0x3ull << 6)
#define CA_DATA_SZ_SHFT 6
#define CA_TNUM (0xffull << 8)
#define CA_TNUM_SHFT 8
#define CA_DW_DATA_EN (0xffull << 16)
#define CA_DW_DATA_EN_SHFT 16
#define CA_GFX_CRED (0xffull << 24)
#define CA_GFX_CRED_SHFT 24
#define CA_MEM_RD_PARAM (0x3ull << 32)
#define CA_MEM_RD_PARAM_SHFT 32
#define CA_PIO_OP (1ull << 34)
#define CA_CW_ERR (1ull << 35)
/* bits 62:36 unused */
#define CA_VALID (1ull << 63)
/* ==== ca_crm_ct_error_detail_2 */
/* bits 2:0 unused */
#define CA_PKT_ADDR (0x1fffffffffffffull << 3)
#define CA_PKT_ADDR_SHFT 3
/* bits 63:56 unused */
/* ==== ca_crm_tnumto */
#define CA_CRM_TNUMTO_VAL (0xffull << 0)
#define CA_CRM_TNUMTO_VAL_SHFT 0
#define CA_CRM_TNUMTO_WR (1ull << 8)
/* bits 63:9 unused */
/* ==== ca_gart_err */
#define CA_GART_ERR_SOURCE (0x3ull << 0)
#define CA_GART_ERR_SOURCE_SHFT 0
/* bits 3:2 unused */
#define CA_GART_ERR_ADDR (0xfffffffffull << 4)
#define CA_GART_ERR_ADDR_SHFT 4
/* bits 63:40 unused */
/* ==== ca_pcierr_type */
#define CA_PCIERR_DATA (0xffffffffull << 0)
#define CA_PCIERR_DATA_SHFT 0
#define CA_PCIERR_ENB (0xfull << 32)
#define CA_PCIERR_ENB_SHFT 32
#define CA_PCIERR_CMD (0xfull << 36)
#define CA_PCIERR_CMD_SHFT 36
#define CA_PCIERR_A64 (1ull << 40)
#define CA_PCIERR_SLV_SERR (1ull << 41)
#define CA_PCIERR_SLV_WR_PERR (1ull << 42)
#define CA_PCIERR_SLV_RD_PERR (1ull << 43)
#define CA_PCIERR_MST_SERR (1ull << 44)
#define CA_PCIERR_MST_WR_PERR (1ull << 45)
#define CA_PCIERR_MST_RD_PERR (1ull << 46)
#define CA_PCIERR_MST_MABT (1ull << 47)
#define CA_PCIERR_MST_TABT (1ull << 48)
#define CA_PCIERR_MST_RETRY_TOUT (1ull << 49)
#define CA_PCIERR_TYPES \
(CA_PCIERR_A64|CA_PCIERR_SLV_SERR| \
CA_PCIERR_SLV_WR_PERR|CA_PCIERR_SLV_RD_PERR| \
CA_PCIERR_MST_SERR|CA_PCIERR_MST_WR_PERR|CA_PCIERR_MST_RD_PERR| \
CA_PCIERR_MST_MABT|CA_PCIERR_MST_TABT|CA_PCIERR_MST_RETRY_TOUT)
/* bits 63:50 unused */
/* ==== ca_pci_dma_addr_extn */
#define CA_UPPER_NODE_OFFSET (0x3full << 0)
#define CA_UPPER_NODE_OFFSET_SHFT 0
/* bits 7:6 unused */
#define CA_CHIPLET_ID (0x3ull << 8)
#define CA_CHIPLET_ID_SHFT 8
/* bits 11:10 unused */
#define CA_PCI_DMA_NODE_ID (0xffffull << 12)
#define CA_PCI_DMA_NODE_ID_SHFT 12
/* bits 27:26 unused */
#define CA_PCI_DMA_PIO_MEM_TYPE (1ull << 28)
/* bits 63:29 unused */
/* ==== ca_agp_dma_addr_extn */
/* bits 19:0 unused */
#define CA_AGP_DMA_NODE_ID (0xffffull << 20)
#define CA_AGP_DMA_NODE_ID_SHFT 20
/* bits 27:26 unused */
#define CA_AGP_DMA_PIO_MEM_TYPE (1ull << 28)
/* bits 63:29 unused */
/* ==== ca_debug_vector_sel */
#define CA_DEBUG_MN_VSEL (0xfull << 0)
#define CA_DEBUG_MN_VSEL_SHFT 0
#define CA_DEBUG_PP_VSEL (0xfull << 4)
#define CA_DEBUG_PP_VSEL_SHFT 4
#define CA_DEBUG_GW_VSEL (0xfull << 8)
#define CA_DEBUG_GW_VSEL_SHFT 8
#define CA_DEBUG_GT_VSEL (0xfull << 12)
#define CA_DEBUG_GT_VSEL_SHFT 12
#define CA_DEBUG_PD_VSEL (0xfull << 16)
#define CA_DEBUG_PD_VSEL_SHFT 16
#define CA_DEBUG_AD_VSEL (0xfull << 20)
#define CA_DEBUG_AD_VSEL_SHFT 20
#define CA_DEBUG_CX_VSEL (0xfull << 24)
#define CA_DEBUG_CX_VSEL_SHFT 24
#define CA_DEBUG_CR_VSEL (0xfull << 28)
#define CA_DEBUG_CR_VSEL_SHFT 28
#define CA_DEBUG_BA_VSEL (0xfull << 32)
#define CA_DEBUG_BA_VSEL_SHFT 32
#define CA_DEBUG_PE_VSEL (0xfull << 36)
#define CA_DEBUG_PE_VSEL_SHFT 36
#define CA_DEBUG_BO_VSEL (0xfull << 40)
#define CA_DEBUG_BO_VSEL_SHFT 40
#define CA_DEBUG_BI_VSEL (0xfull << 44)
#define CA_DEBUG_BI_VSEL_SHFT 44
#define CA_DEBUG_AS_VSEL (0xfull << 48)
#define CA_DEBUG_AS_VSEL_SHFT 48
#define CA_DEBUG_PS_VSEL (0xfull << 52)
#define CA_DEBUG_PS_VSEL_SHFT 52
#define CA_DEBUG_PM_VSEL (0xfull << 56)
#define CA_DEBUG_PM_VSEL_SHFT 56
/* bits 63:60 unused */
/* ==== ca_debug_mux_core_sel */
/* ==== ca_debug_mux_pci_sel */
#define CA_DEBUG_MSEL0 (0x7ull << 0)
#define CA_DEBUG_MSEL0_SHFT 0
/* bit 3 unused */
#define CA_DEBUG_NSEL0 (0x7ull << 4)
#define CA_DEBUG_NSEL0_SHFT 4
/* bit 7 unused */
#define CA_DEBUG_MSEL1 (0x7ull << 8)
#define CA_DEBUG_MSEL1_SHFT 8
/* bit 11 unused */
#define CA_DEBUG_NSEL1 (0x7ull << 12)
#define CA_DEBUG_NSEL1_SHFT 12
/* bit 15 unused */
#define CA_DEBUG_MSEL2 (0x7ull << 16)
#define CA_DEBUG_MSEL2_SHFT 16
/* bit 19 unused */
#define CA_DEBUG_NSEL2 (0x7ull << 20)
#define CA_DEBUG_NSEL2_SHFT 20
/* bit 23 unused */
#define CA_DEBUG_MSEL3 (0x7ull << 24)
#define CA_DEBUG_MSEL3_SHFT 24
/* bit 27 unused */
#define CA_DEBUG_NSEL3 (0x7ull << 28)
#define CA_DEBUG_NSEL3_SHFT 28
/* bit 31 unused */
#define CA_DEBUG_MSEL4 (0x7ull << 32)
#define CA_DEBUG_MSEL4_SHFT 32
/* bit 35 unused */
#define CA_DEBUG_NSEL4 (0x7ull << 36)
#define CA_DEBUG_NSEL4_SHFT 36
/* bit 39 unused */
#define CA_DEBUG_MSEL5 (0x7ull << 40)
#define CA_DEBUG_MSEL5_SHFT 40
/* bit 43 unused */
#define CA_DEBUG_NSEL5 (0x7ull << 44)
#define CA_DEBUG_NSEL5_SHFT 44
/* bit 47 unused */
#define CA_DEBUG_MSEL6 (0x7ull << 48)
#define CA_DEBUG_MSEL6_SHFT 48
/* bit 51 unused */
#define CA_DEBUG_NSEL6 (0x7ull << 52)
#define CA_DEBUG_NSEL6_SHFT 52
/* bit 55 unused */
#define CA_DEBUG_MSEL7 (0x7ull << 56)
#define CA_DEBUG_MSEL7_SHFT 56
/* bit 59 unused */
#define CA_DEBUG_NSEL7 (0x7ull << 60)
#define CA_DEBUG_NSEL7_SHFT 60
/* bit 63 unused */
/* ==== ca_debug_domain_sel */
#define CA_DEBUG_DOMAIN_L (1ull << 0)
#define CA_DEBUG_DOMAIN_H (1ull << 1)
/* bits 63:2 unused */
/* ==== ca_gart_ptr_table */
#define CA_GART_PTR_VAL (1ull << 0)
/* bits 11:1 unused */
#define CA_GART_PTR_ADDR (0xfffffffffffull << 12)
#define CA_GART_PTR_ADDR_SHFT 12
/* bits 63:56 unused */
/* ==== ca_gart_tlb_addr[0-7] */
#define CA_GART_TLB_ADDR (0xffffffffffffffull << 0)
#define CA_GART_TLB_ADDR_SHFT 0
/* bits 62:56 unused */
#define CA_GART_TLB_ENTRY_VAL (1ull << 63)
/*
* PIO address space ranges for TIO:CA
*/
/* CA internal registers */
#define CA_PIO_ADMIN 0x00000000
#define CA_PIO_ADMIN_LEN 0x00010000
/* GFX Write Buffer - Diagnostics */
#define CA_PIO_GFX 0x00010000
#define CA_PIO_GFX_LEN 0x00010000
/* AGP DMA Write Buffer - Diagnostics */
#define CA_PIO_AGP_DMAWRITE 0x00020000
#define CA_PIO_AGP_DMAWRITE_LEN 0x00010000
/* AGP DMA READ Buffer - Diagnostics */
#define CA_PIO_AGP_DMAREAD 0x00030000
#define CA_PIO_AGP_DMAREAD_LEN 0x00010000
/* PCI Config Type 0 */
#define CA_PIO_PCI_TYPE0_CONFIG 0x01000000
#define CA_PIO_PCI_TYPE0_CONFIG_LEN 0x01000000
/* PCI Config Type 1 */
#define CA_PIO_PCI_TYPE1_CONFIG 0x02000000
#define CA_PIO_PCI_TYPE1_CONFIG_LEN 0x01000000
/* PCI I/O Cycles - mapped to PCI Address 0x00000000-0x04ffffff */
#define CA_PIO_PCI_IO 0x03000000
#define CA_PIO_PCI_IO_LEN 0x05000000
/* PCI MEM Cycles - mapped to PCI with CA_PIO_ADDR_OFFSET of ca_control1 */
/* use Fast Write if enabled and coretalk packet type is a GFX request */
#define CA_PIO_PCI_MEM_OFFSET 0x08000000
#define CA_PIO_PCI_MEM_OFFSET_LEN 0x08000000
/* PCI MEM Cycles - mapped to PCI Address 0x00000000-0xbfffffff */
/* use Fast Write if enabled and coretalk packet type is a GFX request */
#define CA_PIO_PCI_MEM 0x40000000
#define CA_PIO_PCI_MEM_LEN 0xc0000000
/*
* DMA space
*
* The CA aperature (ie. bus address range) mapped by the GART is segmented into
* two parts. The lower portion of the aperature is used for mapping 32 bit
* PCI addresses which are managed by the dma interfaces in this file. The
* upper poprtion of the aperature is used for mapping 48 bit AGP addresses.
* The AGP portion of the aperature is managed by the agpgart_be.c driver
* in drivers/linux/agp. There are ca-specific hooks in that driver to
* manipulate the gart, but management of the AGP portion of the aperature
* is the responsibility of that driver.
*
* CA allows three main types of DMA mapping:
*
* PCI 64-bit Managed by this driver
* PCI 32-bit Managed by this driver
* AGP 48-bit Managed by hooks in the /dev/agpgart driver
*
* All of the above can optionally be remapped through the GART. The following
* table lists the combinations of addressing types and GART remapping that
* is currently supported by the driver (h/w supports all, s/w limits this):
*
* PCI64 PCI32 AGP48
* GART no yes yes
* Direct yes yes no
*
* GART remapping of PCI64 is not done because there is no need to. The
* 64 bit PCI address holds all of the information necessary to target any
* memory in the system.
*
* AGP48 is always mapped through the GART. Management of the AGP48 portion
* of the aperature is the responsibility of code in the agpgart_be driver.
*
* The non-64 bit bus address space will currently be partitioned like this:
*
* 0xffff_ffff_ffff +--------
* | AGP48 direct
* | Space managed by this driver
* CA_AGP_DIRECT_BASE +--------
* | AGP GART mapped (gfx aperature)
* | Space managed by /dev/agpgart driver
* | This range is exposed to the agpgart
* | driver as the "graphics aperature"
* CA_AGP_MAPPED_BASE +-----
* | PCI GART mapped
* | Space managed by this driver
* CA_PCI32_MAPPED_BASE +----
* | PCI32 direct
* | Space managed by this driver
* 0xC000_0000 +--------
* (CA_PCI32_DIRECT_BASE)
*
* The bus address range CA_PCI32_MAPPED_BASE through CA_AGP_DIRECT_BASE
* is what we call the CA aperature. Addresses falling in this range will
* be remapped using the GART.
*
* The bus address range CA_AGP_MAPPED_BASE through CA_AGP_DIRECT_BASE
* is what we call the graphics aperature. This is a subset of the CA
* aperature and is under the control of the agpgart_be driver.
*
* CA_PCI32_MAPPED_BASE, CA_AGP_MAPPED_BASE, and CA_AGP_DIRECT_BASE are
* somewhat arbitrary values. The known constraints on choosing these is:
*
* 1) CA_AGP_DIRECT_BASE-CA_PCI32_MAPPED_BASE+1 (the CA aperature size)
* must be one of the values supported by the ca_gart_aperature register.
* Currently valid values are: 4MB through 4096MB in powers of 2 increments
*
* 2) CA_AGP_DIRECT_BASE-CA_AGP_MAPPED_BASE+1 (the gfx aperature size)
* must be in MB units since that's what the agpgart driver assumes.
*/
/*
* Define Bus DMA ranges. These are configurable (see constraints above)
* and will probably need tuning based on experience.
*/
/*
* 11/24/03
* CA has an addressing glitch w.r.t. PCI direct 32 bit DMA that makes it
* generally unusable. The problem is that for PCI direct 32
* DMA's, all 32 bits of the bus address are used to form the lower 32 bits
* of the coretalk address, and coretalk bits 38:32 come from a register.
* Since only PCI bus addresses 0xC0000000-0xFFFFFFFF (1GB) are available
* for DMA (the rest is allocated to PIO), host node addresses need to be
* such that their lower 32 bits fall in the 0xC0000000-0xffffffff range
* as well. So there can be no PCI32 direct DMA below 3GB!! For this
* reason we set the CA_PCI32_DIRECT_SIZE to 0 which essentially makes
* tioca_dma_direct32() a noop but preserves the code flow should this issue
* be fixed in a respin.
*
* For now, all PCI32 DMA's must be mapped through the GART.
*/
#define CA_PCI32_DIRECT_BASE 0xC0000000UL /* BASE not configurable */
#define CA_PCI32_DIRECT_SIZE 0x00000000UL /* 0 MB */
#define CA_PCI32_MAPPED_BASE 0xC0000000UL
#define CA_PCI32_MAPPED_SIZE 0x40000000UL /* 2GB */
#define CA_AGP_MAPPED_BASE 0x80000000UL
#define CA_AGP_MAPPED_SIZE 0x40000000UL /* 2GB */
#define CA_AGP_DIRECT_BASE 0x40000000UL /* 2GB */
#define CA_AGP_DIRECT_SIZE 0x40000000UL
#define CA_APERATURE_BASE (CA_AGP_MAPPED_BASE)
#define CA_APERATURE_SIZE (CA_AGP_MAPPED_SIZE+CA_PCI32_MAPPED_SIZE)
#endif /* _ASM_IA64_SN_TIO_TIOCA_H */

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