Merge remote branch 'nouveau/for-airlied' into drm-next-stage
* nouveau/for-airlied: (25 commits) drm/nouveau: use ALIGN instead of open coding it drm/nouveau: report unknown connector state if lid closed drm/nouveau: support version 0x20 displayport tables drm/nouveau: Fix noaccel/nofbaccel option descriptions. drm/nv50: Implement ctxprog/state generation. drm/nouveau: use dcb connector types throughout the driver drm/nv50: enable hpd on any connector we know the gpio line for drm/nouveau: use dcb connector table for creating drm connectors drm/nouveau: construct a connector table for cards that lack a real one drm/nouveau: check for known dcb connector types drm/nouveau: parse dcb gpio/connector tables after encoders drm/nouveau: reorganise bios header, add dcb connector type enums drm/nouveau: merge nvbios and nouveau_bios_info drm/nouveau: merge parsed_dcb and bios_parsed_dcb into dcb_table drm/nouveau: rename parsed_dcb_gpio to dcb_gpio_table drm/nouveau: allow retrieval of vbios image from debugfs drm/nouveau: fix missing spin_unlock in failure path drm/nouveau: fix i2ctable bounds checking drm/nouveau: fix nouveau_i2c_find bounds checking drm/nouveau: fix pramdac_table range checking ... Conflicts: drivers/gpu/drm/nouveau/nouveau_gem.c
This commit is contained in:
Dave Airlie
+32
-54
@@ -25,13 +25,14 @@
|
||||
#ifndef __NOUVEAU_DRM_H__
|
||||
#define __NOUVEAU_DRM_H__
|
||||
|
||||
#define NOUVEAU_DRM_HEADER_PATCHLEVEL 15
|
||||
#define NOUVEAU_DRM_HEADER_PATCHLEVEL 16
|
||||
|
||||
struct drm_nouveau_channel_alloc {
|
||||
uint32_t fb_ctxdma_handle;
|
||||
uint32_t tt_ctxdma_handle;
|
||||
|
||||
int channel;
|
||||
uint32_t pushbuf_domains;
|
||||
|
||||
/* Notifier memory */
|
||||
uint32_t notifier_handle;
|
||||
@@ -109,68 +110,58 @@ struct drm_nouveau_gem_new {
|
||||
uint32_t align;
|
||||
};
|
||||
|
||||
#define NOUVEAU_GEM_MAX_BUFFERS 1024
|
||||
struct drm_nouveau_gem_pushbuf_bo_presumed {
|
||||
uint32_t valid;
|
||||
uint32_t domain;
|
||||
uint64_t offset;
|
||||
};
|
||||
|
||||
struct drm_nouveau_gem_pushbuf_bo {
|
||||
uint64_t user_priv;
|
||||
uint32_t handle;
|
||||
uint32_t read_domains;
|
||||
uint32_t write_domains;
|
||||
uint32_t valid_domains;
|
||||
uint32_t presumed_ok;
|
||||
uint32_t presumed_domain;
|
||||
uint64_t presumed_offset;
|
||||
struct drm_nouveau_gem_pushbuf_bo_presumed presumed;
|
||||
};
|
||||
|
||||
#define NOUVEAU_GEM_RELOC_LOW (1 << 0)
|
||||
#define NOUVEAU_GEM_RELOC_HIGH (1 << 1)
|
||||
#define NOUVEAU_GEM_RELOC_OR (1 << 2)
|
||||
#define NOUVEAU_GEM_MAX_RELOCS 1024
|
||||
struct drm_nouveau_gem_pushbuf_reloc {
|
||||
uint32_t reloc_bo_index;
|
||||
uint32_t reloc_bo_offset;
|
||||
uint32_t bo_index;
|
||||
uint32_t reloc_index;
|
||||
uint32_t flags;
|
||||
uint32_t data;
|
||||
uint32_t vor;
|
||||
uint32_t tor;
|
||||
};
|
||||
|
||||
#define NOUVEAU_GEM_MAX_BUFFERS 1024
|
||||
#define NOUVEAU_GEM_MAX_RELOCS 1024
|
||||
#define NOUVEAU_GEM_MAX_PUSH 512
|
||||
struct drm_nouveau_gem_pushbuf_push {
|
||||
uint32_t bo_index;
|
||||
uint32_t pad;
|
||||
uint64_t offset;
|
||||
uint64_t length;
|
||||
};
|
||||
|
||||
struct drm_nouveau_gem_pushbuf {
|
||||
uint32_t channel;
|
||||
uint32_t nr_dwords;
|
||||
uint32_t nr_buffers;
|
||||
uint32_t nr_relocs;
|
||||
uint64_t dwords;
|
||||
uint64_t buffers;
|
||||
uint64_t relocs;
|
||||
};
|
||||
|
||||
struct drm_nouveau_gem_pushbuf_call {
|
||||
uint32_t channel;
|
||||
uint32_t handle;
|
||||
uint32_t offset;
|
||||
uint32_t nr_buffers;
|
||||
uint32_t nr_relocs;
|
||||
uint32_t nr_dwords;
|
||||
uint64_t buffers;
|
||||
uint32_t nr_push;
|
||||
uint64_t relocs;
|
||||
uint64_t push;
|
||||
uint32_t suffix0;
|
||||
uint32_t suffix1;
|
||||
/* below only accessed for CALL2 */
|
||||
uint64_t vram_available;
|
||||
uint64_t gart_available;
|
||||
};
|
||||
|
||||
struct drm_nouveau_gem_pin {
|
||||
uint32_t handle;
|
||||
uint32_t domain;
|
||||
uint64_t offset;
|
||||
};
|
||||
|
||||
struct drm_nouveau_gem_unpin {
|
||||
uint32_t handle;
|
||||
};
|
||||
|
||||
#define NOUVEAU_GEM_CPU_PREP_NOWAIT 0x00000001
|
||||
#define NOUVEAU_GEM_CPU_PREP_NOBLOCK 0x00000002
|
||||
#define NOUVEAU_GEM_CPU_PREP_WRITE 0x00000004
|
||||
@@ -183,14 +174,6 @@ struct drm_nouveau_gem_cpu_fini {
|
||||
uint32_t handle;
|
||||
};
|
||||
|
||||
struct drm_nouveau_gem_tile {
|
||||
uint32_t handle;
|
||||
uint32_t offset;
|
||||
uint32_t size;
|
||||
uint32_t tile_mode;
|
||||
uint32_t tile_flags;
|
||||
};
|
||||
|
||||
enum nouveau_bus_type {
|
||||
NV_AGP = 0,
|
||||
NV_PCI = 1,
|
||||
@@ -200,22 +183,17 @@ enum nouveau_bus_type {
|
||||
struct drm_nouveau_sarea {
|
||||
};
|
||||
|
||||
#define DRM_NOUVEAU_CARD_INIT 0x00
|
||||
#define DRM_NOUVEAU_GETPARAM 0x01
|
||||
#define DRM_NOUVEAU_SETPARAM 0x02
|
||||
#define DRM_NOUVEAU_CHANNEL_ALLOC 0x03
|
||||
#define DRM_NOUVEAU_CHANNEL_FREE 0x04
|
||||
#define DRM_NOUVEAU_GROBJ_ALLOC 0x05
|
||||
#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x06
|
||||
#define DRM_NOUVEAU_GPUOBJ_FREE 0x07
|
||||
#define DRM_NOUVEAU_GETPARAM 0x00
|
||||
#define DRM_NOUVEAU_SETPARAM 0x01
|
||||
#define DRM_NOUVEAU_CHANNEL_ALLOC 0x02
|
||||
#define DRM_NOUVEAU_CHANNEL_FREE 0x03
|
||||
#define DRM_NOUVEAU_GROBJ_ALLOC 0x04
|
||||
#define DRM_NOUVEAU_NOTIFIEROBJ_ALLOC 0x05
|
||||
#define DRM_NOUVEAU_GPUOBJ_FREE 0x06
|
||||
#define DRM_NOUVEAU_GEM_NEW 0x40
|
||||
#define DRM_NOUVEAU_GEM_PUSHBUF 0x41
|
||||
#define DRM_NOUVEAU_GEM_PUSHBUF_CALL 0x42
|
||||
#define DRM_NOUVEAU_GEM_PIN 0x43 /* !KMS only */
|
||||
#define DRM_NOUVEAU_GEM_UNPIN 0x44 /* !KMS only */
|
||||
#define DRM_NOUVEAU_GEM_CPU_PREP 0x45
|
||||
#define DRM_NOUVEAU_GEM_CPU_FINI 0x46
|
||||
#define DRM_NOUVEAU_GEM_INFO 0x47
|
||||
#define DRM_NOUVEAU_GEM_PUSHBUF_CALL2 0x48
|
||||
#define DRM_NOUVEAU_GEM_CPU_PREP 0x42
|
||||
#define DRM_NOUVEAU_GEM_CPU_FINI 0x43
|
||||
#define DRM_NOUVEAU_GEM_INFO 0x44
|
||||
|
||||
#endif /* __NOUVEAU_DRM_H__ */
|
||||
|
||||
Reference in New Issue
Block a user