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Merge tag 'xtensa-next-20141215' of git://github.com/czankel/xtensa-linux

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Pull Xtensa fixes from Chris Zankel:
 - fix nommu support
 - remove s6000 variant and s6105 platform
 - fix permissions for kmapped pages so that copy_to_user_page works with them
 - add power management menu to Kconfig to allow use of runtime PM
 - disable linker optimizations because of a linker bug
 - fix sparse error

* tag 'xtensa-next-20141215' of git://github.com/czankel/xtensa-linux:
  xtensa: disable link optimization
  xtensa/uaccess: fix sparse errors
  xtensa: fix kmap_prot definition
  xtensa: add power management menu to Kconfig
  xtensa: remove s6000 variant and s6105 platform
  xtensa: make PLATFORM_DEFAULT_MEM parameters configurable
  xtensa: nommu: clean up memory map dump
  xtensa: nommu: reserve memory below PLATFORM_DEFAULT_MEM_START
  xtensa: nommu: set up cache and atomctl in initialize_mmu
  xtensa: move vecbase SR initialization to _startup
  xtensa: nommu: fix uImage load address
  xtensa: nommu: fix load address definitions
  xtensa: nommu: fix Image.elf reset code and ld script
  xtensa: nommu: add MMU dependency to DEBUG_TLB_SANITY
  xtensa: nommu: don't build most of the cache flushing code
  xtensa: nommu: don't provide arch_get_unmapped_area
  xtensa: nommu: provide MAP_UNINITIALIZED definition
  xtensa: nommu: provide _PAGE_CHG_MASK definition
  xtensa: nommu: provide __invalidate_dcache_page_alias stub
  xtensa: nommu: move init_mmu stub to nommu_context.h
This commit is contained in:
Linus Torvalds
2014-12-16 14:08:53 -08:00
parent 0db2812a52 1f2fdbd007
commit a643fc7253
41 changed files with 149 additions and 3042 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/xtensa/include/asm/cacheflush.h
+5 -2
View File
@@ -67,6 +67,8 @@ extern void __invalidate_dcache_page_alias(unsigned long, unsigned long);
#else
static inline void __flush_invalidate_dcache_page_alias(unsigned long virt,
unsigned long phys) { }
static inline void __invalidate_dcache_page_alias(unsigned long virt,
unsigned long phys) { }
#endif
#if defined(CONFIG_MMU) && (ICACHE_WAY_SIZE > PAGE_SIZE)
extern void __invalidate_icache_page_alias(unsigned long, unsigned long);
@@ -84,7 +86,8 @@ static inline void __invalidate_icache_page_alias(unsigned long virt,
* (see also Documentation/cachetlb.txt)
*/
#if (DCACHE_WAY_SIZE > PAGE_SIZE) || defined(CONFIG_SMP)
#if defined(CONFIG_MMU) && \
((DCACHE_WAY_SIZE > PAGE_SIZE) || defined(CONFIG_SMP))
#ifdef CONFIG_SMP
void flush_cache_all(void);
@@ -150,7 +153,7 @@ void local_flush_cache_page(struct vm_area_struct *vma,
#define flush_dcache_mmap_lock(mapping) do { } while (0)
#define flush_dcache_mmap_unlock(mapping) do { } while (0)
#if (DCACHE_WAY_SIZE > PAGE_SIZE)
#if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
extern void copy_to_user_page(struct vm_area_struct*, struct page*,
unsigned long, void*, const void*, unsigned long);
arch/xtensa/include/asm/highmem.h
+1 -1
View File
@@ -25,7 +25,7 @@
#define PKMAP_NR(virt) (((virt) - PKMAP_BASE) >> PAGE_SHIFT)
#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
#define kmap_prot PAGE_KERNEL
#define kmap_prot PAGE_KERNEL_EXEC
#if DCACHE_WAY_SIZE > PAGE_SIZE
#define get_pkmap_color get_pkmap_color
arch/xtensa/include/asm/initialize_mmu.h
+36 -4
View File
@@ -26,8 +26,16 @@
#include <asm/pgtable.h>
#include <asm/vectors.h>
#if XCHAL_HAVE_PTP_MMU
#define CA_BYPASS (_PAGE_CA_BYPASS | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
#define CA_WRITEBACK (_PAGE_CA_WB | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
#else
#define CA_WRITEBACK (0x4)
#endif
#ifndef XCHAL_SPANNING_WAY
#define XCHAL_SPANNING_WAY 0
#endif
#ifdef __ASSEMBLY__
@@ -75,7 +83,7 @@
/* Step 1: invalidate mapping at 0x40000000..0x5FFFFFFF. */
movi a2, 0x40000006
movi a2, 0x40000000 | XCHAL_SPANNING_WAY
idtlb a2
iitlb a2
isync
@@ -141,9 +149,6 @@
jx a4
1:
movi a2, VECBASE_RESET_VADDR
wsr a2, vecbase
/* Step 5: remove temporary mapping. */
idtlb a7
iitlb a7
@@ -156,6 +161,33 @@
#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU &&
XCHAL_HAVE_SPANNING_WAY */
#if !defined(CONFIG_MMU) && XCHAL_HAVE_TLBS
/* Enable data and instruction cache in the DEFAULT_MEMORY region
* if the processor has DTLB and ITLB.
*/
movi a5, PLATFORM_DEFAULT_MEM_START | XCHAL_SPANNING_WAY
movi a6, ~_PAGE_ATTRIB_MASK
movi a7, CA_WRITEBACK
movi a8, 0x20000000
movi a9, PLATFORM_DEFAULT_MEM_SIZE
j 2f
1:
sub a9, a9, a8
2:
rdtlb1 a3, a5
ritlb1 a4, a5
and a3, a3, a6
and a4, a4, a6
or a3, a3, a7
or a4, a4, a7
wdtlb a3, a5
witlb a4, a5
add a5, a5, a8
bltu a8, a9, 1b
#endif
.endm
#endif /*__ASSEMBLY__*/
arch/xtensa/include/asm/mmu_context.h
-4
View File
@@ -50,11 +50,7 @@ DECLARE_PER_CPU(unsigned long, asid_cache);
#define ASID_MASK ((1 << XCHAL_MMU_ASID_BITS) - 1)
#define ASID_INSERT(x) (0x03020001 | (((x) & ASID_MASK) << 8))
#ifdef CONFIG_MMU
void init_mmu(void);
#else
static inline void init_mmu(void) { }
#endif
static inline void set_rasid_register (unsigned long val)
{
arch/xtensa/include/asm/nommu_context.h
+4
View File
@@ -1,3 +1,7 @@
static inline void init_mmu(void)
{
}
static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
{
}
arch/xtensa/include/asm/page.h
+6 -6
View File
@@ -20,10 +20,10 @@
* Fixed TLB translations in the processor.
*/
#define XCHAL_KSEG_CACHED_VADDR 0xd0000000
#define XCHAL_KSEG_BYPASS_VADDR 0xd8000000
#define XCHAL_KSEG_PADDR 0x00000000
#define XCHAL_KSEG_SIZE 0x08000000
#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000)
#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000)
#define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(0x00000000)
#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000)
/*
* PAGE_SHIFT determines the page size
@@ -37,7 +37,7 @@
#define PAGE_OFFSET XCHAL_KSEG_CACHED_VADDR
#define MAX_MEM_PFN XCHAL_KSEG_SIZE
#else
#define PAGE_OFFSET 0
#define PAGE_OFFSET __XTENSA_UL_CONST(0)
#define MAX_MEM_PFN (PLATFORM_DEFAULT_MEM_START + PLATFORM_DEFAULT_MEM_SIZE)
#endif
@@ -145,7 +145,7 @@ extern void copy_page(void *to, void *from);
* some extra work
*/
#if DCACHE_WAY_SIZE > PAGE_SIZE
#if defined(CONFIG_MMU) && DCACHE_WAY_SIZE > PAGE_SIZE
extern void clear_page_alias(void *vaddr, unsigned long paddr);
extern void copy_page_alias(void *to, void *from,
unsigned long to_paddr, unsigned long from_paddr);
arch/xtensa/include/asm/pgtable.h
+1
View File
@@ -178,6 +178,7 @@
#else /* no mmu */
# define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
# define PAGE_NONE __pgprot(0)
# define PAGE_SHARED __pgprot(0)
# define PAGE_COPY __pgprot(0)
arch/xtensa/include/asm/uaccess.h
+2 -2
View File
@@ -320,7 +320,7 @@ __asm__ __volatile__( \
({ \
long __gu_err, __gu_val; \
__get_user_size(__gu_val,(ptr),(size),__gu_err); \
(x) = (__typeof__(*(ptr)))__gu_val; \
(x) = (__force __typeof__(*(ptr)))__gu_val; \
__gu_err; \
})
@@ -330,7 +330,7 @@ __asm__ __volatile__( \
const __typeof__(*(ptr)) *__gu_addr = (ptr); \
if (access_ok(VERIFY_READ,__gu_addr,size)) \
__get_user_size(__gu_val,__gu_addr,(size),__gu_err); \
(x) = (__typeof__(*(ptr)))__gu_val; \
(x) = (__force __typeof__(*(ptr)))__gu_val; \
__gu_err; \
})
arch/xtensa/include/asm/vectors.h
+4 -3
View File
@@ -19,6 +19,7 @@
#define _XTENSA_VECTORS_H
#include <variant/core.h>
#include <platform/hardware.h>
#define XCHAL_KIO_CACHED_VADDR 0xe0000000
#define XCHAL_KIO_BYPASS_VADDR 0xf0000000
@@ -51,13 +52,13 @@
/* MMU Not being used - Virtual == Physical */
/* VECBASE */
#define VIRTUAL_MEMORY_ADDRESS 0x00002000
#define VIRTUAL_MEMORY_ADDRESS (PLATFORM_DEFAULT_MEM_START + 0x2000)
/* Location of the start of the kernel text, _start */
#define KERNELOFFSET 0x00003000
#define KERNELOFFSET (PLATFORM_DEFAULT_MEM_START + 0x3000)
/* Loaded just above possibly live vectors */
#define LOAD_MEMORY_ADDRESS 0x00003000
#define LOAD_MEMORY_ADDRESS (PLATFORM_DEFAULT_MEM_START + 0x3000)
#endif /* CONFIG_MMU */
arch/xtensa/include/uapi/asm/mman.h
+6
View File
@@ -55,6 +55,12 @@
#define MAP_NONBLOCK 0x20000 /* do not block on IO */
#define MAP_STACK 0x40000 /* give out an address that is best suited for process/thread stacks */
#define MAP_HUGETLB 0x80000 /* create a huge page mapping */
#ifdef CONFIG_MMAP_ALLOW_UNINITIALIZED
# define MAP_UNINITIALIZED 0x4000000 /* For anonymous mmap, memory could be
* uninitialized */
#else
# define MAP_UNINITIALIZED 0x0 /* Don't support this flag */
#endif
/*
* Flags for msync