[ARM] S3C24XX: Move files out of include/asm-arm/plat-s3c*
First move of items out of include/asm-arm/plat-s3c* to their new homes under arch/arm/plat-s3c/include/plat and arch/arm/plat-s3c24xx/include/plat directories. Note, we have to create a dummy arch/arm/plat-s3c/Makefile to allow us to add arch/arm/plat-s3c/include/plat to the path. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Ben Dooks
@@ -1,75 +0,0 @@
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/* linux/include/asm-arm/plat-s3c/debug-macro.S
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*
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* Copyright 2005, 2007 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <asm/plat-s3c/regs-serial.h>
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/* The S3C2440 implementations are used by default as they are the
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* most widely re-used */
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.macro fifo_level_s3c2440 rd, rx
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ldr \rd, [ \rx, # S3C2410_UFSTAT ]
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and \rd, \rd, #S3C2440_UFSTAT_TXMASK
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.endm
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#ifndef fifo_level
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#define fifo_level fifo_level_s3c2410
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#endif
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.macro fifo_full_s3c2440 rd, rx
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ldr \rd, [ \rx, # S3C2410_UFSTAT ]
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tst \rd, #S3C2440_UFSTAT_TXFULL
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.endm
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#ifndef fifo_full
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#define fifo_full fifo_full_s3c2440
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#endif
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.macro senduart,rd,rx
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strb \rd, [\rx, # S3C2410_UTXH ]
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.endm
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.macro busyuart, rd, rx
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ldr \rd, [ \rx, # S3C2410_UFCON ]
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tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
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beq 1001f @
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@ FIFO enabled...
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1003:
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fifo_full \rd, \rx
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bne 1003b
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b 1002f
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1001:
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@ busy waiting for non fifo
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ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
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tst \rd, #S3C2410_UTRSTAT_TXFE
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beq 1001b
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1002: @ exit busyuart
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.endm
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.macro waituart,rd,rx
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ldr \rd, [ \rx, # S3C2410_UFCON ]
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tst \rd, #S3C2410_UFCON_FIFOMODE @ fifo enabled?
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beq 1001f @
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@ FIFO enabled...
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1003:
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fifo_level \rd, \rx
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teq \rd, #0
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bne 1003b
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b 1002f
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1001:
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@ idle waiting for non fifo
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ldr \rd, [ \rx, # S3C2410_UTRSTAT ]
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tst \rd, #S3C2410_UTRSTAT_TXFE
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beq 1001b
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1002: @ exit busyuart
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.endm
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@@ -1,232 +0,0 @@
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/* arch/arm/mach-s3c2410/include/mach/regs-serial.h
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*
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* From linux/include/asm-arm/hardware/serial_s3c2410.h
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*
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* Internal header file for Samsung S3C2410 serial ports (UART0-2)
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*
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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*
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* Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
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*
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* Adapted from:
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*
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* Internal header file for MX1ADS serial ports (UART1 & 2)
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*
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* Copyright (C) 2002 Shane Nay (shane@minirl.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef __ASM_ARM_REGS_SERIAL_H
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#define __ASM_ARM_REGS_SERIAL_H
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#define S3C24XX_VA_UART0 (S3C_VA_UART)
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#define S3C24XX_VA_UART1 (S3C_VA_UART + 0x4000 )
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#define S3C24XX_VA_UART2 (S3C_VA_UART + 0x8000 )
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#define S3C24XX_VA_UART3 (S3C_VA_UART + 0xC000 )
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#define S3C2410_PA_UART0 (S3C24XX_PA_UART)
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#define S3C2410_PA_UART1 (S3C24XX_PA_UART + 0x4000 )
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#define S3C2410_PA_UART2 (S3C24XX_PA_UART + 0x8000 )
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#define S3C2443_PA_UART3 (S3C24XX_PA_UART + 0xC000 )
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#define S3C2410_URXH (0x24)
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#define S3C2410_UTXH (0x20)
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#define S3C2410_ULCON (0x00)
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#define S3C2410_UCON (0x04)
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#define S3C2410_UFCON (0x08)
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#define S3C2410_UMCON (0x0C)
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#define S3C2410_UBRDIV (0x28)
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#define S3C2410_UTRSTAT (0x10)
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#define S3C2410_UERSTAT (0x14)
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#define S3C2410_UFSTAT (0x18)
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#define S3C2410_UMSTAT (0x1C)
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#define S3C2410_LCON_CFGMASK ((0xF<<3)|(0x3))
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#define S3C2410_LCON_CS5 (0x0)
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#define S3C2410_LCON_CS6 (0x1)
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#define S3C2410_LCON_CS7 (0x2)
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#define S3C2410_LCON_CS8 (0x3)
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#define S3C2410_LCON_CSMASK (0x3)
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#define S3C2410_LCON_PNONE (0x0)
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#define S3C2410_LCON_PEVEN (0x5 << 3)
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#define S3C2410_LCON_PODD (0x4 << 3)
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#define S3C2410_LCON_PMASK (0x7 << 3)
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#define S3C2410_LCON_STOPB (1<<2)
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#define S3C2410_LCON_IRM (1<<6)
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#define S3C2440_UCON_CLKMASK (3<<10)
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#define S3C2440_UCON_PCLK (0<<10)
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#define S3C2440_UCON_UCLK (1<<10)
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#define S3C2440_UCON_PCLK2 (2<<10)
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#define S3C2440_UCON_FCLK (3<<10)
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#define S3C2443_UCON_EPLL (3<<10)
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#define S3C2440_UCON2_FCLK_EN (1<<15)
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#define S3C2440_UCON0_DIVMASK (15 << 12)
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#define S3C2440_UCON1_DIVMASK (15 << 12)
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#define S3C2440_UCON2_DIVMASK (7 << 12)
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#define S3C2440_UCON_DIVSHIFT (12)
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#define S3C2412_UCON_CLKMASK (3<<10)
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#define S3C2412_UCON_UCLK (1<<10)
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#define S3C2412_UCON_USYSCLK (3<<10)
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#define S3C2412_UCON_PCLK (0<<10)
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#define S3C2412_UCON_PCLK2 (2<<10)
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#define S3C2410_UCON_UCLK (1<<10)
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#define S3C2410_UCON_SBREAK (1<<4)
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#define S3C2410_UCON_TXILEVEL (1<<9)
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#define S3C2410_UCON_RXILEVEL (1<<8)
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#define S3C2410_UCON_TXIRQMODE (1<<2)
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#define S3C2410_UCON_RXIRQMODE (1<<0)
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#define S3C2410_UCON_RXFIFO_TOI (1<<7)
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#define S3C2443_UCON_RXERR_IRQEN (1<<6)
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#define S3C2443_UCON_LOOPBACK (1<<5)
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#define S3C2410_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
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S3C2410_UCON_RXILEVEL | \
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S3C2410_UCON_TXIRQMODE | \
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S3C2410_UCON_RXIRQMODE | \
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S3C2410_UCON_RXFIFO_TOI)
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#define S3C2410_UFCON_FIFOMODE (1<<0)
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#define S3C2410_UFCON_TXTRIG0 (0<<6)
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#define S3C2410_UFCON_RXTRIG8 (1<<4)
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#define S3C2410_UFCON_RXTRIG12 (2<<4)
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/* S3C2440 FIFO trigger levels */
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#define S3C2440_UFCON_RXTRIG1 (0<<4)
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#define S3C2440_UFCON_RXTRIG8 (1<<4)
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#define S3C2440_UFCON_RXTRIG16 (2<<4)
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#define S3C2440_UFCON_RXTRIG32 (3<<4)
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#define S3C2440_UFCON_TXTRIG0 (0<<6)
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#define S3C2440_UFCON_TXTRIG16 (1<<6)
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#define S3C2440_UFCON_TXTRIG32 (2<<6)
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#define S3C2440_UFCON_TXTRIG48 (3<<6)
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#define S3C2410_UFCON_RESETBOTH (3<<1)
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#define S3C2410_UFCON_RESETTX (1<<2)
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#define S3C2410_UFCON_RESETRX (1<<1)
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#define S3C2410_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
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S3C2410_UFCON_TXTRIG0 | \
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S3C2410_UFCON_RXTRIG8 )
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#define S3C2410_UMCOM_AFC (1<<4)
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#define S3C2410_UMCOM_RTS_LOW (1<<0)
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#define S3C2412_UMCON_AFC_63 (0<<5) /* same as s3c2443 */
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#define S3C2412_UMCON_AFC_56 (1<<5)
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#define S3C2412_UMCON_AFC_48 (2<<5)
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#define S3C2412_UMCON_AFC_40 (3<<5)
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#define S3C2412_UMCON_AFC_32 (4<<5)
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#define S3C2412_UMCON_AFC_24 (5<<5)
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#define S3C2412_UMCON_AFC_16 (6<<5)
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#define S3C2412_UMCON_AFC_8 (7<<5)
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#define S3C2410_UFSTAT_TXFULL (1<<9)
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#define S3C2410_UFSTAT_RXFULL (1<<8)
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#define S3C2410_UFSTAT_TXMASK (15<<4)
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#define S3C2410_UFSTAT_TXSHIFT (4)
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#define S3C2410_UFSTAT_RXMASK (15<<0)
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#define S3C2410_UFSTAT_RXSHIFT (0)
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/* UFSTAT S3C2443 same as S3C2440 */
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#define S3C2440_UFSTAT_TXFULL (1<<14)
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#define S3C2440_UFSTAT_RXFULL (1<<6)
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#define S3C2440_UFSTAT_TXSHIFT (8)
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#define S3C2440_UFSTAT_RXSHIFT (0)
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#define S3C2440_UFSTAT_TXMASK (63<<8)
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#define S3C2440_UFSTAT_RXMASK (63)
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#define S3C2410_UTRSTAT_TXE (1<<2)
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#define S3C2410_UTRSTAT_TXFE (1<<1)
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#define S3C2410_UTRSTAT_RXDR (1<<0)
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#define S3C2410_UERSTAT_OVERRUN (1<<0)
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#define S3C2410_UERSTAT_FRAME (1<<2)
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#define S3C2410_UERSTAT_BREAK (1<<3)
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#define S3C2443_UERSTAT_PARITY (1<<1)
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#define S3C2410_UERSTAT_ANY (S3C2410_UERSTAT_OVERRUN | \
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S3C2410_UERSTAT_FRAME | \
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S3C2410_UERSTAT_BREAK)
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#define S3C2410_UMSTAT_CTS (1<<0)
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#define S3C2410_UMSTAT_DeltaCTS (1<<2)
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#define S3C2443_DIVSLOT (0x2C)
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#ifndef __ASSEMBLY__
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/* struct s3c24xx_uart_clksrc
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*
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* this structure defines a named clock source that can be used for the
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* uart, so that the best clock can be selected for the requested baud
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* rate.
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*
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* min_baud and max_baud define the range of baud-rates this clock is
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* acceptable for, if they are both zero, it is assumed any baud rate that
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* can be generated from this clock will be used.
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*
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* divisor gives the divisor from the clock to the one seen by the uart
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*/
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struct s3c24xx_uart_clksrc {
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const char *name;
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unsigned int divisor;
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unsigned int min_baud;
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unsigned int max_baud;
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};
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/* configuration structure for per-machine configurations for the
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* serial port
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*
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* the pointer is setup by the machine specific initialisation from the
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* arch/arm/mach-s3c2410/ directory.
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*/
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struct s3c2410_uartcfg {
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unsigned char hwport; /* hardware port number */
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unsigned char unused;
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unsigned short flags;
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upf_t uart_flags; /* default uart flags */
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unsigned long ucon; /* value of ucon for port */
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unsigned long ulcon; /* value of ulcon for port */
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unsigned long ufcon; /* value of ufcon for port */
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struct s3c24xx_uart_clksrc *clocks;
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unsigned int clocks_size;
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};
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/* s3c24xx_uart_devs
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*
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* this is exported from the core as we cannot use driver_register(),
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* or platform_add_device() before the console_initcall()
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*/
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extern struct platform_device *s3c24xx_uart_devs[3];
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#endif /* __ASSEMBLY__ */
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#endif /* __ASM_ARM_REGS_SERIAL_H */
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@@ -1,115 +0,0 @@
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/* arch/arm/mach-s3c2410/include/mach/regs-timer.h
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*
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* Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
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* http://www.simtec.co.uk/products/SWLINUX/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* S3C2410 Timer configuration
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*/
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#ifndef __ASM_ARCH_REGS_TIMER_H
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#define __ASM_ARCH_REGS_TIMER_H
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#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
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#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
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#define S3C2410_TCFG0 S3C_TIMERREG(0x00)
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#define S3C2410_TCFG1 S3C_TIMERREG(0x04)
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#define S3C2410_TCON S3C_TIMERREG(0x08)
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#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
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#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
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#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
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#define S3C2410_TCFG_DEADZONE_MASK (255<<16)
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#define S3C2410_TCFG_DEADZONE_SHIFT (16)
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#define S3C2410_TCFG1_MUX4_DIV2 (0<<16)
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#define S3C2410_TCFG1_MUX4_DIV4 (1<<16)
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#define S3C2410_TCFG1_MUX4_DIV8 (2<<16)
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#define S3C2410_TCFG1_MUX4_DIV16 (3<<16)
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#define S3C2410_TCFG1_MUX4_TCLK1 (4<<16)
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#define S3C2410_TCFG1_MUX4_MASK (15<<16)
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#define S3C2410_TCFG1_MUX4_SHIFT (16)
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#define S3C2410_TCFG1_MUX3_DIV2 (0<<12)
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#define S3C2410_TCFG1_MUX3_DIV4 (1<<12)
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#define S3C2410_TCFG1_MUX3_DIV8 (2<<12)
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#define S3C2410_TCFG1_MUX3_DIV16 (3<<12)
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#define S3C2410_TCFG1_MUX3_TCLK1 (4<<12)
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#define S3C2410_TCFG1_MUX3_MASK (15<<12)
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#define S3C2410_TCFG1_MUX2_DIV2 (0<<8)
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#define S3C2410_TCFG1_MUX2_DIV4 (1<<8)
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#define S3C2410_TCFG1_MUX2_DIV8 (2<<8)
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#define S3C2410_TCFG1_MUX2_DIV16 (3<<8)
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#define S3C2410_TCFG1_MUX2_TCLK1 (4<<8)
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#define S3C2410_TCFG1_MUX2_MASK (15<<8)
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#define S3C2410_TCFG1_MUX1_DIV2 (0<<4)
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#define S3C2410_TCFG1_MUX1_DIV4 (1<<4)
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#define S3C2410_TCFG1_MUX1_DIV8 (2<<4)
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#define S3C2410_TCFG1_MUX1_DIV16 (3<<4)
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#define S3C2410_TCFG1_MUX1_TCLK0 (4<<4)
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#define S3C2410_TCFG1_MUX1_MASK (15<<4)
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#define S3C2410_TCFG1_MUX0_DIV2 (0<<0)
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#define S3C2410_TCFG1_MUX0_DIV4 (1<<0)
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#define S3C2410_TCFG1_MUX0_DIV8 (2<<0)
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#define S3C2410_TCFG1_MUX0_DIV16 (3<<0)
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#define S3C2410_TCFG1_MUX0_TCLK0 (4<<0)
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#define S3C2410_TCFG1_MUX0_MASK (15<<0)
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#define S3C2410_TCFG1_MUX_DIV2 (0<<0)
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#define S3C2410_TCFG1_MUX_DIV4 (1<<0)
|
||||
#define S3C2410_TCFG1_MUX_DIV8 (2<<0)
|
||||
#define S3C2410_TCFG1_MUX_DIV16 (3<<0)
|
||||
#define S3C2410_TCFG1_MUX_TCLK (4<<0)
|
||||
#define S3C2410_TCFG1_MUX_MASK (15<<0)
|
||||
|
||||
#define S3C2410_TCFG1_SHIFT(x) ((x) * 4)
|
||||
|
||||
/* for each timer, we have an count buffer, an compare buffer and
|
||||
* an observation buffer
|
||||
*/
|
||||
|
||||
/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
|
||||
|
||||
#define S3C2410_TCNTB(tmr) S3C_TIMERREG2(tmr, 0x00)
|
||||
#define S3C2410_TCMPB(tmr) S3C_TIMERREG2(tmr, 0x04)
|
||||
#define S3C2410_TCNTO(tmr) S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
|
||||
|
||||
#define S3C2410_TCON_T4RELOAD (1<<22)
|
||||
#define S3C2410_TCON_T4MANUALUPD (1<<21)
|
||||
#define S3C2410_TCON_T4START (1<<20)
|
||||
|
||||
#define S3C2410_TCON_T3RELOAD (1<<19)
|
||||
#define S3C2410_TCON_T3INVERT (1<<18)
|
||||
#define S3C2410_TCON_T3MANUALUPD (1<<17)
|
||||
#define S3C2410_TCON_T3START (1<<16)
|
||||
|
||||
#define S3C2410_TCON_T2RELOAD (1<<15)
|
||||
#define S3C2410_TCON_T2INVERT (1<<14)
|
||||
#define S3C2410_TCON_T2MANUALUPD (1<<13)
|
||||
#define S3C2410_TCON_T2START (1<<12)
|
||||
|
||||
#define S3C2410_TCON_T1RELOAD (1<<11)
|
||||
#define S3C2410_TCON_T1INVERT (1<<10)
|
||||
#define S3C2410_TCON_T1MANUALUPD (1<<9)
|
||||
#define S3C2410_TCON_T1START (1<<8)
|
||||
|
||||
#define S3C2410_TCON_T0DEADZONE (1<<4)
|
||||
#define S3C2410_TCON_T0RELOAD (1<<3)
|
||||
#define S3C2410_TCON_T0INVERT (1<<2)
|
||||
#define S3C2410_TCON_T0MANUALUPD (1<<1)
|
||||
#define S3C2410_TCON_T0START (1<<0)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_TIMER_H */
|
||||
|
||||
|
||||
|
||||
@@ -27,7 +27,7 @@ static void arch_detect_cpu(void);
|
||||
|
||||
/* defines for UART registers */
|
||||
|
||||
#include <asm/plat-s3c/regs-serial.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <asm/plat-s3c/regs-watchdog.h>
|
||||
|
||||
/* working in physical space... */
|
||||
|
||||
@@ -1,54 +0,0 @@
|
||||
/* linux/include/asm-arm/plat-s3c24xx/cpu.h
|
||||
*
|
||||
* Copyright (c) 2004-2005 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Header file for S3C24XX CPU support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* todo - fix when rmk changes iodescs to use `void __iomem *` */
|
||||
|
||||
#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
|
||||
|
||||
#ifndef MHZ
|
||||
#define MHZ (1000*1000)
|
||||
#endif
|
||||
|
||||
#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
|
||||
|
||||
/* forward declaration */
|
||||
struct s3c24xx_uart_resources;
|
||||
struct platform_device;
|
||||
struct s3c2410_uartcfg;
|
||||
struct map_desc;
|
||||
|
||||
/* core initialisation functions */
|
||||
|
||||
extern void s3c24xx_init_irq(void);
|
||||
|
||||
extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
|
||||
|
||||
extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
|
||||
extern void s3c24xx_init_clocks(int xtal);
|
||||
|
||||
extern void s3c24xx_init_uartdevs(char *name,
|
||||
struct s3c24xx_uart_resources *res,
|
||||
struct s3c2410_uartcfg *cfg, int no);
|
||||
|
||||
/* timer for 2410/2440 */
|
||||
|
||||
struct sys_timer;
|
||||
extern struct sys_timer s3c24xx_timer;
|
||||
|
||||
/* system device classes */
|
||||
|
||||
extern struct sysdev_class s3c2410_sysclass;
|
||||
extern struct sysdev_class s3c2412_sysclass;
|
||||
extern struct sysdev_class s3c2440_sysclass;
|
||||
extern struct sysdev_class s3c2442_sysclass;
|
||||
extern struct sysdev_class s3c2443_sysclass;
|
||||
@@ -1,49 +0,0 @@
|
||||
/* linux/include/asm-arm/plat-s3c24xx/devs.h
|
||||
*
|
||||
* Copyright (c) 2004 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Header file for s3c2410 standard platform devices
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <linux/platform_device.h>
|
||||
|
||||
struct s3c24xx_uart_resources {
|
||||
struct resource *resources;
|
||||
unsigned long nr_resources;
|
||||
};
|
||||
|
||||
extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
|
||||
|
||||
extern struct platform_device *s3c24xx_uart_devs[];
|
||||
extern struct platform_device *s3c24xx_uart_src[];
|
||||
|
||||
extern struct platform_device s3c_device_timer[];
|
||||
|
||||
extern struct platform_device s3c_device_usb;
|
||||
extern struct platform_device s3c_device_lcd;
|
||||
extern struct platform_device s3c_device_wdt;
|
||||
extern struct platform_device s3c_device_i2c;
|
||||
extern struct platform_device s3c_device_iis;
|
||||
extern struct platform_device s3c_device_rtc;
|
||||
extern struct platform_device s3c_device_adc;
|
||||
extern struct platform_device s3c_device_sdi;
|
||||
extern struct platform_device s3c_device_hsmmc;
|
||||
|
||||
extern struct platform_device s3c_device_spi0;
|
||||
extern struct platform_device s3c_device_spi1;
|
||||
|
||||
extern struct platform_device s3c_device_nand;
|
||||
|
||||
extern struct platform_device s3c_device_usbgadget;
|
||||
|
||||
/* s3c2440 specific devices */
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
|
||||
extern struct platform_device s3c_device_camif;
|
||||
|
||||
#endif
|
||||
@@ -1,109 +0,0 @@
|
||||
/* linux/include/asm-arm/plat-s3c24xx/irq.h
|
||||
*
|
||||
* Copyright (c) 2004-2005 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Header file for S3C24XX CPU IRQ support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#define irqdbf(x...)
|
||||
#define irqdbf2(x...)
|
||||
|
||||
#define EXTINT_OFF (IRQ_EINT4 - 4)
|
||||
|
||||
/* these are exported for arch/arm/mach-* usage */
|
||||
extern struct irq_chip s3c_irq_level_chip;
|
||||
extern struct irq_chip s3c_irq_chip;
|
||||
|
||||
static inline void
|
||||
s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
|
||||
int subcheck)
|
||||
{
|
||||
unsigned long mask;
|
||||
unsigned long submask;
|
||||
|
||||
submask = __raw_readl(S3C2410_INTSUBMSK);
|
||||
mask = __raw_readl(S3C2410_INTMSK);
|
||||
|
||||
submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
|
||||
|
||||
/* check to see if we need to mask the parent IRQ */
|
||||
|
||||
if ((submask & subcheck) == subcheck) {
|
||||
__raw_writel(mask | parentbit, S3C2410_INTMSK);
|
||||
}
|
||||
|
||||
/* write back masks */
|
||||
__raw_writel(submask, S3C2410_INTSUBMSK);
|
||||
|
||||
}
|
||||
|
||||
static inline void
|
||||
s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
|
||||
{
|
||||
unsigned long mask;
|
||||
unsigned long submask;
|
||||
|
||||
submask = __raw_readl(S3C2410_INTSUBMSK);
|
||||
mask = __raw_readl(S3C2410_INTMSK);
|
||||
|
||||
submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
|
||||
mask &= ~parentbit;
|
||||
|
||||
/* write back masks */
|
||||
__raw_writel(submask, S3C2410_INTSUBMSK);
|
||||
__raw_writel(mask, S3C2410_INTMSK);
|
||||
}
|
||||
|
||||
|
||||
static inline void
|
||||
s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
|
||||
{
|
||||
unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
|
||||
|
||||
s3c_irqsub_mask(irqno, parentmask, group);
|
||||
|
||||
__raw_writel(bit, S3C2410_SUBSRCPND);
|
||||
|
||||
/* only ack parent if we've got all the irqs (seems we must
|
||||
* ack, all and hope that the irq system retriggers ok when
|
||||
* the interrupt goes off again)
|
||||
*/
|
||||
|
||||
if (1) {
|
||||
__raw_writel(parentmask, S3C2410_SRCPND);
|
||||
__raw_writel(parentmask, S3C2410_INTPND);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void
|
||||
s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
|
||||
{
|
||||
unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
|
||||
|
||||
__raw_writel(bit, S3C2410_SUBSRCPND);
|
||||
|
||||
/* only ack parent if we've got all the irqs (seems we must
|
||||
* ack, all and hope that the irq system retriggers ok when
|
||||
* the interrupt goes off again)
|
||||
*/
|
||||
|
||||
if (1) {
|
||||
__raw_writel(parentmask, S3C2410_SRCPND);
|
||||
__raw_writel(parentmask, S3C2410_INTPND);
|
||||
}
|
||||
}
|
||||
|
||||
/* exported for use in arch/arm/mach-s3c2410 */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern int s3c_irq_wake(unsigned int irqno, unsigned int state);
|
||||
#else
|
||||
#define s3c_irq_wake NULL
|
||||
#endif
|
||||
|
||||
extern int s3c_irqext_type(unsigned int irq, unsigned int type);
|
||||
@@ -1,73 +0,0 @@
|
||||
/* linux/include/asm-arm/plat-s3c24xx/pm.h
|
||||
*
|
||||
* Copyright (c) 2004 Simtec Electronics
|
||||
* Written by Ben Dooks, <ben@simtec.co.uk>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* s3c2410_pm_init
|
||||
*
|
||||
* called from board at initialisation time to setup the power
|
||||
* management
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
|
||||
extern __init int s3c2410_pm_init(void);
|
||||
|
||||
#else
|
||||
|
||||
static inline int s3c2410_pm_init(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* configuration for the IRQ mask over sleep */
|
||||
extern unsigned long s3c_irqwake_intmask;
|
||||
extern unsigned long s3c_irqwake_eintmask;
|
||||
|
||||
/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
|
||||
extern unsigned long s3c_irqwake_intallow;
|
||||
extern unsigned long s3c_irqwake_eintallow;
|
||||
|
||||
/* per-cpu sleep functions */
|
||||
|
||||
extern void (*pm_cpu_prep)(void);
|
||||
extern void (*pm_cpu_sleep)(void);
|
||||
|
||||
/* Flags for PM Control */
|
||||
|
||||
extern unsigned long s3c_pm_flags;
|
||||
|
||||
/* from sleep.S */
|
||||
|
||||
extern int s3c2410_cpu_save(unsigned long *saveblk);
|
||||
extern void s3c2410_cpu_suspend(void);
|
||||
extern void s3c2410_cpu_resume(void);
|
||||
|
||||
extern unsigned long s3c2410_sleep_save_phys;
|
||||
|
||||
/* sleep save info */
|
||||
|
||||
struct sleep_save {
|
||||
void __iomem *reg;
|
||||
unsigned long val;
|
||||
};
|
||||
|
||||
#define SAVE_ITEM(x) \
|
||||
{ .reg = (x) }
|
||||
|
||||
extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count);
|
||||
extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count);
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
|
||||
extern int s3c24xx_irq_resume(struct sys_device *dev);
|
||||
#else
|
||||
#define s3c24xx_irq_suspend NULL
|
||||
#define s3c24xx_irq_resume NULL
|
||||
#endif
|
||||
@@ -1,31 +0,0 @@
|
||||
/* linux/include/asm-arm/plat-s3c24xx/s3c2400.h
|
||||
*
|
||||
* Copyright (c) 2004 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Header file for S3C2400 cpu support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* Modifications:
|
||||
* 09-Fev-2006 LCVR First version, based on s3c2410.h
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2400
|
||||
|
||||
extern int s3c2400_init(void);
|
||||
|
||||
extern void s3c2400_map_io(struct map_desc *mach_desc, int size);
|
||||
|
||||
extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
|
||||
extern void s3c2400_init_clocks(int xtal);
|
||||
|
||||
#else
|
||||
#define s3c2400_init_clocks NULL
|
||||
#define s3c2400_init_uarts NULL
|
||||
#define s3c2400_map_io NULL
|
||||
#define s3c2400_init NULL
|
||||
#endif
|
||||
@@ -1,31 +0,0 @@
|
||||
/* linux/include/asm-arm/plat-s3c24xx/s3c2410.h
|
||||
*
|
||||
* Copyright (c) 2004 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Header file for s3c2410 machine directory
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2410
|
||||
|
||||
extern int s3c2410_init(void);
|
||||
|
||||
extern void s3c2410_map_io(struct map_desc *mach_desc, int size);
|
||||
|
||||
extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
|
||||
extern void s3c2410_init_clocks(int xtal);
|
||||
|
||||
#else
|
||||
#define s3c2410_init_clocks NULL
|
||||
#define s3c2410_init_uarts NULL
|
||||
#define s3c2410_map_io NULL
|
||||
#define s3c2410_init NULL
|
||||
#endif
|
||||
|
||||
extern int s3c2410_baseclk_add(void);
|
||||
@@ -1,17 +0,0 @@
|
||||
/* linux/include/asm-arm/plat-s3c24xx/s3c2440.h
|
||||
*
|
||||
* Copyright (c) 2004-2005 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Header file for s3c2440 cpu support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2440
|
||||
extern int s3c2440_init(void);
|
||||
#else
|
||||
#define s3c2440_init NULL
|
||||
#endif
|
||||
@@ -1,17 +0,0 @@
|
||||
/* linux/include/asm-arm/plat-s3c24xx/s3c2442.h
|
||||
*
|
||||
* Copyright (c) 2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Header file for s3c2442 cpu support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2442
|
||||
extern int s3c2442_init(void);
|
||||
#else
|
||||
#define s3c2442_init NULL
|
||||
#endif
|
||||
@@ -1,32 +0,0 @@
|
||||
/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h
|
||||
*
|
||||
* Copyright (c) 2004-2005 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Header file for s3c2443 cpu support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_CPU_S3C2443
|
||||
|
||||
struct s3c2410_uartcfg;
|
||||
|
||||
extern int s3c2443_init(void);
|
||||
|
||||
extern void s3c2443_map_io(struct map_desc *mach_desc, int size);
|
||||
|
||||
extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
|
||||
|
||||
extern void s3c2443_init_clocks(int xtal);
|
||||
|
||||
extern int s3c2443_baseclk_add(void);
|
||||
|
||||
#else
|
||||
#define s3c2443_init_clocks NULL
|
||||
#define s3c2443_init_uarts NULL
|
||||
#define s3c2443_map_io NULL
|
||||
#define s3c2443_init NULL
|
||||
#endif
|
||||
Reference in New Issue
Block a user