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Merge commit 'v2.6.38-rc3' into next

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This commit is contained in:
Dmitry Torokhov
2011-01-31 21:16:22 -08:00
parent 723d928417 ebf53826e1
commit a1f3d4bba8
9226 changed files with 580606 additions and 278736 deletions
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include/linux/mfd/ab8500.h
+32 -26
View File
@@ -74,32 +74,37 @@
#define AB8500_INT_ACC_DETECT_21DB_F 37
#define AB8500_INT_ACC_DETECT_21DB_R 38
#define AB8500_INT_GP_SW_ADC_CONV_END 39
#define AB8500_INT_BTEMP_LOW 72
#define AB8500_INT_BTEMP_LOW_MEDIUM 73
#define AB8500_INT_BTEMP_MEDIUM_HIGH 74
#define AB8500_INT_BTEMP_HIGH 75
#define AB8500_INT_USB_CHARGER_NOT_OK 81
#define AB8500_INT_ID_WAKEUP_R 82
#define AB8500_INT_ID_DET_R1R 84
#define AB8500_INT_ID_DET_R2R 85
#define AB8500_INT_ID_DET_R3R 86
#define AB8500_INT_ID_DET_R4R 87
#define AB8500_INT_ID_WAKEUP_F 88
#define AB8500_INT_ID_DET_R1F 90
#define AB8500_INT_ID_DET_R2F 91
#define AB8500_INT_ID_DET_R3F 92
#define AB8500_INT_ID_DET_R4F 93
#define AB8500_INT_USB_CHG_DET_DONE 94
#define AB8500_INT_USB_CH_TH_PROT_F 96
#define AB8500_INT_USB_CH_TH_PROP_R 97
#define AB8500_INT_MAIN_CH_TH_PROP_F 98
#define AB8500_INT_MAIN_CH_TH_PROT_R 99
#define AB8500_INT_USB_CHARGER_NOT_OKF 103
#define AB8500_INT_ADP_SOURCE_ERROR 72
#define AB8500_INT_ADP_SINK_ERROR 73
#define AB8500_INT_ADP_PROBE_PLUG 74
#define AB8500_INT_ADP_PROBE_UNPLUG 75
#define AB8500_INT_ADP_SENSE_OFF 76
#define AB8500_INT_USB_PHY_POWER_ERR 78
#define AB8500_INT_USB_LINK_STATUS 79
#define AB8500_INT_BTEMP_LOW 80
#define AB8500_INT_BTEMP_LOW_MEDIUM 81
#define AB8500_INT_BTEMP_MEDIUM_HIGH 82
#define AB8500_INT_BTEMP_HIGH 83
#define AB8500_INT_USB_CHARGER_NOT_OK 89
#define AB8500_INT_ID_WAKEUP_R 90
#define AB8500_INT_ID_DET_R1R 92
#define AB8500_INT_ID_DET_R2R 93
#define AB8500_INT_ID_DET_R3R 94
#define AB8500_INT_ID_DET_R4R 95
#define AB8500_INT_ID_WAKEUP_F 96
#define AB8500_INT_ID_DET_R1F 98
#define AB8500_INT_ID_DET_R2F 99
#define AB8500_INT_ID_DET_R3F 100
#define AB8500_INT_ID_DET_R4F 101
#define AB8500_INT_USB_CHG_DET_DONE 102
#define AB8500_INT_USB_CH_TH_PROT_F 104
#define AB8500_INT_USB_CH_TH_PROT_R 105
#define AB8500_INT_MAIN_CH_TH_PROT_F 106
#define AB8500_INT_MAIN_CH_TH_PROT_R 107
#define AB8500_INT_USB_CHARGER_NOT_OKF 111
#define AB8500_NR_IRQS 104
#define AB8500_NUM_IRQ_REGS 13
#define AB8500_NUM_REGULATORS 15
#define AB8500_NR_IRQS 112
#define AB8500_NUM_IRQ_REGS 14
/**
* struct ab8500 - ab8500 internal structure
@@ -145,7 +150,8 @@ struct regulator_init_data;
struct ab8500_platform_data {
int irq_base;
void (*init) (struct ab8500 *);
struct regulator_init_data *regulator[AB8500_NUM_REGULATORS];
int num_regulator;
struct regulator_init_data *regulator;
};
extern int __devinit ab8500_init(struct ab8500 *ab8500);
include/linux/mfd/core.h
+7 -1
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@@ -39,7 +39,7 @@ struct mfd_cell {
size_t data_size;
/*
* This resources can be specified relatievly to the parent device.
* This resources can be specified relatively to the parent device.
* For accessing device you should use resources from device
*/
int num_resources;
@@ -47,6 +47,12 @@ struct mfd_cell {
/* don't check for resource conflicts */
bool ignore_resource_conflicts;
/*
* Disable runtime PM callbacks for this subdevice - see
* pm_runtime_no_callbacks().
*/
bool pm_runtime_no_callbacks;
};
extern int mfd_add_devices(struct device *parent, int id,
include/linux/mfd/max8998-private.h
+2
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@@ -159,10 +159,12 @@ struct max8998_dev {
u8 irq_masks_cur[MAX8998_NUM_IRQ_REGS];
u8 irq_masks_cache[MAX8998_NUM_IRQ_REGS];
int type;
bool wakeup;
};
int max8998_irq_init(struct max8998_dev *max8998);
void max8998_irq_exit(struct max8998_dev *max8998);
int max8998_irq_resume(struct max8998_dev *max8998);
extern int max8998_read_reg(struct i2c_client *i2c, u8 reg, u8 *dest);
extern int max8998_bulk_read(struct i2c_client *i2c, u8 reg, int count,
include/linux/mfd/max8998.h
+25 -6
View File
@@ -70,24 +70,43 @@ struct max8998_regulator_data {
* @num_regulators: number of regultors used
* @irq_base: base IRQ number for max8998, required for IRQs
* @ono: power onoff IRQ number for max8998
* @buck1_max_voltage1: BUCK1 maximum alowed voltage register 1
* @buck1_max_voltage2: BUCK1 maximum alowed voltage register 2
* @buck2_max_voltage: BUCK2 maximum alowed voltage
* @buck_voltage_lock: Do NOT change the values of the following six
* registers set by buck?_voltage?. The voltage of BUCK1/2 cannot
* be other than the preset values.
* @buck1_voltage1: BUCK1 DVS mode 1 voltage register
* @buck1_voltage2: BUCK1 DVS mode 2 voltage register
* @buck1_voltage3: BUCK1 DVS mode 3 voltage register
* @buck1_voltage4: BUCK1 DVS mode 4 voltage register
* @buck2_voltage1: BUCK2 DVS mode 1 voltage register
* @buck2_voltage2: BUCK2 DVS mode 2 voltage register
* @buck1_set1: BUCK1 gpio pin 1 to set output voltage
* @buck1_set2: BUCK1 gpio pin 2 to set output voltage
* @buck1_default_idx: Default for BUCK1 gpio pin 1, 2
* @buck2_set3: BUCK2 gpio pin to set output voltage
* @buck2_default_idx: Default for BUCK2 gpio pin.
* @wakeup: Allow to wake up from suspend
* @rtc_delay: LP3974 RTC chip bug that requires delay after a register
* write before reading it.
*/
struct max8998_platform_data {
struct max8998_regulator_data *regulators;
int num_regulators;
int irq_base;
int ono;
int buck1_max_voltage1;
int buck1_max_voltage2;
int buck2_max_voltage;
bool buck_voltage_lock;
int buck1_voltage1;
int buck1_voltage2;
int buck1_voltage3;
int buck1_voltage4;
int buck2_voltage1;
int buck2_voltage2;
int buck1_set1;
int buck1_set2;
int buck1_default_idx;
int buck2_set3;
int buck2_default_idx;
bool wakeup;
bool rtc_delay;
};
#endif /* __LINUX_MFD_MAX8998_H */
include/linux/mfd/mc13783.h
+34 -33
View File
@@ -1,4 +1,5 @@
/*
* Copyright 2010 Yong Shen <yong.shen@linaro.org>
* Copyright 2009-2010 Pengutronix
* Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
*
@@ -122,39 +123,39 @@ int mc13783_adc_do_conversion(struct mc13783 *mc13783, unsigned int mode,
unsigned int channel, unsigned int *sample);
#define MC13783_SW_SW1A 0
#define MC13783_SW_SW1B 1
#define MC13783_SW_SW2A 2
#define MC13783_SW_SW2B 3
#define MC13783_SW_SW3 4
#define MC13783_SW_PLL 5
#define MC13783_REGU_VAUDIO 6
#define MC13783_REGU_VIOHI 7
#define MC13783_REGU_VIOLO 8
#define MC13783_REGU_VDIG 9
#define MC13783_REGU_VGEN 10
#define MC13783_REGU_VRFDIG 11
#define MC13783_REGU_VRFREF 12
#define MC13783_REGU_VRFCP 13
#define MC13783_REGU_VSIM 14
#define MC13783_REGU_VESIM 15
#define MC13783_REGU_VCAM 16
#define MC13783_REGU_VRFBG 17
#define MC13783_REGU_VVIB 18
#define MC13783_REGU_VRF1 19
#define MC13783_REGU_VRF2 20
#define MC13783_REGU_VMMC1 21
#define MC13783_REGU_VMMC2 22
#define MC13783_REGU_GPO1 23
#define MC13783_REGU_GPO2 24
#define MC13783_REGU_GPO3 25
#define MC13783_REGU_GPO4 26
#define MC13783_REGU_V1 27
#define MC13783_REGU_V2 28
#define MC13783_REGU_V3 29
#define MC13783_REGU_V4 30
#define MC13783_REGU_PWGT1SPI 31
#define MC13783_REGU_PWGT2SPI 32
#define MC13783_REG_SW1A 0
#define MC13783_REG_SW1B 1
#define MC13783_REG_SW2A 2
#define MC13783_REG_SW2B 3
#define MC13783_REG_SW3 4
#define MC13783_REG_PLL 5
#define MC13783_REG_VAUDIO 6
#define MC13783_REG_VIOHI 7
#define MC13783_REG_VIOLO 8
#define MC13783_REG_VDIG 9
#define MC13783_REG_VGEN 10
#define MC13783_REG_VRFDIG 11
#define MC13783_REG_VRFREF 12
#define MC13783_REG_VRFCP 13
#define MC13783_REG_VSIM 14
#define MC13783_REG_VESIM 15
#define MC13783_REG_VCAM 16
#define MC13783_REG_VRFBG 17
#define MC13783_REG_VVIB 18
#define MC13783_REG_VRF1 19
#define MC13783_REG_VRF2 20
#define MC13783_REG_VMMC1 21
#define MC13783_REG_VMMC2 22
#define MC13783_REG_GPO1 23
#define MC13783_REG_GPO2 24
#define MC13783_REG_GPO3 25
#define MC13783_REG_GPO4 26
#define MC13783_REG_V1 27
#define MC13783_REG_V2 28
#define MC13783_REG_V3 29
#define MC13783_REG_V4 30
#define MC13783_REG_PWGT1SPI 31
#define MC13783_REG_PWGT2SPI 32
#define MC13783_IRQ_ADCDONE MC13XXX_IRQ_ADCDONE
#define MC13783_IRQ_ADCBISDONE MC13XXX_IRQ_ADCBISDONE
include/linux/mfd/mc13892.h
+39
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@@ -0,0 +1,39 @@
/*
* Copyright 2010 Yong Shen <yong.shen@linaro.org>
*
* This program is free software; you can redistribute it and/or modify it under
* the terms of the GNU General Public License version 2 as published by the
* Free Software Foundation.
*/
#ifndef __LINUX_MFD_MC13892_H
#define __LINUX_MFD_MC13892_H
#include <linux/mfd/mc13xxx.h>
#define MC13892_SW1 0
#define MC13892_SW2 1
#define MC13892_SW3 2
#define MC13892_SW4 3
#define MC13892_SWBST 4
#define MC13892_VIOHI 5
#define MC13892_VPLL 6
#define MC13892_VDIG 7
#define MC13892_VSD 8
#define MC13892_VUSB2 9
#define MC13892_VVIDEO 10
#define MC13892_VAUDIO 11
#define MC13892_VCAM 12
#define MC13892_VGEN1 13
#define MC13892_VGEN2 14
#define MC13892_VGEN3 15
#define MC13892_VUSB 16
#define MC13892_GPO1 17
#define MC13892_GPO2 18
#define MC13892_GPO3 19
#define MC13892_GPO4 20
#define MC13892_PWGT1SPI 21
#define MC13892_PWGT2SPI 22
#define MC13892_VCOINCELL 23
#endif
include/linux/mfd/tc35892.h
-136
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@@ -1,136 +0,0 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License, version 2
*/
#ifndef __LINUX_MFD_TC35892_H
#define __LINUX_MFD_TC35892_H
#include <linux/device.h>
#define TC35892_RSTCTRL_IRQRST (1 << 4)
#define TC35892_RSTCTRL_TIMRST (1 << 3)
#define TC35892_RSTCTRL_ROTRST (1 << 2)
#define TC35892_RSTCTRL_KBDRST (1 << 1)
#define TC35892_RSTCTRL_GPIRST (1 << 0)
#define TC35892_IRQST 0x91
#define TC35892_MANFCODE_MAGIC 0x03
#define TC35892_MANFCODE 0x80
#define TC35892_VERSION 0x81
#define TC35892_IOCFG 0xA7
#define TC35892_CLKMODE 0x88
#define TC35892_CLKCFG 0x89
#define TC35892_CLKEN 0x8A
#define TC35892_RSTCTRL 0x82
#define TC35892_EXTRSTN 0x83
#define TC35892_RSTINTCLR 0x84
#define TC35892_GPIOIS0 0xC9
#define TC35892_GPIOIS1 0xCA
#define TC35892_GPIOIS2 0xCB
#define TC35892_GPIOIBE0 0xCC
#define TC35892_GPIOIBE1 0xCD
#define TC35892_GPIOIBE2 0xCE
#define TC35892_GPIOIEV0 0xCF
#define TC35892_GPIOIEV1 0xD0
#define TC35892_GPIOIEV2 0xD1
#define TC35892_GPIOIE0 0xD2
#define TC35892_GPIOIE1 0xD3
#define TC35892_GPIOIE2 0xD4
#define TC35892_GPIORIS0 0xD6
#define TC35892_GPIORIS1 0xD7
#define TC35892_GPIORIS2 0xD8
#define TC35892_GPIOMIS0 0xD9
#define TC35892_GPIOMIS1 0xDA
#define TC35892_GPIOMIS2 0xDB
#define TC35892_GPIOIC0 0xDC
#define TC35892_GPIOIC1 0xDD
#define TC35892_GPIOIC2 0xDE
#define TC35892_GPIODATA0 0xC0
#define TC35892_GPIOMASK0 0xc1
#define TC35892_GPIODATA1 0xC2
#define TC35892_GPIOMASK1 0xc3
#define TC35892_GPIODATA2 0xC4
#define TC35892_GPIOMASK2 0xC5
#define TC35892_GPIODIR0 0xC6
#define TC35892_GPIODIR1 0xC7
#define TC35892_GPIODIR2 0xC8
#define TC35892_GPIOSYNC0 0xE6
#define TC35892_GPIOSYNC1 0xE7
#define TC35892_GPIOSYNC2 0xE8
#define TC35892_GPIOWAKE0 0xE9
#define TC35892_GPIOWAKE1 0xEA
#define TC35892_GPIOWAKE2 0xEB
#define TC35892_GPIOODM0 0xE0
#define TC35892_GPIOODE0 0xE1
#define TC35892_GPIOODM1 0xE2
#define TC35892_GPIOODE1 0xE3
#define TC35892_GPIOODM2 0xE4
#define TC35892_GPIOODE2 0xE5
#define TC35892_INT_GPIIRQ 0
#define TC35892_INT_TI0IRQ 1
#define TC35892_INT_TI1IRQ 2
#define TC35892_INT_TI2IRQ 3
#define TC35892_INT_ROTIRQ 5
#define TC35892_INT_KBDIRQ 6
#define TC35892_INT_PORIRQ 7
#define TC35892_NR_INTERNAL_IRQS 8
#define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x))
struct tc35892 {
struct mutex lock;
struct device *dev;
struct i2c_client *i2c;
int irq_base;
int num_gpio;
struct tc35892_platform_data *pdata;
};
extern int tc35892_reg_write(struct tc35892 *tc35892, u8 reg, u8 data);
extern int tc35892_reg_read(struct tc35892 *tc35892, u8 reg);
extern int tc35892_block_read(struct tc35892 *tc35892, u8 reg, u8 length,
u8 *values);
extern int tc35892_block_write(struct tc35892 *tc35892, u8 reg, u8 length,
const u8 *values);
extern int tc35892_set_bits(struct tc35892 *tc35892, u8 reg, u8 mask, u8 val);
/**
* struct tc35892_gpio_platform_data - TC35892 GPIO platform data
* @gpio_base: first gpio number assigned to TC35892. A maximum of
* %TC35892_NR_GPIOS GPIOs will be allocated.
* @setup: callback for board-specific initialization
* @remove: callback for board-specific teardown
*/
struct tc35892_gpio_platform_data {
int gpio_base;
void (*setup)(struct tc35892 *tc35892, unsigned gpio_base);
void (*remove)(struct tc35892 *tc35892, unsigned gpio_base);
};
/**
* struct tc35892_platform_data - TC35892 platform data
* @irq_base: base IRQ number. %TC35892_NR_IRQS irqs will be used.
* @gpio: GPIO-specific platform data
*/
struct tc35892_platform_data {
int irq_base;
struct tc35892_gpio_platform_data *gpio;
};
#define TC35892_NR_GPIOS 24
#define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS)
#endif
include/linux/mfd/tc3589x.h
+195
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@@ -0,0 +1,195 @@
/*
* Copyright (C) ST-Ericsson SA 2010
*
* License Terms: GNU General Public License, version 2
*/
#ifndef __LINUX_MFD_TC3589x_H
#define __LINUX_MFD_TC3589x_H
#include <linux/device.h>
enum tx3589x_block {
TC3589x_BLOCK_GPIO = 1 << 0,
TC3589x_BLOCK_KEYPAD = 1 << 1,
};
#define TC3589x_RSTCTRL_IRQRST (1 << 4)
#define TC3589x_RSTCTRL_TIMRST (1 << 3)
#define TC3589x_RSTCTRL_ROTRST (1 << 2)
#define TC3589x_RSTCTRL_KBDRST (1 << 1)
#define TC3589x_RSTCTRL_GPIRST (1 << 0)
/* Keyboard Configuration Registers */
#define TC3589x_KBDSETTLE_REG 0x01
#define TC3589x_KBDBOUNCE 0x02
#define TC3589x_KBDSIZE 0x03
#define TC3589x_KBCFG_LSB 0x04
#define TC3589x_KBCFG_MSB 0x05
#define TC3589x_KBDIC 0x08
#define TC3589x_KBDMSK 0x09
#define TC3589x_EVTCODE_FIFO 0x10
#define TC3589x_KBDMFS 0x8F
#define TC3589x_IRQST 0x91
#define TC3589x_MANFCODE_MAGIC 0x03
#define TC3589x_MANFCODE 0x80
#define TC3589x_VERSION 0x81
#define TC3589x_IOCFG 0xA7
#define TC3589x_CLKMODE 0x88
#define TC3589x_CLKCFG 0x89
#define TC3589x_CLKEN 0x8A
#define TC3589x_RSTCTRL 0x82
#define TC3589x_EXTRSTN 0x83
#define TC3589x_RSTINTCLR 0x84
/* Pull up/down configuration registers */
#define TC3589x_IOCFG 0xA7
#define TC3589x_IOPULLCFG0_LSB 0xAA
#define TC3589x_IOPULLCFG0_MSB 0xAB
#define TC3589x_IOPULLCFG1_LSB 0xAC
#define TC3589x_IOPULLCFG1_MSB 0xAD
#define TC3589x_IOPULLCFG2_LSB 0xAE
#define TC3589x_GPIOIS0 0xC9
#define TC3589x_GPIOIS1 0xCA
#define TC3589x_GPIOIS2 0xCB
#define TC3589x_GPIOIBE0 0xCC
#define TC3589x_GPIOIBE1 0xCD
#define TC3589x_GPIOIBE2 0xCE
#define TC3589x_GPIOIEV0 0xCF
#define TC3589x_GPIOIEV1 0xD0
#define TC3589x_GPIOIEV2 0xD1
#define TC3589x_GPIOIE0 0xD2
#define TC3589x_GPIOIE1 0xD3
#define TC3589x_GPIOIE2 0xD4
#define TC3589x_GPIORIS0 0xD6
#define TC3589x_GPIORIS1 0xD7
#define TC3589x_GPIORIS2 0xD8
#define TC3589x_GPIOMIS0 0xD9
#define TC3589x_GPIOMIS1 0xDA
#define TC3589x_GPIOMIS2 0xDB
#define TC3589x_GPIOIC0 0xDC
#define TC3589x_GPIOIC1 0xDD
#define TC3589x_GPIOIC2 0xDE
#define TC3589x_GPIODATA0 0xC0
#define TC3589x_GPIOMASK0 0xc1
#define TC3589x_GPIODATA1 0xC2
#define TC3589x_GPIOMASK1 0xc3
#define TC3589x_GPIODATA2 0xC4
#define TC3589x_GPIOMASK2 0xC5
#define TC3589x_GPIODIR0 0xC6
#define TC3589x_GPIODIR1 0xC7
#define TC3589x_GPIODIR2 0xC8
#define TC3589x_GPIOSYNC0 0xE6
#define TC3589x_GPIOSYNC1 0xE7
#define TC3589x_GPIOSYNC2 0xE8
#define TC3589x_GPIOWAKE0 0xE9
#define TC3589x_GPIOWAKE1 0xEA
#define TC3589x_GPIOWAKE2 0xEB
#define TC3589x_GPIOODM0 0xE0
#define TC3589x_GPIOODE0 0xE1
#define TC3589x_GPIOODM1 0xE2
#define TC3589x_GPIOODE1 0xE3
#define TC3589x_GPIOODM2 0xE4
#define TC3589x_GPIOODE2 0xE5
#define TC3589x_INT_GPIIRQ 0
#define TC3589x_INT_TI0IRQ 1
#define TC3589x_INT_TI1IRQ 2
#define TC3589x_INT_TI2IRQ 3
#define TC3589x_INT_ROTIRQ 5
#define TC3589x_INT_KBDIRQ 6
#define TC3589x_INT_PORIRQ 7
#define TC3589x_NR_INTERNAL_IRQS 8
#define TC3589x_INT_GPIO(x) (TC3589x_NR_INTERNAL_IRQS + (x))
struct tc3589x {
struct mutex lock;
struct device *dev;
struct i2c_client *i2c;
int irq_base;
int num_gpio;
struct tc3589x_platform_data *pdata;
};
extern int tc3589x_reg_write(struct tc3589x *tc3589x, u8 reg, u8 data);
extern int tc3589x_reg_read(struct tc3589x *tc3589x, u8 reg);
extern int tc3589x_block_read(struct tc3589x *tc3589x, u8 reg, u8 length,
u8 *values);
extern int tc3589x_block_write(struct tc3589x *tc3589x, u8 reg, u8 length,
const u8 *values);
extern int tc3589x_set_bits(struct tc3589x *tc3589x, u8 reg, u8 mask, u8 val);
/*
* Keypad related platform specific constants
* These values may be modified for fine tuning
*/
#define TC_KPD_ROWS 0x8
#define TC_KPD_COLUMNS 0x8
#define TC_KPD_DEBOUNCE_PERIOD 0xA3
#define TC_KPD_SETTLE_TIME 0xA3
/**
* struct tc35893_platform_data - data structure for platform specific data
* @keymap_data: matrix scan code table for keycodes
* @krow: mask for available rows, value is 0xFF
* @kcol: mask for available columns, value is 0xFF
* @debounce_period: platform specific debounce time
* @settle_time: platform specific settle down time
* @irqtype: type of interrupt, falling or rising edge
* @enable_wakeup: specifies if keypad event can wake up system from sleep
* @no_autorepeat: flag for auto repetition
*/
struct tc3589x_keypad_platform_data {
const struct matrix_keymap_data *keymap_data;
u8 krow;
u8 kcol;
u8 debounce_period;
u8 settle_time;
unsigned long irqtype;
bool enable_wakeup;
bool no_autorepeat;
};
/**
* struct tc3589x_gpio_platform_data - TC3589x GPIO platform data
* @gpio_base: first gpio number assigned to TC3589x. A maximum of
* %TC3589x_NR_GPIOS GPIOs will be allocated.
* @setup: callback for board-specific initialization
* @remove: callback for board-specific teardown
*/
struct tc3589x_gpio_platform_data {
int gpio_base;
void (*setup)(struct tc3589x *tc3589x, unsigned gpio_base);
void (*remove)(struct tc3589x *tc3589x, unsigned gpio_base);
};
/**
* struct tc3589x_platform_data - TC3589x platform data
* @block: bitmask of blocks to enable (use TC3589x_BLOCK_*)
* @irq_base: base IRQ number. %TC3589x_NR_IRQS irqs will be used.
* @gpio: GPIO-specific platform data
* @keypad: keypad-specific platform data
*/
struct tc3589x_platform_data {
unsigned int block;
int irq_base;
struct tc3589x_gpio_platform_data *gpio;
const struct tc3589x_keypad_platform_data *keypad;
};
#define TC3589x_NR_GPIOS 24
#define TC3589x_NR_IRQS TC3589x_INT_GPIO(TC3589x_NR_GPIOS)
#endif
include/linux/mfd/tmio.h
+5
View File
@@ -57,6 +57,10 @@
* is configured in 4-bit mode.
*/
#define TMIO_MMC_BLKSZ_2BYTES (1 << 1)
/*
* Some controllers can support SDIO IRQ signalling.
*/
#define TMIO_MMC_SDIO_IRQ (1 << 2)
int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
@@ -66,6 +70,7 @@ void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
struct tmio_mmc_dma {
void *chan_priv_tx;
void *chan_priv_rx;
int alignment_shift;
};
/*
include/linux/mfd/wl1273-core.h
+288
View File
@@ -0,0 +1,288 @@
/*
* include/linux/mfd/wl1273-core.h
*
* Some definitions for the wl1273 radio receiver/transmitter chip.
*
* Copyright (C) 2010 Nokia Corporation
* Author: Matti J. Aaltonen <matti.j.aaltonen@nokia.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
* 02110-1301 USA
*/
#ifndef WL1273_CORE_H
#define WL1273_CORE_H
#include <linux/i2c.h>
#include <linux/mfd/core.h>
#define WL1273_FM_DRIVER_NAME "wl1273-fm"
#define RX71_FM_I2C_ADDR 0x22
#define WL1273_STEREO_GET 0
#define WL1273_RSSI_LVL_GET 1
#define WL1273_IF_COUNT_GET 2
#define WL1273_FLAG_GET 3
#define WL1273_RDS_SYNC_GET 4
#define WL1273_RDS_DATA_GET 5
#define WL1273_FREQ_SET 10
#define WL1273_AF_FREQ_SET 11
#define WL1273_MOST_MODE_SET 12
#define WL1273_MOST_BLEND_SET 13
#define WL1273_DEMPH_MODE_SET 14
#define WL1273_SEARCH_LVL_SET 15
#define WL1273_BAND_SET 16
#define WL1273_MUTE_STATUS_SET 17
#define WL1273_RDS_PAUSE_LVL_SET 18
#define WL1273_RDS_PAUSE_DUR_SET 19
#define WL1273_RDS_MEM_SET 20
#define WL1273_RDS_BLK_B_SET 21
#define WL1273_RDS_MSK_B_SET 22
#define WL1273_RDS_PI_MASK_SET 23
#define WL1273_RDS_PI_SET 24
#define WL1273_RDS_SYSTEM_SET 25
#define WL1273_INT_MASK_SET 26
#define WL1273_SEARCH_DIR_SET 27
#define WL1273_VOLUME_SET 28
#define WL1273_AUDIO_ENABLE 29
#define WL1273_PCM_MODE_SET 30
#define WL1273_I2S_MODE_CONFIG_SET 31
#define WL1273_POWER_SET 32
#define WL1273_INTX_CONFIG_SET 33
#define WL1273_PULL_EN_SET 34
#define WL1273_HILO_SET 35
#define WL1273_SWITCH2FREF 36
#define WL1273_FREQ_DRIFT_REPORT 37
#define WL1273_PCE_GET 40
#define WL1273_FIRM_VER_GET 41
#define WL1273_ASIC_VER_GET 42
#define WL1273_ASIC_ID_GET 43
#define WL1273_MAN_ID_GET 44
#define WL1273_TUNER_MODE_SET 45
#define WL1273_STOP_SEARCH 46
#define WL1273_RDS_CNTRL_SET 47
#define WL1273_WRITE_HARDWARE_REG 100
#define WL1273_CODE_DOWNLOAD 101
#define WL1273_RESET 102
#define WL1273_FM_POWER_MODE 254
#define WL1273_FM_INTERRUPT 255
/* Transmitter API */
#define WL1273_CHANL_SET 55
#define WL1273_SCAN_SPACING_SET 56
#define WL1273_REF_SET 57
#define WL1273_POWER_ENB_SET 90
#define WL1273_POWER_ATT_SET 58
#define WL1273_POWER_LEV_SET 59
#define WL1273_AUDIO_DEV_SET 60
#define WL1273_PILOT_DEV_SET 61
#define WL1273_RDS_DEV_SET 62
#define WL1273_PUPD_SET 91
#define WL1273_AUDIO_IO_SET 63
#define WL1273_PREMPH_SET 64
#define WL1273_MONO_SET 66
#define WL1273_MUTE 92
#define WL1273_MPX_LMT_ENABLE 67
#define WL1273_PI_SET 93
#define WL1273_ECC_SET 69
#define WL1273_PTY 70
#define WL1273_AF 71
#define WL1273_DISPLAY_MODE 74
#define WL1273_RDS_REP_SET 77
#define WL1273_RDS_CONFIG_DATA_SET 98
#define WL1273_RDS_DATA_SET 99
#define WL1273_RDS_DATA_ENB 94
#define WL1273_TA_SET 78
#define WL1273_TP_SET 79
#define WL1273_DI_SET 80
#define WL1273_MS_SET 81
#define WL1273_PS_SCROLL_SPEED 82
#define WL1273_TX_AUDIO_LEVEL_TEST 96
#define WL1273_TX_AUDIO_LEVEL_TEST_THRESHOLD 73
#define WL1273_TX_AUDIO_INPUT_LEVEL_RANGE_SET 54
#define WL1273_RX_ANTENNA_SELECT 87
#define WL1273_I2C_DEV_ADDR_SET 86
#define WL1273_REF_ERR_CALIB_PARAM_SET 88
#define WL1273_REF_ERR_CALIB_PERIODICITY_SET 89
#define WL1273_SOC_INT_TRIGGER 52
#define WL1273_SOC_AUDIO_PATH_SET 83
#define WL1273_SOC_PCMI_OVERRIDE 84
#define WL1273_SOC_I2S_OVERRIDE 85
#define WL1273_RSSI_BLOCK_SCAN_FREQ_SET 95
#define WL1273_RSSI_BLOCK_SCAN_START 97
#define WL1273_RSSI_BLOCK_SCAN_DATA_GET 5
#define WL1273_READ_FMANT_TUNE_VALUE 104
#define WL1273_RDS_OFF 0
#define WL1273_RDS_ON 1
#define WL1273_RDS_RESET 2
#define WL1273_AUDIO_DIGITAL 0
#define WL1273_AUDIO_ANALOG 1
#define WL1273_MODE_RX BIT(0)
#define WL1273_MODE_TX BIT(1)
#define WL1273_MODE_OFF BIT(2)
#define WL1273_MODE_SUSPENDED BIT(3)
#define WL1273_RADIO_CHILD BIT(0)
#define WL1273_CODEC_CHILD BIT(1)
#define WL1273_RX_MONO 1
#define WL1273_RX_STEREO 0
#define WL1273_TX_MONO 0
#define WL1273_TX_STEREO 1
#define WL1273_MAX_VOLUME 0xffff
#define WL1273_DEFAULT_VOLUME 0x78b8
/* I2S protocol, left channel first, data width 16 bits */
#define WL1273_PCM_DEF_MODE 0x00
/* Rx */
#define WL1273_AUDIO_ENABLE_I2S BIT(0)
#define WL1273_AUDIO_ENABLE_ANALOG BIT(1)
/* Tx */
#define WL1273_AUDIO_IO_SET_ANALOG 0
#define WL1273_AUDIO_IO_SET_I2S 1
#define WL1273_PUPD_SET_OFF 0x00
#define WL1273_PUPD_SET_ON 0x01
#define WL1273_PUPD_SET_RETENTION 0x10
/* I2S mode */
#define WL1273_IS2_WIDTH_32 0x0
#define WL1273_IS2_WIDTH_40 0x1
#define WL1273_IS2_WIDTH_22_23 0x2
#define WL1273_IS2_WIDTH_23_22 0x3
#define WL1273_IS2_WIDTH_48 0x4
#define WL1273_IS2_WIDTH_50 0x5
#define WL1273_IS2_WIDTH_60 0x6
#define WL1273_IS2_WIDTH_64 0x7
#define WL1273_IS2_WIDTH_80 0x8
#define WL1273_IS2_WIDTH_96 0x9
#define WL1273_IS2_WIDTH_128 0xa
#define WL1273_IS2_WIDTH 0xf
#define WL1273_IS2_FORMAT_STD (0x0 << 4)
#define WL1273_IS2_FORMAT_LEFT (0x1 << 4)
#define WL1273_IS2_FORMAT_RIGHT (0x2 << 4)
#define WL1273_IS2_FORMAT_USER (0x3 << 4)
#define WL1273_IS2_MASTER (0x0 << 6)
#define WL1273_IS2_SLAVEW (0x1 << 6)
#define WL1273_IS2_TRI_AFTER_SENDING (0x0 << 7)
#define WL1273_IS2_TRI_ALWAYS_ACTIVE (0x1 << 7)
#define WL1273_IS2_SDOWS_RR (0x0 << 8)
#define WL1273_IS2_SDOWS_RF (0x1 << 8)
#define WL1273_IS2_SDOWS_FR (0x2 << 8)
#define WL1273_IS2_SDOWS_FF (0x3 << 8)
#define WL1273_IS2_TRI_OPT (0x0 << 10)
#define WL1273_IS2_TRI_ALWAYS (0x1 << 10)
#define WL1273_IS2_RATE_48K (0x0 << 12)
#define WL1273_IS2_RATE_44_1K (0x1 << 12)
#define WL1273_IS2_RATE_32K (0x2 << 12)
#define WL1273_IS2_RATE_22_05K (0x4 << 12)
#define WL1273_IS2_RATE_16K (0x5 << 12)
#define WL1273_IS2_RATE_12K (0x8 << 12)
#define WL1273_IS2_RATE_11_025 (0x9 << 12)
#define WL1273_IS2_RATE_8K (0xa << 12)
#define WL1273_IS2_RATE (0xf << 12)
#define WL1273_I2S_DEF_MODE (WL1273_IS2_WIDTH_32 | \
WL1273_IS2_FORMAT_STD | \
WL1273_IS2_MASTER | \
WL1273_IS2_TRI_AFTER_SENDING | \
WL1273_IS2_SDOWS_RR | \
WL1273_IS2_TRI_OPT | \
WL1273_IS2_RATE_48K)
#define SCHAR_MIN (-128)
#define SCHAR_MAX 127
#define WL1273_FR_EVENT BIT(0)
#define WL1273_BL_EVENT BIT(1)
#define WL1273_RDS_EVENT BIT(2)
#define WL1273_BBLK_EVENT BIT(3)
#define WL1273_LSYNC_EVENT BIT(4)
#define WL1273_LEV_EVENT BIT(5)
#define WL1273_IFFR_EVENT BIT(6)
#define WL1273_PI_EVENT BIT(7)
#define WL1273_PD_EVENT BIT(8)
#define WL1273_STIC_EVENT BIT(9)
#define WL1273_MAL_EVENT BIT(10)
#define WL1273_POW_ENB_EVENT BIT(11)
#define WL1273_SCAN_OVER_EVENT BIT(12)
#define WL1273_ERROR_EVENT BIT(13)
#define TUNER_MODE_STOP_SEARCH 0
#define TUNER_MODE_PRESET 1
#define TUNER_MODE_AUTO_SEEK 2
#define TUNER_MODE_AF 3
#define TUNER_MODE_AUTO_SEEK_PI 4
#define TUNER_MODE_AUTO_SEEK_BULK 5
#define RDS_BLOCK_SIZE 3
struct wl1273_fm_platform_data {
int (*request_resources) (struct i2c_client *client);
void (*free_resources) (void);
void (*enable) (void);
void (*disable) (void);
u8 forbidden_modes;
unsigned int children;
};
#define WL1273_FM_CORE_CELLS 2
#define WL1273_BAND_OTHER 0
#define WL1273_BAND_JAPAN 1
#define WL1273_BAND_JAPAN_LOW 76000
#define WL1273_BAND_JAPAN_HIGH 90000
#define WL1273_BAND_OTHER_LOW 87500
#define WL1273_BAND_OTHER_HIGH 108000
#define WL1273_BAND_TX_LOW 76000
#define WL1273_BAND_TX_HIGH 108000
struct wl1273_core {
struct mfd_cell cells[WL1273_FM_CORE_CELLS];
struct wl1273_fm_platform_data *pdata;
unsigned int mode;
unsigned int i2s_mode;
unsigned int volume;
unsigned int audio_mode;
unsigned int channel_number;
struct mutex lock; /* for serializing fm radio operations */
struct i2c_client *client;
int (*write)(struct wl1273_core *core, u8, u16);
int (*set_audio)(struct wl1273_core *core, unsigned int);
int (*set_volume)(struct wl1273_core *core, unsigned int);
};
#endif /* ifndef WL1273_CORE_H */
include/linux/mfd/wm831x/core.h
+1
View File
@@ -245,6 +245,7 @@ enum wm831x_parent {
WM8320 = 0x8320,
WM8321 = 0x8321,
WM8325 = 0x8325,
WM8326 = 0x8326,
};
struct wm831x {
include/linux/mfd/wm8350/audio.h
-3
View File
@@ -522,9 +522,6 @@
#define WM8350_MCLK_SEL_PLL_32K 3
#define WM8350_MCLK_SEL_MCLK 5
#define WM8350_MCLK_DIR_OUT 0
#define WM8350_MCLK_DIR_IN 1
/* clock divider id's */
#define WM8350_ADC_CLKDIV 0
#define WM8350_DAC_CLKDIV 1
include/linux/mfd/wm8994/core.h
+8
View File
@@ -17,6 +17,11 @@
#include <linux/interrupt.h>
enum wm8994_type {
WM8994 = 0,
WM8958 = 1,
};
struct regulator_dev;
struct regulator_bulk_data;
@@ -48,6 +53,8 @@ struct wm8994 {
struct mutex io_lock;
struct mutex irq_lock;
enum wm8994_type type;
struct device *dev;
int (*read_dev)(struct wm8994 *wm8994, unsigned short reg,
int bytes, void *dest);
@@ -68,6 +75,7 @@ struct wm8994 {
u16 gpio_regs[WM8994_NUM_GPIO_REGS];
struct regulator_dev *dbvdd;
int num_supplies;
struct regulator_bulk_data *supplies;
};
include/linux/mfd/wm8994/pdata.h
+18 -1
View File
@@ -29,7 +29,9 @@ struct wm8994_ldo_pdata {
#define WM8994_CONFIGURE_GPIO 0x8000
#define WM8994_DRC_REGS 5
#define WM8994_EQ_REGS 19
#define WM8994_EQ_REGS 20
#define WM8958_MBC_CUTOFF_REGS 20
#define WM8958_MBC_COEFF_REGS 48
/**
* DRC configurations are specified with a label and a set of register
@@ -59,6 +61,18 @@ struct wm8994_retune_mobile_cfg {
u16 regs[WM8994_EQ_REGS];
};
/**
* Multiband compressor configurations are specified with a label and
* two sets of values to write. Configurations are expected to be
* generated using the multiband compressor configuration panel in
* WISCE - see http://www.wolfsonmicro.com/wisce/
*/
struct wm8958_mbc_cfg {
const char *name;
u16 cutoff_regs[WM8958_MBC_CUTOFF_REGS];
u16 coeff_regs[WM8958_MBC_COEFF_REGS];
};
struct wm8994_pdata {
int gpio_base;
@@ -78,6 +92,9 @@ struct wm8994_pdata {
int num_retune_mobile_cfgs;
struct wm8994_retune_mobile_cfg *retune_mobile_cfgs;
int num_mbc_cfgs;
struct wm8958_mbc_cfg *mbc_cfgs;
/* LINEOUT can be differential or single ended */
unsigned int lineout1_diff:1;
unsigned int lineout2_diff:1;
include/linux/mfd/wm8994/registers.h
+302
View File
@@ -64,12 +64,16 @@
#define WM8994_LDO_1 0x3B
#define WM8994_LDO_2 0x3C
#define WM8994_CHARGE_PUMP_1 0x4C
#define WM8958_CHARGE_PUMP_2 0x4D
#define WM8994_CLASS_W_1 0x51
#define WM8994_DC_SERVO_1 0x54
#define WM8994_DC_SERVO_2 0x55
#define WM8994_DC_SERVO_4 0x57
#define WM8994_DC_SERVO_READBACK 0x58
#define WM8994_ANALOGUE_HP_1 0x60
#define WM8958_MIC_DETECT_1 0xD0
#define WM8958_MIC_DETECT_2 0xD1
#define WM8958_MIC_DETECT_3 0xD2
#define WM8994_CHIP_REVISION 0x100
#define WM8994_CONTROL_INTERFACE 0x101
#define WM8994_WRITE_SEQUENCER_CTRL_1 0x110
@@ -109,6 +113,10 @@
#define WM8994_AIF2DAC_LRCLK 0x315
#define WM8994_AIF2DAC_DATA 0x316
#define WM8994_AIF2ADC_DATA 0x317
#define WM8958_AIF3_CONTROL_1 0x320
#define WM8958_AIF3_CONTROL_2 0x321
#define WM8958_AIF3DAC_DATA 0x322
#define WM8958_AIF3ADC_DATA 0x323
#define WM8994_AIF1_ADC1_LEFT_VOLUME 0x400
#define WM8994_AIF1_ADC1_RIGHT_VOLUME 0x401
#define WM8994_AIF1_DAC1_LEFT_VOLUME 0x402
@@ -242,6 +250,83 @@
#define WM8994_INTERRUPT_STATUS_2_MASK 0x739
#define WM8994_INTERRUPT_CONTROL 0x740
#define WM8994_IRQ_DEBOUNCE 0x748
#define WM8958_DSP2_PROGRAM 0x900
#define WM8958_DSP2_CONFIG 0x901
#define WM8958_DSP2_MAGICNUM 0xA00
#define WM8958_DSP2_RELEASEYEAR 0xA01
#define WM8958_DSP2_RELEASEMONTHDAY 0xA02
#define WM8958_DSP2_RELEASETIME 0xA03
#define WM8958_DSP2_VERMAJMIN 0xA04
#define WM8958_DSP2_VERBUILD 0xA05
#define WM8958_DSP2_EXECCONTROL 0xA0D
#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_1 0x2200
#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C1_2 0x2201
#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_1 0x2202
#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C2_2 0x2203
#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_1 0x2204
#define WM8958_MBC_BAND_2_LOWER_CUTOFF_C3_2 0x2205
#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_1 0x2206
#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C2_2 0x2207
#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_1 0x2208
#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C3_2 0x2209
#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_1 0x220A
#define WM8958_MBC_BAND_2_UPPER_CUTOFF_C1_2 0x220B
#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_1 0x220C
#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C1_2 0x220D
#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_1 0x220E
#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C2_2 0x220F
#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_1 0x2210
#define WM8958_MBC_BAND_1_UPPER_CUTOFF_C3_2 0x2211
#define WM8958_MBC_BAND_1_LOWER_CUTOFF_1 0x2212
#define WM8958_MBC_BAND_1_LOWER_CUTOFF_2 0x2213
#define WM8958_MBC_BAND_1_K_1 0x2400
#define WM8958_MBC_BAND_1_K_2 0x2401
#define WM8958_MBC_BAND_1_N1_1 0x2402
#define WM8958_MBC_BAND_1_N1_2 0x2403
#define WM8958_MBC_BAND_1_N2_1 0x2404
#define WM8958_MBC_BAND_1_N2_2 0x2405
#define WM8958_MBC_BAND_1_N3_1 0x2406
#define WM8958_MBC_BAND_1_N3_2 0x2407
#define WM8958_MBC_BAND_1_N4_1 0x2408
#define WM8958_MBC_BAND_1_N4_2 0x2409
#define WM8958_MBC_BAND_1_N5_1 0x240A
#define WM8958_MBC_BAND_1_N5_2 0x240B
#define WM8958_MBC_BAND_1_X1_1 0x240C
#define WM8958_MBC_BAND_1_X1_2 0x240D
#define WM8958_MBC_BAND_1_X2_1 0x240E
#define WM8958_MBC_BAND_1_X2_2 0x240F
#define WM8958_MBC_BAND_1_X3_1 0x2410
#define WM8958_MBC_BAND_1_X3_2 0x2411
#define WM8958_MBC_BAND_1_ATTACK_1 0x2412
#define WM8958_MBC_BAND_1_ATTACK_2 0x2413
#define WM8958_MBC_BAND_1_DECAY_1 0x2414
#define WM8958_MBC_BAND_1_DECAY_2 0x2415
#define WM8958_MBC_BAND_2_K_1 0x2416
#define WM8958_MBC_BAND_2_K_2 0x2417
#define WM8958_MBC_BAND_2_N1_1 0x2418
#define WM8958_MBC_BAND_2_N1_2 0x2419
#define WM8958_MBC_BAND_2_N2_1 0x241A
#define WM8958_MBC_BAND_2_N2_2 0x241B
#define WM8958_MBC_BAND_2_N3_1 0x241C
#define WM8958_MBC_BAND_2_N3_2 0x241D
#define WM8958_MBC_BAND_2_N4_1 0x241E
#define WM8958_MBC_BAND_2_N4_2 0x241F
#define WM8958_MBC_BAND_2_N5_1 0x2420
#define WM8958_MBC_BAND_2_N5_2 0x2421
#define WM8958_MBC_BAND_2_X1_1 0x2422
#define WM8958_MBC_BAND_2_X1_2 0x2423
#define WM8958_MBC_BAND_2_X2_1 0x2424
#define WM8958_MBC_BAND_2_X2_2 0x2425
#define WM8958_MBC_BAND_2_X3_1 0x2426
#define WM8958_MBC_BAND_2_X3_2 0x2427
#define WM8958_MBC_BAND_2_ATTACK_1 0x2428
#define WM8958_MBC_BAND_2_ATTACK_2 0x2429
#define WM8958_MBC_BAND_2_DECAY_1 0x242A
#define WM8958_MBC_BAND_2_DECAY_2 0x242B
#define WM8958_MBC_B2_PG2_1 0x242C
#define WM8958_MBC_B2_PG2_2 0x242D
#define WM8958_MBC_B1_PG2_1 0x242E
#define WM8958_MBC_B1_PG2_2 0x242F
#define WM8994_WRITE_SEQUENCER_0 0x3000
#define WM8994_WRITE_SEQUENCER_1 0x3001
#define WM8994_WRITE_SEQUENCER_2 0x3002
@@ -992,6 +1077,12 @@
/*
* R6 (0x06) - Power Management (6)
*/
#define WM8958_AIF3ADC_SRC_MASK 0x0600 /* AIF3ADC_SRC - [10:9] */
#define WM8958_AIF3ADC_SRC_SHIFT 9 /* AIF3ADC_SRC - [10:9] */
#define WM8958_AIF3ADC_SRC_WIDTH 2 /* AIF3ADC_SRC - [10:9] */
#define WM8958_AIF2DAC_SRC_MASK 0x0180 /* AIF2DAC_SRC - [8:7] */
#define WM8958_AIF2DAC_SRC_SHIFT 7 /* AIF2DAC_SRC - [8:7] */
#define WM8958_AIF2DAC_SRC_WIDTH 2 /* AIF2DAC_SRC - [8:7] */
#define WM8994_AIF3_TRI 0x0020 /* AIF3_TRI */
#define WM8994_AIF3_TRI_MASK 0x0020 /* AIF3_TRI */
#define WM8994_AIF3_TRI_SHIFT 5 /* AIF3_TRI */
@@ -1835,6 +1926,14 @@
#define WM8994_CP_ENA_SHIFT 15 /* CP_ENA */
#define WM8994_CP_ENA_WIDTH 1 /* CP_ENA */
/*
* R77 (0x4D) - Charge Pump (2)
*/
#define WM8958_CP_DISCH 0x8000 /* CP_DISCH */
#define WM8958_CP_DISCH_MASK 0x8000 /* CP_DISCH */
#define WM8958_CP_DISCH_SHIFT 15 /* CP_DISCH */
#define WM8958_CP_DISCH_WIDTH 1 /* CP_DISCH */
/*
* R81 (0x51) - Class W (1)
*/
@@ -1951,6 +2050,46 @@
#define WM8994_HPOUT1R_DLY_SHIFT 1 /* HPOUT1R_DLY */
#define WM8994_HPOUT1R_DLY_WIDTH 1 /* HPOUT1R_DLY */
/*
* R208 (0xD0) - Mic Detect 1
*/
#define WM8958_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */
#define WM8958_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */
#define WM8958_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */
#define WM8958_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */
#define WM8958_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */
#define WM8958_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */
#define WM8958_MICD_DBTIME 0x0002 /* MICD_DBTIME */
#define WM8958_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */
#define WM8958_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */
#define WM8958_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */
#define WM8958_MICD_ENA 0x0001 /* MICD_ENA */
#define WM8958_MICD_ENA_MASK 0x0001 /* MICD_ENA */
#define WM8958_MICD_ENA_SHIFT 0 /* MICD_ENA */
#define WM8958_MICD_ENA_WIDTH 1 /* MICD_ENA */
/*
* R209 (0xD1) - Mic Detect 2
*/
#define WM8958_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */
#define WM8958_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */
#define WM8958_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */
/*
* R210 (0xD2) - Mic Detect 3
*/
#define WM8958_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */
#define WM8958_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */
#define WM8958_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */
#define WM8958_MICD_VALID 0x0002 /* MICD_VALID */
#define WM8958_MICD_VALID_MASK 0x0002 /* MICD_VALID */
#define WM8958_MICD_VALID_SHIFT 1 /* MICD_VALID */
#define WM8958_MICD_VALID_WIDTH 1 /* MICD_VALID */
#define WM8958_MICD_STS 0x0001 /* MICD_STS */
#define WM8958_MICD_STS_MASK 0x0001 /* MICD_STS */
#define WM8958_MICD_STS_SHIFT 0 /* MICD_STS */
#define WM8958_MICD_STS_WIDTH 1 /* MICD_STS */
/*
* R256 (0x100) - Chip Revision
*/
@@ -2069,6 +2208,14 @@
/*
* R520 (0x208) - Clocking (1)
*/
#define WM8958_DSP2CLK_ENA 0x4000 /* DSP2CLK_ENA */
#define WM8958_DSP2CLK_ENA_MASK 0x4000 /* DSP2CLK_ENA */
#define WM8958_DSP2CLK_ENA_SHIFT 14 /* DSP2CLK_ENA */
#define WM8958_DSP2CLK_ENA_WIDTH 1 /* DSP2CLK_ENA */
#define WM8958_DSP2CLK_SRC 0x1000 /* DSP2CLK_SRC */
#define WM8958_DSP2CLK_SRC_MASK 0x1000 /* DSP2CLK_SRC */
#define WM8958_DSP2CLK_SRC_SHIFT 12 /* DSP2CLK_SRC */
#define WM8958_DSP2CLK_SRC_WIDTH 1 /* DSP2CLK_SRC */
#define WM8994_TOCLK_ENA 0x0010 /* TOCLK_ENA */
#define WM8994_TOCLK_ENA_MASK 0x0010 /* TOCLK_ENA */
#define WM8994_TOCLK_ENA_SHIFT 4 /* TOCLK_ENA */
@@ -2552,6 +2699,63 @@
#define WM8994_AIF2ADCR_DAT_INV_SHIFT 0 /* AIF2ADCR_DAT_INV */
#define WM8994_AIF2ADCR_DAT_INV_WIDTH 1 /* AIF2ADCR_DAT_INV */
/*
* R800 (0x320) - AIF3 Control (1)
*/
#define WM8958_AIF3_LRCLK_INV 0x0080 /* AIF3_LRCLK_INV */
#define WM8958_AIF3_LRCLK_INV_MASK 0x0080 /* AIF3_LRCLK_INV */
#define WM8958_AIF3_LRCLK_INV_SHIFT 7 /* AIF3_LRCLK_INV */
#define WM8958_AIF3_LRCLK_INV_WIDTH 1 /* AIF3_LRCLK_INV */
#define WM8958_AIF3_WL_MASK 0x0060 /* AIF3_WL - [6:5] */
#define WM8958_AIF3_WL_SHIFT 5 /* AIF3_WL - [6:5] */
#define WM8958_AIF3_WL_WIDTH 2 /* AIF3_WL - [6:5] */
#define WM8958_AIF3_FMT_MASK 0x0018 /* AIF3_FMT - [4:3] */
#define WM8958_AIF3_FMT_SHIFT 3 /* AIF3_FMT - [4:3] */
#define WM8958_AIF3_FMT_WIDTH 2 /* AIF3_FMT - [4:3] */
/*
* R801 (0x321) - AIF3 Control (2)
*/
#define WM8958_AIF3DAC_BOOST_MASK 0x0C00 /* AIF3DAC_BOOST - [11:10] */
#define WM8958_AIF3DAC_BOOST_SHIFT 10 /* AIF3DAC_BOOST - [11:10] */
#define WM8958_AIF3DAC_BOOST_WIDTH 2 /* AIF3DAC_BOOST - [11:10] */
#define WM8958_AIF3DAC_COMP 0x0010 /* AIF3DAC_COMP */
#define WM8958_AIF3DAC_COMP_MASK 0x0010 /* AIF3DAC_COMP */
#define WM8958_AIF3DAC_COMP_SHIFT 4 /* AIF3DAC_COMP */
#define WM8958_AIF3DAC_COMP_WIDTH 1 /* AIF3DAC_COMP */
#define WM8958_AIF3DAC_COMPMODE 0x0008 /* AIF3DAC_COMPMODE */
#define WM8958_AIF3DAC_COMPMODE_MASK 0x0008 /* AIF3DAC_COMPMODE */
#define WM8958_AIF3DAC_COMPMODE_SHIFT 3 /* AIF3DAC_COMPMODE */
#define WM8958_AIF3DAC_COMPMODE_WIDTH 1 /* AIF3DAC_COMPMODE */
#define WM8958_AIF3ADC_COMP 0x0004 /* AIF3ADC_COMP */
#define WM8958_AIF3ADC_COMP_MASK 0x0004 /* AIF3ADC_COMP */
#define WM8958_AIF3ADC_COMP_SHIFT 2 /* AIF3ADC_COMP */
#define WM8958_AIF3ADC_COMP_WIDTH 1 /* AIF3ADC_COMP */
#define WM8958_AIF3ADC_COMPMODE 0x0002 /* AIF3ADC_COMPMODE */
#define WM8958_AIF3ADC_COMPMODE_MASK 0x0002 /* AIF3ADC_COMPMODE */
#define WM8958_AIF3ADC_COMPMODE_SHIFT 1 /* AIF3ADC_COMPMODE */
#define WM8958_AIF3ADC_COMPMODE_WIDTH 1 /* AIF3ADC_COMPMODE */
#define WM8958_AIF3_LOOPBACK 0x0001 /* AIF3_LOOPBACK */
#define WM8958_AIF3_LOOPBACK_MASK 0x0001 /* AIF3_LOOPBACK */
#define WM8958_AIF3_LOOPBACK_SHIFT 0 /* AIF3_LOOPBACK */
#define WM8958_AIF3_LOOPBACK_WIDTH 1 /* AIF3_LOOPBACK */
/*
* R802 (0x322) - AIF3DAC Data
*/
#define WM8958_AIF3DAC_DAT_INV 0x0001 /* AIF3DAC_DAT_INV */
#define WM8958_AIF3DAC_DAT_INV_MASK 0x0001 /* AIF3DAC_DAT_INV */
#define WM8958_AIF3DAC_DAT_INV_SHIFT 0 /* AIF3DAC_DAT_INV */
#define WM8958_AIF3DAC_DAT_INV_WIDTH 1 /* AIF3DAC_DAT_INV */
/*
* R803 (0x323) - AIF3ADC Data
*/
#define WM8958_AIF3ADC_DAT_INV 0x0001 /* AIF3ADC_DAT_INV */
#define WM8958_AIF3ADC_DAT_INV_MASK 0x0001 /* AIF3ADC_DAT_INV */
#define WM8958_AIF3ADC_DAT_INV_SHIFT 0 /* AIF3ADC_DAT_INV */
#define WM8958_AIF3ADC_DAT_INV_WIDTH 1 /* AIF3ADC_DAT_INV */
/*
* R1024 (0x400) - AIF1 ADC1 Left Volume
*/
@@ -4289,4 +4493,102 @@
#define WM8994_TEMP_SHUT_DB_SHIFT 0 /* TEMP_SHUT_DB */
#define WM8994_TEMP_SHUT_DB_WIDTH 1 /* TEMP_SHUT_DB */
/*
* R2304 (0x900) - DSP2_Program
*/
#define WM8958_DSP2_ENA 0x0001 /* DSP2_ENA */
#define WM8958_DSP2_ENA_MASK 0x0001 /* DSP2_ENA */
#define WM8958_DSP2_ENA_SHIFT 0 /* DSP2_ENA */
#define WM8958_DSP2_ENA_WIDTH 1 /* DSP2_ENA */
/*
* R2305 (0x901) - DSP2_Config
*/
#define WM8958_MBC_SEL_MASK 0x0030 /* MBC_SEL - [5:4] */
#define WM8958_MBC_SEL_SHIFT 4 /* MBC_SEL - [5:4] */
#define WM8958_MBC_SEL_WIDTH 2 /* MBC_SEL - [5:4] */
#define WM8958_MBC_ENA 0x0001 /* MBC_ENA */
#define WM8958_MBC_ENA_MASK 0x0001 /* MBC_ENA */
#define WM8958_MBC_ENA_SHIFT 0 /* MBC_ENA */
#define WM8958_MBC_ENA_WIDTH 1 /* MBC_ENA */
/*
* R2560 (0xA00) - DSP2_MagicNum
*/
#define WM8958_DSP2_MAGIC_NUM_MASK 0xFFFF /* DSP2_MAGIC_NUM - [15:0] */
#define WM8958_DSP2_MAGIC_NUM_SHIFT 0 /* DSP2_MAGIC_NUM - [15:0] */
#define WM8958_DSP2_MAGIC_NUM_WIDTH 16 /* DSP2_MAGIC_NUM - [15:0] */
/*
* R2561 (0xA01) - DSP2_ReleaseYear
*/
#define WM8958_DSP2_RELEASE_YEAR_MASK 0xFFFF /* DSP2_RELEASE_YEAR - [15:0] */
#define WM8958_DSP2_RELEASE_YEAR_SHIFT 0 /* DSP2_RELEASE_YEAR - [15:0] */
#define WM8958_DSP2_RELEASE_YEAR_WIDTH 16 /* DSP2_RELEASE_YEAR - [15:0] */
/*
* R2562 (0xA02) - DSP2_ReleaseMonthDay
*/
#define WM8958_DSP2_RELEASE_MONTH_MASK 0xFF00 /* DSP2_RELEASE_MONTH - [15:8] */
#define WM8958_DSP2_RELEASE_MONTH_SHIFT 8 /* DSP2_RELEASE_MONTH - [15:8] */
#define WM8958_DSP2_RELEASE_MONTH_WIDTH 8 /* DSP2_RELEASE_MONTH - [15:8] */
#define WM8958_DSP2_RELEASE_DAY_MASK 0x00FF /* DSP2_RELEASE_DAY - [7:0] */
#define WM8958_DSP2_RELEASE_DAY_SHIFT 0 /* DSP2_RELEASE_DAY - [7:0] */
#define WM8958_DSP2_RELEASE_DAY_WIDTH 8 /* DSP2_RELEASE_DAY - [7:0] */
/*
* R2563 (0xA03) - DSP2_ReleaseTime
*/
#define WM8958_DSP2_RELEASE_HOURS_MASK 0xFF00 /* DSP2_RELEASE_HOURS - [15:8] */
#define WM8958_DSP2_RELEASE_HOURS_SHIFT 8 /* DSP2_RELEASE_HOURS - [15:8] */
#define WM8958_DSP2_RELEASE_HOURS_WIDTH 8 /* DSP2_RELEASE_HOURS - [15:8] */
#define WM8958_DSP2_RELEASE_MINS_MASK 0x00FF /* DSP2_RELEASE_MINS - [7:0] */
#define WM8958_DSP2_RELEASE_MINS_SHIFT 0 /* DSP2_RELEASE_MINS - [7:0] */
#define WM8958_DSP2_RELEASE_MINS_WIDTH 8 /* DSP2_RELEASE_MINS - [7:0] */
/*
* R2564 (0xA04) - DSP2_VerMajMin
*/
#define WM8958_DSP2_MAJOR_VER_MASK 0xFF00 /* DSP2_MAJOR_VER - [15:8] */
#define WM8958_DSP2_MAJOR_VER_SHIFT 8 /* DSP2_MAJOR_VER - [15:8] */
#define WM8958_DSP2_MAJOR_VER_WIDTH 8 /* DSP2_MAJOR_VER - [15:8] */
#define WM8958_DSP2_MINOR_VER_MASK 0x00FF /* DSP2_MINOR_VER - [7:0] */
#define WM8958_DSP2_MINOR_VER_SHIFT 0 /* DSP2_MINOR_VER - [7:0] */
#define WM8958_DSP2_MINOR_VER_WIDTH 8 /* DSP2_MINOR_VER - [7:0] */
/*
* R2565 (0xA05) - DSP2_VerBuild
*/
#define WM8958_DSP2_BUILD_VER_MASK 0xFFFF /* DSP2_BUILD_VER - [15:0] */
#define WM8958_DSP2_BUILD_VER_SHIFT 0 /* DSP2_BUILD_VER - [15:0] */
#define WM8958_DSP2_BUILD_VER_WIDTH 16 /* DSP2_BUILD_VER - [15:0] */
/*
* R2573 (0xA0D) - DSP2_ExecControl
*/
#define WM8958_DSP2_STOPC 0x0020 /* DSP2_STOPC */
#define WM8958_DSP2_STOPC_MASK 0x0020 /* DSP2_STOPC */
#define WM8958_DSP2_STOPC_SHIFT 5 /* DSP2_STOPC */
#define WM8958_DSP2_STOPC_WIDTH 1 /* DSP2_STOPC */
#define WM8958_DSP2_STOPS 0x0010 /* DSP2_STOPS */
#define WM8958_DSP2_STOPS_MASK 0x0010 /* DSP2_STOPS */
#define WM8958_DSP2_STOPS_SHIFT 4 /* DSP2_STOPS */
#define WM8958_DSP2_STOPS_WIDTH 1 /* DSP2_STOPS */
#define WM8958_DSP2_STOPI 0x0008 /* DSP2_STOPI */
#define WM8958_DSP2_STOPI_MASK 0x0008 /* DSP2_STOPI */
#define WM8958_DSP2_STOPI_SHIFT 3 /* DSP2_STOPI */
#define WM8958_DSP2_STOPI_WIDTH 1 /* DSP2_STOPI */
#define WM8958_DSP2_STOP 0x0004 /* DSP2_STOP */
#define WM8958_DSP2_STOP_MASK 0x0004 /* DSP2_STOP */
#define WM8958_DSP2_STOP_SHIFT 2 /* DSP2_STOP */
#define WM8958_DSP2_STOP_WIDTH 1 /* DSP2_STOP */
#define WM8958_DSP2_RUNR 0x0002 /* DSP2_RUNR */
#define WM8958_DSP2_RUNR_MASK 0x0002 /* DSP2_RUNR */
#define WM8958_DSP2_RUNR_SHIFT 1 /* DSP2_RUNR */
#define WM8958_DSP2_RUNR_WIDTH 1 /* DSP2_RUNR */
#define WM8958_DSP2_RUN 0x0001 /* DSP2_RUN */
#define WM8958_DSP2_RUN_MASK 0x0001 /* DSP2_RUN */
#define WM8958_DSP2_RUN_SHIFT 0 /* DSP2_RUN */
#define WM8958_DSP2_RUN_WIDTH 1 /* DSP2_RUN */
#endif