From 9a41e64762fae1b0656c61e3351dec034cfcad31 Mon Sep 17 00:00:00 2001 From: Sibi Sankar Date: Tue, 11 Mar 2025 08:51:19 +0900 Subject: [PATCH] arm64: dts: qcom: x1e80100: Resize GIC Redistributor register region BugLink: https://bugs.launchpad.net/bugs/2101915 [ Upstream commit 9ed1a2b8784262e85ec300792a1a37ebd8473be2 ] Resize the GICR register region as it currently seeps into the CPU Control Processor mailbox RX region. Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts") Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Sibi Sankar Link: https://lore.kernel.org/r/20240612124056.39230-4-quic_sibis@quicinc.com Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin Signed-off-by: Koichiro Den Signed-off-by: Stefan Bader --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 5ba7924aa435..9c07697bde88 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -3284,7 +3284,7 @@ intc: interrupt-controller@17000000 { compatible = "arm,gic-v3"; reg = <0 0x17000000 0 0x10000>, /* GICD */ - <0 0x17080000 0 0x480000>; /* GICR * 12 */ + <0 0x17080000 0 0x300000>; /* GICR * 12 */ interrupts = ;