perf/x86/intel/ds: Add PEBS format 6

BugLink: https://bugs.launchpad.net/bugs/2103869

commit b8c3a2502a205321fe66c356f4b70cabd8e1a5fc upstream.

The only difference between 5 and 6 is the new counters snapshotting
group, without the following counters snapshotting enabling patches,
it's impossible to utilize the feature in a PEBS record. It's safe to
share the same code path with format 5.

Add format 6, so the end user can at least utilize the legacy PEBS
features.

Fixes: a932aa0e868f ("perf/x86: Add Lunar Lake and Arrow Lake support")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20241216204505.748363-1-kan.liang@linux.intel.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Manuel Diewald <manuel.diewald@canonical.com>
Signed-off-by: Mehmet Basaran <mehmet.basaran@canonical.com>

This commit is contained in:

Kan Liang

2024-12-16 12:45:02 -08:00

committed by

Mehmet Basaran

parent 946952f0e7

commit 94fed90547

1 changed files with 1 additions and 0 deletions

									
										arch/x86/events/intel/ds.c
									
		+1
		
												View File
												
				@@ -2381,6 +2381,7 @@ void __init intel_ds_init(void)

							x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME;

							break;

						case 6:

						case 5:

							x86_pmu.pebs_ept = 1;

							fallthrough;