Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linux
Pull drm updates from Dave Airlie:
"This is the main drm pull, it has a shared branch with some alsa
crossover but everything should be acked by relevant people.
New drivers:
- ATMEL HLCDC driver
- designware HDMI core support (used in multiple SoCs).
core:
- lots more atomic modesetting work, properties and atomic ioctl
(hidden under option)
- bridge rework allows support for Samsung exynos chromebooks to
work finally.
- some more panels supported
i915:
- atomic plane update support
- DSI uses shared DSI infrastructure
- Skylake basic support is all merged now
- component framework used for i915/snd-hda interactions
- write-combine cpu memory mappings
- engine init code refactored
- full ppgtt enabled where execlists are enabled.
- cherryview rps/gpu turbo and pipe CRC support.
radeon:
- indirect draw support for evergreen/cayman
- SMC and manual fan control for SI/CI
- Displayport audio support
amdkfd:
- SDMA usermode queue support
- replace suballocator usage with more suitable one
- rework for allowing interfacing to more than radeon
nouveau:
- major renaming in prep for later splitting work
- merge arm platform driver into nouveau
- GK20A reclocking support
msm:
- conversion to atomic modesetting
- YUV support for mdp4/5
- eDP support
- hw cursor for mdp5
tegra:
- conversion to atomic modesetting
- better suspend/resume support for child devices
rcar-du:
- interlaced support
imx:
- move to using dw_hdmi shared support
- mode_fixup support
sti:
- DVO support
- HDMI infoframe support
exynos:
- refactoring and cleanup, removed lots of internal unnecessary
abstraction
- exynos7 DECON display controller support
Along with the usual bunch of fixes, cleanups etc"
* 'drm-next' of git://people.freedesktop.org/~airlied/linux: (724 commits)
drm/radeon: fix voltage setup on hawaii
drm/radeon/dp: Set EDP_CONFIGURATION_SET for bridge chips if necessary
drm/radeon: only enable kv/kb dpm interrupts once v3
drm/radeon: workaround for CP HW bug on CIK
drm/radeon: Don't try to enable write-combining without PAT
drm/radeon: use 0-255 rather than 0-100 for pwm fan range
drm/i915: Clamp efficient frequency to valid range
drm/i915: Really ignore long HPD pulses on eDP
drm/exynos: Add DECON driver
drm/i915: Correct the base value while updating LP_OUTPUT_HOLD in MIPI_PORT_CTRL
drm/i915: Insert a command barrier on BLT/BSD cache flushes
drm/i915: Drop vblank wait from intel_dp_link_down
drm/exynos: fix NULL pointer reference
drm/exynos: remove exynos_plane_dpms
drm/exynos: remove mode property of exynos crtc
drm/exynos: Remove exynos_plane_dpms() call with no effect
drm/i915: Squelch overzealous uncore reset WARN_ON
drm/i915: Take runtime pm reference on hangcheck_info
drm/i915: Correct the IOSF Dev_FN field for IOSF transfers
drm/exynos: fix DMA_ATTR_NO_KERNEL_MAPPING usage
...
This commit is contained in:
Linus Torvalds
@@ -654,6 +654,13 @@ struct drm_get_cap {
|
||||
*/
|
||||
#define DRM_CLIENT_CAP_UNIVERSAL_PLANES 2
|
||||
|
||||
/**
|
||||
* DRM_CLIENT_CAP_ATOMIC
|
||||
*
|
||||
* If set to 1, the DRM core will expose atomic properties to userspace
|
||||
*/
|
||||
#define DRM_CLIENT_CAP_ATOMIC 3
|
||||
|
||||
/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
|
||||
struct drm_set_client_cap {
|
||||
__u64 capability;
|
||||
@@ -777,6 +784,7 @@ struct drm_prime_handle {
|
||||
#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
|
||||
#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
|
||||
#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
|
||||
#define DRM_IOCTL_MODE_ATOMIC DRM_IOWR(0xBC, struct drm_mode_atomic)
|
||||
|
||||
/**
|
||||
* Device specific ioctls should only be in their respective headers
|
||||
|
||||
@@ -109,9 +109,6 @@
|
||||
#define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
|
||||
#define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
|
||||
|
||||
/* special NV12 tiled format */
|
||||
#define DRM_FORMAT_NV12MT fourcc_code('T', 'M', '1', '2') /* 2x2 subsampled Cr:Cb plane 64x32 macroblocks */
|
||||
|
||||
/*
|
||||
* 3 plane YCbCr
|
||||
* index 0: Y plane, [7:0] Y
|
||||
|
||||
@@ -272,6 +272,13 @@ struct drm_mode_get_connector {
|
||||
#define DRM_MODE_PROP_OBJECT DRM_MODE_PROP_TYPE(1)
|
||||
#define DRM_MODE_PROP_SIGNED_RANGE DRM_MODE_PROP_TYPE(2)
|
||||
|
||||
/* the PROP_ATOMIC flag is used to hide properties from userspace that
|
||||
* is not aware of atomic properties. This is mostly to work around
|
||||
* older userspace (DDX drivers) that read/write each prop they find,
|
||||
* witout being aware that this could be triggering a lengthy modeset.
|
||||
*/
|
||||
#define DRM_MODE_PROP_ATOMIC 0x80000000
|
||||
|
||||
struct drm_mode_property_enum {
|
||||
__u64 value;
|
||||
char name[DRM_PROP_NAME_LEN];
|
||||
@@ -338,7 +345,7 @@ struct drm_mode_fb_cmd2 {
|
||||
|
||||
/*
|
||||
* In case of planar formats, this ioctl allows up to 4
|
||||
* buffer objects with offets and pitches per plane.
|
||||
* buffer objects with offsets and pitches per plane.
|
||||
* The pitch and offset order is dictated by the fourcc,
|
||||
* e.g. NV12 (http://fourcc.org/yuv.php#NV12) is described as:
|
||||
*
|
||||
@@ -346,9 +353,9 @@ struct drm_mode_fb_cmd2 {
|
||||
* followed by an interleaved U/V plane containing
|
||||
* 8 bit 2x2 subsampled colour difference samples.
|
||||
*
|
||||
* So it would consist of Y as offset[0] and UV as
|
||||
* offeset[1]. Note that offset[0] will generally
|
||||
* be 0.
|
||||
* So it would consist of Y as offsets[0] and UV as
|
||||
* offsets[1]. Note that offsets[0] will generally
|
||||
* be 0 (but this is not required).
|
||||
*/
|
||||
__u32 handles[4];
|
||||
__u32 pitches[4]; /* pitch for each plane */
|
||||
@@ -519,4 +526,27 @@ struct drm_mode_destroy_dumb {
|
||||
uint32_t handle;
|
||||
};
|
||||
|
||||
/* page-flip flags are valid, plus: */
|
||||
#define DRM_MODE_ATOMIC_TEST_ONLY 0x0100
|
||||
#define DRM_MODE_ATOMIC_NONBLOCK 0x0200
|
||||
#define DRM_MODE_ATOMIC_ALLOW_MODESET 0x0400
|
||||
|
||||
#define DRM_MODE_ATOMIC_FLAGS (\
|
||||
DRM_MODE_PAGE_FLIP_EVENT |\
|
||||
DRM_MODE_PAGE_FLIP_ASYNC |\
|
||||
DRM_MODE_ATOMIC_TEST_ONLY |\
|
||||
DRM_MODE_ATOMIC_NONBLOCK |\
|
||||
DRM_MODE_ATOMIC_ALLOW_MODESET)
|
||||
|
||||
struct drm_mode_atomic {
|
||||
__u32 flags;
|
||||
__u32 count_objs;
|
||||
__u64 objs_ptr;
|
||||
__u64 count_props_ptr;
|
||||
__u64 props_ptr;
|
||||
__u64 prop_values_ptr;
|
||||
__u64 reserved;
|
||||
__u64 user_data;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@@ -224,6 +224,8 @@ typedef struct _drm_i915_sarea {
|
||||
#define DRM_I915_REG_READ 0x31
|
||||
#define DRM_I915_GET_RESET_STATS 0x32
|
||||
#define DRM_I915_GEM_USERPTR 0x33
|
||||
#define DRM_I915_GEM_CONTEXT_GETPARAM 0x34
|
||||
#define DRM_I915_GEM_CONTEXT_SETPARAM 0x35
|
||||
|
||||
#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
|
||||
#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
|
||||
@@ -275,6 +277,8 @@ typedef struct _drm_i915_sarea {
|
||||
#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
|
||||
#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
|
||||
#define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr)
|
||||
#define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param)
|
||||
#define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param)
|
||||
|
||||
/* Allow drivers to submit batchbuffers directly to hardware, relying
|
||||
* on the security mechanisms provided by hardware.
|
||||
@@ -341,6 +345,8 @@ typedef struct drm_i915_irq_wait {
|
||||
#define I915_PARAM_HAS_WT 27
|
||||
#define I915_PARAM_CMD_PARSER_VERSION 28
|
||||
#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
|
||||
#define I915_PARAM_MMAP_VERSION 30
|
||||
#define I915_PARAM_HAS_BSD2 31
|
||||
|
||||
typedef struct drm_i915_getparam {
|
||||
int param;
|
||||
@@ -488,6 +494,14 @@ struct drm_i915_gem_mmap {
|
||||
* This is a fixed-size type for 32/64 compatibility.
|
||||
*/
|
||||
__u64 addr_ptr;
|
||||
|
||||
/**
|
||||
* Flags for extended behaviour.
|
||||
*
|
||||
* Added in version 2.
|
||||
*/
|
||||
__u64 flags;
|
||||
#define I915_MMAP_WC 0x1
|
||||
};
|
||||
|
||||
struct drm_i915_gem_mmap_gtt {
|
||||
@@ -737,7 +751,13 @@ struct drm_i915_gem_execbuffer2 {
|
||||
*/
|
||||
#define I915_EXEC_HANDLE_LUT (1<<12)
|
||||
|
||||
#define __I915_EXEC_UNKNOWN_FLAGS -(I915_EXEC_HANDLE_LUT<<1)
|
||||
/** Used for switching BSD rings on the platforms with two BSD rings */
|
||||
#define I915_EXEC_BSD_MASK (3<<13)
|
||||
#define I915_EXEC_BSD_DEFAULT (0<<13) /* default ping-pong mode */
|
||||
#define I915_EXEC_BSD_RING1 (1<<13)
|
||||
#define I915_EXEC_BSD_RING2 (2<<13)
|
||||
|
||||
#define __I915_EXEC_UNKNOWN_FLAGS -(1<<15)
|
||||
|
||||
#define I915_EXEC_CONTEXT_ID_MASK (0xffffffff)
|
||||
#define i915_execbuffer2_set_context_id(eb2, context) \
|
||||
@@ -1073,4 +1093,12 @@ struct drm_i915_gem_userptr {
|
||||
__u32 handle;
|
||||
};
|
||||
|
||||
struct drm_i915_gem_context_param {
|
||||
__u32 ctx_id;
|
||||
__u32 size;
|
||||
__u64 param;
|
||||
#define I915_CONTEXT_PARAM_BAN_PERIOD 0x1
|
||||
__u64 value;
|
||||
};
|
||||
|
||||
#endif /* _UAPI_I915_DRM_H_ */
|
||||
|
||||
Reference in New Issue
Block a user