NVIDIA: SAUCE: firmware: bpmp: build bpmp hv driver as built-in driver
skip building tegra_bpmp driver for oot kernel from nvidia-oot repo and start building with oot kernel as inbuild driver to improve boot KPI. http://nvbugs/4551265 Signed-off-by: Manish Bhardwaj <mbhardwaj@nvidia.com> Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com> Tested-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Vishwaroop A <va@nvidia.com> Acked-by: Noah Wager <noah.wager@canonical.com> Acked-by: Jacob Martin <jacob.martin@canonical.com> Signed-off-by: Noah Wager <noah.wager@canonical.com>
This commit is contained in:
Manish Bhardwaj
committed by
Noah Wager
Noah Wager
parent
b1aca4ebc0
commit
72ac5288b5
@@ -1,9 +1,11 @@
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# SPDX-License-Identifier: GPL-2.0-only
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# SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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tegra-bpmp-y = bpmp.o
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tegra-bpmp-$(CONFIG_ARCH_TEGRA_210_SOC) += bpmp-tegra210.o
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tegra-bpmp-$(CONFIG_ARCH_TEGRA_186_SOC) += bpmp-tegra186.o
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tegra-bpmp-$(CONFIG_ARCH_TEGRA_194_SOC) += bpmp-tegra186.o
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tegra-bpmp-$(CONFIG_ARCH_TEGRA_234_SOC) += bpmp-tegra186.o
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tegra-bpmp-$(CONFIG_TEGRA_HV_DRIVER) += bpmp-tegra194-hv.o
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tegra-bpmp-$(CONFIG_DEBUG_FS) += bpmp-debugfs.o
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obj-$(CONFIG_TEGRA_BPMP) += tegra-bpmp.o
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obj-$(CONFIG_TEGRA_IVC) += ivc.o
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@@ -1,7 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2018, NVIDIA CORPORATION.
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*/
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
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#ifndef __FIRMWARE_TEGRA_BPMP_PRIVATE_H
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#define __FIRMWARE_TEGRA_BPMP_PRIVATE_H
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@@ -31,5 +29,7 @@ extern const struct tegra_bpmp_ops tegra186_bpmp_ops;
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
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extern const struct tegra_bpmp_ops tegra210_bpmp_ops;
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#endif
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#if IS_ENABLED(CONFIG_TEGRA_HV_DRIVER)
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extern const struct tegra_bpmp_ops tegra194_bpmp_hv_ops;
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#endif
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#endif
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@@ -0,0 +1,267 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
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#include <linux/interrupt.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <soc/tegra/bpmp.h>
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#include <soc/tegra/ivc.h>
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#include <soc/tegra/virt/hv-ivc.h>
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#include "bpmp-private.h"
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/* utilizing the struct tegra_ivc *ivc in struct tegra_bpmp_channel
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* to store struct tegra_hv_ivc_cookie pointer, being used by this driver
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* to use hypervisor exposed ivc queue implementation, so that we do not
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* need to introduced new member in struct tegra_bpmp_channel which
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* will be unused in upstream kernel
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*/
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#define to_hv_ivc(ivc) ((struct tegra_hv_ivc_cookie *)ivc)
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static struct tegra_hv_ivc_cookie **hv_bpmp_ivc_cookies;
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static struct device_node *hv_of_node;
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static irqreturn_t tegra194_hv_bpmp_rx_handler(int irq, void *bpmp)
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{
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tegra_bpmp_handle_rx(bpmp);
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return IRQ_HANDLED;
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}
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static int tegra194_hv_bpmp_channel_init(struct tegra_bpmp_channel *channel,
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struct tegra_bpmp *bpmp,
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unsigned int queue_id, bool threaded)
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{
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static int cookie_idx;
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struct tegra_hv_ivc_cookie *hv_ivc;
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int err;
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hv_ivc = tegra_hv_ivc_reserve(hv_of_node, queue_id, NULL);
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channel->ivc = (void *)hv_ivc;
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if (IS_ERR_OR_NULL(hv_ivc)) {
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pr_err("%s: Failed to reserve ivc queue @index %d\n",
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__func__, queue_id);
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goto request_cleanup;
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}
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if (hv_ivc->frame_size < MSG_DATA_MIN_SZ) {
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pr_err("%s: Frame size is too small\n", __func__);
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goto request_cleanup;
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}
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hv_bpmp_ivc_cookies[cookie_idx++] = hv_ivc;
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/* init completion */
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init_completion(&channel->completion);
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channel->bpmp = bpmp;
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if (threaded) {
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err = request_threaded_irq(
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hv_ivc->irq,
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tegra194_hv_bpmp_rx_handler, NULL,
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IRQF_NO_SUSPEND,
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"bpmp_irq_handler", bpmp);
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} else {
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err = 0;
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}
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if (err) {
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pr_err("%s: Failed to request irq %d for index %d\n",
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__func__, hv_ivc->irq, queue_id);
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goto request_cleanup;
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}
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return 0;
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request_cleanup:
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return -1;
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}
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static bool tegra194_bpmp_hv_is_message_ready(struct tegra_bpmp_channel *channel)
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{
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struct tegra_hv_ivc_cookie *hv_ivc = to_hv_ivc(channel->ivc);
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void *frame;
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frame = tegra_hv_ivc_read_get_next_frame(hv_ivc);
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if (IS_ERR(frame)) {
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iosys_map_clear(&channel->ib);
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return false;
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}
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iosys_map_set_vaddr(&channel->ib, frame);
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return true;
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}
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static int tegra194_bpmp_hv_ack_message(struct tegra_bpmp_channel *channel)
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{
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struct tegra_hv_ivc_cookie *hv_ivc = to_hv_ivc(channel->ivc);
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return tegra_hv_ivc_read_advance(hv_ivc);
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}
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static bool tegra194_hv_bpmp_is_channel_free(struct tegra_bpmp_channel *channel)
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{
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struct tegra_hv_ivc_cookie *hv_ivc = to_hv_ivc(channel->ivc);
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void *frame;
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frame = tegra_hv_ivc_write_get_next_frame(hv_ivc);
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if (IS_ERR(frame)) {
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iosys_map_clear(&channel->ob);
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return false;
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}
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iosys_map_set_vaddr(&channel->ob, frame);
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return true;
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}
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static int tegra194_hv_bpmp_post_message(struct tegra_bpmp_channel *channel)
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{
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struct tegra_hv_ivc_cookie *hv_ivc = to_hv_ivc(channel->ivc);
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return tegra_hv_ivc_write_advance(hv_ivc);
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}
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static void tegra194_hv_bpmp_channel_reset(struct tegra_bpmp_channel *channel)
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{
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struct tegra_hv_ivc_cookie *hv_ivc = to_hv_ivc(channel->ivc);
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/* reset the channel state */
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tegra_hv_ivc_channel_reset(hv_ivc);
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/* sync the channel state with BPMP */
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while (tegra_hv_ivc_channel_notified(hv_ivc));
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}
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static int tegra194_hv_bpmp_resume(struct tegra_bpmp *bpmp)
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{
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unsigned int i;
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/* reset message channels */
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tegra194_hv_bpmp_channel_reset(bpmp->tx_channel);
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for (i = 0; i < bpmp->threaded.count; i++)
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tegra194_hv_bpmp_channel_reset(&bpmp->threaded_channels[i]);
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return 0;
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}
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static int tegra194_hv_ivc_notify(struct tegra_bpmp *bpmp)
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{
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struct tegra_hv_ivc_cookie *hv_ivc = to_hv_ivc(bpmp->tx_channel->ivc);
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tegra_hv_ivc_notify(hv_ivc);
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return 0;
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}
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static int tegra194_hv_bpmp_init(struct tegra_bpmp *bpmp)
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{
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struct device_node *of_node = bpmp->dev->of_node;
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int err, index;
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uint32_t first_ivc_queue, num_ivc_queues;
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/* get starting ivc queue id & ivc queue count */
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hv_of_node = of_parse_phandle(of_node, "ivc_queue", 0);
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if (!hv_of_node) {
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pr_err("%s: Unable to find hypervisor node\n", __func__);
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return -EINVAL;
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}
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of_node_put(hv_of_node);
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err = of_property_read_u32_index(of_node, "ivc_queue", 1,
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&first_ivc_queue);
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if (err) {
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pr_err("%s: Failed to read start IVC queue\n",
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__func__);
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return err;
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}
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err = of_property_read_u32_index(of_node, "ivc_queue", 2,
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&num_ivc_queues);
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if (err) {
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pr_err("%s: Failed to read range of IVC queues\n",
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__func__);
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return err;
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}
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/* verify total queue count meets expectations */
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if (num_ivc_queues < (bpmp->soc->channels.thread.count +
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bpmp->soc->channels.cpu_tx.count + bpmp->soc->channels.cpu_rx.count)) {
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pr_err("%s: no of ivc queues in DT < required no of channels\n", __func__);
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return -EINVAL;
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}
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hv_bpmp_ivc_cookies = kzalloc(sizeof(struct tegra_hv_ivc_cookie *) *
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num_ivc_queues, GFP_KERNEL);
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if (!hv_bpmp_ivc_cookies) {
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pr_err("%s: Failed to allocate memory\n", __func__);
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return -ENOMEM;
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}
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err = tegra194_hv_bpmp_channel_init(bpmp->tx_channel, bpmp,
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bpmp->soc->channels.cpu_tx.offset + first_ivc_queue, false);
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if (err < 0) {
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pr_err("%s: Failed initialize tx channel\n", __func__);
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goto cleanup;
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}
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for (index = 0; index < bpmp->threaded.count; index++) {
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unsigned int idx = bpmp->soc->channels.thread.offset + index;
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err = tegra194_hv_bpmp_channel_init(&bpmp->threaded_channels[index],
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bpmp, idx + first_ivc_queue, true);
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if (err < 0) {
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pr_err("%s: Failed initialize tx channel\n", __func__);
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goto cleanup;
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}
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}
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tegra194_hv_bpmp_resume(bpmp);
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return 0;
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cleanup:
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for (index = 0; index < num_ivc_queues; index++) {
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if (hv_bpmp_ivc_cookies[index]) {
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tegra_hv_ivc_unreserve(hv_bpmp_ivc_cookies[index]);
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hv_bpmp_ivc_cookies[index] = NULL;
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}
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}
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kfree(hv_bpmp_ivc_cookies);
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return err;
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}
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static void tegra194_hv_bpmp_channel_cleanup(struct tegra_bpmp_channel *channel)
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{
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struct tegra_hv_ivc_cookie *hv_ivc = to_hv_ivc(channel->ivc);
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free_irq(hv_ivc->irq, &hv_ivc);
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tegra_hv_ivc_unreserve(hv_ivc);
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kfree(hv_ivc);
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}
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static void tegra194_hv_bpmp_deinit(struct tegra_bpmp *bpmp)
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{
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unsigned int i;
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tegra194_hv_bpmp_channel_cleanup(bpmp->tx_channel);
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for (i = 0; i < bpmp->threaded.count; i++)
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tegra194_hv_bpmp_channel_cleanup(&bpmp->threaded_channels[i]);
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}
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const struct tegra_bpmp_ops tegra194_bpmp_hv_ops = {
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.init = tegra194_hv_bpmp_init,
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.deinit = tegra194_hv_bpmp_deinit,
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.is_response_ready = tegra194_bpmp_hv_is_message_ready,
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.is_request_ready = tegra194_bpmp_hv_is_message_ready,
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.ack_response = tegra194_bpmp_hv_ack_message,
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.ack_request = tegra194_bpmp_hv_ack_message,
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.is_response_channel_free = tegra194_hv_bpmp_is_channel_free,
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.is_request_channel_free = tegra194_hv_bpmp_is_channel_free,
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.post_response = tegra194_hv_bpmp_post_message,
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.post_request = tegra194_hv_bpmp_post_message,
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.ring_doorbell = tegra194_hv_ivc_notify,
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.resume = tegra194_hv_bpmp_resume,
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};
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@@ -1,10 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*/
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* SPDX-FileCopyrightText: Copyright (c) 2016-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
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#include <linux/clk/tegra.h>
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#include <linux/genalloc.h>
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#include <linux/iosys-map.h>
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#include <linux/mailbox_client.h>
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#include <linux/module.h>
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#include <linux/of.h>
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@@ -557,7 +556,9 @@ static int tegra_bpmp_ping(struct tegra_bpmp *bpmp)
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struct mrq_ping_response response;
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struct mrq_ping_request request;
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struct tegra_bpmp_message msg;
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#if (!IS_ENABLED(CONFIG_PREEMPT_RT))
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unsigned long flags;
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#endif
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ktime_t start, end;
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int err;
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@@ -573,11 +574,17 @@ static int tegra_bpmp_ping(struct tegra_bpmp *bpmp)
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msg.rx.data = &response;
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msg.rx.size = sizeof(response);
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#if (!IS_ENABLED(CONFIG_PREEMPT_RT))
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local_irq_save(flags);
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start = ktime_get();
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err = tegra_bpmp_transfer_atomic(bpmp, &msg);
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end = ktime_get();
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local_irq_restore(flags);
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#else
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start = ktime_get();
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err = tegra_bpmp_transfer(bpmp, &msg);
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end = ktime_get();
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#endif
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if (!err)
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dev_dbg(bpmp->dev,
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@@ -678,7 +685,10 @@ void tegra_bpmp_handle_rx(struct tegra_bpmp *bpmp)
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count = bpmp->soc->channels.thread.count;
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busy = bpmp->threaded.busy;
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if (tegra_bpmp_is_request_ready(channel)) {
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/* Check if supported incoming channel.
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* This won't be called for Guest Linux as channel->ib mapping won't be set.
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*/
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if (iosys_map_is_set(&channel->ib) && tegra_bpmp_is_request_ready(channel)) {
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unsigned int mrq = tegra_bpmp_mb_read_field(&channel->ib, code);
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tegra_bpmp_handle_mrq(bpmp, mrq, channel);
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@@ -884,6 +894,25 @@ static const struct tegra_bpmp_soc tegra210_soc = {
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};
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#endif
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#if IS_ENABLED(CONFIG_TEGRA_HV_DRIVER)
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static const struct tegra_bpmp_soc t194_safe_hv_soc = {
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.channels = {
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.cpu_tx = {
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.offset = 3,
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.count = 1,
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.timeout = 30 * USEC_PER_SEC,
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},
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.thread = {
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.offset = 0,
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.count = 3,
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.timeout = 30 * USEC_PER_SEC,
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},
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},
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.ops = &tegra194_bpmp_hv_ops,
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.num_resets = 193,
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};
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#endif
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static const struct of_device_id tegra_bpmp_match[] = {
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) || \
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IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
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@@ -892,6 +921,9 @@ static const struct of_device_id tegra_bpmp_match[] = {
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#endif
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#if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
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{ .compatible = "nvidia,tegra210-bpmp", .data = &tegra210_soc },
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#endif
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#if IS_ENABLED(CONFIG_TEGRA_HV_DRIVER)
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{ .compatible = "nvidia,tegra194-safe-bpmp-hv", .data = &t194_safe_hv_soc },
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#endif
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{ }
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};
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