Merge branch 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6
* 'for-next' of git://git.kernel.org/pub/scm/linux/kernel/git/sameo/mfd-2.6: (66 commits) mfd: Fix ucb1x00 build failure for collie_defconfig mfd: Fix lpc_sch related depends/selects, fix build error gpio: Fix sch_gpio warning gpio: add Intel SCH GPIO controller driver i2c: convert i2c-isch to platform_device mfd: Use completion interrupt for WM831x AUXADC mfd: Use completion interrupt for WM835x AUXADC mfd: Introduce remove_script function for twl4030 mfd/mmc: SDHI Kconfig update mfd: sh_mobile_sdhi MMC_CAP_MMC_HIGHSPEED support gpiolib: Force wm831x GPIOs into GPIO mode when requested mfd: Add WM831x revision B support gpiolib: Correct debugfs display of WM831x GPIO inversion gpiolib: Actually set output state in wm831x_gpio_direction_output() tmio_mmc: Balance cell enable()/disable() calls tmio_mmc: Remove const from platform data V3 tmio_mmc: Use 100ms mmc_detect_change() delay tmio_mmc: Add MMC_CAP_MMC_HIGHSPEED support V2 tmio_mmc: Keep card-detect interrupts enabled mfd: Add twl6030 base addr for ID0, ID1, ID2 ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,24 @@
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#ifndef __LINUX_HTCPLD_H
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#define __LINUX_HTCPLD_H
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struct htcpld_chip_platform_data {
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unsigned int addr;
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unsigned int reset;
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unsigned int num_gpios;
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unsigned int gpio_out_base;
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unsigned int gpio_in_base;
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unsigned int irq_base;
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unsigned int num_irqs;
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};
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struct htcpld_core_platform_data {
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unsigned int int_reset_gpio_hi;
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unsigned int int_reset_gpio_lo;
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unsigned int i2c_adapter_id;
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struct htcpld_chip_platform_data *chip;
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unsigned int num_chip;
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};
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#endif /* __LINUX_HTCPLD_H */
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+22
-6
@@ -80,6 +80,11 @@
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#define TWL_MODULE_PM_MASTER TWL4030_MODULE_PM_MASTER
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#define TWL_MODULE_PM_RECEIVER TWL4030_MODULE_PM_RECEIVER
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#define TWL_MODULE_RTC TWL4030_MODULE_RTC
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#define TWL_MODULE_PWM TWL4030_MODULE_PWM0
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#define TWL6030_MODULE_ID0 0x0D
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#define TWL6030_MODULE_ID1 0x0E
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#define TWL6030_MODULE_ID2 0x0F
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#define GPIO_INTR_OFFSET 0
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#define KEYPAD_INTR_OFFSET 1
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@@ -239,6 +244,21 @@ int twl6030_interrupt_mask(u8 bit_mask, u8 offset);
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/*----------------------------------------------------------------------*/
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/*Interface Bit Register (INTBR) offsets
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*(Use TWL_4030_MODULE_INTBR)
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*/
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#define REG_GPPUPDCTR1 0x0F
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/*I2C1 and I2C4(SR) SDA/SCL pull-up control bits */
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#define I2C_SCL_CTRL_PU BIT(0)
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#define I2C_SDA_CTRL_PU BIT(2)
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#define SR_I2C_SCL_CTRL_PU BIT(4)
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#define SR_I2C_SDA_CTRL_PU BIT(6)
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/*----------------------------------------------------------------------*/
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/*
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* Keypad register offsets (use TWL4030_MODULE_KEYPAD)
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* ... SIH/interrupt only
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@@ -530,6 +550,7 @@ struct twl4030_power_data {
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};
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extern void twl4030_power_init(struct twl4030_power_data *triton2_scripts);
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extern int twl4030_remove_script(u8 flags);
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struct twl4030_codec_audio_data {
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unsigned int audio_mclk;
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@@ -605,12 +626,7 @@ int twl4030_sih_setup(int module);
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#define TWL4030_VAUX3_DEV_GRP 0x1F
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#define TWL4030_VAUX3_DEDICATED 0x22
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#if defined(CONFIG_TWL4030_BCI_BATTERY) || \
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defined(CONFIG_TWL4030_BCI_BATTERY_MODULE)
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extern int twl4030charger_usb_en(int enable);
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#else
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static inline int twl4030charger_usb_en(int enable) { return 0; }
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#endif
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static inline int twl4030charger_usb_en(int enable) { return 0; }
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/*----------------------------------------------------------------------*/
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@@ -1,217 +0,0 @@
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/*
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* Marvell 88PM8607 Interface
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*
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* Copyright (C) 2009 Marvell International Ltd.
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* Haojian Zhuang <haojian.zhuang@marvell.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
|
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*/
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#ifndef __LINUX_MFD_88PM8607_H
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#define __LINUX_MFD_88PM8607_H
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enum {
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PM8607_ID_BUCK1 = 0,
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PM8607_ID_BUCK2,
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PM8607_ID_BUCK3,
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PM8607_ID_LDO1,
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PM8607_ID_LDO2,
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PM8607_ID_LDO3,
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PM8607_ID_LDO4,
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PM8607_ID_LDO5,
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PM8607_ID_LDO6,
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PM8607_ID_LDO7,
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PM8607_ID_LDO8,
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PM8607_ID_LDO9,
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PM8607_ID_LDO10,
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PM8607_ID_LDO12,
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PM8607_ID_LDO14,
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PM8607_ID_RG_MAX,
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};
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#define CHIP_ID (0x40)
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#define CHIP_ID_MASK (0xF8)
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/* Interrupt Registers */
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#define PM8607_STATUS_1 (0x01)
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#define PM8607_STATUS_2 (0x02)
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#define PM8607_INT_STATUS1 (0x03)
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#define PM8607_INT_STATUS2 (0x04)
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#define PM8607_INT_STATUS3 (0x05)
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#define PM8607_INT_MASK_1 (0x06)
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#define PM8607_INT_MASK_2 (0x07)
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#define PM8607_INT_MASK_3 (0x08)
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/* Regulator Control Registers */
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#define PM8607_LDO1 (0x10)
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#define PM8607_LDO2 (0x11)
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#define PM8607_LDO3 (0x12)
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#define PM8607_LDO4 (0x13)
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#define PM8607_LDO5 (0x14)
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#define PM8607_LDO6 (0x15)
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#define PM8607_LDO7 (0x16)
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#define PM8607_LDO8 (0x17)
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#define PM8607_LDO9 (0x18)
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#define PM8607_LDO10 (0x19)
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#define PM8607_LDO12 (0x1A)
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#define PM8607_LDO14 (0x1B)
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#define PM8607_SLEEP_MODE1 (0x1C)
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#define PM8607_SLEEP_MODE2 (0x1D)
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#define PM8607_SLEEP_MODE3 (0x1E)
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#define PM8607_SLEEP_MODE4 (0x1F)
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#define PM8607_GO (0x20)
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#define PM8607_SLEEP_BUCK1 (0x21)
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#define PM8607_SLEEP_BUCK2 (0x22)
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#define PM8607_SLEEP_BUCK3 (0x23)
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#define PM8607_BUCK1 (0x24)
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#define PM8607_BUCK2 (0x25)
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#define PM8607_BUCK3 (0x26)
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#define PM8607_BUCK_CONTROLS (0x27)
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#define PM8607_SUPPLIES_EN11 (0x2B)
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#define PM8607_SUPPLIES_EN12 (0x2C)
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#define PM8607_GROUP1 (0x2D)
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#define PM8607_GROUP2 (0x2E)
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#define PM8607_GROUP3 (0x2F)
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#define PM8607_GROUP4 (0x30)
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#define PM8607_GROUP5 (0x31)
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#define PM8607_GROUP6 (0x32)
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#define PM8607_SUPPLIES_EN21 (0x33)
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#define PM8607_SUPPLIES_EN22 (0x34)
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/* RTC Control Registers */
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#define PM8607_RTC1 (0xA0)
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#define PM8607_RTC_COUNTER1 (0xA1)
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#define PM8607_RTC_COUNTER2 (0xA2)
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#define PM8607_RTC_COUNTER3 (0xA3)
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#define PM8607_RTC_COUNTER4 (0xA4)
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#define PM8607_RTC_EXPIRE1 (0xA5)
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#define PM8607_RTC_EXPIRE2 (0xA6)
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#define PM8607_RTC_EXPIRE3 (0xA7)
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#define PM8607_RTC_EXPIRE4 (0xA8)
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#define PM8607_RTC_TRIM1 (0xA9)
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#define PM8607_RTC_TRIM2 (0xAA)
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#define PM8607_RTC_TRIM3 (0xAB)
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#define PM8607_RTC_TRIM4 (0xAC)
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#define PM8607_RTC_MISC1 (0xAD)
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#define PM8607_RTC_MISC2 (0xAE)
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#define PM8607_RTC_MISC3 (0xAF)
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/* Misc Registers */
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#define PM8607_CHIP_ID (0x00)
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#define PM8607_LDO1 (0x10)
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#define PM8607_DVC3 (0x26)
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#define PM8607_MISC1 (0x40)
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/* bit definitions for PM8607 events */
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#define PM8607_EVENT_ONKEY (1 << 0)
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#define PM8607_EVENT_EXTON (1 << 1)
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#define PM8607_EVENT_CHG (1 << 2)
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#define PM8607_EVENT_BAT (1 << 3)
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#define PM8607_EVENT_RTC (1 << 4)
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#define PM8607_EVENT_CC (1 << 5)
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#define PM8607_EVENT_VBAT (1 << 8)
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#define PM8607_EVENT_VCHG (1 << 9)
|
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#define PM8607_EVENT_VSYS (1 << 10)
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#define PM8607_EVENT_TINT (1 << 11)
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#define PM8607_EVENT_GPADC0 (1 << 12)
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#define PM8607_EVENT_GPADC1 (1 << 13)
|
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#define PM8607_EVENT_GPADC2 (1 << 14)
|
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#define PM8607_EVENT_GPADC3 (1 << 15)
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#define PM8607_EVENT_AUDIO_SHORT (1 << 16)
|
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#define PM8607_EVENT_PEN (1 << 17)
|
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#define PM8607_EVENT_HEADSET (1 << 18)
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#define PM8607_EVENT_HOOK (1 << 19)
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#define PM8607_EVENT_MICIN (1 << 20)
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#define PM8607_EVENT_CHG_TIMEOUT (1 << 21)
|
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#define PM8607_EVENT_CHG_DONE (1 << 22)
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#define PM8607_EVENT_CHG_FAULT (1 << 23)
|
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|
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/* bit definitions of Status Query Interface */
|
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#define PM8607_STATUS_CC (1 << 3)
|
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#define PM8607_STATUS_PEN (1 << 4)
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#define PM8607_STATUS_HEADSET (1 << 5)
|
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#define PM8607_STATUS_HOOK (1 << 6)
|
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#define PM8607_STATUS_MICIN (1 << 7)
|
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#define PM8607_STATUS_ONKEY (1 << 8)
|
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#define PM8607_STATUS_EXTON (1 << 9)
|
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#define PM8607_STATUS_CHG (1 << 10)
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#define PM8607_STATUS_BAT (1 << 11)
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#define PM8607_STATUS_VBUS (1 << 12)
|
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#define PM8607_STATUS_OV (1 << 13)
|
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|
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/* bit definitions of BUCK3 */
|
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#define PM8607_BUCK3_DOUBLE (1 << 6)
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|
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/* bit definitions of Misc1 */
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#define PM8607_MISC1_PI2C (1 << 0)
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|
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/* Interrupt Number in 88PM8607 */
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enum {
|
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PM8607_IRQ_ONKEY = 0,
|
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PM8607_IRQ_EXTON,
|
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PM8607_IRQ_CHG,
|
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PM8607_IRQ_BAT,
|
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PM8607_IRQ_RTC,
|
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PM8607_IRQ_VBAT = 8,
|
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PM8607_IRQ_VCHG,
|
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PM8607_IRQ_VSYS,
|
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PM8607_IRQ_TINT,
|
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PM8607_IRQ_GPADC0,
|
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PM8607_IRQ_GPADC1,
|
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PM8607_IRQ_GPADC2,
|
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PM8607_IRQ_GPADC3,
|
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PM8607_IRQ_AUDIO_SHORT = 16,
|
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PM8607_IRQ_PEN,
|
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PM8607_IRQ_HEADSET,
|
||||
PM8607_IRQ_HOOK,
|
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PM8607_IRQ_MICIN,
|
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PM8607_IRQ_CHG_FAIL,
|
||||
PM8607_IRQ_CHG_DONE,
|
||||
PM8607_IRQ_CHG_FAULT,
|
||||
};
|
||||
|
||||
enum {
|
||||
PM8607_CHIP_A0 = 0x40,
|
||||
PM8607_CHIP_A1 = 0x41,
|
||||
PM8607_CHIP_B0 = 0x48,
|
||||
};
|
||||
|
||||
|
||||
struct pm8607_chip {
|
||||
struct device *dev;
|
||||
struct mutex io_lock;
|
||||
struct i2c_client *client;
|
||||
|
||||
int (*read)(struct pm8607_chip *chip, int reg, int bytes, void *dest);
|
||||
int (*write)(struct pm8607_chip *chip, int reg, int bytes, void *src);
|
||||
|
||||
int buck3_double; /* DVC ramp slope double */
|
||||
unsigned char chip_id;
|
||||
|
||||
};
|
||||
|
||||
#define PM8607_MAX_REGULATOR 15 /* 3 Bucks, 12 LDOs */
|
||||
|
||||
enum {
|
||||
GI2C_PORT = 0,
|
||||
PI2C_PORT,
|
||||
};
|
||||
|
||||
struct pm8607_platform_data {
|
||||
int i2c_port; /* Controlled by GI2C or PI2C */
|
||||
struct regulator_init_data *regulator[PM8607_MAX_REGULATOR];
|
||||
};
|
||||
|
||||
extern int pm8607_reg_read(struct pm8607_chip *, int);
|
||||
extern int pm8607_reg_write(struct pm8607_chip *, int, unsigned char);
|
||||
extern int pm8607_bulk_read(struct pm8607_chip *, int, int,
|
||||
unsigned char *);
|
||||
extern int pm8607_bulk_write(struct pm8607_chip *, int, int,
|
||||
unsigned char *);
|
||||
extern int pm8607_set_bits(struct pm8607_chip *, int, unsigned char,
|
||||
unsigned char);
|
||||
#endif /* __LINUX_MFD_88PM8607_H */
|
||||
@@ -0,0 +1,375 @@
|
||||
/*
|
||||
* Marvell 88PM860x Interface
|
||||
*
|
||||
* Copyright (C) 2009 Marvell International Ltd.
|
||||
* Haojian Zhuang <haojian.zhuang@marvell.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_88PM860X_H
|
||||
#define __LINUX_MFD_88PM860X_H
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#define MFD_NAME_SIZE (40)
|
||||
|
||||
enum {
|
||||
CHIP_INVALID = 0,
|
||||
CHIP_PM8606,
|
||||
CHIP_PM8607,
|
||||
CHIP_MAX,
|
||||
};
|
||||
|
||||
enum {
|
||||
PM8606_ID_INVALID,
|
||||
PM8606_ID_BACKLIGHT,
|
||||
PM8606_ID_LED,
|
||||
PM8606_ID_VIBRATOR,
|
||||
PM8606_ID_TOUCH,
|
||||
PM8606_ID_SOUND,
|
||||
PM8606_ID_CHARGER,
|
||||
PM8606_ID_MAX,
|
||||
};
|
||||
|
||||
enum {
|
||||
PM8606_BACKLIGHT1 = 0,
|
||||
PM8606_BACKLIGHT2,
|
||||
PM8606_BACKLIGHT3,
|
||||
};
|
||||
|
||||
enum {
|
||||
PM8606_LED1_RED = 0,
|
||||
PM8606_LED1_GREEN,
|
||||
PM8606_LED1_BLUE,
|
||||
PM8606_LED2_RED,
|
||||
PM8606_LED2_GREEN,
|
||||
PM8606_LED2_BLUE,
|
||||
PM8607_LED_VIBRATOR,
|
||||
};
|
||||
|
||||
|
||||
/* 8606 Registers */
|
||||
#define PM8606_DCM_BOOST (0x00)
|
||||
#define PM8606_PWM (0x01)
|
||||
|
||||
/* Backlight Registers */
|
||||
#define PM8606_WLED1A (0x02)
|
||||
#define PM8606_WLED1B (0x03)
|
||||
#define PM8606_WLED2A (0x04)
|
||||
#define PM8606_WLED2B (0x05)
|
||||
#define PM8606_WLED3A (0x06)
|
||||
#define PM8606_WLED3B (0x07)
|
||||
|
||||
/* LED Registers */
|
||||
#define PM8606_RGB2A (0x08)
|
||||
#define PM8606_RGB2B (0x09)
|
||||
#define PM8606_RGB2C (0x0A)
|
||||
#define PM8606_RGB2D (0x0B)
|
||||
#define PM8606_RGB1A (0x0C)
|
||||
#define PM8606_RGB1B (0x0D)
|
||||
#define PM8606_RGB1C (0x0E)
|
||||
#define PM8606_RGB1D (0x0F)
|
||||
|
||||
#define PM8606_PREREGULATORA (0x10)
|
||||
#define PM8606_PREREGULATORB (0x11)
|
||||
#define PM8606_VIBRATORA (0x12)
|
||||
#define PM8606_VIBRATORB (0x13)
|
||||
#define PM8606_VCHG (0x14)
|
||||
#define PM8606_VSYS (0x15)
|
||||
#define PM8606_MISC (0x16)
|
||||
#define PM8606_CHIP_ID (0x17)
|
||||
#define PM8606_STATUS (0x18)
|
||||
#define PM8606_FLAGS (0x19)
|
||||
#define PM8606_PROTECTA (0x1A)
|
||||
#define PM8606_PROTECTB (0x1B)
|
||||
#define PM8606_PROTECTC (0x1C)
|
||||
|
||||
/* Bit definitions of PM8606 registers */
|
||||
#define PM8606_DCM_500MA (0x0) /* current limit */
|
||||
#define PM8606_DCM_750MA (0x1)
|
||||
#define PM8606_DCM_1000MA (0x2)
|
||||
#define PM8606_DCM_1250MA (0x3)
|
||||
#define PM8606_DCM_250MV (0x0 << 2)
|
||||
#define PM8606_DCM_300MV (0x1 << 2)
|
||||
#define PM8606_DCM_350MV (0x2 << 2)
|
||||
#define PM8606_DCM_400MV (0x3 << 2)
|
||||
|
||||
#define PM8606_PWM_31200HZ (0x0)
|
||||
#define PM8606_PWM_15600HZ (0x1)
|
||||
#define PM8606_PWM_7800HZ (0x2)
|
||||
#define PM8606_PWM_3900HZ (0x3)
|
||||
#define PM8606_PWM_1950HZ (0x4)
|
||||
#define PM8606_PWM_976HZ (0x5)
|
||||
#define PM8606_PWM_488HZ (0x6)
|
||||
#define PM8606_PWM_244HZ (0x7)
|
||||
#define PM8606_PWM_FREQ_MASK (0x7)
|
||||
|
||||
#define PM8606_WLED_ON (1 << 0)
|
||||
#define PM8606_WLED_CURRENT(x) ((x & 0x1F) << 1)
|
||||
|
||||
#define PM8606_LED_CURRENT(x) (((x >> 2) & 0x07) << 5)
|
||||
|
||||
#define PM8606_VSYS_EN (1 << 1)
|
||||
|
||||
#define PM8606_MISC_OSC_EN (1 << 4)
|
||||
|
||||
enum {
|
||||
PM8607_ID_BUCK1 = 0,
|
||||
PM8607_ID_BUCK2,
|
||||
PM8607_ID_BUCK3,
|
||||
|
||||
PM8607_ID_LDO1,
|
||||
PM8607_ID_LDO2,
|
||||
PM8607_ID_LDO3,
|
||||
PM8607_ID_LDO4,
|
||||
PM8607_ID_LDO5,
|
||||
PM8607_ID_LDO6,
|
||||
PM8607_ID_LDO7,
|
||||
PM8607_ID_LDO8,
|
||||
PM8607_ID_LDO9,
|
||||
PM8607_ID_LDO10,
|
||||
PM8607_ID_LDO12,
|
||||
PM8607_ID_LDO14,
|
||||
|
||||
PM8607_ID_RG_MAX,
|
||||
};
|
||||
|
||||
#define PM8607_VERSION (0x40) /* 8607 chip ID */
|
||||
#define PM8607_VERSION_MASK (0xF0) /* 8607 chip ID mask */
|
||||
|
||||
/* Interrupt Registers */
|
||||
#define PM8607_STATUS_1 (0x01)
|
||||
#define PM8607_STATUS_2 (0x02)
|
||||
#define PM8607_INT_STATUS1 (0x03)
|
||||
#define PM8607_INT_STATUS2 (0x04)
|
||||
#define PM8607_INT_STATUS3 (0x05)
|
||||
#define PM8607_INT_MASK_1 (0x06)
|
||||
#define PM8607_INT_MASK_2 (0x07)
|
||||
#define PM8607_INT_MASK_3 (0x08)
|
||||
|
||||
/* Regulator Control Registers */
|
||||
#define PM8607_LDO1 (0x10)
|
||||
#define PM8607_LDO2 (0x11)
|
||||
#define PM8607_LDO3 (0x12)
|
||||
#define PM8607_LDO4 (0x13)
|
||||
#define PM8607_LDO5 (0x14)
|
||||
#define PM8607_LDO6 (0x15)
|
||||
#define PM8607_LDO7 (0x16)
|
||||
#define PM8607_LDO8 (0x17)
|
||||
#define PM8607_LDO9 (0x18)
|
||||
#define PM8607_LDO10 (0x19)
|
||||
#define PM8607_LDO12 (0x1A)
|
||||
#define PM8607_LDO14 (0x1B)
|
||||
#define PM8607_SLEEP_MODE1 (0x1C)
|
||||
#define PM8607_SLEEP_MODE2 (0x1D)
|
||||
#define PM8607_SLEEP_MODE3 (0x1E)
|
||||
#define PM8607_SLEEP_MODE4 (0x1F)
|
||||
#define PM8607_GO (0x20)
|
||||
#define PM8607_SLEEP_BUCK1 (0x21)
|
||||
#define PM8607_SLEEP_BUCK2 (0x22)
|
||||
#define PM8607_SLEEP_BUCK3 (0x23)
|
||||
#define PM8607_BUCK1 (0x24)
|
||||
#define PM8607_BUCK2 (0x25)
|
||||
#define PM8607_BUCK3 (0x26)
|
||||
#define PM8607_BUCK_CONTROLS (0x27)
|
||||
#define PM8607_SUPPLIES_EN11 (0x2B)
|
||||
#define PM8607_SUPPLIES_EN12 (0x2C)
|
||||
#define PM8607_GROUP1 (0x2D)
|
||||
#define PM8607_GROUP2 (0x2E)
|
||||
#define PM8607_GROUP3 (0x2F)
|
||||
#define PM8607_GROUP4 (0x30)
|
||||
#define PM8607_GROUP5 (0x31)
|
||||
#define PM8607_GROUP6 (0x32)
|
||||
#define PM8607_SUPPLIES_EN21 (0x33)
|
||||
#define PM8607_SUPPLIES_EN22 (0x34)
|
||||
|
||||
/* Vibrator Control Registers */
|
||||
#define PM8607_VIBRATOR_SET (0x28)
|
||||
#define PM8607_VIBRATOR_PWM (0x29)
|
||||
|
||||
/* GPADC Registers */
|
||||
#define PM8607_GP_BIAS1 (0x4F)
|
||||
#define PM8607_MEAS_EN1 (0x50)
|
||||
#define PM8607_MEAS_EN2 (0x51)
|
||||
#define PM8607_MEAS_EN3 (0x52)
|
||||
#define PM8607_MEAS_OFF_TIME1 (0x53)
|
||||
#define PM8607_MEAS_OFF_TIME2 (0x54)
|
||||
#define PM8607_TSI_PREBIAS (0x55) /* prebias time */
|
||||
#define PM8607_PD_PREBIAS (0x56) /* prebias time */
|
||||
#define PM8607_GPADC_MISC1 (0x57)
|
||||
|
||||
/* RTC Control Registers */
|
||||
#define PM8607_RTC1 (0xA0)
|
||||
#define PM8607_RTC_COUNTER1 (0xA1)
|
||||
#define PM8607_RTC_COUNTER2 (0xA2)
|
||||
#define PM8607_RTC_COUNTER3 (0xA3)
|
||||
#define PM8607_RTC_COUNTER4 (0xA4)
|
||||
#define PM8607_RTC_EXPIRE1 (0xA5)
|
||||
#define PM8607_RTC_EXPIRE2 (0xA6)
|
||||
#define PM8607_RTC_EXPIRE3 (0xA7)
|
||||
#define PM8607_RTC_EXPIRE4 (0xA8)
|
||||
#define PM8607_RTC_TRIM1 (0xA9)
|
||||
#define PM8607_RTC_TRIM2 (0xAA)
|
||||
#define PM8607_RTC_TRIM3 (0xAB)
|
||||
#define PM8607_RTC_TRIM4 (0xAC)
|
||||
#define PM8607_RTC_MISC1 (0xAD)
|
||||
#define PM8607_RTC_MISC2 (0xAE)
|
||||
#define PM8607_RTC_MISC3 (0xAF)
|
||||
|
||||
/* Misc Registers */
|
||||
#define PM8607_CHIP_ID (0x00)
|
||||
#define PM8607_B0_MISC1 (0x0C)
|
||||
#define PM8607_LDO1 (0x10)
|
||||
#define PM8607_DVC3 (0x26)
|
||||
#define PM8607_A1_MISC1 (0x40)
|
||||
|
||||
/* bit definitions of Status Query Interface */
|
||||
#define PM8607_STATUS_CC (1 << 3)
|
||||
#define PM8607_STATUS_PEN (1 << 4)
|
||||
#define PM8607_STATUS_HEADSET (1 << 5)
|
||||
#define PM8607_STATUS_HOOK (1 << 6)
|
||||
#define PM8607_STATUS_MICIN (1 << 7)
|
||||
#define PM8607_STATUS_ONKEY (1 << 8)
|
||||
#define PM8607_STATUS_EXTON (1 << 9)
|
||||
#define PM8607_STATUS_CHG (1 << 10)
|
||||
#define PM8607_STATUS_BAT (1 << 11)
|
||||
#define PM8607_STATUS_VBUS (1 << 12)
|
||||
#define PM8607_STATUS_OV (1 << 13)
|
||||
|
||||
/* bit definitions of BUCK3 */
|
||||
#define PM8607_BUCK3_DOUBLE (1 << 6)
|
||||
|
||||
/* bit definitions of Misc1 */
|
||||
#define PM8607_A1_MISC1_PI2C (1 << 0)
|
||||
#define PM8607_B0_MISC1_INV_INT (1 << 0)
|
||||
#define PM8607_B0_MISC1_INT_CLEAR (1 << 1)
|
||||
#define PM8607_B0_MISC1_INT_MASK (1 << 2)
|
||||
#define PM8607_B0_MISC1_PI2C (1 << 3)
|
||||
#define PM8607_B0_MISC1_RESET (1 << 6)
|
||||
|
||||
/* bits definitions of GPADC */
|
||||
#define PM8607_GPADC_EN (1 << 0)
|
||||
#define PM8607_GPADC_PREBIAS_MASK (3 << 1)
|
||||
#define PM8607_GPADC_SLOT_CYCLE_MASK (3 << 3) /* slow mode */
|
||||
#define PM8607_GPADC_OFF_SCALE_MASK (3 << 5) /* GP sleep mode */
|
||||
#define PM8607_GPADC_SW_CAL_MASK (1 << 7)
|
||||
|
||||
#define PM8607_PD_PREBIAS_MASK (0x1F << 0)
|
||||
#define PM8607_PD_PRECHG_MASK (7 << 5)
|
||||
|
||||
/* Interrupt Number in 88PM8607 */
|
||||
enum {
|
||||
PM8607_IRQ_ONKEY,
|
||||
PM8607_IRQ_EXTON,
|
||||
PM8607_IRQ_CHG,
|
||||
PM8607_IRQ_BAT,
|
||||
PM8607_IRQ_RTC,
|
||||
PM8607_IRQ_CC,
|
||||
PM8607_IRQ_VBAT,
|
||||
PM8607_IRQ_VCHG,
|
||||
PM8607_IRQ_VSYS,
|
||||
PM8607_IRQ_TINT,
|
||||
PM8607_IRQ_GPADC0,
|
||||
PM8607_IRQ_GPADC1,
|
||||
PM8607_IRQ_GPADC2,
|
||||
PM8607_IRQ_GPADC3,
|
||||
PM8607_IRQ_AUDIO_SHORT,
|
||||
PM8607_IRQ_PEN,
|
||||
PM8607_IRQ_HEADSET,
|
||||
PM8607_IRQ_HOOK,
|
||||
PM8607_IRQ_MICIN,
|
||||
PM8607_IRQ_CHG_FAIL,
|
||||
PM8607_IRQ_CHG_DONE,
|
||||
PM8607_IRQ_CHG_FAULT,
|
||||
};
|
||||
|
||||
enum {
|
||||
PM8607_CHIP_A0 = 0x40,
|
||||
PM8607_CHIP_A1 = 0x41,
|
||||
PM8607_CHIP_B0 = 0x48,
|
||||
};
|
||||
|
||||
struct pm860x_chip {
|
||||
struct device *dev;
|
||||
struct mutex io_lock;
|
||||
struct mutex irq_lock;
|
||||
struct i2c_client *client;
|
||||
struct i2c_client *companion; /* companion chip client */
|
||||
|
||||
int buck3_double; /* DVC ramp slope double */
|
||||
unsigned short companion_addr;
|
||||
int id;
|
||||
int irq_mode;
|
||||
int irq_base;
|
||||
int core_irq;
|
||||
unsigned char chip_version;
|
||||
|
||||
};
|
||||
|
||||
#define PM8607_MAX_REGULATOR 15 /* 3 Bucks, 12 LDOs */
|
||||
|
||||
enum {
|
||||
GI2C_PORT = 0,
|
||||
PI2C_PORT,
|
||||
};
|
||||
|
||||
struct pm860x_backlight_pdata {
|
||||
int id;
|
||||
int pwm;
|
||||
int iset;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
struct pm860x_led_pdata {
|
||||
int id;
|
||||
int iset;
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
struct pm860x_touch_pdata {
|
||||
int gpadc_prebias;
|
||||
int slot_cycle;
|
||||
int off_scale;
|
||||
int sw_cal;
|
||||
int tsi_prebias; /* time, slot */
|
||||
int pen_prebias; /* time, slot */
|
||||
int pen_prechg; /* time, slot */
|
||||
int res_x; /* resistor of Xplate */
|
||||
unsigned long flags;
|
||||
};
|
||||
|
||||
struct pm860x_power_pdata {
|
||||
unsigned fast_charge; /* charge current */
|
||||
};
|
||||
|
||||
struct pm860x_platform_data {
|
||||
struct pm860x_backlight_pdata *backlight;
|
||||
struct pm860x_led_pdata *led;
|
||||
struct pm860x_touch_pdata *touch;
|
||||
struct pm860x_power_pdata *power;
|
||||
|
||||
unsigned short companion_addr; /* I2C address of companion chip */
|
||||
int i2c_port; /* Controlled by GI2C or PI2C */
|
||||
int irq_mode; /* Clear interrupt by read/write(0/1) */
|
||||
int irq_base; /* IRQ base number of 88pm860x */
|
||||
struct regulator_init_data *regulator[PM8607_MAX_REGULATOR];
|
||||
};
|
||||
|
||||
extern char pm860x_backlight_name[][MFD_NAME_SIZE];
|
||||
extern char pm860x_led_name[][MFD_NAME_SIZE];
|
||||
|
||||
extern int pm860x_reg_read(struct i2c_client *, int);
|
||||
extern int pm860x_reg_write(struct i2c_client *, int, unsigned char);
|
||||
extern int pm860x_bulk_read(struct i2c_client *, int, int, unsigned char *);
|
||||
extern int pm860x_bulk_write(struct i2c_client *, int, int, unsigned char *);
|
||||
extern int pm860x_set_bits(struct i2c_client *, int, unsigned char,
|
||||
unsigned char);
|
||||
|
||||
extern int pm860x_device_init(struct pm860x_chip *chip,
|
||||
struct pm860x_platform_data *pdata);
|
||||
extern void pm860x_device_exit(struct pm860x_chip *chip);
|
||||
|
||||
#endif /* __LINUX_MFD_88PM860X_H */
|
||||
@@ -6,7 +6,6 @@
|
||||
*/
|
||||
|
||||
#include <linux/device.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
|
||||
#ifndef MFD_AB3100_H
|
||||
@@ -74,7 +73,6 @@
|
||||
* @testreg_client: secondary client for test registers
|
||||
* @chip_name: name of this chip variant
|
||||
* @chip_id: 8 bit chip ID for this chip variant
|
||||
* @work: an event handling worker
|
||||
* @event_subscribers: event subscribers are listed here
|
||||
* @startup_events: a copy of the first reading of the event registers
|
||||
* @startup_events_read: whether the first events have been read
|
||||
@@ -90,7 +88,6 @@ struct ab3100 {
|
||||
struct i2c_client *testreg_client;
|
||||
char chip_name[32];
|
||||
u8 chip_id;
|
||||
struct work_struct work;
|
||||
struct blocking_notifier_head event_subscribers;
|
||||
u32 startup_events;
|
||||
bool startup_events_read;
|
||||
|
||||
@@ -0,0 +1,253 @@
|
||||
/*
|
||||
* Maxim8925 Interface
|
||||
*
|
||||
* Copyright (C) 2009 Marvell International Ltd.
|
||||
* Haojian Zhuang <haojian.zhuang@marvell.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __LINUX_MFD_MAX8925_H
|
||||
#define __LINUX_MFD_MAX8925_H
|
||||
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
/* Unified sub device IDs for MAX8925 */
|
||||
enum {
|
||||
MAX8925_ID_SD1,
|
||||
MAX8925_ID_SD2,
|
||||
MAX8925_ID_SD3,
|
||||
MAX8925_ID_LDO1,
|
||||
MAX8925_ID_LDO2,
|
||||
MAX8925_ID_LDO3,
|
||||
MAX8925_ID_LDO4,
|
||||
MAX8925_ID_LDO5,
|
||||
MAX8925_ID_LDO6,
|
||||
MAX8925_ID_LDO7,
|
||||
MAX8925_ID_LDO8,
|
||||
MAX8925_ID_LDO9,
|
||||
MAX8925_ID_LDO10,
|
||||
MAX8925_ID_LDO11,
|
||||
MAX8925_ID_LDO12,
|
||||
MAX8925_ID_LDO13,
|
||||
MAX8925_ID_LDO14,
|
||||
MAX8925_ID_LDO15,
|
||||
MAX8925_ID_LDO16,
|
||||
MAX8925_ID_LDO17,
|
||||
MAX8925_ID_LDO18,
|
||||
MAX8925_ID_LDO19,
|
||||
MAX8925_ID_LDO20,
|
||||
MAX8925_ID_MAX,
|
||||
};
|
||||
|
||||
enum {
|
||||
/*
|
||||
* Charging current threshold trigger going from fast charge
|
||||
* to TOPOFF charge. From 5% to 20% of fasting charging current.
|
||||
*/
|
||||
MAX8925_TOPOFF_THR_5PER,
|
||||
MAX8925_TOPOFF_THR_10PER,
|
||||
MAX8925_TOPOFF_THR_15PER,
|
||||
MAX8925_TOPOFF_THR_20PER,
|
||||
};
|
||||
|
||||
enum {
|
||||
/* Fast charging current */
|
||||
MAX8925_FCHG_85MA,
|
||||
MAX8925_FCHG_300MA,
|
||||
MAX8925_FCHG_460MA,
|
||||
MAX8925_FCHG_600MA,
|
||||
MAX8925_FCHG_700MA,
|
||||
MAX8925_FCHG_800MA,
|
||||
MAX8925_FCHG_900MA,
|
||||
MAX8925_FCHG_1000MA,
|
||||
};
|
||||
|
||||
/* Charger registers */
|
||||
#define MAX8925_CHG_IRQ1 (0x7e)
|
||||
#define MAX8925_CHG_IRQ2 (0x7f)
|
||||
#define MAX8925_CHG_IRQ1_MASK (0x80)
|
||||
#define MAX8925_CHG_IRQ2_MASK (0x81)
|
||||
#define MAX8925_CHG_STATUS (0x82)
|
||||
|
||||
/* GPM registers */
|
||||
#define MAX8925_SYSENSEL (0x00)
|
||||
#define MAX8925_ON_OFF_IRQ1 (0x01)
|
||||
#define MAX8925_ON_OFF_IRQ1_MASK (0x02)
|
||||
#define MAX8925_ON_OFF_STATUS (0x03)
|
||||
#define MAX8925_ON_OFF_IRQ2 (0x0d)
|
||||
#define MAX8925_ON_OFF_IRQ2_MASK (0x0e)
|
||||
#define MAX8925_RESET_CNFG (0x0f)
|
||||
|
||||
/* Touch registers */
|
||||
#define MAX8925_TSC_IRQ (0x00)
|
||||
#define MAX8925_TSC_IRQ_MASK (0x01)
|
||||
#define MAX8925_TSC_CNFG1 (0x02)
|
||||
#define MAX8925_ADC_SCHED (0x10)
|
||||
#define MAX8925_ADC_RES_END (0x6f)
|
||||
|
||||
#define MAX8925_NREF_OK (1 << 4)
|
||||
|
||||
/* RTC registers */
|
||||
#define MAX8925_ALARM0_CNTL (0x18)
|
||||
#define MAX8925_ALARM1_CNTL (0x19)
|
||||
#define MAX8925_RTC_IRQ (0x1c)
|
||||
#define MAX8925_RTC_IRQ_MASK (0x1d)
|
||||
#define MAX8925_MPL_CNTL (0x1e)
|
||||
|
||||
/* WLED registers */
|
||||
#define MAX8925_WLED_MODE_CNTL (0x84)
|
||||
#define MAX8925_WLED_CNTL (0x85)
|
||||
|
||||
/* MAX8925 Registers */
|
||||
#define MAX8925_SDCTL1 (0x04)
|
||||
#define MAX8925_SDCTL2 (0x07)
|
||||
#define MAX8925_SDCTL3 (0x0A)
|
||||
#define MAX8925_SDV1 (0x06)
|
||||
#define MAX8925_SDV2 (0x09)
|
||||
#define MAX8925_SDV3 (0x0C)
|
||||
#define MAX8925_LDOCTL1 (0x18)
|
||||
#define MAX8925_LDOCTL2 (0x1C)
|
||||
#define MAX8925_LDOCTL3 (0x20)
|
||||
#define MAX8925_LDOCTL4 (0x24)
|
||||
#define MAX8925_LDOCTL5 (0x28)
|
||||
#define MAX8925_LDOCTL6 (0x2C)
|
||||
#define MAX8925_LDOCTL7 (0x30)
|
||||
#define MAX8925_LDOCTL8 (0x34)
|
||||
#define MAX8925_LDOCTL9 (0x38)
|
||||
#define MAX8925_LDOCTL10 (0x3C)
|
||||
#define MAX8925_LDOCTL11 (0x40)
|
||||
#define MAX8925_LDOCTL12 (0x44)
|
||||
#define MAX8925_LDOCTL13 (0x48)
|
||||
#define MAX8925_LDOCTL14 (0x4C)
|
||||
#define MAX8925_LDOCTL15 (0x50)
|
||||
#define MAX8925_LDOCTL16 (0x10)
|
||||
#define MAX8925_LDOCTL17 (0x14)
|
||||
#define MAX8925_LDOCTL18 (0x72)
|
||||
#define MAX8925_LDOCTL19 (0x5C)
|
||||
#define MAX8925_LDOCTL20 (0x9C)
|
||||
#define MAX8925_LDOVOUT1 (0x1A)
|
||||
#define MAX8925_LDOVOUT2 (0x1E)
|
||||
#define MAX8925_LDOVOUT3 (0x22)
|
||||
#define MAX8925_LDOVOUT4 (0x26)
|
||||
#define MAX8925_LDOVOUT5 (0x2A)
|
||||
#define MAX8925_LDOVOUT6 (0x2E)
|
||||
#define MAX8925_LDOVOUT7 (0x32)
|
||||
#define MAX8925_LDOVOUT8 (0x36)
|
||||
#define MAX8925_LDOVOUT9 (0x3A)
|
||||
#define MAX8925_LDOVOUT10 (0x3E)
|
||||
#define MAX8925_LDOVOUT11 (0x42)
|
||||
#define MAX8925_LDOVOUT12 (0x46)
|
||||
#define MAX8925_LDOVOUT13 (0x4A)
|
||||
#define MAX8925_LDOVOUT14 (0x4E)
|
||||
#define MAX8925_LDOVOUT15 (0x52)
|
||||
#define MAX8925_LDOVOUT16 (0x12)
|
||||
#define MAX8925_LDOVOUT17 (0x16)
|
||||
#define MAX8925_LDOVOUT18 (0x74)
|
||||
#define MAX8925_LDOVOUT19 (0x5E)
|
||||
#define MAX8925_LDOVOUT20 (0x9E)
|
||||
|
||||
/* bit definitions */
|
||||
#define CHG_IRQ1_MASK (0x07)
|
||||
#define CHG_IRQ2_MASK (0xff)
|
||||
#define ON_OFF_IRQ1_MASK (0xff)
|
||||
#define ON_OFF_IRQ2_MASK (0x03)
|
||||
#define TSC_IRQ_MASK (0x03)
|
||||
#define RTC_IRQ_MASK (0x0c)
|
||||
|
||||
#define MAX8925_MAX_REGULATOR (23)
|
||||
|
||||
#define MAX8925_NAME_SIZE (32)
|
||||
|
||||
/* IRQ definitions */
|
||||
enum {
|
||||
MAX8925_IRQ_VCHG_DC_OVP,
|
||||
MAX8925_IRQ_VCHG_DC_F,
|
||||
MAX8925_IRQ_VCHG_DC_R,
|
||||
MAX8925_IRQ_VCHG_USB_OVP,
|
||||
MAX8925_IRQ_VCHG_USB_F,
|
||||
MAX8925_IRQ_VCHG_USB_R,
|
||||
MAX8925_IRQ_VCHG_THM_OK_R,
|
||||
MAX8925_IRQ_VCHG_THM_OK_F,
|
||||
MAX8925_IRQ_VCHG_SYSLOW_F,
|
||||
MAX8925_IRQ_VCHG_SYSLOW_R,
|
||||
MAX8925_IRQ_VCHG_RST,
|
||||
MAX8925_IRQ_VCHG_DONE,
|
||||
MAX8925_IRQ_VCHG_TOPOFF,
|
||||
MAX8925_IRQ_VCHG_TMR_FAULT,
|
||||
MAX8925_IRQ_GPM_RSTIN,
|
||||
MAX8925_IRQ_GPM_MPL,
|
||||
MAX8925_IRQ_GPM_SW_3SEC,
|
||||
MAX8925_IRQ_GPM_EXTON_F,
|
||||
MAX8925_IRQ_GPM_EXTON_R,
|
||||
MAX8925_IRQ_GPM_SW_1SEC,
|
||||
MAX8925_IRQ_GPM_SW_F,
|
||||
MAX8925_IRQ_GPM_SW_R,
|
||||
MAX8925_IRQ_GPM_SYSCKEN_F,
|
||||
MAX8925_IRQ_GPM_SYSCKEN_R,
|
||||
MAX8925_IRQ_RTC_ALARM1,
|
||||
MAX8925_IRQ_RTC_ALARM0,
|
||||
MAX8925_IRQ_TSC_STICK,
|
||||
MAX8925_IRQ_TSC_NSTICK,
|
||||
MAX8925_NR_IRQS,
|
||||
};
|
||||
|
||||
struct max8925_chip {
|
||||
struct device *dev;
|
||||
struct i2c_client *i2c;
|
||||
struct i2c_client *adc;
|
||||
struct i2c_client *rtc;
|
||||
struct mutex io_lock;
|
||||
struct mutex irq_lock;
|
||||
|
||||
int irq_base;
|
||||
int core_irq;
|
||||
int tsc_irq;
|
||||
};
|
||||
|
||||
struct max8925_backlight_pdata {
|
||||
int lxw_scl; /* 0/1 -- 0.8Ohm/0.4Ohm */
|
||||
int lxw_freq; /* 700KHz ~ 1400KHz */
|
||||
int dual_string; /* 0/1 -- single/dual string */
|
||||
};
|
||||
|
||||
struct max8925_touch_pdata {
|
||||
unsigned int flags;
|
||||
};
|
||||
|
||||
struct max8925_power_pdata {
|
||||
int (*set_charger)(int);
|
||||
unsigned batt_detect:1;
|
||||
unsigned topoff_threshold:2;
|
||||
unsigned fast_charge:3; /* charge current */
|
||||
};
|
||||
|
||||
/*
|
||||
* irq_base: stores IRQ base number of MAX8925 in platform
|
||||
* tsc_irq: stores IRQ number of MAX8925 TSC
|
||||
*/
|
||||
struct max8925_platform_data {
|
||||
struct max8925_backlight_pdata *backlight;
|
||||
struct max8925_touch_pdata *touch;
|
||||
struct max8925_power_pdata *power;
|
||||
struct regulator_init_data *regulator[MAX8925_MAX_REGULATOR];
|
||||
|
||||
int irq_base;
|
||||
int tsc_irq;
|
||||
};
|
||||
|
||||
extern int max8925_reg_read(struct i2c_client *, int);
|
||||
extern int max8925_reg_write(struct i2c_client *, int, unsigned char);
|
||||
extern int max8925_bulk_read(struct i2c_client *, int, int, unsigned char *);
|
||||
extern int max8925_bulk_write(struct i2c_client *, int, int, unsigned char *);
|
||||
extern int max8925_set_bits(struct i2c_client *, int, unsigned char,
|
||||
unsigned char);
|
||||
|
||||
extern int max8925_device_init(struct max8925_chip *,
|
||||
struct max8925_platform_data *);
|
||||
extern void max8925_device_exit(struct max8925_chip *);
|
||||
#endif /* __LINUX_MFD_MAX8925_H */
|
||||
|
||||
@@ -59,7 +59,8 @@ void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
|
||||
* data for the MMC controller
|
||||
*/
|
||||
struct tmio_mmc_data {
|
||||
const unsigned int hclk;
|
||||
unsigned int hclk;
|
||||
unsigned long capabilities;
|
||||
void (*set_pwr)(struct platform_device *host, int state);
|
||||
void (*set_clk_div)(struct platform_device *host, int state);
|
||||
};
|
||||
|
||||
@@ -12,6 +12,7 @@
|
||||
|
||||
#include <linux/mfd/mcp.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/semaphore.h>
|
||||
|
||||
#define UCB_IO_DATA 0x00
|
||||
#define UCB_IO_DIR 0x01
|
||||
|
||||
@@ -15,6 +15,7 @@
|
||||
#ifndef __MFD_WM831X_CORE_H__
|
||||
#define __MFD_WM831X_CORE_H__
|
||||
|
||||
#include <linux/completion.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
/*
|
||||
@@ -254,9 +255,14 @@ struct wm831x {
|
||||
int irq_masks_cur[WM831X_NUM_IRQ_REGS]; /* Currently active value */
|
||||
int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
|
||||
|
||||
/* Chip revision based flags */
|
||||
unsigned has_gpio_ena:1; /* Has GPIO enable bit */
|
||||
unsigned has_cs_sts:1; /* Has current sink status bit */
|
||||
|
||||
int num_gpio;
|
||||
|
||||
struct mutex auxadc_lock;
|
||||
struct completion auxadc_done;
|
||||
|
||||
/* The WM831x has a security key blocking access to certain
|
||||
* registers. The mutex is taken by the accessors for locking
|
||||
|
||||
@@ -41,6 +41,10 @@
|
||||
#define WM831X_GPN_OD_MASK 0x0200 /* GPN_OD */
|
||||
#define WM831X_GPN_OD_SHIFT 9 /* GPN_OD */
|
||||
#define WM831X_GPN_OD_WIDTH 1 /* GPN_OD */
|
||||
#define WM831X_GPN_ENA 0x0080 /* GPN_ENA */
|
||||
#define WM831X_GPN_ENA_MASK 0x0080 /* GPN_ENA */
|
||||
#define WM831X_GPN_ENA_SHIFT 7 /* GPN_ENA */
|
||||
#define WM831X_GPN_ENA_WIDTH 1 /* GPN_ENA */
|
||||
#define WM831X_GPN_TRI 0x0080 /* GPN_TRI */
|
||||
#define WM831X_GPN_TRI_MASK 0x0080 /* GPN_TRI */
|
||||
#define WM831X_GPN_TRI_SHIFT 7 /* GPN_TRI */
|
||||
|
||||
@@ -16,6 +16,7 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/mutex.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/completion.h>
|
||||
|
||||
#include <linux/mfd/wm8350/audio.h>
|
||||
#include <linux/mfd/wm8350/gpio.h>
|
||||
@@ -579,6 +580,8 @@
|
||||
|
||||
#define WM8350_NUM_IRQ 63
|
||||
|
||||
#define WM8350_NUM_IRQ_REGS 7
|
||||
|
||||
struct wm8350_reg_access {
|
||||
u16 readable; /* Mask of readable bits */
|
||||
u16 writable; /* Mask of writable bits */
|
||||
@@ -600,11 +603,6 @@ extern const u16 wm8352_mode3_defaults[];
|
||||
|
||||
struct wm8350;
|
||||
|
||||
struct wm8350_irq {
|
||||
irq_handler_t handler;
|
||||
void *data;
|
||||
};
|
||||
|
||||
struct wm8350_hwmon {
|
||||
struct platform_device *pdev;
|
||||
struct device *classdev;
|
||||
@@ -624,11 +622,13 @@ struct wm8350 {
|
||||
u16 *reg_cache;
|
||||
|
||||
struct mutex auxadc_mutex;
|
||||
struct completion auxadc_done;
|
||||
|
||||
/* Interrupt handling */
|
||||
struct mutex irq_mutex; /* IRQ table mutex */
|
||||
struct wm8350_irq irq[WM8350_NUM_IRQ];
|
||||
struct mutex irq_lock;
|
||||
int chip_irq;
|
||||
int irq_base;
|
||||
u16 irq_masks[WM8350_NUM_IRQ_REGS];
|
||||
|
||||
/* Client devices */
|
||||
struct wm8350_codec codec;
|
||||
@@ -647,11 +647,13 @@ struct wm8350 {
|
||||
* used by the platform to configure GPIO functions and similar.
|
||||
* @irq_high: Set if WM8350 IRQ is active high.
|
||||
* @irq_base: Base IRQ for genirq (not currently used).
|
||||
* @gpio_base: Base for gpiolib.
|
||||
*/
|
||||
struct wm8350_platform_data {
|
||||
int (*init)(struct wm8350 *wm8350);
|
||||
int irq_high;
|
||||
int irq_base;
|
||||
int gpio_base;
|
||||
};
|
||||
|
||||
|
||||
@@ -677,12 +679,33 @@ int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src);
|
||||
/*
|
||||
* WM8350 internal interrupts
|
||||
*/
|
||||
int wm8350_register_irq(struct wm8350 *wm8350, int irq,
|
||||
irq_handler_t handler, unsigned long flags,
|
||||
const char *name, void *data);
|
||||
int wm8350_free_irq(struct wm8350 *wm8350, int irq);
|
||||
int wm8350_mask_irq(struct wm8350 *wm8350, int irq);
|
||||
int wm8350_unmask_irq(struct wm8350 *wm8350, int irq);
|
||||
static inline int wm8350_register_irq(struct wm8350 *wm8350, int irq,
|
||||
irq_handler_t handler,
|
||||
unsigned long flags,
|
||||
const char *name, void *data)
|
||||
{
|
||||
if (!wm8350->irq_base)
|
||||
return -ENODEV;
|
||||
|
||||
return request_threaded_irq(irq + wm8350->irq_base, NULL,
|
||||
handler, flags, name, data);
|
||||
}
|
||||
|
||||
static inline void wm8350_free_irq(struct wm8350 *wm8350, int irq, void *data)
|
||||
{
|
||||
free_irq(irq + wm8350->irq_base, data);
|
||||
}
|
||||
|
||||
static inline void wm8350_mask_irq(struct wm8350 *wm8350, int irq)
|
||||
{
|
||||
disable_irq(irq + wm8350->irq_base);
|
||||
}
|
||||
|
||||
static inline void wm8350_unmask_irq(struct wm8350 *wm8350, int irq)
|
||||
{
|
||||
enable_irq(irq + wm8350->irq_base);
|
||||
}
|
||||
|
||||
int wm8350_irq_init(struct wm8350 *wm8350, int irq,
|
||||
struct wm8350_platform_data *pdata);
|
||||
int wm8350_irq_exit(struct wm8350 *wm8350);
|
||||
|
||||
@@ -29,6 +29,7 @@
|
||||
#define WM8350_GPIO_FUNCTION_SELECT_2 0x8D
|
||||
#define WM8350_GPIO_FUNCTION_SELECT_3 0x8E
|
||||
#define WM8350_GPIO_FUNCTION_SELECT_4 0x8F
|
||||
#define WM8350_GPIO_LEVEL 0xE6
|
||||
|
||||
/*
|
||||
* GPIO Functions
|
||||
|
||||
@@ -263,6 +263,7 @@ struct wm8350_rtc {
|
||||
struct platform_device *pdev;
|
||||
struct rtc_device *rtc;
|
||||
int alarm_enabled; /* used over suspend/resume */
|
||||
int update_enabled;
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,54 @@
|
||||
/*
|
||||
* include/linux/mfd/wm8994/core.h -- Core interface for WM8994
|
||||
*
|
||||
* Copyright 2009 Wolfson Microelectronics PLC.
|
||||
*
|
||||
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MFD_WM8994_CORE_H__
|
||||
#define __MFD_WM8994_CORE_H__
|
||||
|
||||
struct regulator_dev;
|
||||
struct regulator_bulk_data;
|
||||
|
||||
#define WM8994_NUM_GPIO_REGS 11
|
||||
#define WM8994_NUM_LDO_REGS 2
|
||||
|
||||
struct wm8994 {
|
||||
struct mutex io_lock;
|
||||
|
||||
struct device *dev;
|
||||
int (*read_dev)(struct wm8994 *wm8994, unsigned short reg,
|
||||
int bytes, void *dest);
|
||||
int (*write_dev)(struct wm8994 *wm8994, unsigned short reg,
|
||||
int bytes, void *src);
|
||||
|
||||
void *control_data;
|
||||
|
||||
int gpio_base;
|
||||
|
||||
/* Used over suspend/resume */
|
||||
u16 ldo_regs[WM8994_NUM_LDO_REGS];
|
||||
u16 gpio_regs[WM8994_NUM_GPIO_REGS];
|
||||
|
||||
struct regulator_dev *dbvdd;
|
||||
struct regulator_bulk_data *supplies;
|
||||
};
|
||||
|
||||
/* Device I/O API */
|
||||
int wm8994_reg_read(struct wm8994 *wm8994, unsigned short reg);
|
||||
int wm8994_reg_write(struct wm8994 *wm8994, unsigned short reg,
|
||||
unsigned short val);
|
||||
int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg,
|
||||
unsigned short mask, unsigned short val);
|
||||
int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg,
|
||||
int count, u16 *buf);
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,72 @@
|
||||
/*
|
||||
* include/linux/mfd/wm8994/gpio.h - GPIO configuration for WM8994
|
||||
*
|
||||
* Copyright 2009 Wolfson Microelectronics PLC.
|
||||
*
|
||||
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MFD_WM8994_GPIO_H__
|
||||
#define __MFD_WM8994_GPIO_H__
|
||||
|
||||
#define WM8994_GPIO_MAX 11
|
||||
|
||||
#define WM8994_GP_FN_PIN_SPECIFIC 0
|
||||
#define WM8994_GP_FN_GPIO 1
|
||||
#define WM8994_GP_FN_SDOUT 2
|
||||
#define WM8994_GP_FN_IRQ 3
|
||||
#define WM8994_GP_FN_TEMPERATURE 4
|
||||
#define WM8994_GP_FN_MICBIAS1_DET 5
|
||||
#define WM8994_GP_FN_MICBIAS1_SHORT 6
|
||||
#define WM8994_GP_FN_MICBIAS2_DET 7
|
||||
#define WM8994_GP_FN_MICBIAS2_SHORT 8
|
||||
#define WM8994_GP_FN_FLL1_LOCK 9
|
||||
#define WM8994_GP_FN_FLL2_LOCK 10
|
||||
#define WM8994_GP_FN_SRC1_LOCK 11
|
||||
#define WM8994_GP_FN_SRC2_LOCK 12
|
||||
#define WM8994_GP_FN_DRC1_ACT 13
|
||||
#define WM8994_GP_FN_DRC2_ACT 14
|
||||
#define WM8994_GP_FN_DRC3_ACT 15
|
||||
#define WM8994_GP_FN_WSEQ_STATUS 16
|
||||
#define WM8994_GP_FN_FIFO_ERROR 17
|
||||
#define WM8994_GP_FN_OPCLK 18
|
||||
|
||||
#define WM8994_GPN_DIR 0x8000 /* GPN_DIR */
|
||||
#define WM8994_GPN_DIR_MASK 0x8000 /* GPN_DIR */
|
||||
#define WM8994_GPN_DIR_SHIFT 15 /* GPN_DIR */
|
||||
#define WM8994_GPN_DIR_WIDTH 1 /* GPN_DIR */
|
||||
#define WM8994_GPN_PU 0x4000 /* GPN_PU */
|
||||
#define WM8994_GPN_PU_MASK 0x4000 /* GPN_PU */
|
||||
#define WM8994_GPN_PU_SHIFT 14 /* GPN_PU */
|
||||
#define WM8994_GPN_PU_WIDTH 1 /* GPN_PU */
|
||||
#define WM8994_GPN_PD 0x2000 /* GPN_PD */
|
||||
#define WM8994_GPN_PD_MASK 0x2000 /* GPN_PD */
|
||||
#define WM8994_GPN_PD_SHIFT 13 /* GPN_PD */
|
||||
#define WM8994_GPN_PD_WIDTH 1 /* GPN_PD */
|
||||
#define WM8994_GPN_POL 0x0400 /* GPN_POL */
|
||||
#define WM8994_GPN_POL_MASK 0x0400 /* GPN_POL */
|
||||
#define WM8994_GPN_POL_SHIFT 10 /* GPN_POL */
|
||||
#define WM8994_GPN_POL_WIDTH 1 /* GPN_POL */
|
||||
#define WM8994_GPN_OP_CFG 0x0200 /* GPN_OP_CFG */
|
||||
#define WM8994_GPN_OP_CFG_MASK 0x0200 /* GPN_OP_CFG */
|
||||
#define WM8994_GPN_OP_CFG_SHIFT 9 /* GPN_OP_CFG */
|
||||
#define WM8994_GPN_OP_CFG_WIDTH 1 /* GPN_OP_CFG */
|
||||
#define WM8994_GPN_DB 0x0100 /* GPN_DB */
|
||||
#define WM8994_GPN_DB_MASK 0x0100 /* GPN_DB */
|
||||
#define WM8994_GPN_DB_SHIFT 8 /* GPN_DB */
|
||||
#define WM8994_GPN_DB_WIDTH 1 /* GPN_DB */
|
||||
#define WM8994_GPN_LVL 0x0040 /* GPN_LVL */
|
||||
#define WM8994_GPN_LVL_MASK 0x0040 /* GPN_LVL */
|
||||
#define WM8994_GPN_LVL_SHIFT 6 /* GPN_LVL */
|
||||
#define WM8994_GPN_LVL_WIDTH 1 /* GPN_LVL */
|
||||
#define WM8994_GPN_FN_MASK 0x001F /* GPN_FN - [4:0] */
|
||||
#define WM8994_GPN_FN_SHIFT 0 /* GPN_FN - [4:0] */
|
||||
#define WM8994_GPN_FN_WIDTH 5 /* GPN_FN - [4:0] */
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,97 @@
|
||||
/*
|
||||
* include/linux/mfd/wm8994/pdata.h -- Platform data for WM8994
|
||||
*
|
||||
* Copyright 2009 Wolfson Microelectronics PLC.
|
||||
*
|
||||
* Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __MFD_WM8994_PDATA_H__
|
||||
#define __MFD_WM8994_PDATA_H__
|
||||
|
||||
#define WM8994_NUM_LDO 2
|
||||
#define WM8994_NUM_GPIO 11
|
||||
|
||||
struct wm8994_ldo_pdata {
|
||||
/** GPIOs to enable regulator, 0 or less if not available */
|
||||
int enable;
|
||||
|
||||
const char *supply;
|
||||
struct regulator_init_data *init_data;
|
||||
};
|
||||
|
||||
#define WM8994_CONFIGURE_GPIO 0x8000
|
||||
|
||||
#define WM8994_DRC_REGS 5
|
||||
#define WM8994_EQ_REGS 19
|
||||
|
||||
/**
|
||||
* DRC configurations are specified with a label and a set of register
|
||||
* values to write (the enable bits will be ignored). At runtime an
|
||||
* enumerated control will be presented for each DRC block allowing
|
||||
* the user to choose the configration to use.
|
||||
*
|
||||
* Configurations may be generated by hand or by using the DRC control
|
||||
* panel provided by the WISCE - see http://www.wolfsonmicro.com/wisce/
|
||||
* for details.
|
||||
*/
|
||||
struct wm8994_drc_cfg {
|
||||
const char *name;
|
||||
u16 regs[WM8994_DRC_REGS];
|
||||
};
|
||||
|
||||
/**
|
||||
* ReTune Mobile configurations are specified with a label, sample
|
||||
* rate and set of values to write (the enable bits will be ignored).
|
||||
*
|
||||
* Configurations are expected to be generated using the ReTune Mobile
|
||||
* control panel in WISCE - see http://www.wolfsonmicro.com/wisce/
|
||||
*/
|
||||
struct wm8994_retune_mobile_cfg {
|
||||
const char *name;
|
||||
unsigned int rate;
|
||||
u16 regs[WM8994_EQ_REGS];
|
||||
};
|
||||
|
||||
struct wm8994_pdata {
|
||||
int gpio_base;
|
||||
|
||||
/**
|
||||
* Default values for GPIOs if non-zero, WM8994_CONFIGURE_GPIO
|
||||
* can be used for all zero values.
|
||||
*/
|
||||
int gpio_defaults[WM8994_NUM_GPIO];
|
||||
|
||||
struct wm8994_ldo_pdata ldo[WM8994_NUM_LDO];
|
||||
|
||||
|
||||
int num_drc_cfgs;
|
||||
struct wm8994_drc_cfg *drc_cfgs;
|
||||
|
||||
int num_retune_mobile_cfgs;
|
||||
struct wm8994_retune_mobile_cfg *retune_mobile_cfgs;
|
||||
|
||||
/* LINEOUT can be differential or single ended */
|
||||
unsigned int lineout1_diff:1;
|
||||
unsigned int lineout2_diff:1;
|
||||
|
||||
/* Common mode feedback */
|
||||
unsigned int lineout1fb:1;
|
||||
unsigned int lineout2fb:1;
|
||||
|
||||
/* Microphone biases: 0=0.9*AVDD1 1=0.65*AVVD1 */
|
||||
unsigned int micbias1_lvl:1;
|
||||
unsigned int micbias2_lvl:1;
|
||||
|
||||
/* Jack detect threashold levels, see datasheet for values */
|
||||
unsigned int jd_scthr:2;
|
||||
unsigned int jd_thr:2;
|
||||
};
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user