x86/xsaves: Detect xsaves/xrstors feature

Detect the xsaveopt, xsavec, xgetbv, and xsaves features in processor extended
state enumberation sub-leaf (eax=0x0d, ecx=1):
Bit 00: XSAVEOPT is available
Bit 01: Supports XSAVEC and the compacted form of XRSTOR if set
Bit 02: Supports XGETBV with ECX = 1 if set
Bit 03: Supports XSAVES/XRSTORS and IA32_XSS if set

The above features are defined in the new word 10 in cpu features.

The IA32_XSS MSR (index DA0H) contains a state-component bitmap that specifies
the state components that software has enabled xsaves and xrstors to manage.
If the bit corresponding to a state component is clear in XCR0 | IA32_XSS,
xsaves and xrstors will not operate on that state component, regardless of
the value of the instruction mask.

Signed-off-by: Fenghua Yu <fenghua.yu@intel.com>
Link: http://lkml.kernel.org/r/1401387164-43416-3-git-send-email-fenghua.yu@intel.com
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

This commit is contained in:

Fenghua Yu

2014-05-29 11:12:30 -07:00

committed by

H. Peter Anvin

parent 446fd806f5

commit 6229ad278c

4 changed files with 19 additions and 3 deletions

									
										arch/x86/include/uapi/asm/msr-index.h
									
		+2
		
												View File
												
				@@ -297,6 +297,8 @@

				#define MSR_IA32_TSC_ADJUST             0x0000003b

				#define MSR_IA32_BNDCFGS		0x00000d90

				#define MSR_IA32_XSS			0x00000da0

				#define FEATURE_CONTROL_LOCKED				(1<<0)

				#define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX	(1<<1)

				#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX	(1<<2)