pwm: stm32: Fix calculation of prescaler
BugLink: https://bugs.launchpad.net/bugs/2076435 commit dab8f9f0fe3aada61c0eb013dcf7d3ff75a2c336 upstream. A small prescaler is beneficial, as this improves the resolution of the duty_cycle configuration. However if the prescaler is too small, the maximal possible period becomes considerably smaller than the requested value. One situation where this goes wrong is the following: With a parent clock rate of 208877930 Hz and max_arr = 0xffff = 65535, a request for period = 941243 ns currently results in PSC = 1. The value for ARR is then calculated to ARR = 941243 * 208877930 / (1000000000 * 2) - 1 = 98301 This value is bigger than 65535 however and so doesn't fit into the respective register field. In this particular case the PWM was configured for a period of 313733.4806027616 ns (with ARR = 98301 & 0xffff). Even if ARR was configured to its maximal value, only period = 627495.6861167669 ns would be achievable. Fix the calculation accordingly and adapt the comment to match the new algorithm. With the calculation fixed the above case results in PSC = 2 and so an actual period of 941229.1667195285 ns. Fixes: 8002fbeef1e4 ("pwm: stm32: Calculate prescaler with a division instead of a loop") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@baylibre.com> Link: https://lore.kernel.org/r/b4d96b79917617434a540df45f20cb5de4142f88.1718979150.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König <ukleinek@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Portia Stephens <portia.stephens@canonical.com> Signed-off-by: Roxana Nicolescu <roxana.nicolescu@canonical.com>
This commit is contained in:
committed by
Stefan Bader
parent
c7ff906634
commit
59651ef7f8
+14
-10
@@ -1,5 +1,5 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) STMicroelectronics 2016
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*
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* Author: Gerald Baeza <gerald.baeza@st.com>
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@@ -321,19 +321,23 @@ static int stm32_pwm_config(struct stm32_pwm *priv, unsigned int ch,
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* First we need to find the minimal value for prescaler such that
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*
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* period_ns * clkrate
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* ------------------------------
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* ------------------------------ < max_arr + 1
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* NSEC_PER_SEC * (prescaler + 1)
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*
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* isn't bigger than max_arr.
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* This equation is equivalent to
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*
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* period_ns * clkrate
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* ---------------------------- < prescaler + 1
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* NSEC_PER_SEC * (max_arr + 1)
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*
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* Using integer division and knowing that the right hand side is
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* integer, this is further equivalent to
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*
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* (period_ns * clkrate) // (NSEC_PER_SEC * (max_arr + 1)) ≤ prescaler
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*/
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prescaler = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk),
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(u64)NSEC_PER_SEC * priv->max_arr);
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if (prescaler > 0)
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prescaler -= 1;
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if (prescaler > MAX_TIM_PSC)
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return -EINVAL;
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(u64)NSEC_PER_SEC * ((u64)priv->max_arr + 1));
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prd = mul_u64_u64_div_u64(period_ns, clk_get_rate(priv->clk),
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(u64)NSEC_PER_SEC * (prescaler + 1));
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