From 595530f4ade1a5a36bb14c611ba5ace128ab6d90 Mon Sep 17 00:00:00 2001
From: Prathamesh Shete <pshete@nvidia.com>
Date: Tue, 26 Mar 2024 09:59:50 +0000
Subject: [PATCH] NVIDIA: SAUCE: arm64: config: Enable
 CONFIG_ARM64_SW_TTBR0_PAN

BugLink: https://bugs.launchpad.net/bugs/2072591

This enable prevents the kernel from accessing user-space
memory directly by pointing TTBR0_EL1 to a reserved
zeroed area and reserved ASID.

http://nvbugs/3870276

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Ketan Patil <ketanp@nvidia.com>
Signed-off-by: Satish Seelamsetti <sseelamsetti@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 60c5790f34aa..317cb91da9bf 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -82,6 +82,7 @@ CONFIG_SCHED_MC=y
 CONFIG_SCHED_SMT=y
 CONFIG_NUMA=y
 CONFIG_XEN=y
+CONFIG_ARM64_SW_TTBR0_PAN=y
 CONFIG_COMPAT=y
 CONFIG_ARM64_PMEM=y
 CONFIG_RANDOMIZE_BASE=y