Merge branch 'next' of git://git.infradead.org/users/vkoul/slave-dma
* 'next' of git://git.infradead.org/users/vkoul/slave-dma: (53 commits)
ARM: mach-shmobile: specify CHCLR registers on SH7372
dma: shdma: fix runtime PM: clear channel buffers on reset
dma/imx-sdma: save irq flags when use spin_lock in sdma_tx_submit
dmaengine/ste_dma40: clear LNK on channel startup
dmaengine: intel_mid_dma: remove legacy pm interface
ASoC: mxs: correct 'direction' of device_prep_dma_cyclic
dmaengine: intel_mid_dma: error path fix
dmaengine: intel_mid_dma: locking and freeing fixes
mtd: gpmi-nand: move to dma_transfer_direction
mtd: fix compile error for gpmi-nand
mmc: mxs-mmc: fix the dma_transfer_direction migration
dmaengine: add DMA_TRANS_NONE to dma_transfer_direction
dma: mxs-dma: Don't use CLKGATE bits in CTRL0 to disable DMA channels
dma: mxs-dma: make mxs_dma_prep_slave_sg() multi user safe
dma: mxs-dma: Always leave mxs_dma_init() with the clock disabled.
dma: mxs-dma: fix a typo in comment
DMA: PL330: Remove pm_runtime_xxx calls from pl330 probe/remove
video i.MX IPU: Fix display connections
i.MX IPU DMA: Fix wrong burstsize settings
dmaengine/ste_dma40: allow fixed physical channel
...
Fix up conflicts in drivers/dma/{Kconfig,mxs-dma.c,pl330.c}
The conflicts looked pretty trivial, but I'll ask people to verify them.
This commit is contained in:
Linus Torvalds
@@ -134,7 +134,7 @@ struct pl08x_txd {
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struct dma_async_tx_descriptor tx;
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struct list_head node;
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struct list_head dsg_list;
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enum dma_data_direction direction;
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enum dma_transfer_direction direction;
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dma_addr_t llis_bus;
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struct pl08x_lli *llis_va;
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/* Default cctl value for LLIs */
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@@ -197,7 +197,7 @@ struct pl08x_dma_chan {
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dma_addr_t dst_addr;
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u32 src_cctl;
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u32 dst_cctl;
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enum dma_data_direction runtime_direction;
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enum dma_transfer_direction runtime_direction;
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dma_cookie_t lc;
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struct list_head pend_list;
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struct pl08x_txd *at;
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@@ -23,7 +23,6 @@
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#include <linux/device.h>
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#include <linux/uio.h>
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#include <linux/dma-direction.h>
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#include <linux/scatterlist.h>
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#include <linux/bitmap.h>
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#include <asm/page.h>
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@@ -72,11 +71,93 @@ enum dma_transaction_type {
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DMA_ASYNC_TX,
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DMA_SLAVE,
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DMA_CYCLIC,
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DMA_INTERLEAVE,
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/* last transaction type for creation of the capabilities mask */
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DMA_TX_TYPE_END,
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};
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/* last transaction type for creation of the capabilities mask */
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#define DMA_TX_TYPE_END (DMA_CYCLIC + 1)
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/**
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* enum dma_transfer_direction - dma transfer mode and direction indicator
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* @DMA_MEM_TO_MEM: Async/Memcpy mode
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* @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
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* @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
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* @DMA_DEV_TO_DEV: Slave mode & From Device to Device
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*/
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enum dma_transfer_direction {
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DMA_MEM_TO_MEM,
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DMA_MEM_TO_DEV,
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DMA_DEV_TO_MEM,
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DMA_DEV_TO_DEV,
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DMA_TRANS_NONE,
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};
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/**
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* Interleaved Transfer Request
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* ----------------------------
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* A chunk is collection of contiguous bytes to be transfered.
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* The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
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* ICGs may or maynot change between chunks.
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* A FRAME is the smallest series of contiguous {chunk,icg} pairs,
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* that when repeated an integral number of times, specifies the transfer.
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* A transfer template is specification of a Frame, the number of times
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* it is to be repeated and other per-transfer attributes.
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*
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* Practically, a client driver would have ready a template for each
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* type of transfer it is going to need during its lifetime and
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* set only 'src_start' and 'dst_start' before submitting the requests.
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*
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*
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* | Frame-1 | Frame-2 | ~ | Frame-'numf' |
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* |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
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*
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* == Chunk size
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* ... ICG
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*/
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/**
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* struct data_chunk - Element of scatter-gather list that makes a frame.
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* @size: Number of bytes to read from source.
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* size_dst := fn(op, size_src), so doesn't mean much for destination.
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* @icg: Number of bytes to jump after last src/dst address of this
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* chunk and before first src/dst address for next chunk.
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* Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
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* Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
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*/
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struct data_chunk {
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size_t size;
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size_t icg;
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};
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/**
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* struct dma_interleaved_template - Template to convey DMAC the transfer pattern
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* and attributes.
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* @src_start: Bus address of source for the first chunk.
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* @dst_start: Bus address of destination for the first chunk.
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* @dir: Specifies the type of Source and Destination.
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* @src_inc: If the source address increments after reading from it.
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* @dst_inc: If the destination address increments after writing to it.
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* @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
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* Otherwise, source is read contiguously (icg ignored).
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* Ignored if src_inc is false.
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* @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
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* Otherwise, destination is filled contiguously (icg ignored).
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* Ignored if dst_inc is false.
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* @numf: Number of frames in this template.
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* @frame_size: Number of chunks in a frame i.e, size of sgl[].
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* @sgl: Array of {chunk,icg} pairs that make up a frame.
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*/
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struct dma_interleaved_template {
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dma_addr_t src_start;
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dma_addr_t dst_start;
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enum dma_transfer_direction dir;
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bool src_inc;
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bool dst_inc;
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bool src_sgl;
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bool dst_sgl;
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size_t numf;
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size_t frame_size;
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struct data_chunk sgl[0];
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};
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/**
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* enum dma_ctrl_flags - DMA flags to augment operation preparation,
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@@ -269,7 +350,7 @@ enum dma_slave_buswidth {
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* struct, if applicable.
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*/
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struct dma_slave_config {
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enum dma_data_direction direction;
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enum dma_transfer_direction direction;
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dma_addr_t src_addr;
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dma_addr_t dst_addr;
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enum dma_slave_buswidth src_addr_width;
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@@ -433,6 +514,7 @@ struct dma_tx_state {
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* @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
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* The function takes a buffer of size buf_len. The callback function will
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* be called after period_len bytes have been transferred.
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* @device_prep_interleaved_dma: Transfer expression in a generic way.
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* @device_control: manipulate all pending operations on a channel, returns
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* zero or error code
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* @device_tx_status: poll for transaction completion, the optional
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@@ -492,11 +574,14 @@ struct dma_device {
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struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
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struct dma_chan *chan, struct scatterlist *sgl,
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unsigned int sg_len, enum dma_data_direction direction,
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unsigned int sg_len, enum dma_transfer_direction direction,
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unsigned long flags);
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struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
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struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
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size_t period_len, enum dma_data_direction direction);
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size_t period_len, enum dma_transfer_direction direction);
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struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
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struct dma_chan *chan, struct dma_interleaved_template *xt,
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unsigned long flags);
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int (*device_control)(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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unsigned long arg);
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@@ -522,7 +607,7 @@ static inline int dmaengine_slave_config(struct dma_chan *chan,
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static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
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struct dma_chan *chan, void *buf, size_t len,
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enum dma_data_direction dir, unsigned long flags)
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enum dma_transfer_direction dir, unsigned long flags)
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{
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struct scatterlist sg;
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sg_init_one(&sg, buf, len);
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@@ -127,7 +127,7 @@ struct dw_cyclic_desc {
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struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
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dma_addr_t buf_addr, size_t buf_len, size_t period_len,
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enum dma_data_direction direction);
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enum dma_transfer_direction direction);
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void dw_dma_cyclic_free(struct dma_chan *chan);
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int dw_dma_cyclic_start(struct dma_chan *chan);
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void dw_dma_cyclic_stop(struct dma_chan *chan);
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@@ -0,0 +1,68 @@
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/*
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* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef __MACH_MXS_GPMI_NAND_H__
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#define __MACH_MXS_GPMI_NAND_H__
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/* The size of the resources is fixed. */
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#define GPMI_NAND_RES_SIZE 6
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/* Resource names for the GPMI NAND driver. */
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#define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "GPMI NAND GPMI Registers"
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#define GPMI_NAND_GPMI_INTERRUPT_RES_NAME "GPMI NAND GPMI Interrupt"
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#define GPMI_NAND_BCH_REGS_ADDR_RES_NAME "GPMI NAND BCH Registers"
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#define GPMI_NAND_BCH_INTERRUPT_RES_NAME "GPMI NAND BCH Interrupt"
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#define GPMI_NAND_DMA_CHANNELS_RES_NAME "GPMI NAND DMA Channels"
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#define GPMI_NAND_DMA_INTERRUPT_RES_NAME "GPMI NAND DMA Interrupt"
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/**
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* struct gpmi_nand_platform_data - GPMI NAND driver platform data.
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*
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* This structure communicates platform-specific information to the GPMI NAND
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* driver that can't be expressed as resources.
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*
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* @platform_init: A pointer to a function the driver will call to
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* initialize the platform (e.g., set up the pin mux).
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* @min_prop_delay_in_ns: Minimum propagation delay of GPMI signals to and
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* from the NAND Flash device, in nanoseconds.
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* @max_prop_delay_in_ns: Maximum propagation delay of GPMI signals to and
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* from the NAND Flash device, in nanoseconds.
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* @max_chip_count: The maximum number of chips for which the driver
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* should configure the hardware. This value most
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* likely reflects the number of pins that are
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* connected to a NAND Flash device. If this is
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* greater than the SoC hardware can support, the
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* driver will print a message and fail to initialize.
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* @partitions: An optional pointer to an array of partition
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* descriptions.
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* @partition_count: The number of elements in the partitions array.
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*/
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struct gpmi_nand_platform_data {
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/* SoC hardware information. */
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int (*platform_init)(void);
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/* NAND Flash information. */
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unsigned int min_prop_delay_in_ns;
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unsigned int max_prop_delay_in_ns;
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unsigned int max_chip_count;
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/* Medium information. */
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struct mtd_partition *partitions;
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unsigned partition_count;
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};
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#endif
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@@ -30,7 +30,7 @@ struct sh_desc {
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struct sh_dmae_regs hw;
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struct list_head node;
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struct dma_async_tx_descriptor async_tx;
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enum dma_data_direction direction;
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enum dma_transfer_direction direction;
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dma_cookie_t cookie;
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size_t partial;
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int chunks;
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@@ -48,6 +48,7 @@ struct sh_dmae_channel {
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unsigned int offset;
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unsigned int dmars;
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unsigned int dmars_bit;
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unsigned int chclr_offset;
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};
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struct sh_dmae_pdata {
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@@ -68,6 +69,7 @@ struct sh_dmae_pdata {
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unsigned int dmaor_is_32bit:1;
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unsigned int needs_tend_set:1;
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unsigned int no_dmars:1;
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unsigned int chclr_present:1;
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};
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/* DMA register */
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@@ -0,0 +1,6 @@
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#ifndef _SIRFSOC_DMA_H_
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#define _SIRFSOC_DMA_H_
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bool sirfsoc_dma_filter_id(struct dma_chan *chan, void *chan_id);
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#endif
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