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NVIDIA: SAUCE: perf arm-spe: Add Poseidon-AE to neoverse list

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Add Poseidon-AE MIDR to neoverse_spe range list to support
data source packet decoding.

https://jirasw.nvidia.com/browse/MSST-704

Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Noah Wager <noah.wager@canonical.com>
Acked-by: Jacob Martin <jacob.martin@canonical.com>
Signed-off-by: Noah Wager <noah.wager@canonical.com>
[nwager: Fix conflict with upstream dc6abbbde4b0 by adding these changes
after the lines added by upstream]
Signed-off-by: Noah Wager <noah.wager@canonical.com>
This commit is contained in:
Besar Wicaksono
2024-10-26 05:27:02 +00:00
committed by Noah Wager
parent faa69f679e
commit 37f47a2683
2 changed files with 3 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
tools/arch/arm64/include/asm/cputype.h
+2
View File
@@ -88,6 +88,7 @@
#define ARM_CPU_PART_NEOVERSE_V2 0xD4F
#define ARM_CPU_PART_CORTEX_X4 0xD82
#define ARM_CPU_PART_NEOVERSE_V3 0xD84
#define ARM_CPU_PART_NEOVERSE_V3AE 0xD83
#define APM_CPU_PART_XGENE 0x000
#define APM_CPU_VAR_POTENZA 0x00
@@ -162,6 +163,7 @@
#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
#define MIDR_CORTEX_X4 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X4)
#define MIDR_NEOVERSE_V3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3)
#define MIDR_NEOVERSE_V3AE MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V3AE)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
tools/perf/util/arm-spe.c
+1
View File
@@ -413,6 +413,7 @@ static const struct midr_range neoverse_spe[] = {
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N1),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE),
{},
};