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ARM: fix cacheflush with PAN

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BugLink: https://bugs.launchpad.net/bugs/2101042

[ Upstream commit ca29cfcc4a21083d671522ad384532e28a43f033 ]

It seems that the cacheflush syscall got broken when PAN for LPAE was
implemented. User access was not enabled around the cache maintenance
instructions, causing them to fault.

Fixes: 7af5b901e847 ("ARM: 9358/2: Implement PAN for LPAE by TTBR0 page table walks disablement")
Reported-by: Michał Pecio <michal.pecio@gmail.com>
Tested-by: Michał Pecio <michal.pecio@gmail.com>
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Manuel Diewald <manuel.diewald@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
This commit is contained in:
Russell King (Oracle)
2024-11-12 10:16:13 +00:00
committed by Stefan Bader
parent a572e73848
commit 1a1220a9ac
1 changed files with 3 additions and 0 deletions
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arch/arm/kernel/traps.c
+3
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@@ -569,6 +569,7 @@ static int bad_syscall(int n, struct pt_regs *regs)
static inline int
__do_cache_op(unsigned long start, unsigned long end)
{
unsigned int ua_flags;
int ret;
do {
@@ -577,7 +578,9 @@ __do_cache_op(unsigned long start, unsigned long end)
if (fatal_signal_pending(current))
return 0;
ua_flags = uaccess_save_and_enable();
ret = flush_icache_user_range(start, start + chunk);
uaccess_restore(ua_flags);
if (ret)
return ret;