arm64: dts: mediatek: mt8186: Fix supported-hw mask for GPU OPPs
BugLink: https://bugs.launchpad.net/bugs/2089340
[ Upstream commit 2317d018b835842df0501d8f9e9efa843068a101 ]
The speedbin eFuse reads a value 'x' from 0 to 7 and, in order to
make that compatible with opp-supported-hw, it gets post processed
as BIT(x).
Change all of the 0x30 supported-hw to 0x20 to avoid getting
duplicate OPPs for speedbin 4, and also change all of the 0x8 to
0xcf because speedbins different from 4 and 5 do support 900MHz,
950MHz, 1000MHz with the higher voltage of 850mV, 900mV, 950mV
respectively.
Fixes: f38ea593ad ("arm64: dts: mediatek: mt8186: Wire up GPU voltage/frequency scaling")
Link: https://lore.kernel.org/r/20240725072243.173104-1-angelogioacchino.delregno@collabora.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
Signed-off-by: Portia Stephens <portia.stephens@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
This commit is contained in:
committed by
Mehmet Basaran
parent
2bc25eb9fe
commit
18db765bd0
@@ -731,7 +731,7 @@
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opp-900000000-3 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <850000>;
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opp-supported-hw = <0x8>;
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opp-supported-hw = <0xcf>;
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};
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opp-900000000-4 {
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@@ -743,13 +743,13 @@
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opp-900000000-5 {
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opp-hz = /bits/ 64 <900000000>;
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opp-microvolt = <825000>;
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opp-supported-hw = <0x30>;
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opp-supported-hw = <0x20>;
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};
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opp-950000000-3 {
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opp-hz = /bits/ 64 <950000000>;
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opp-microvolt = <900000>;
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opp-supported-hw = <0x8>;
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opp-supported-hw = <0xcf>;
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};
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opp-950000000-4 {
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@@ -761,13 +761,13 @@
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opp-950000000-5 {
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opp-hz = /bits/ 64 <950000000>;
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opp-microvolt = <850000>;
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opp-supported-hw = <0x30>;
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opp-supported-hw = <0x20>;
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};
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opp-1000000000-3 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <950000>;
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opp-supported-hw = <0x8>;
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opp-supported-hw = <0xcf>;
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};
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opp-1000000000-4 {
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@@ -779,7 +779,7 @@
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opp-1000000000-5 {
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opp-hz = /bits/ 64 <1000000000>;
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opp-microvolt = <875000>;
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opp-supported-hw = <0x30>;
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opp-supported-hw = <0x20>;
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};
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};
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