From 0276f69f13e23b828a149d765d5712e214182ee7 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Wed, 14 Jun 2023 15:39:59 +0200 Subject: [PATCH 001/136] soc: qcom: icc-bwmon: Set default thresholds dynamically Currently we use predefined initial threshold values. This works, but does not really scale well with more and more SoCs gaining bwmon support, as the necessary kickoff values may differ between platforms due to memory type and/or controller setup. All of the data we need for that is already provided in the device tree, anyway. Change the thresholds to: * low = 0 (as we've been doing up until now) * med = high = BW_MIN Throughput going below the med threshold nudges bwmon into signaling that we should slow down (e.g. if we inherited too high bandwidth from the bootloader). Throughput going above the high threshold nudges bwmon into signaling that we should speed up so as not to choke the bus traffic due to insufficient transfer rates. F_MIN is a perfect initial value for both of these cases - if we go above it (and there's a 99.99% chance it'll happen at boot time), we should definitely make the memory go faster, whereas if we go below it, we should slow down, no matter what performance state we were at before (it's only possible for them to be >= FMIN). This only changes the values programmed at probe time, as high and med thresholds are updated at interrupt, also based on the OPP table from DT. Signed-off-by: Konrad Dybcio Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230610-topic-bwmon_opp-v2-1-0d25c1ce7dca@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/icc-bwmon.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index 40068a285913..8daf0eb03279 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -165,9 +165,6 @@ enum bwmon_fields { struct icc_bwmon_data { unsigned int sample_ms; unsigned int count_unit_kb; /* kbytes */ - unsigned int default_highbw_kbps; - unsigned int default_medbw_kbps; - unsigned int default_lowbw_kbps; u8 zone1_thres_count; u8 zone3_thres_count; unsigned int quirks; @@ -564,20 +561,21 @@ static void bwmon_set_threshold(struct icc_bwmon *bwmon, static void bwmon_start(struct icc_bwmon *bwmon) { const struct icc_bwmon_data *data = bwmon->data; + u32 bw_low = 0; int window; + /* No need to check for errors, as this must have succeeded before. */ + dev_pm_opp_find_bw_ceil(bwmon->dev, &bw_low, 0); + bwmon_clear_counters(bwmon, true); window = mult_frac(bwmon->data->sample_ms, HW_TIMER_HZ, MSEC_PER_SEC); /* Maximum sampling window: 0xffffff for v4 and 0xfffff for v5 */ regmap_field_write(bwmon->regs[F_SAMPLE_WINDOW], window); - bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_HIGH], - data->default_highbw_kbps); - bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_MED], - data->default_medbw_kbps); - bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_LOW], - data->default_lowbw_kbps); + bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_HIGH], bw_low); + bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_MED], bw_low); + bwmon_set_threshold(bwmon, bwmon->regs[F_THRESHOLD_LOW], 0); regmap_field_write(bwmon->regs[F_THRESHOLD_COUNT_ZONE0], BWMON_THRESHOLD_COUNT_ZONE0_DEFAULT); @@ -807,9 +805,6 @@ static int bwmon_remove(struct platform_device *pdev) static const struct icc_bwmon_data msm8998_bwmon_data = { .sample_ms = 4, .count_unit_kb = 1024, - .default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */ - .default_medbw_kbps = 512 * 1024, /* 512 MBps */ - .default_lowbw_kbps = 0, .zone1_thres_count = 16, .zone3_thres_count = 1, .quirks = BWMON_HAS_GLOBAL_IRQ, @@ -822,9 +817,6 @@ static const struct icc_bwmon_data msm8998_bwmon_data = { static const struct icc_bwmon_data sdm845_cpu_bwmon_data = { .sample_ms = 4, .count_unit_kb = 64, - .default_highbw_kbps = 4800 * 1024, /* 4.8 GBps */ - .default_medbw_kbps = 512 * 1024, /* 512 MBps */ - .default_lowbw_kbps = 0, .zone1_thres_count = 16, .zone3_thres_count = 1, .quirks = BWMON_HAS_GLOBAL_IRQ, @@ -835,9 +827,6 @@ static const struct icc_bwmon_data sdm845_cpu_bwmon_data = { static const struct icc_bwmon_data sdm845_llcc_bwmon_data = { .sample_ms = 4, .count_unit_kb = 1024, - .default_highbw_kbps = 800 * 1024, /* 800 MBps */ - .default_medbw_kbps = 256 * 1024, /* 256 MBps */ - .default_lowbw_kbps = 0, .zone1_thres_count = 16, .zone3_thres_count = 1, .regmap_fields = sdm845_llcc_bwmon_reg_fields, @@ -847,9 +836,6 @@ static const struct icc_bwmon_data sdm845_llcc_bwmon_data = { static const struct icc_bwmon_data sc7280_llcc_bwmon_data = { .sample_ms = 4, .count_unit_kb = 64, - .default_highbw_kbps = 800 * 1024, /* 800 MBps */ - .default_medbw_kbps = 256 * 1024, /* 256 MBps */ - .default_lowbw_kbps = 0, .zone1_thres_count = 16, .zone3_thres_count = 1, .quirks = BWMON_NEEDS_FORCE_CLEAR, From a7b484b1c9332a1ee12e8799d62a11ee3f8e0801 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 14 Jun 2023 18:35:47 +0200 Subject: [PATCH 002/136] soc: qcom: ocmem: Fix NUM_PORTS & NUM_MACROS macros Since we're using these two macros to read a value from a register, we need to use the FIELD_GET instead of the FIELD_PREP macro, otherwise we're getting wrong values. So instead of: [ 3.111779] ocmem fdd00000.sram: 2 ports, 1 regions, 512 macros, not interleaved we now get the correct value of: [ 3.129672] ocmem fdd00000.sram: 2 ports, 1 regions, 2 macros, not interleaved Fixes: 88c1e9404f1d ("soc: qcom: add OCMEM driver") Reviewed-by: Caleb Connolly Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20230506-msm8226-ocmem-v3-1-79da95a2581f@z3ntu.xyz Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/ocmem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/ocmem.c b/drivers/soc/qcom/ocmem.c index aaddc3cc53b7..ef7c1748242a 100644 --- a/drivers/soc/qcom/ocmem.c +++ b/drivers/soc/qcom/ocmem.c @@ -80,8 +80,8 @@ struct ocmem { #define OCMEM_HW_VERSION_MINOR(val) FIELD_GET(GENMASK(27, 16), val) #define OCMEM_HW_VERSION_STEP(val) FIELD_GET(GENMASK(15, 0), val) -#define OCMEM_HW_PROFILE_NUM_PORTS(val) FIELD_PREP(0x0000000f, (val)) -#define OCMEM_HW_PROFILE_NUM_MACROS(val) FIELD_PREP(0x00003f00, (val)) +#define OCMEM_HW_PROFILE_NUM_PORTS(val) FIELD_GET(0x0000000f, (val)) +#define OCMEM_HW_PROFILE_NUM_MACROS(val) FIELD_GET(0x00003f00, (val)) #define OCMEM_HW_PROFILE_LAST_REGN_HALFSIZE 0x00010000 #define OCMEM_HW_PROFILE_INTERLEAVING 0x00020000 From 7a2fcba1f4031fa472f069fcd856f19d367b5808 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 14 Jun 2023 18:35:48 +0200 Subject: [PATCH 003/136] soc: qcom: ocmem: Use dev_err_probe where appropriate Use dev_err_probe in the driver probe function where useful, to simplify getting PTR_ERR and to ensure the underlying errors are included in the error message. Reviewed-by: Caleb Connolly Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20230506-msm8226-ocmem-v3-2-79da95a2581f@z3ntu.xyz Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/ocmem.c | 23 ++++++++--------------- 1 file changed, 8 insertions(+), 15 deletions(-) diff --git a/drivers/soc/qcom/ocmem.c b/drivers/soc/qcom/ocmem.c index ef7c1748242a..462514dfd9e3 100644 --- a/drivers/soc/qcom/ocmem.c +++ b/drivers/soc/qcom/ocmem.c @@ -321,18 +321,13 @@ static int ocmem_dev_probe(struct platform_device *pdev) ocmem->config = device_get_match_data(dev); ret = devm_clk_bulk_get(dev, ARRAY_SIZE(ocmem_clks), ocmem_clks); - if (ret) { - if (ret != -EPROBE_DEFER) - dev_err(dev, "Unable to get clocks\n"); - - return ret; - } + if (ret) + return dev_err_probe(dev, ret, "Unable to get clocks\n"); ocmem->mmio = devm_platform_ioremap_resource_byname(pdev, "ctrl"); - if (IS_ERR(ocmem->mmio)) { - dev_err(&pdev->dev, "Failed to ioremap ocmem_ctrl resource\n"); - return PTR_ERR(ocmem->mmio); - } + if (IS_ERR(ocmem->mmio)) + return dev_err_probe(&pdev->dev, PTR_ERR(ocmem->mmio), + "Failed to ioremap ocmem_ctrl resource\n"); ocmem->memory = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); @@ -345,16 +340,14 @@ static int ocmem_dev_probe(struct platform_device *pdev) WARN_ON(clk_set_rate(ocmem_clks[OCMEM_CLK_CORE_IDX].clk, 1000) < 0); ret = clk_bulk_prepare_enable(ARRAY_SIZE(ocmem_clks), ocmem_clks); - if (ret) { - dev_info(ocmem->dev, "Failed to enable clocks\n"); - return ret; - } + if (ret) + return dev_err_probe(ocmem->dev, ret, "Failed to enable clocks\n"); if (qcom_scm_restore_sec_cfg_available()) { dev_dbg(dev, "configuring scm\n"); ret = qcom_scm_restore_sec_cfg(QCOM_SCM_OCMEM_DEV_ID, 0); if (ret) { - dev_err(dev, "Could not enable secure configuration\n"); + dev_err_probe(dev, ret, "Could not enable secure configuration\n"); goto err_clk_disable; } } From a7e12e7bda08c367460eed0e4aea5c3694959df1 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 14 Jun 2023 18:35:49 +0200 Subject: [PATCH 004/136] soc: qcom: ocmem: make iface clock optional Some platforms such as msm8226 do not have an iface clk. Since clk_bulk APIs don't offer to a way to treat some clocks as optional simply add core_clk and iface_clk members to our drvdata. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20230506-msm8226-ocmem-v3-3-79da95a2581f@z3ntu.xyz Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/ocmem.c | 42 +++++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 18 deletions(-) diff --git a/drivers/soc/qcom/ocmem.c b/drivers/soc/qcom/ocmem.c index 462514dfd9e3..ff8d01b0ac68 100644 --- a/drivers/soc/qcom/ocmem.c +++ b/drivers/soc/qcom/ocmem.c @@ -54,6 +54,8 @@ struct ocmem { const struct ocmem_config *config; struct resource *memory; void __iomem *mmio; + struct clk *core_clk; + struct clk *iface_clk; unsigned int num_ports; unsigned int num_macros; bool interleaved; @@ -95,16 +97,6 @@ struct ocmem { #define OCMEM_PSGSC_CTL_MACRO2_MODE(val) FIELD_PREP(0x00000700, (val)) #define OCMEM_PSGSC_CTL_MACRO3_MODE(val) FIELD_PREP(0x00007000, (val)) -#define OCMEM_CLK_CORE_IDX 0 -static struct clk_bulk_data ocmem_clks[] = { - { - .id = "core", - }, - { - .id = "iface", - }, -}; - static inline void ocmem_write(struct ocmem *ocmem, u32 reg, u32 data) { writel(data, ocmem->mmio + reg); @@ -320,9 +312,15 @@ static int ocmem_dev_probe(struct platform_device *pdev) ocmem->dev = dev; ocmem->config = device_get_match_data(dev); - ret = devm_clk_bulk_get(dev, ARRAY_SIZE(ocmem_clks), ocmem_clks); - if (ret) - return dev_err_probe(dev, ret, "Unable to get clocks\n"); + ocmem->core_clk = devm_clk_get(dev, "core"); + if (IS_ERR(ocmem->core_clk)) + return dev_err_probe(dev, PTR_ERR(ocmem->core_clk), + "Unable to get core clock\n"); + + ocmem->iface_clk = devm_clk_get_optional(dev, "iface"); + if (IS_ERR(ocmem->iface_clk)) + return dev_err_probe(dev, PTR_ERR(ocmem->iface_clk), + "Unable to get iface clock\n"); ocmem->mmio = devm_platform_ioremap_resource_byname(pdev, "ctrl"); if (IS_ERR(ocmem->mmio)) @@ -337,11 +335,15 @@ static int ocmem_dev_probe(struct platform_device *pdev) } /* The core clock is synchronous with graphics */ - WARN_ON(clk_set_rate(ocmem_clks[OCMEM_CLK_CORE_IDX].clk, 1000) < 0); + WARN_ON(clk_set_rate(ocmem->core_clk, 1000) < 0); - ret = clk_bulk_prepare_enable(ARRAY_SIZE(ocmem_clks), ocmem_clks); + ret = clk_prepare_enable(ocmem->core_clk); if (ret) - return dev_err_probe(ocmem->dev, ret, "Failed to enable clocks\n"); + return dev_err_probe(ocmem->dev, ret, "Failed to enable core clock\n"); + + ret = clk_prepare_enable(ocmem->iface_clk); + if (ret) + return dev_err_probe(ocmem->dev, ret, "Failed to enable iface clock\n"); if (qcom_scm_restore_sec_cfg_available()) { dev_dbg(dev, "configuring scm\n"); @@ -406,13 +408,17 @@ static int ocmem_dev_probe(struct platform_device *pdev) return 0; err_clk_disable: - clk_bulk_disable_unprepare(ARRAY_SIZE(ocmem_clks), ocmem_clks); + clk_disable_unprepare(ocmem->core_clk); + clk_disable_unprepare(ocmem->iface_clk); return ret; } static int ocmem_dev_remove(struct platform_device *pdev) { - clk_bulk_disable_unprepare(ARRAY_SIZE(ocmem_clks), ocmem_clks); + struct ocmem *ocmem = platform_get_drvdata(pdev); + + clk_disable_unprepare(ocmem->core_clk); + clk_disable_unprepare(ocmem->iface_clk); return 0; } From f77b2d7607d0f4c23052f02788052dbea04831bc Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 14 Jun 2023 18:35:50 +0200 Subject: [PATCH 005/136] dt-bindings: sram: qcom,ocmem: Add msm8226 support Add the compatible for the OCMEM found on msm8226 which compared to msm8974 only has a core clock and no iface clock. Reviewed-by: Conor Dooley Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20230506-msm8226-ocmem-v3-4-79da95a2581f@z3ntu.xyz Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/sram/qcom,ocmem.yaml | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml index 4bbf6db0b6bd..61c784ef7b51 100644 --- a/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,ocmem.yaml @@ -15,7 +15,9 @@ description: | properties: compatible: - const: qcom,msm8974-ocmem + enum: + - qcom,msm8226-ocmem # v1.1.0 + - qcom,msm8974-ocmem # v1.4.0 reg: items: @@ -28,11 +30,13 @@ properties: - const: mem clocks: + minItems: 1 items: - description: Core clock - description: Interface clock clock-names: + minItems: 1 items: - const: core - const: iface @@ -58,6 +62,26 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8974-ocmem + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + else: + properties: + clocks: + minItems: 1 + clock-names: + minItems: 1 + patternProperties: "-sram@[0-9a-f]+$": type: object From 2976eec238dcd89475664795f54d4a4d3d05e0f9 Mon Sep 17 00:00:00 2001 From: Luca Weiss Date: Wed, 14 Jun 2023 18:35:51 +0200 Subject: [PATCH 006/136] soc: qcom: ocmem: Add support for msm8226 The msm8226 SoC also contains OCMEM but with one region only. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Link: https://lore.kernel.org/r/20230506-msm8226-ocmem-v3-5-79da95a2581f@z3ntu.xyz Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/ocmem.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/qcom/ocmem.c b/drivers/soc/qcom/ocmem.c index ff8d01b0ac68..2064e9512301 100644 --- a/drivers/soc/qcom/ocmem.c +++ b/drivers/soc/qcom/ocmem.c @@ -423,12 +423,18 @@ static int ocmem_dev_remove(struct platform_device *pdev) return 0; } +static const struct ocmem_config ocmem_8226_config = { + .num_regions = 1, + .macro_size = SZ_128K, +}; + static const struct ocmem_config ocmem_8974_config = { .num_regions = 3, .macro_size = SZ_128K, }; static const struct of_device_id ocmem_of_match[] = { + { .compatible = "qcom,msm8226-ocmem", .data = &ocmem_8226_config }, { .compatible = "qcom,msm8974-ocmem", .data = &ocmem_8974_config }, { } }; From 98c8b3efacaec61287a096dd37ca3c197f298b70 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Mon, 19 Jun 2023 14:32:26 +0200 Subject: [PATCH 007/136] soc: qcom: rpmpd: Add sync_state Add a sync_state implementation, very similar to the one already present in the RPMhPD driver. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230619-topic-rpmpd_syncstate-v1-1-54f986cf9444@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmpd.c | 34 +++++++++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index 99b017fd76b7..fa58c04214ee 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -58,6 +58,7 @@ struct rpmpd { struct qcom_smd_rpm *rpm; unsigned int max_state; __le32 key; + bool state_synced; }; struct rpmpd_desc { @@ -823,7 +824,11 @@ static int rpmpd_aggregate_corner(struct rpmpd *pd) unsigned int this_active_corner = 0, this_sleep_corner = 0; unsigned int peer_active_corner = 0, peer_sleep_corner = 0; - to_active_sleep(pd, pd->corner, &this_active_corner, &this_sleep_corner); + /* Clamp to the highest corner/level if sync_state isn't done yet */ + if (!pd->state_synced) + this_active_corner = this_sleep_corner = pd->max_state - 1; + else + to_active_sleep(pd, pd->corner, &this_active_corner, &this_sleep_corner); if (peer && peer->enabled) to_active_sleep(peer, peer->corner, &peer_active_corner, @@ -973,11 +978,38 @@ static int rpmpd_probe(struct platform_device *pdev) return of_genpd_add_provider_onecell(pdev->dev.of_node, data); } +static void rpmpd_sync_state(struct device *dev) +{ + const struct rpmpd_desc *desc = of_device_get_match_data(dev); + struct rpmpd **rpmpds = desc->rpmpds; + struct rpmpd *pd; + unsigned int i; + int ret; + + mutex_lock(&rpmpd_lock); + for (i = 0; i < desc->num_pds; i++) { + pd = rpmpds[i]; + if (!pd) + continue; + + pd->state_synced = true; + + if (!pd->enabled) + pd->corner = 0; + + ret = rpmpd_aggregate_corner(pd); + if (ret) + dev_err(dev, "failed to sync %s: %d\n", pd->pd.name, ret); + } + mutex_unlock(&rpmpd_lock); +} + static struct platform_driver rpmpd_driver = { .driver = { .name = "qcom-rpmpd", .of_match_table = rpmpd_match_table, .suppress_bind_attrs = true, + .sync_state = rpmpd_sync_state, }, .probe = rpmpd_probe, }; From d4600cbd5bcbaa2b296b5cf9a5c04408eedb4ef3 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 20 Jun 2023 14:37:03 -0700 Subject: [PATCH 008/136] soc: qcom: cmd-db: Drop NUL bytes from debugfs output The debugfs dump of Command DB relies uses %*pEp to print the resource identifiers, with escaping of non-printable characters. But p (ESCAPE_NP) does not escape NUL characters, so for identifiers less than 8 bytes in length the output will retain these. This does not cause an issue while looking at the dump in the terminal (no known complaints at least), but when programmatically consuming the debugfs output the extra characters are unwanted. Change the fixed 8-byte sizeof() to a dynamic strnlen() to avoid printing these NUL characters. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230620213703.283583-1-quic_bjorande@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/cmd-db.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/cmd-db.c b/drivers/soc/qcom/cmd-db.c index 33856abd560c..34c40368d5b5 100644 --- a/drivers/soc/qcom/cmd-db.c +++ b/drivers/soc/qcom/cmd-db.c @@ -284,7 +284,7 @@ static int cmd_db_debugfs_dump(struct seq_file *seq, void *p) ent = rsc_to_entry_header(rsc); for (j = 0; j < le16_to_cpu(rsc->cnt); j++, ent++) { seq_printf(seq, "0x%05x: %*pEp", le32_to_cpu(ent->addr), - (int)sizeof(ent->id), ent->id); + (int)strnlen(ent->id, sizeof(ent->id)), ent->id); len = le16_to_cpu(ent->len); if (len) { From 1b06d8ca087a8fd9b395b577048636926db22f0e Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Tue, 20 Jun 2023 16:00:58 -0700 Subject: [PATCH 009/136] soc: qcom: rpmh-rsc: Include state in trace event When tracing messages written to the RSC it's very useful to know the type of TCS being targeted, in particular if/when the code borrows a WAKE TCS for ACTIVE votes. Add the "state" of the message to the traced information. While at it, drop the "send-msg:" substring, as this is already captured by the trace event itself. Signed-off-by: Bjorn Andersson Acked-by: Manivannan Sadhasivam Acked-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230620230058.428833-1-quic_bjorande@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmh-rsc.c | 2 +- drivers/soc/qcom/trace-rpmh.h | 16 ++++++++++++---- 2 files changed, 13 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c index 0dd4363ebac8..a021dc71807b 100644 --- a/drivers/soc/qcom/rpmh-rsc.c +++ b/drivers/soc/qcom/rpmh-rsc.c @@ -516,7 +516,7 @@ static void __tcs_buffer_write(struct rsc_drv *drv, int tcs_id, int cmd_id, write_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_MSGID], tcs_id, j, msgid); write_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_ADDR], tcs_id, j, cmd->addr); write_tcs_cmd(drv, drv->regs[RSC_DRV_CMD_DATA], tcs_id, j, cmd->data); - trace_rpmh_send_msg(drv, tcs_id, j, msgid, cmd); + trace_rpmh_send_msg(drv, tcs_id, msg->state, j, msgid, cmd); } cmd_enable |= read_tcs_reg(drv, drv->regs[RSC_DRV_CMD_ENABLE], tcs_id); diff --git a/drivers/soc/qcom/trace-rpmh.h b/drivers/soc/qcom/trace-rpmh.h index 12b676b20cb2..be6b42ecc1f8 100644 --- a/drivers/soc/qcom/trace-rpmh.h +++ b/drivers/soc/qcom/trace-rpmh.h @@ -38,14 +38,15 @@ TRACE_EVENT(rpmh_tx_done, TRACE_EVENT(rpmh_send_msg, - TP_PROTO(struct rsc_drv *d, int m, int n, u32 h, + TP_PROTO(struct rsc_drv *d, int m, enum rpmh_state state, int n, u32 h, const struct tcs_cmd *c), - TP_ARGS(d, m, n, h, c), + TP_ARGS(d, m, state, n, h, c), TP_STRUCT__entry( __string(name, d->name) __field(int, m) + __field(u32, state) __field(int, n) __field(u32, hdr) __field(u32, addr) @@ -56,6 +57,7 @@ TRACE_EVENT(rpmh_send_msg, TP_fast_assign( __assign_str(name, d->name); __entry->m = m; + __entry->state = state; __entry->n = n; __entry->hdr = h; __entry->addr = c->addr; @@ -63,8 +65,14 @@ TRACE_EVENT(rpmh_send_msg, __entry->wait = c->wait; ), - TP_printk("%s: send-msg: tcs(m): %d cmd(n): %d msgid: %#x addr: %#x data: %#x complete: %d", - __get_str(name), __entry->m, __entry->n, __entry->hdr, + TP_printk("%s: tcs(m): %d [%s] cmd(n): %d msgid: %#x addr: %#x data: %#x complete: %d", + __get_str(name), __entry->m, + __print_symbolic(__entry->state, + { RPMH_SLEEP_STATE, "sleep" }, + { RPMH_WAKE_ONLY_STATE, "wake" }, + { RPMH_ACTIVE_ONLY_STATE, "active" }), + __entry->n, + __entry->hdr, __entry->addr, __entry->data, __entry->wait) ); From 412bf52d3ed7deb7b2dbde977413190072fbe0ea Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Thu, 22 Jun 2023 17:56:15 +0200 Subject: [PATCH 010/136] dt-bindings: firmware: qcom,scm: Allow interconnect on SC8280XP Just like all other Qualcomm SoCs, SC8280XP SCM should be fed an interconnect path. Do so. Signed-off-by: Konrad Dybcio Acked-by: Conor Dooley Reviewed-by: Johan Hovold Tested-by: Johan Hovold Link: https://lore.kernel.org/r/20230622-topic-8280scmicc-v1-1-6ef318919ea5@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/firmware/qcom,scm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index bdbee58a542b..4233ea839bfc 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -176,6 +176,7 @@ allOf: contains: enum: - qcom,scm-qdu1000 + - qcom,scm-sc8280xp - qcom,scm-sm8450 - qcom,scm-sm8550 then: From 7bc1cfaee1f03008e8b1fd29e621cb50a9512263 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Wed, 5 Jul 2023 20:26:41 +0800 Subject: [PATCH 011/136] soc: qcom: spm: Convert to devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li Link: https://lore.kernel.org/r/20230705122644.32236-3-frank.li@vivo.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/spm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index a6cbeb40831b..bab4897267b9 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -275,15 +275,13 @@ static int spm_dev_probe(struct platform_device *pdev) { const struct of_device_id *match_id; struct spm_driver_data *drv; - struct resource *res; void __iomem *addr; drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL); if (!drv) return -ENOMEM; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - drv->reg_base = devm_ioremap_resource(&pdev->dev, res); + drv->reg_base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(drv->reg_base)) return PTR_ERR(drv->reg_base); From e88640651ed42c76336dc21f080dca63244cdcff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Date: Wed, 28 Jun 2023 10:36:36 +0200 Subject: [PATCH 012/136] driver: soc: xilinx: Convert to platform remove callback returning void MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the only effect compared to returning zero is that the core emits an error message. By converting to .remove_new() (which is semantically equivalent to return 0 in .remove()) this error message is suppressed which is a good thing as xlnx_event_manager_remove() already emits an better error message. Signed-off-by: Uwe Kleine-König Link: https://lore.kernel.org/r/20230628083636.684394-1-u.kleine-koenig@pengutronix.de Signed-off-by: Michal Simek --- drivers/soc/xilinx/xlnx_event_manager.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/soc/xilinx/xlnx_event_manager.c b/drivers/soc/xilinx/xlnx_event_manager.c index f9d9b82b562d..86a048a10a13 100644 --- a/drivers/soc/xilinx/xlnx_event_manager.c +++ b/drivers/soc/xilinx/xlnx_event_manager.c @@ -666,7 +666,7 @@ static int xlnx_event_manager_probe(struct platform_device *pdev) return ret; } -static int xlnx_event_manager_remove(struct platform_device *pdev) +static void xlnx_event_manager_remove(struct platform_device *pdev) { int i; struct registered_event_data *eve_data; @@ -691,13 +691,11 @@ static int xlnx_event_manager_remove(struct platform_device *pdev) xlnx_event_cleanup_sgi(pdev); event_manager_availability = -EACCES; - - return ret; } static struct platform_driver xlnx_event_manager_driver = { .probe = xlnx_event_manager_probe, - .remove = xlnx_event_manager_remove, + .remove_new = xlnx_event_manager_remove, .driver = { .name = "xlnx_event_manager", }, From 9225bcdedf16297a346082e7d23b0e8434aa98ed Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 20 Jun 2023 08:03:29 -0500 Subject: [PATCH 013/136] firmware: ti_sci: Use system_state to determine polling Commit b9e8a7d950ff ("firmware: ti_sci: Switch transport to polled mode during system suspend") aims to resolve issues with tisci operations during system suspend operation. However, the system may enter a no_irq stage in various other usage modes, including power-off and restart. To determine if polling mode is appropriate, use the system_state instead. While at this, drop the unused is_suspending state variable and related helpers. Fixes: b9e8a7d950ff ("firmware: ti_sci: Switch transport to polled mode during system suspend") Reported-by: Francesco Dolcini Reported-by: Wadim Egorov Tested-by: Francesco Dolcini # Toradex Verdin AM62 Link: https://lore.kernel.org/r/20230620130329.4120443-1-nm@ti.com Closes: https://lore.kernel.org/all/ZGeHMjlnob2GFyHF@francesco-nb.int.toradex.com/ Signed-off-by: Nishanth Menon --- drivers/firmware/ti_sci.c | 36 ++---------------------------------- 1 file changed, 2 insertions(+), 34 deletions(-) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 039d92a595ec..91aaa0ca9bde 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -97,7 +97,6 @@ struct ti_sci_desc { * @node: list head * @host_id: Host ID * @users: Number of users of this instance - * @is_suspending: Flag set to indicate in suspend path. */ struct ti_sci_info { struct device *dev; @@ -116,7 +115,6 @@ struct ti_sci_info { u8 host_id; /* protected by ti_sci_list_mutex */ int users; - bool is_suspending; }; #define cl_to_ti_sci_info(c) container_of(c, struct ti_sci_info, cl) @@ -418,14 +416,14 @@ static inline int ti_sci_do_xfer(struct ti_sci_info *info, ret = 0; - if (!info->is_suspending) { + if (system_state <= SYSTEM_RUNNING) { /* And we wait for the response. */ timeout = msecs_to_jiffies(info->desc->max_rx_timeout_ms); if (!wait_for_completion_timeout(&xfer->done, timeout)) ret = -ETIMEDOUT; } else { /* - * If we are suspending, we cannot use wait_for_completion_timeout + * If we are !running, we cannot use wait_for_completion_timeout * during noirq phase, so we must manually poll the completion. */ ret = read_poll_timeout_atomic(try_wait_for_completion, done_state, @@ -3281,35 +3279,6 @@ static int tisci_reboot_handler(struct notifier_block *nb, unsigned long mode, return NOTIFY_BAD; } -static void ti_sci_set_is_suspending(struct ti_sci_info *info, bool is_suspending) -{ - info->is_suspending = is_suspending; -} - -static int ti_sci_suspend(struct device *dev) -{ - struct ti_sci_info *info = dev_get_drvdata(dev); - /* - * We must switch operation to polled mode now as drivers and the genpd - * layer may make late TI SCI calls to change clock and device states - * from the noirq phase of suspend. - */ - ti_sci_set_is_suspending(info, true); - - return 0; -} - -static int ti_sci_resume(struct device *dev) -{ - struct ti_sci_info *info = dev_get_drvdata(dev); - - ti_sci_set_is_suspending(info, false); - - return 0; -} - -static DEFINE_SIMPLE_DEV_PM_OPS(ti_sci_pm_ops, ti_sci_suspend, ti_sci_resume); - /* Description for K2G */ static const struct ti_sci_desc ti_sci_pmmc_k2g_desc = { .default_host_id = 2, @@ -3516,7 +3485,6 @@ static struct platform_driver ti_sci_driver = { .driver = { .name = "ti-sci", .of_match_table = of_match_ptr(ti_sci_of_match), - .pm = &ti_sci_pm_ops, }, }; module_platform_driver(ti_sci_driver); From 3e67fd8dd2711a63adfe0fa087de38d86a6eb8d5 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 20 Jun 2023 21:16:19 -0500 Subject: [PATCH 014/136] firmware: ti_sci: Fixup documentation errors Fix up documentation errors, squashes the following warnings: drivers/firmware/ti_sci.c:1986: warning: Excess function parameter 'vint_irq' description in 'ti_sci_cmd_set_irq' drivers/firmware/ti_sci.c:2034: warning: Excess function parameter 'vint_irq' description in 'ti_sci_cmd_free_irq' drivers/firmware/ti_sci.c:2630: warning: Function parameter or member 'bootvector' not described in 'ti_sci_cmd_proc_set_config' drivers/firmware/ti_sci.c:2746: warning: Function parameter or member 'bv' not described in 'ti_sci_cmd_proc_get_status' drivers/firmware/ti_sci.c:2746: warning: Function parameter or member 'cfg_flags' not described in 'ti_sci_cmd_proc_get_status' drivers/firmware/ti_sci.c:2746: warning: Function parameter or member 'ctrl_flags' not described in 'ti_sci_cmd_proc_get_status' drivers/firmware/ti_sci.c:2746: warning: Function parameter or member 'sts_flags' not described in 'ti_sci_cmd_proc_get_status' drivers/firmware/ti_sci.c:2746: warning: expecting prototype for ti_sci_cmd_get_boot_status(). Prototype was for ti_sci_cmd_proc_get_status() instead drivers/firmware/ti_sci.c:3265: warning: Function parameter or member 'sub_type' not described in 'devm_ti_sci_get_resource' drivers/firmware/ti_sci.c:3265: warning: Excess function parameter 'suub_type' description in 'devm_ti_sci_get_resource' Link: https://lore.kernel.org/r/20230621021619.265162-1-nm@ti.com Signed-off-by: Nishanth Menon --- drivers/firmware/ti_sci.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index 91aaa0ca9bde..26a37f47f4ca 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -1976,8 +1976,6 @@ static int ti_sci_free_irq(const struct ti_sci_handle *handle, u32 valid_params, * @src_index: IRQ source index within the source device * @dst_id: Device ID of the IRQ destination * @dst_host_irq: IRQ number of the destination device - * @vint_irq: Boolean specifying if this interrupt belongs to - * Interrupt Aggregator. * * Return: 0 if all went fine, else return appropriate error. */ @@ -2024,8 +2022,6 @@ static int ti_sci_cmd_set_event_map(const struct ti_sci_handle *handle, * @src_index: IRQ source index within the source device * @dst_id: Device ID of the IRQ destination * @dst_host_irq: IRQ number of the destination device - * @vint_irq: Boolean specifying if this interrupt belongs to - * Interrupt Aggregator. * * Return: 0 if all went fine, else return appropriate error. */ @@ -2618,6 +2614,7 @@ fail: * configuration flags * @handle: Pointer to TI SCI handle * @proc_id: Processor ID this request is for + * @bootvector: Processor Boot vector (start address) * @config_flags_set: Configuration flags to be set * @config_flags_clear: Configuration flags to be cleared. * @@ -2734,9 +2731,13 @@ fail: } /** - * ti_sci_cmd_get_boot_status() - Command to get the processor boot status + * ti_sci_cmd_proc_get_status() - Command to get the processor boot status * @handle: Pointer to TI SCI handle * @proc_id: Processor ID this request is for + * @bv: Processor Boot vector (start address) + * @cfg_flags: Processor specific configuration flags + * @ctrl_flags: Processor specific control flags + * @sts_flags: Processor specific status flags * * Return: 0 if all went well, else returns appropriate error value. */ @@ -3254,7 +3255,7 @@ EXPORT_SYMBOL_GPL(devm_ti_sci_get_of_resource); * @handle: TISCI handle * @dev: Device pointer to which the resource is assigned * @dev_id: TISCI device id to which the resource is assigned - * @suub_type: TISCI resource subytpe representing the resource. + * @sub_type: TISCI resource subytpe representing the resource. * * Return: Pointer to ti_sci_resource if all went well else appropriate * error pointer. From bffd3a805d8eb7a61e31eebb99bf089cf2229079 Mon Sep 17 00:00:00 2001 From: Nishanth Menon Date: Tue, 20 Jun 2023 21:34:42 -0500 Subject: [PATCH 015/136] soc: ti: k3-ringacc: Fixup documentation errors Fixup couple of misses in documentation. This squashes the following warnings: drivers/soc/ti/k3-ringacc.c:135: warning: Function parameter or member 'tdown_complete' not described in 'k3_ring_state' drivers/soc/ti/k3-ringacc.c:238: warning: expecting prototype for struct k3_ringacc. Prototype was for struct k3_ringacc_soc_data instead While at this, replace "w/a" to indicate workaround to help clarify. Cc: Peter Ujfalusi Reviewed-by: Randy Dunlap Link: https://lore.kernel.org/r/20230621023442.275128-1-nm@ti.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/k3-ringacc.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index 8f131368a758..999403e1b9e0 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -125,6 +125,7 @@ struct k3_ring_ops { * @occ: Occupancy * @windex: Write index * @rindex: Read index + * @tdown_complete: Tear down complete state */ struct k3_ring_state { u32 free; @@ -192,7 +193,7 @@ struct k3_ringacc_ops { * @num_rings: number of ring in RA * @rings_inuse: bitfield for ring usage tracking * @rm_gp_range: general purpose rings range from tisci - * @dma_ring_reset_quirk: DMA reset w/a enable + * @dma_ring_reset_quirk: DMA reset workaround enable * @num_proxies: number of RA proxies * @proxy_inuse: bitfield for proxy usage tracking * @rings: array of rings descriptors (struct @k3_ring) @@ -229,9 +230,9 @@ struct k3_ringacc { }; /** - * struct k3_ringacc - Rings accelerator SoC data + * struct k3_ringacc_soc_data - Rings accelerator SoC data * - * @dma_ring_reset_quirk: DMA reset w/a enable + * @dma_ring_reset_quirk: DMA reset workaround enable */ struct k3_ringacc_soc_data { unsigned dma_ring_reset_quirk:1; From bc0e769647d78cb2693376fbbd52e9abb9ab0ac2 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Thu, 6 Jul 2023 15:20:41 +0800 Subject: [PATCH 016/136] bus: vexpress-config: Convert to devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li Link: https://lore.kernel.org/r/20230706072042.31296-6-frank.li@vivo.com Signed-off-by: Sudeep Holla --- drivers/bus/vexpress-config.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/bus/vexpress-config.c b/drivers/bus/vexpress-config.c index 472a570bd53a..c4e1becbb2d2 100644 --- a/drivers/bus/vexpress-config.c +++ b/drivers/bus/vexpress-config.c @@ -350,7 +350,6 @@ static struct vexpress_config_bridge_ops vexpress_syscfg_bridge_ops = { static int vexpress_syscfg_probe(struct platform_device *pdev) { struct vexpress_syscfg *syscfg; - struct resource *res; struct vexpress_config_bridge *bridge; struct device_node *node; int master; @@ -362,8 +361,7 @@ static int vexpress_syscfg_probe(struct platform_device *pdev) syscfg->dev = &pdev->dev; INIT_LIST_HEAD(&syscfg->funcs); - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - syscfg->base = devm_ioremap_resource(&pdev->dev, res); + syscfg->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(syscfg->base)) return PTR_ERR(syscfg->base); From cbdd13bfea785667f9c9df4c6ec46fc841ef6c4a Mon Sep 17 00:00:00 2001 From: Christophe JAILLET Date: Wed, 12 Jul 2023 22:42:15 +0200 Subject: [PATCH 017/136] soc: qcom: smem: Use struct_size() Use struct_size() instead of hand-writing it, when allocating a structure with a flex array. This is less verbose. Signed-off-by: Christophe JAILLET Reviewed-by: Kees Cook Link: https://lore.kernel.org/r/f74328551cfab0262ba353f37d047ac74bf616e1.1689194490.git.christophe.jaillet@wanadoo.fr Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smem.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index b0d59e815c3b..776096b2e965 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -1059,7 +1059,6 @@ static int qcom_smem_probe(struct platform_device *pdev) struct reserved_mem *rmem; struct qcom_smem *smem; unsigned long flags; - size_t array_size; int num_regions; int hwlock_id; u32 version; @@ -1071,8 +1070,8 @@ static int qcom_smem_probe(struct platform_device *pdev) if (of_property_present(pdev->dev.of_node, "qcom,rpm-msg-ram")) num_regions++; - array_size = num_regions * sizeof(struct smem_region); - smem = devm_kzalloc(&pdev->dev, sizeof(*smem) + array_size, GFP_KERNEL); + smem = devm_kzalloc(&pdev->dev, struct_size(smem, regions, num_regions), + GFP_KERNEL); if (!smem) return -ENOMEM; From fe604ee3e09787a603010f91cf5c58b7ea4c5bd9 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 15 Jun 2023 18:50:34 +0200 Subject: [PATCH 018/136] dt-bindings soc: qcom: smd-rpm: Fix sort order Some of the enum entries are not properly ordered, fix that. Acked-by: Krzysztof Kozlowski Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-1-a07dcdefd918@gerhold.net Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 65c02a7fef80..fe814b991559 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -44,12 +44,12 @@ properties: - qcom,rpm-msm8994 - qcom,rpm-msm8996 - qcom,rpm-msm8998 + - qcom,rpm-qcm2290 + - qcom,rpm-qcs404 - qcom,rpm-sdm660 - qcom,rpm-sm6115 - qcom,rpm-sm6125 - qcom,rpm-sm6375 - - qcom,rpm-qcm2290 - - qcom,rpm-qcs404 clock-controller: $ref: /schemas/clock/qcom,rpmcc.yaml# @@ -84,9 +84,9 @@ if: - qcom,rpm-msm8226 - qcom,rpm-msm8916 - qcom,rpm-msm8936 + - qcom,rpm-msm8953 - qcom,rpm-msm8974 - qcom,rpm-msm8976 - - qcom,rpm-msm8953 - qcom,rpm-msm8994 then: properties: From 7b583c490a4e90316d8ac70aa299b4f7a568792c Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 15 Jun 2023 18:50:35 +0200 Subject: [PATCH 019/136] dt-bindings: soc: qcom: smd-rpm: Add MSM8909 to qcom,smd-channels MSM8909 is using qcom,smd-channels but is missing in the list, add it there as well. Fixes: 709d473dd5e1 ("dt-bindings: soc: qcom: smd-rpm: Add MSM8909") Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-2-a07dcdefd918@gerhold.net Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index fe814b991559..78822315edeb 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -82,6 +82,7 @@ if: enum: - qcom,rpm-apq8084 - qcom,rpm-msm8226 + - qcom,rpm-msm8909 - qcom,rpm-msm8916 - qcom,rpm-msm8936 - qcom,rpm-msm8953 From 029bf2941901cc57de0ae008bbd4c5c0717ab39b Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 15 Jun 2023 18:50:36 +0200 Subject: [PATCH 020/136] dt-bindings: soc: qcom: smd-rpm: Add some more compatibles To avoid several more small patches adding new RPM compatibles in the future, add MDM9607, MSM8610, MSM8917, MSM8937 and MSM8952 at once. All of these have been worked on over the time by some people and are definitely compatible as-is with the smd-rpm driver. Acked-by: Krzysztof Kozlowski Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-3-a07dcdefd918@gerhold.net Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index 78822315edeb..c6930706bfa9 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -34,10 +34,15 @@ properties: - qcom,rpm-apq8084 - qcom,rpm-ipq6018 - qcom,rpm-ipq9574 + - qcom,rpm-mdm9607 - qcom,rpm-msm8226 + - qcom,rpm-msm8610 - qcom,rpm-msm8909 - qcom,rpm-msm8916 + - qcom,rpm-msm8917 - qcom,rpm-msm8936 + - qcom,rpm-msm8937 + - qcom,rpm-msm8952 - qcom,rpm-msm8953 - qcom,rpm-msm8974 - qcom,rpm-msm8976 @@ -81,10 +86,15 @@ if: contains: enum: - qcom,rpm-apq8084 + - qcom,rpm-mdm9607 - qcom,rpm-msm8226 + - qcom,rpm-msm8610 - qcom,rpm-msm8909 - qcom,rpm-msm8916 + - qcom,rpm-msm8917 - qcom,rpm-msm8936 + - qcom,rpm-msm8937 + - qcom,rpm-msm8952 - qcom,rpm-msm8953 - qcom,rpm-msm8974 - qcom,rpm-msm8976 From bcabe1e09135cd4fc1f5cddc6d4a45a221a768cc Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 15 Jun 2023 18:50:37 +0200 Subject: [PATCH 021/136] soc: qcom: smd-rpm: Match rpmsg channel instead of compatible There is an ever growing list of compatibles in the smd-rpm.c driver. A fallback compatible would help here but would still require keeping the current list around for backwards compatibility. As an alternative, let's switch the driver to match the rpmsg_device_id instead, which is always "rpm_requests" on all platforms. Add a check to ensure that there is a device tree node defined for the device since otherwise the of_platform_populate() call will operate on the root node (/). Similar approaches with matching rpmsg_device_id are already used in qcom_sysmon, qcom_glink_ssr, qrtr, and rpmsg_wwan_ctrl. Tested-by: Konrad Dybcio # SM6375 (G-Link) Reviewed-by: Konrad Dybcio Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-4-a07dcdefd918@gerhold.net Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smd-rpm.c | 35 +++++++++-------------------------- 1 file changed, 9 insertions(+), 26 deletions(-) diff --git a/drivers/soc/qcom/smd-rpm.c b/drivers/soc/qcom/smd-rpm.c index 0c1aa809cc4e..13d8c52330d0 100644 --- a/drivers/soc/qcom/smd-rpm.c +++ b/drivers/soc/qcom/smd-rpm.c @@ -199,6 +199,9 @@ static int qcom_smd_rpm_probe(struct rpmsg_device *rpdev) struct qcom_smd_rpm *rpm; int ret; + if (!rpdev->dev.of_node) + return -EINVAL; + rpm = devm_kzalloc(&rpdev->dev, sizeof(*rpm), GFP_KERNEL); if (!rpm) return -ENOMEM; @@ -230,38 +233,18 @@ static void qcom_smd_rpm_remove(struct rpmsg_device *rpdev) of_platform_depopulate(&rpdev->dev); } -static const struct of_device_id qcom_smd_rpm_of_match[] = { - { .compatible = "qcom,rpm-apq8084" }, - { .compatible = "qcom,rpm-ipq6018" }, - { .compatible = "qcom,rpm-ipq9574" }, - { .compatible = "qcom,rpm-msm8226" }, - { .compatible = "qcom,rpm-msm8909" }, - { .compatible = "qcom,rpm-msm8916" }, - { .compatible = "qcom,rpm-msm8936" }, - { .compatible = "qcom,rpm-msm8953" }, - { .compatible = "qcom,rpm-msm8974" }, - { .compatible = "qcom,rpm-msm8976" }, - { .compatible = "qcom,rpm-msm8994" }, - { .compatible = "qcom,rpm-msm8996" }, - { .compatible = "qcom,rpm-msm8998" }, - { .compatible = "qcom,rpm-sdm660" }, - { .compatible = "qcom,rpm-sm6115" }, - { .compatible = "qcom,rpm-sm6125" }, - { .compatible = "qcom,rpm-sm6375" }, - { .compatible = "qcom,rpm-qcm2290" }, - { .compatible = "qcom,rpm-qcs404" }, - {} +static const struct rpmsg_device_id qcom_smd_rpm_id_table[] = { + { .name = "rpm_requests", }, + { /* sentinel */ } }; -MODULE_DEVICE_TABLE(of, qcom_smd_rpm_of_match); +MODULE_DEVICE_TABLE(rpmsg, qcom_smd_rpm_id_table); static struct rpmsg_driver qcom_smd_rpm_driver = { .probe = qcom_smd_rpm_probe, .remove = qcom_smd_rpm_remove, .callback = qcom_smd_rpm_callback, - .drv = { - .name = "qcom_smd_rpm", - .of_match_table = qcom_smd_rpm_of_match, - }, + .id_table = qcom_smd_rpm_id_table, + .drv.name = "qcom_smd_rpm", }; static int __init qcom_smd_rpm_init(void) From b3a12c2996ce152309a8263c26824a20cea12d1d Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 15 Jun 2023 18:50:38 +0200 Subject: [PATCH 022/136] dt-bindings: remoteproc: glink-rpm-edge: Use "glink-edge" as node name Semantically glink-edge and glink-rpm-edge are similar: Both describe the communication channels to a remote processor. The RPM glink-edge is a special case that needs slightly different properties but otherwise it is used exactly the same. To improve consistency use the same "glink-edge" node name also for glink-rpm-edge. Drop the $nodename from qcom,glink-edge.yaml to avoid matching the wrong schema. qcom,glink-edge.yaml is always referenced explicitly from other schemas. This will already ensure that the nodes are being checked, so it's not necessary to bind to all nodes named "glink-edge". Signed-off-by: Stephan Gerhold Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-5-a07dcdefd918@gerhold.net Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/remoteproc/qcom,glink-edge.yaml | 3 --- .../devicetree/bindings/remoteproc/qcom,glink-rpm-edge.yaml | 2 +- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml index 7b43ad3daa56..e78a89c9ec41 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,glink-edge.yaml @@ -14,9 +14,6 @@ description: related to the remote processor. properties: - $nodename: - const: glink-edge - apr: $ref: /schemas/soc/qcom/qcom,apr.yaml# required: diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,glink-rpm-edge.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,glink-rpm-edge.yaml index f5a044e20c4e..884158bccd50 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,glink-rpm-edge.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,glink-rpm-edge.yaml @@ -84,7 +84,7 @@ examples: - | #include - rpm-glink { + glink-edge { compatible = "qcom,glink-rpm"; interrupts = ; mboxes = <&apcs_glb 0>; From 9a2c674ee7816ef4d68e10e63f4b23fc4c725cbe Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 15 Jun 2023 18:50:39 +0200 Subject: [PATCH 023/136] dt-bindings: remoteproc: Add Qualcomm RPM processor/subsystem On Qualcomm platforms, most subsystems (e.g. audio/modem DSP) are described as remote processors in the device tree, with a dedicated node where properties and services related to them can be described. The Resource Power Manager (RPM) is also such a subsystem, with a remote processor that is running a special firmware. Unfortunately, the RPM never got a dedicated node representing it properly in the device tree. Most of the RPM services are described below a top-level /smd or /rpm-glink node. However, SMD/GLINK is just one of the communication channels to the RPM firmware. For example, the MPM interrupt functionality provided by the RPM does not use SMD/GLINK but writes directly to a special memory region allocated by the RPM firmware in combination with a mailbox. Currently there is no good place in the device tree to describe this functionality. It doesn't belong below SMD/GLINK but it's not an independent top-level device either. Introduce a new "qcom,rpm-proc" compatible that allows describing the RPM as a remote processor/subsystem like all others. The SMD/GLINK node is moved to a "smd-edge"/"glink-edge" subnode consistent with other existing bindings. Additional subnodes (e.g. interrupt-controller for MPM, rpm-master-stats) can be also added there. Deprecate using the old top-level /smd node since all SMD edges are now specified as subnodes of the remote processor. Signed-off-by: Stephan Gerhold Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-6-a07dcdefd918@gerhold.net Signed-off-by: Bjorn Andersson --- .../bindings/remoteproc/qcom,rpm-proc.yaml | 171 ++++++++++++++++++ .../bindings/soc/qcom/qcom,smd-rpm.yaml | 6 +- .../bindings/soc/qcom/qcom,smd.yaml | 7 + 3 files changed, 181 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml new file mode 100644 index 000000000000..7afafde17a38 --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml @@ -0,0 +1,171 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,rpm-proc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Resource Power Manager (RPM) Processor/Subsystem + +maintainers: + - Bjorn Andersson + - Konrad Dybcio + - Stephan Gerhold + +description: | + Resource Power Manager (RPM) subsystem found in various Qualcomm platforms: + + +--------------------------------------------+ + | RPM subsystem (qcom,rpm-proc) | + | | + reset | +---------------+ +-----+ +-----+ | + --------->| | | MPM | | CPR | ... | + IPC interrupts | | ARM Cortex-M3 |--- +-----+ +-----+ | + ----------------->| | | | | | + | +---------------+ |---------------------- | + | +---------------+ | | + | | Code RAM |--| +------------------+ | + | +---------------+ | | | | + | +---------------+ |--| Message RAM | | + | | Data RAM |--| | | | + | +---------------+ | +------------------+ | + +--------------------|-----------------------+ + v + NoC + + The firmware running on the processor inside the RPM subsystem allows each + component in the system to vote for state of the system resources, such as + clocks, regulators and bus frequencies. It implements multiple separate + communication interfaces that are described in subnodes, e.g. SMD and MPM: + + +------------------------------+ + | ARM Cortex-M3 | + | | +------------------------------+ + | +--------------------------+ | | Message RAM | + | | RPM firmware | | | | + IPC IRQ 0 | | +----------------------+ | | | +--------------------------+ | + -------------->| SMD server |<------->| SMD data structures | | + | | | +--------------+ | | | | | +--------------+ | | + | | | | rpm_requests | ... | | | | | | rpm_requests | ... | | + | | | +--------------+ | | | | | +--------------+ | | + IPC IRQ 1 | | +----------------------+ | | | +--------------------------+ | + -------------->| MPM virtualization |<--------| MPM register copy (vMPM) | | + | | +----------------------+ | | | +--------------------------+ | + | | ... | | | | ... | + | +--------------------|-----+ | +------------------------------+ + +----------------------|-------+ + v + +--------------+ + | MPM Hardware | + +--------------+ + + The services provided by the firmware are only available after the firmware + has been loaded and the processor has been released from reset. Usually this + happens early in the boot process before the operating system is started. + +properties: + compatible: + items: + - enum: + - qcom,apq8084-rpm-proc + - qcom,ipq6018-rpm-proc + - qcom,ipq9574-rpm-proc + - qcom,mdm9607-rpm-proc + - qcom,msm8226-rpm-proc + - qcom,msm8610-rpm-proc + - qcom,msm8909-rpm-proc + - qcom,msm8916-rpm-proc + - qcom,msm8917-rpm-proc + - qcom,msm8936-rpm-proc + - qcom,msm8937-rpm-proc + - qcom,msm8952-rpm-proc + - qcom,msm8953-rpm-proc + - qcom,msm8974-rpm-proc + - qcom,msm8976-rpm-proc + - qcom,msm8994-rpm-proc + - qcom,msm8996-rpm-proc + - qcom,msm8998-rpm-proc + - qcom,qcm2290-rpm-proc + - qcom,qcs404-rpm-proc + - qcom,sdm660-rpm-proc + - qcom,sm6115-rpm-proc + - qcom,sm6125-rpm-proc + - qcom,sm6375-rpm-proc + - const: qcom,rpm-proc + + smd-edge: + $ref: /schemas/remoteproc/qcom,smd-edge.yaml# + description: + Qualcomm Shared Memory subnode which represents communication edge, + channels and devices related to the RPM subsystem. + + glink-edge: + $ref: /schemas/remoteproc/qcom,glink-rpm-edge.yaml# + description: + Qualcomm G-Link subnode which represents communication edge, + channels and devices related to the RPM subsystem. + + interrupt-controller: + type: object + $ref: /schemas/interrupt-controller/qcom,mpm.yaml# + description: + MSM Power Manager (MPM) interrupt controller that monitors interrupts + when the system is asleep. + + master-stats: + $ref: /schemas/soc/qcom/qcom,rpm-master-stats.yaml# + description: + Subsystem-level low-power mode statistics provided by RPM. + +required: + - compatible + +oneOf: + - required: + - smd-edge + - required: + - glink-edge + +additionalProperties: false + +examples: + # SMD + - | + #include + #include + + remoteproc { + compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc"; + + smd-edge { + interrupts = ; + qcom,ipc = <&apcs 8 0>; + qcom,smd-edge = <15>; + + rpm-requests { + compatible = "qcom,rpm-msm8916"; + qcom,smd-channels = "rpm_requests"; + /* ... */ + }; + }; + }; + # GLINK + - | + #include + #include + + remoteproc { + compatible = "qcom,qcm2290-rpm-proc", "qcom,rpm-proc"; + + glink-edge { + compatible = "qcom,glink-rpm"; + interrupts = ; + qcom,rpm-msg-ram = <&rpm_msg_ram>; + mboxes = <&apcs_glb 0>; + + rpm-requests { + compatible = "qcom,rpm-qcm2290"; + qcom,glink-channels = "rpm_requests"; + /* ... */ + }; + }; + }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml index c6930706bfa9..2fa725b8af5d 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd-rpm.yaml @@ -120,10 +120,10 @@ examples: #include #include - smd { - compatible = "qcom,smd"; + remoteproc { + compatible = "qcom,msm8916-rpm-proc", "qcom,rpm-proc"; - rpm { + smd-edge { interrupts = ; qcom,ipc = <&apcs 8 0>; qcom,smd-edge = <15>; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml index 063e595c12f7..4819ce90d206 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,smd.yaml @@ -15,6 +15,12 @@ description: The Qualcomm Shared Memory Driver is a FIFO based communication channel for sending data between the various subsystems in Qualcomm platforms. + Using the top-level SMD node is deprecated. Instead, the SMD edges are defined + directly below the device node representing the respective remote subsystem + or remote processor. + +deprecated: true + properties: compatible: const: qcom,smd @@ -37,6 +43,7 @@ examples: # The following example represents a smd node, with one edge representing the # "rpm" subsystem. For the "rpm" subsystem we have a device tied to the # "rpm_request" channel. + # NOTE: This is deprecated, represent the RPM using "qcom,rpm-proc" instead. - | #include From 4dbb9e2322a3a9c912ce796c20c27045ae8dae22 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 15 Jun 2023 18:50:40 +0200 Subject: [PATCH 024/136] soc: qcom: smem: Add qcom_smem_is_available() Avoid having to look up a dummy item from SMEM to detect if it is already available or if we need to defer probing. Reviewed-by: Konrad Dybcio Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-7-a07dcdefd918@gerhold.net Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smem.c | 11 +++++++++++ include/linux/soc/qcom/smem.h | 1 + 2 files changed, 12 insertions(+) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index 776096b2e965..aa4a199efefb 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -359,6 +359,17 @@ static struct qcom_smem *__smem; /* Timeout (ms) for the trylock of remote spinlocks */ #define HWSPINLOCK_TIMEOUT 1000 +/** + * qcom_smem_is_available() - Check if SMEM is available + * + * Return: true if SMEM is available, false otherwise. + */ +bool qcom_smem_is_available(void) +{ + return !!__smem; +} +EXPORT_SYMBOL(qcom_smem_is_available); + static int qcom_smem_alloc_private(struct qcom_smem *smem, struct smem_partition *part, unsigned item, diff --git a/include/linux/soc/qcom/smem.h b/include/linux/soc/qcom/smem.h index 223db6a9c733..a36a3b9d4929 100644 --- a/include/linux/soc/qcom/smem.h +++ b/include/linux/soc/qcom/smem.h @@ -4,6 +4,7 @@ #define QCOM_SMEM_HOST_ANY -1 +bool qcom_smem_is_available(void); int qcom_smem_alloc(unsigned host, unsigned item, size_t size); void *qcom_smem_get(unsigned host, unsigned item, size_t *size); From 181563be4373e70bfab82773e3fce571edea9629 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 15 Jun 2023 18:50:41 +0200 Subject: [PATCH 025/136] rpmsg: qcom_smd: Use qcom_smem_is_available() Rather than looking up a dummy item from SMEM, use the new qcom_smem_is_available() function to make the code more clear (and reduce the overhead slightly). Add the same check to qcom_smd_register_edge() as well to ensure that it only succeeds if SMEM is already available - if a driver calls the function and SMEM is not available yet then the initial state will be read incorrectly and the RPMSG devices might never become available. Reviewed-by: Konrad Dybcio Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-8-a07dcdefd918@gerhold.net Signed-off-by: Bjorn Andersson --- drivers/rpmsg/qcom_smd.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/rpmsg/qcom_smd.c b/drivers/rpmsg/qcom_smd.c index 7b9c298aa491..43f601c84b4f 100644 --- a/drivers/rpmsg/qcom_smd.c +++ b/drivers/rpmsg/qcom_smd.c @@ -1479,6 +1479,9 @@ struct qcom_smd_edge *qcom_smd_register_edge(struct device *parent, struct qcom_smd_edge *edge; int ret; + if (!qcom_smem_is_available()) + return ERR_PTR(-EPROBE_DEFER); + edge = kzalloc(sizeof(*edge), GFP_KERNEL); if (!edge) return ERR_PTR(-ENOMEM); @@ -1553,12 +1556,9 @@ EXPORT_SYMBOL(qcom_smd_unregister_edge); static int qcom_smd_probe(struct platform_device *pdev) { struct device_node *node; - void *p; - /* Wait for smem */ - p = qcom_smem_get(QCOM_SMEM_HOST_ANY, smem_items[0].alloc_tbl_id, NULL); - if (PTR_ERR(p) == -EPROBE_DEFER) - return PTR_ERR(p); + if (!qcom_smem_is_available()) + return -EPROBE_DEFER; for_each_available_child_of_node(pdev->dev.of_node, node) qcom_smd_register_edge(&pdev->dev, node); From 8ddfa81d090c71fd6cb3cb8ca1d420c0da33a575 Mon Sep 17 00:00:00 2001 From: Stephan Gerhold Date: Thu, 15 Jun 2023 18:50:42 +0200 Subject: [PATCH 026/136] soc: qcom: Add RPM processor/subsystem driver Add a simple driver for the qcom,rpm-proc compatible that registers the "smd-edge" and populates other children defined in the device tree. Note that the DT schema belongs to the remoteproc subsystem while this driver is added inside soc/qcom. I argue that the RPM *is* a remoteproc, but as an implementation detail in Linux it can currently not benefit from anything provided by the remoteproc subsystem. The RPM firmware is usually already loaded and started by earlier components in the boot chain and is not meant to be ever restarted. To avoid breaking existing kernel configurations the driver is always built when smd-rpm.c is also built. They belong closely together anyway. To avoid build errors CONFIG_RPMSG_QCOM_SMD must be also built-in if rpm-proc is. Reviewed-by: Konrad Dybcio Signed-off-by: Stephan Gerhold Link: https://lore.kernel.org/r/20230531-rpm-rproc-v3-9-a07dcdefd918@gerhold.net Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/Kconfig | 1 + drivers/soc/qcom/Makefile | 2 +- drivers/soc/qcom/rpm-proc.c | 77 +++++++++++++++++++++++++++++++++++++ 3 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/qcom/rpm-proc.c diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index e597799e8121..715348869d04 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -191,6 +191,7 @@ config QCOM_SMD_RPM tristate "Qualcomm Resource Power Manager (RPM) over SMD" depends on ARCH_QCOM || COMPILE_TEST depends on RPMSG + depends on RPMSG_QCOM_SMD || RPMSG_QCOM_SMD=n help If you say yes to this option, support will be included for the Resource Power Manager system found in the Qualcomm 8974 based diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index 99114c71092b..113b9ff2ad43 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -18,7 +18,7 @@ obj-$(CONFIG_QCOM_RPM_MASTER_STATS) += rpm_master_stats.o obj-$(CONFIG_QCOM_RPMH) += qcom_rpmh.o qcom_rpmh-y += rpmh-rsc.o qcom_rpmh-y += rpmh.o -obj-$(CONFIG_QCOM_SMD_RPM) += smd-rpm.o +obj-$(CONFIG_QCOM_SMD_RPM) += rpm-proc.o smd-rpm.o obj-$(CONFIG_QCOM_SMEM) += smem.o obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o obj-$(CONFIG_QCOM_SMP2P) += smp2p.o diff --git a/drivers/soc/qcom/rpm-proc.c b/drivers/soc/qcom/rpm-proc.c new file mode 100644 index 000000000000..2995d9b90190 --- /dev/null +++ b/drivers/soc/qcom/rpm-proc.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Copyright (c) 2021-2023, Stephan Gerhold */ + +#include +#include +#include +#include +#include + +static int rpm_proc_probe(struct platform_device *pdev) +{ + struct qcom_smd_edge *edge = NULL; + struct device *dev = &pdev->dev; + struct device_node *edge_node; + int ret; + + edge_node = of_get_child_by_name(dev->of_node, "smd-edge"); + if (edge_node) { + edge = qcom_smd_register_edge(dev, edge_node); + of_node_put(edge_node); + if (IS_ERR(edge)) + return dev_err_probe(dev, PTR_ERR(edge), + "Failed to register smd-edge\n"); + } + + ret = devm_of_platform_populate(dev); + if (ret) { + dev_err(dev, "Failed to populate child devices: %d\n", ret); + goto err; + } + + platform_set_drvdata(pdev, edge); + return 0; +err: + if (edge) + qcom_smd_unregister_edge(edge); + return ret; +} + +static void rpm_proc_remove(struct platform_device *pdev) +{ + struct qcom_smd_edge *edge = platform_get_drvdata(pdev); + + if (edge) + qcom_smd_unregister_edge(edge); +} + +static const struct of_device_id rpm_proc_of_match[] = { + { .compatible = "qcom,rpm-proc", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rpm_proc_of_match); + +static struct platform_driver rpm_proc_driver = { + .probe = rpm_proc_probe, + .remove_new = rpm_proc_remove, + .driver = { + .name = "qcom-rpm-proc", + .of_match_table = rpm_proc_of_match, + }, +}; + +static int __init rpm_proc_init(void) +{ + return platform_driver_register(&rpm_proc_driver); +} +arch_initcall(rpm_proc_init); + +static void __exit rpm_proc_exit(void) +{ + platform_driver_unregister(&rpm_proc_driver); +} +module_exit(rpm_proc_exit); + +MODULE_DESCRIPTION("Qualcomm RPM processor/subsystem driver"); +MODULE_AUTHOR("Stephan Gerhold "); +MODULE_LICENSE("GPL"); From 6484be9dd109bded43953ae7883bd69b5d841a0b Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 14 Jul 2023 11:51:41 -0600 Subject: [PATCH 027/136] soc: qcom: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230714175142.4067795-1-robh@kernel.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/cpr.c | 1 - drivers/soc/qcom/icc-bwmon.c | 2 +- drivers/soc/qcom/ice.c | 2 ++ drivers/soc/qcom/llcc-qcom.c | 1 - drivers/soc/qcom/ocmem.c | 3 ++- drivers/soc/qcom/pmic_glink.c | 2 +- drivers/soc/qcom/pmic_glink_altmode.c | 1 + drivers/soc/qcom/rpmhpd.c | 1 - drivers/soc/qcom/rpmpd.c | 1 - drivers/soc/qcom/spm.c | 2 -- drivers/soc/qcom/wcnss_ctrl.c | 1 + 11 files changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/soc/qcom/cpr.c b/drivers/soc/qcom/cpr.c index 144ea68e0920..94a3f0977212 100644 --- a/drivers/soc/qcom/cpr.c +++ b/drivers/soc/qcom/cpr.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/soc/qcom/icc-bwmon.c b/drivers/soc/qcom/icc-bwmon.c index 8daf0eb03279..adf2d523f103 100644 --- a/drivers/soc/qcom/icc-bwmon.c +++ b/drivers/soc/qcom/icc-bwmon.c @@ -12,7 +12,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index a6123ea96272..fbab7fe5c652 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -11,7 +11,9 @@ #include #include #include +#include #include +#include #include diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 67c19ed2219a..e32a4161a8d0 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/soc/qcom/ocmem.c b/drivers/soc/qcom/ocmem.c index 2064e9512301..6edc18b211aa 100644 --- a/drivers/soc/qcom/ocmem.c +++ b/drivers/soc/qcom/ocmem.c @@ -14,7 +14,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index c87056769ebd..264e63493bfe 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -4,8 +4,8 @@ * Copyright (c) 2022, Linaro Ltd */ #include -#include #include +#include #include #include #include diff --git a/drivers/soc/qcom/pmic_glink_altmode.c b/drivers/soc/qcom/pmic_glink_altmode.c index df48fbea4b68..1dedacc52aea 100644 --- a/drivers/soc/qcom/pmic_glink_altmode.c +++ b/drivers/soc/qcom/pmic_glink_altmode.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index 63c35a32065b..2cae1d0aef48 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/soc/qcom/rpmpd.c b/drivers/soc/qcom/rpmpd.c index fa58c04214ee..3135dd1dafe0 100644 --- a/drivers/soc/qcom/rpmpd.c +++ b/drivers/soc/qcom/rpmpd.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index bab4897267b9..2f0b1bfe7658 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -12,8 +12,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/drivers/soc/qcom/wcnss_ctrl.c b/drivers/soc/qcom/wcnss_ctrl.c index 2a06d631e415..ad9942412c58 100644 --- a/drivers/soc/qcom/wcnss_ctrl.c +++ b/drivers/soc/qcom/wcnss_ctrl.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include From 7b95e20e32c9169d6232d097c26de825839872e8 Mon Sep 17 00:00:00 2001 From: Alexander Stein Date: Thu, 6 Jul 2023 09:46:29 +0200 Subject: [PATCH 028/136] soc: imx: imx93-blk-ctrl: Add dedicated lockdep class for nested genpd locks This is the same approach as being used within imx8mp-blk-ctrl. This fixes the lockdep warning about 'possible recursive locking detected' with the following (reduced) backtrace: genpd_lock_mtx+0x14/0x1c genpd_runtime_resume+0x108/0x308 __rpm_callback+0x44/0x19c rpm_callback+0x64/0x70 rpm_resume+0x438/0x6d8 __pm_runtime_resume+0x54/0xb0 imx93_blk_ctrl_power_on+0x100/0x294 _genpd_power_on+0x8c/0x16c genpd_power_on.part.0+0xa0/0x1a0 __genpd_dev_pm_attach+0x14c/0x2e4 genpd_dev_pm_attach+0x58/0x64 dev_pm_domain_attach+0x1c/0x2c Signed-off-by: Alexander Stein Signed-off-by: Shawn Guo --- drivers/soc/imx/imx93-blk-ctrl.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/soc/imx/imx93-blk-ctrl.c b/drivers/soc/imx/imx93-blk-ctrl.c index 2c600329436c..14eb991a670e 100644 --- a/drivers/soc/imx/imx93-blk-ctrl.c +++ b/drivers/soc/imx/imx93-blk-ctrl.c @@ -187,6 +187,8 @@ static int imx93_blk_ctrl_power_off(struct generic_pm_domain *genpd) return 0; } +static struct lock_class_key blk_ctrl_genpd_lock_class; + static int imx93_blk_ctrl_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -269,6 +271,19 @@ static int imx93_blk_ctrl_probe(struct platform_device *pdev) goto cleanup_pds; } + /* + * We use runtime PM to trigger power on/off of the upstream GPC + * domain, as a strict hierarchical parent/child power domain + * setup doesn't allow us to meet the sequencing requirements. + * This means we have nested locking of genpd locks, without the + * nesting being visible at the genpd level, so we need a + * separate lock class to make lockdep aware of the fact that + * this are separate domain locks that can be nested without a + * self-deadlock. + */ + lockdep_set_class(&domain->genpd.mlock, + &blk_ctrl_genpd_lock_class); + bc->onecell_data.domains[i] = &domain->genpd; } From 0e40e5fe87f11a8d282afc0dacc8c8b4f8a57630 Mon Sep 17 00:00:00 2001 From: Martin Kaiser Date: Sun, 9 Jul 2023 15:39:44 +0200 Subject: [PATCH 029/136] bus: imx-weim: use devm_platform_ioremap_resource devm_platform_get_and_ioremap_resource maps a resource and returns its physical address. If we don't need the physical address, we should call devm_platform_ioremap_resource instead. Signed-off-by: Martin Kaiser Signed-off-by: Shawn Guo --- drivers/bus/imx-weim.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c index 52a5d0447390..42c9386a7b42 100644 --- a/drivers/bus/imx-weim.c +++ b/drivers/bus/imx-weim.c @@ -273,7 +273,7 @@ static int weim_probe(struct platform_device *pdev) return -ENOMEM; /* get the resource */ - base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); + base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) return PTR_ERR(base); From ef2c1c84bcb98b66565facbba8dd32ce797b97eb Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 14 Jul 2023 11:51:33 -0600 Subject: [PATCH 030/136] soc: imx: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Signed-off-by: Shawn Guo --- drivers/soc/imx/gpcv2.c | 2 +- drivers/soc/imx/imx8m-blk-ctrl.c | 3 ++- drivers/soc/imx/imx8mp-blk-ctrl.c | 2 +- drivers/soc/imx/imx93-blk-ctrl.c | 2 +- drivers/soc/imx/imx93-pd.c | 2 +- 5 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index 4b3300b090a8..fbd3d92f8cd8 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -9,7 +9,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c index afbca0d48c14..cc5ef6e2f0a8 100644 --- a/drivers/soc/imx/imx8m-blk-ctrl.c +++ b/drivers/soc/imx/imx8m-blk-ctrl.c @@ -8,7 +8,8 @@ #include #include #include -#include +#include +#include #include #include #include diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c index 870aecc0202a..5a9f5ece43d9 100644 --- a/drivers/soc/imx/imx8mp-blk-ctrl.c +++ b/drivers/soc/imx/imx8mp-blk-ctrl.c @@ -10,7 +10,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/soc/imx/imx93-blk-ctrl.c b/drivers/soc/imx/imx93-blk-ctrl.c index 14eb991a670e..40bd90f8b977 100644 --- a/drivers/soc/imx/imx93-blk-ctrl.c +++ b/drivers/soc/imx/imx93-blk-ctrl.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/soc/imx/imx93-pd.c b/drivers/soc/imx/imx93-pd.c index 832deeed8fd6..b9e60d136875 100644 --- a/drivers/soc/imx/imx93-pd.c +++ b/drivers/soc/imx/imx93-pd.c @@ -5,8 +5,8 @@ #include #include -#include #include +#include #include #include #include From 4c4458375c5633954eda8fb9e7d31d56836b2bbd Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 14 Jul 2023 11:51:46 -0600 Subject: [PATCH 031/136] soc: samsung: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Acked-by: Alim Akhtar Link: https://lore.kernel.org/r/20230714175147.4068046-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- drivers/soc/samsung/exynos-chipid.c | 1 - drivers/soc/samsung/exynos-pmu.c | 2 +- drivers/soc/samsung/pm_domains.c | 3 ++- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/soc/samsung/exynos-chipid.c b/drivers/soc/samsung/exynos-chipid.c index 0fb3631e7346..7ba45c4aff97 100644 --- a/drivers/soc/samsung/exynos-chipid.c +++ b/drivers/soc/samsung/exynos-chipid.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index 5b2664da9853..250537d7cfd6 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -7,9 +7,9 @@ #include #include -#include #include #include +#include #include #include diff --git a/drivers/soc/samsung/pm_domains.c b/drivers/soc/samsung/pm_domains.c index d07f3c9d6903..9b502e8751d1 100644 --- a/drivers/soc/samsung/pm_domains.c +++ b/drivers/soc/samsung/pm_domains.c @@ -11,11 +11,12 @@ #include #include +#include #include #include #include +#include #include -#include #include struct exynos_pm_domain_config { From edf049c708681b4defacc740e3b254a5daa90e5e Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 14 Jul 2023 07:02:23 +0200 Subject: [PATCH 032/136] MAINTAINERS: samsung: Un-support cpuidle and clock drivers Since few years no one is really paid to support drivers for Samsung Exynos SoC CPU idle and clock controllers. Correct the status to keep them as maintained. Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20230714050223.8327-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- MAINTAINERS | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 3be1bdfe8ecc..ae2f478c0bac 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -5360,7 +5360,7 @@ M: Kukjin Kim R: Krzysztof Kozlowski L: linux-pm@vger.kernel.org L: linux-samsung-soc@vger.kernel.org -S: Supported +S: Maintained F: arch/arm/mach-exynos/pm.c F: drivers/cpuidle/cpuidle-exynos.c F: include/linux/platform_data/cpuidle-exynos.h @@ -18849,7 +18849,7 @@ M: Tomasz Figa M: Chanwoo Choi R: Alim Akhtar L: linux-samsung-soc@vger.kernel.org -S: Supported +S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/snawrocki/clk.git F: Documentation/devicetree/bindings/clock/samsung,*.yaml From 8297603c79821fa9bcf92cef28aaf8ea58725183 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 14 Jul 2023 11:51:54 -0600 Subject: [PATCH 033/136] soc/tegra: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Signed-off-by: Thierry Reding --- drivers/soc/tegra/cbb/tegra-cbb.c | 4 ---- drivers/soc/tegra/cbb/tegra194-cbb.c | 4 +--- drivers/soc/tegra/cbb/tegra234-cbb.c | 3 --- drivers/soc/tegra/fuse/fuse-tegra20.c | 2 +- drivers/soc/tegra/fuse/fuse-tegra30.c | 2 -- 5 files changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/soc/tegra/cbb/tegra-cbb.c b/drivers/soc/tegra/cbb/tegra-cbb.c index bd96204a68ee..be76c6aa131c 100644 --- a/drivers/soc/tegra/cbb/tegra-cbb.c +++ b/drivers/soc/tegra/cbb/tegra-cbb.c @@ -7,13 +7,9 @@ #include #include #include -#include -#include #include #include #include -#include -#include #include #include #include diff --git a/drivers/soc/tegra/cbb/tegra194-cbb.c b/drivers/soc/tegra/cbb/tegra194-cbb.c index 54d7ce05c636..cf6886f362d3 100644 --- a/drivers/soc/tegra/cbb/tegra194-cbb.c +++ b/drivers/soc/tegra/cbb/tegra194-cbb.c @@ -15,12 +15,10 @@ #include #include #include -#include +#include #include #include #include -#include -#include #include #include #include diff --git a/drivers/soc/tegra/cbb/tegra234-cbb.c b/drivers/soc/tegra/cbb/tegra234-cbb.c index 5d16161b2566..5cf0e8c34164 100644 --- a/drivers/soc/tegra/cbb/tegra234-cbb.c +++ b/drivers/soc/tegra/cbb/tegra234-cbb.c @@ -16,12 +16,9 @@ #include #include #include -#include #include #include #include -#include -#include #include #include #include diff --git a/drivers/soc/tegra/fuse/fuse-tegra20.c b/drivers/soc/tegra/fuse/fuse-tegra20.c index 12503f563e36..fdecf7b7c246 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra20.c +++ b/drivers/soc/tegra/fuse/fuse-tegra20.c @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/soc/tegra/fuse/fuse-tegra30.c b/drivers/soc/tegra/fuse/fuse-tegra30.c index c759fb7c8adc..e94d46372a63 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra30.c +++ b/drivers/soc/tegra/fuse/fuse-tegra30.c @@ -10,8 +10,6 @@ #include #include #include -#include -#include #include #include #include From 6674c9808048f28f979fc4c57994d936d477d3ed Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Wed, 5 Jul 2023 20:26:40 +0800 Subject: [PATCH 034/136] soc/tegra: fuse: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/fuse-tegra.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/soc/tegra/fuse/fuse-tegra.c b/drivers/soc/tegra/fuse/fuse-tegra.c index d7a37f5d4527..a2c28f493a75 100644 --- a/drivers/soc/tegra/fuse/fuse-tegra.c +++ b/drivers/soc/tegra/fuse/fuse-tegra.c @@ -125,13 +125,10 @@ static int tegra_fuse_probe(struct platform_device *pdev) return err; /* take over the memory region from the early initialization */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + fuse->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(fuse->base)) + return PTR_ERR(fuse->base); fuse->phys = res->start; - fuse->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(fuse->base)) { - err = PTR_ERR(fuse->base); - return err; - } fuse->clk = devm_clk_get(&pdev->dev, "fuse"); if (IS_ERR(fuse->clk)) { From df823d210395341c58e8d346dfc37d6e67e9f2c6 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Thu, 6 Jul 2023 15:20:40 +0800 Subject: [PATCH 035/136] bus: tegra-gmi: Convert to devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li Signed-off-by: Thierry Reding --- drivers/bus/tegra-gmi.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/bus/tegra-gmi.c b/drivers/bus/tegra-gmi.c index e3506ef37051..59919e99f7cc 100644 --- a/drivers/bus/tegra-gmi.c +++ b/drivers/bus/tegra-gmi.c @@ -211,7 +211,6 @@ static int tegra_gmi_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct tegra_gmi *gmi; - struct resource *res; int err; gmi = devm_kzalloc(dev, sizeof(*gmi), GFP_KERNEL); @@ -221,8 +220,7 @@ static int tegra_gmi_probe(struct platform_device *pdev) platform_set_drvdata(pdev, gmi); gmi->dev = dev; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - gmi->base = devm_ioremap_resource(dev, res); + gmi->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(gmi->base)) return PTR_ERR(gmi->base); From 7f31667d29f48e560172468636e5b07af4882026 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 19 Jul 2023 10:52:41 +0530 Subject: [PATCH 036/136] dt-bindings: power: qcom,rpmhpd: Add Generic RPMh PD indexes Add Generic RPMh Power Domain indexes that can be used for all the Qualcomm SoC henceforth. The power domain indexes of these bindings are based on compatibility with current targets like SM8[2345]50 targets. Signed-off-by: Rohit Agarwal Suggested-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/1689744162-9421-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/power/qcom,rpmhpd.h | 30 +++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 include/dt-bindings/power/qcom,rpmhpd.h diff --git a/include/dt-bindings/power/qcom,rpmhpd.h b/include/dt-bindings/power/qcom,rpmhpd.h new file mode 100644 index 000000000000..7c201a66bc69 --- /dev/null +++ b/include/dt-bindings/power/qcom,rpmhpd.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_POWER_QCOM_RPMHPD_H +#define _DT_BINDINGS_POWER_QCOM_RPMHPD_H + +/* Generic RPMH Power Domain Indexes */ +#define RPMHPD_CX 0 +#define RPMHPD_CX_AO 1 +#define RPMHPD_EBI 2 +#define RPMHPD_GFX 3 +#define RPMHPD_LCX 4 +#define RPMHPD_LMX 5 +#define RPMHPD_MMCX 6 +#define RPMHPD_MMCX_AO 7 +#define RPMHPD_MX 8 +#define RPMHPD_MX_AO 9 +#define RPMHPD_MXC 10 +#define RPMHPD_MXC_AO 11 +#define RPMHPD_MSS 12 +#define RPMHPD_NSP 13 +#define RPMHPD_NSP0 14 +#define RPMHPD_NSP1 15 +#define RPMHPD_QPHY 16 +#define RPMHPD_DDR 17 +#define RPMHPD_XO 18 + +#endif From de3acb7af908ef4fa9fda19cdfce1cc30cb48388 Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Wed, 19 Jul 2023 10:52:42 +0530 Subject: [PATCH 037/136] soc: qcom: rpmhpd: Use the newly created generic RPMHPD bindings Update the SoC SM8[2345]50 entries to use the new generic RPMHPD bindings. Signed-off-by: Rohit Agarwal Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/1689744162-9421-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmhpd.c | 101 +++++++++++++++++++------------------- 1 file changed, 51 insertions(+), 50 deletions(-) diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index 2cae1d0aef48..6641d5228bc6 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -14,6 +14,7 @@ #include #include #include +#include #define domain_to_rpmhpd(domain) container_of(domain, struct rpmhpd, pd) @@ -358,16 +359,16 @@ static const struct rpmhpd_desc sa8155p_desc = { /* SM8250 RPMH powerdomains */ static struct rpmhpd *sm8250_rpmhpds[] = { - [SM8250_CX] = &cx_w_mx_parent, - [SM8250_CX_AO] = &cx_ao_w_mx_parent, - [SM8250_EBI] = &ebi, - [SM8250_GFX] = &gfx, - [SM8250_LCX] = &lcx, - [SM8250_LMX] = &lmx, - [SM8250_MMCX] = &mmcx, - [SM8250_MMCX_AO] = &mmcx_ao, - [SM8250_MX] = &mx, - [SM8250_MX_AO] = &mx_ao, + [RPMHPD_CX] = &cx_w_mx_parent, + [RPMHPD_CX_AO] = &cx_ao_w_mx_parent, + [RPMHPD_EBI] = &ebi, + [RPMHPD_GFX] = &gfx, + [RPMHPD_LCX] = &lcx, + [RPMHPD_LMX] = &lmx, + [RPMHPD_MMCX] = &mmcx, + [RPMHPD_MMCX_AO] = &mmcx_ao, + [RPMHPD_MX] = &mx, + [RPMHPD_MX_AO] = &mx_ao, }; static const struct rpmhpd_desc sm8250_desc = { @@ -377,19 +378,19 @@ static const struct rpmhpd_desc sm8250_desc = { /* SM8350 Power domains */ static struct rpmhpd *sm8350_rpmhpds[] = { - [SM8350_CX] = &cx_w_mx_parent, - [SM8350_CX_AO] = &cx_ao_w_mx_parent, - [SM8350_EBI] = &ebi, - [SM8350_GFX] = &gfx, - [SM8350_LCX] = &lcx, - [SM8350_LMX] = &lmx, - [SM8350_MMCX] = &mmcx, - [SM8350_MMCX_AO] = &mmcx_ao, - [SM8350_MSS] = &mss, - [SM8350_MX] = &mx, - [SM8350_MX_AO] = &mx_ao, - [SM8350_MXC] = &mxc, - [SM8350_MXC_AO] = &mxc_ao, + [RPMHPD_CX] = &cx_w_mx_parent, + [RPMHPD_CX_AO] = &cx_ao_w_mx_parent, + [RPMHPD_EBI] = &ebi, + [RPMHPD_GFX] = &gfx, + [RPMHPD_LCX] = &lcx, + [RPMHPD_LMX] = &lmx, + [RPMHPD_MMCX] = &mmcx, + [RPMHPD_MMCX_AO] = &mmcx_ao, + [RPMHPD_MSS] = &mss, + [RPMHPD_MX] = &mx, + [RPMHPD_MX_AO] = &mx_ao, + [RPMHPD_MXC] = &mxc, + [RPMHPD_MXC_AO] = &mxc_ao, }; static const struct rpmhpd_desc sm8350_desc = { @@ -399,19 +400,19 @@ static const struct rpmhpd_desc sm8350_desc = { /* SM8450 RPMH powerdomains */ static struct rpmhpd *sm8450_rpmhpds[] = { - [SM8450_CX] = &cx, - [SM8450_CX_AO] = &cx_ao, - [SM8450_EBI] = &ebi, - [SM8450_GFX] = &gfx, - [SM8450_LCX] = &lcx, - [SM8450_LMX] = &lmx, - [SM8450_MMCX] = &mmcx_w_cx_parent, - [SM8450_MMCX_AO] = &mmcx_ao_w_cx_parent, - [SM8450_MSS] = &mss, - [SM8450_MX] = &mx, - [SM8450_MX_AO] = &mx_ao, - [SM8450_MXC] = &mxc, - [SM8450_MXC_AO] = &mxc_ao, + [RPMHPD_CX] = &cx, + [RPMHPD_CX_AO] = &cx_ao, + [RPMHPD_EBI] = &ebi, + [RPMHPD_GFX] = &gfx, + [RPMHPD_LCX] = &lcx, + [RPMHPD_LMX] = &lmx, + [RPMHPD_MMCX] = &mmcx_w_cx_parent, + [RPMHPD_MMCX_AO] = &mmcx_ao_w_cx_parent, + [RPMHPD_MSS] = &mss, + [RPMHPD_MX] = &mx, + [RPMHPD_MX_AO] = &mx_ao, + [RPMHPD_MXC] = &mxc, + [RPMHPD_MXC_AO] = &mxc_ao, }; static const struct rpmhpd_desc sm8450_desc = { @@ -421,20 +422,20 @@ static const struct rpmhpd_desc sm8450_desc = { /* SM8550 RPMH powerdomains */ static struct rpmhpd *sm8550_rpmhpds[] = { - [SM8550_CX] = &cx, - [SM8550_CX_AO] = &cx_ao, - [SM8550_EBI] = &ebi, - [SM8550_GFX] = &gfx, - [SM8550_LCX] = &lcx, - [SM8550_LMX] = &lmx, - [SM8550_MMCX] = &mmcx_w_cx_parent, - [SM8550_MMCX_AO] = &mmcx_ao_w_cx_parent, - [SM8550_MSS] = &mss, - [SM8550_MX] = &mx, - [SM8550_MX_AO] = &mx_ao, - [SM8550_MXC] = &mxc, - [SM8550_MXC_AO] = &mxc_ao, - [SM8550_NSP] = &nsp, + [RPMHPD_CX] = &cx, + [RPMHPD_CX_AO] = &cx_ao, + [RPMHPD_EBI] = &ebi, + [RPMHPD_GFX] = &gfx, + [RPMHPD_LCX] = &lcx, + [RPMHPD_LMX] = &lmx, + [RPMHPD_MMCX] = &mmcx_w_cx_parent, + [RPMHPD_MMCX_AO] = &mmcx_ao_w_cx_parent, + [RPMHPD_MSS] = &mss, + [RPMHPD_MX] = &mx, + [RPMHPD_MX_AO] = &mx_ao, + [RPMHPD_MXC] = &mxc, + [RPMHPD_MXC_AO] = &mxc_ao, + [RPMHPD_NSP] = &nsp, }; static const struct rpmhpd_desc sm8550_desc = { From 489d7a8cc286f37f52156100b95751b10e240941 Mon Sep 17 00:00:00 2001 From: Yuanjun Gong Date: Thu, 20 Jul 2023 22:08:34 +0800 Subject: [PATCH 038/136] soc: qcom: use devm_clk_get_enabled() in gsbi_probe() in gsbi_probe(), the return value of function clk_prepare_enable() should be checked, since it may fail. using devm_clk_get_enabled() instead of devm_clk_get() and clk_prepare_enable() can avoid this problem. Signed-off-by: Yuanjun Gong Link: https://lore.kernel.org/r/20230720140834.33557-1-ruc_gongyuanjun@163.com [bjorn: Dropped unnecessary "ret" variable] Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom_gsbi.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/soc/qcom/qcom_gsbi.c b/drivers/soc/qcom/qcom_gsbi.c index f1742e5bddb9..df7907a83aa8 100644 --- a/drivers/soc/qcom/qcom_gsbi.c +++ b/drivers/soc/qcom/qcom_gsbi.c @@ -129,7 +129,7 @@ static int gsbi_probe(struct platform_device *pdev) const struct of_device_id *match; void __iomem *base; struct gsbi_info *gsbi; - int i, ret; + int i; u32 mask, gsbi_num; const struct crci_config *config = NULL; @@ -178,12 +178,10 @@ static int gsbi_probe(struct platform_device *pdev) dev_info(&pdev->dev, "GSBI port protocol: %d crci: %d\n", gsbi->mode, gsbi->crci); - gsbi->hclk = devm_clk_get(&pdev->dev, "iface"); + gsbi->hclk = devm_clk_get_enabled(&pdev->dev, "iface"); if (IS_ERR(gsbi->hclk)) return PTR_ERR(gsbi->hclk); - clk_prepare_enable(gsbi->hclk); - writel_relaxed((gsbi->mode << GSBI_PROTOCOL_SHIFT) | gsbi->crci, base + GSBI_CTRL_REG); @@ -211,10 +209,7 @@ static int gsbi_probe(struct platform_device *pdev) platform_set_drvdata(pdev, gsbi); - ret = of_platform_populate(node, NULL, NULL, &pdev->dev); - if (ret) - clk_disable_unprepare(gsbi->hclk); - return ret; + return of_platform_populate(node, NULL, NULL, &pdev->dev); } static int gsbi_remove(struct platform_device *pdev) From 7dc3ea5ea8e8df2a82a1e78bef2382fb2c982ed3 Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Tue, 27 Jun 2023 18:24:25 +0200 Subject: [PATCH 039/136] dt-bindings: arm: msm: kpss-acc: Make the optional reg truly optional The description of reg[1] says that register is optional. Adjust minItems to make it truly optional. Fixes: 4260ddfb6496 ("dt-bindings: arm: msm: Convert and split kpss-acc driver Documentation to yaml") Signed-off-by: Konrad Dybcio Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230627-topic-more_bindings-v1-9-6b4b6cd081e5@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml b/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml index 202a5d51ee88..facaafefb441 100644 --- a/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml +++ b/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml @@ -21,6 +21,7 @@ properties: const: qcom,kpss-acc-v2 reg: + minItems: 1 items: - description: Base address and size of the register region - description: Optional base address and size of the alias register region From 5130464a14d382c30662faf090fd2be11558183a Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 24 Jun 2023 14:23:45 +0200 Subject: [PATCH 040/136] firmware: qcom_scm: Always try to consume all three clocks The code for handling more than 1 clock is a bit messy and requires one to add new, SoC-specific compatibles if one wants to attach a clock. Switch devm_clk_get to devm_clk_get_optional to prevent throwing it from throwing errors when the clock is absent and defer checking the clock requirements to dt schema. This lets us get rid of compatibles that aren't necessary for backwards compatibility *and* will hopefully prevent the addition of meaningless new compatibles. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230623-topic-scm_cleanup-v2-1-9db8c583138d@linaro.org Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom_scm.c | 73 +++++++------------------------------ 1 file changed, 13 insertions(+), 60 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index fde33acd46b7..237d05d6208b 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -26,10 +26,6 @@ static bool download_mode = IS_ENABLED(CONFIG_QCOM_SCM_DOWNLOAD_MODE_DEFAULT); module_param(download_mode, bool, 0); -#define SCM_HAS_CORE_CLK BIT(0) -#define SCM_HAS_IFACE_CLK BIT(1) -#define SCM_HAS_BUS_CLK BIT(2) - struct qcom_scm { struct device *dev; struct clk *core_clk; @@ -1405,7 +1401,6 @@ out: static int qcom_scm_probe(struct platform_device *pdev) { struct qcom_scm *scm; - unsigned long clks; int irq, ret; scm = devm_kzalloc(&pdev->dev, sizeof(*scm), GFP_KERNEL); @@ -1418,50 +1413,27 @@ static int qcom_scm_probe(struct platform_device *pdev) mutex_init(&scm->scm_bw_lock); - clks = (unsigned long)of_device_get_match_data(&pdev->dev); - scm->path = devm_of_icc_get(&pdev->dev, NULL); if (IS_ERR(scm->path)) return dev_err_probe(&pdev->dev, PTR_ERR(scm->path), "failed to acquire interconnect path\n"); - scm->core_clk = devm_clk_get(&pdev->dev, "core"); + scm->core_clk = devm_clk_get_optional(&pdev->dev, "core"); if (IS_ERR(scm->core_clk)) { if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER) return PTR_ERR(scm->core_clk); - - if (clks & SCM_HAS_CORE_CLK) { - dev_err(&pdev->dev, "failed to acquire core clk\n"); - return PTR_ERR(scm->core_clk); - } - - scm->core_clk = NULL; } - scm->iface_clk = devm_clk_get(&pdev->dev, "iface"); + scm->iface_clk = devm_clk_get_optional(&pdev->dev, "iface"); if (IS_ERR(scm->iface_clk)) { if (PTR_ERR(scm->iface_clk) == -EPROBE_DEFER) return PTR_ERR(scm->iface_clk); - - if (clks & SCM_HAS_IFACE_CLK) { - dev_err(&pdev->dev, "failed to acquire iface clk\n"); - return PTR_ERR(scm->iface_clk); - } - - scm->iface_clk = NULL; } - scm->bus_clk = devm_clk_get(&pdev->dev, "bus"); + scm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); if (IS_ERR(scm->bus_clk)) { if (PTR_ERR(scm->bus_clk) == -EPROBE_DEFER) return PTR_ERR(scm->bus_clk); - - if (clks & SCM_HAS_BUS_CLK) { - dev_err(&pdev->dev, "failed to acquire bus clk\n"); - return PTR_ERR(scm->bus_clk); - } - - scm->bus_clk = NULL; } scm->reset.ops = &qcom_scm_pas_reset_ops; @@ -1512,38 +1484,19 @@ static void qcom_scm_shutdown(struct platform_device *pdev) } static const struct of_device_id qcom_scm_dt_match[] = { - { .compatible = "qcom,scm-apq8064", - /* FIXME: This should have .data = (void *) SCM_HAS_CORE_CLK */ - }, - { .compatible = "qcom,scm-apq8084", .data = (void *)(SCM_HAS_CORE_CLK | - SCM_HAS_IFACE_CLK | - SCM_HAS_BUS_CLK) - }, + { .compatible = "qcom,scm-apq8064" }, + { .compatible = "qcom,scm-apq8084" }, { .compatible = "qcom,scm-ipq4019" }, - { .compatible = "qcom,scm-mdm9607", .data = (void *)(SCM_HAS_CORE_CLK | - SCM_HAS_IFACE_CLK | - SCM_HAS_BUS_CLK) }, - { .compatible = "qcom,scm-msm8660", .data = (void *) SCM_HAS_CORE_CLK }, - { .compatible = "qcom,scm-msm8960", .data = (void *) SCM_HAS_CORE_CLK }, - { .compatible = "qcom,scm-msm8916", .data = (void *)(SCM_HAS_CORE_CLK | - SCM_HAS_IFACE_CLK | - SCM_HAS_BUS_CLK) - }, - { .compatible = "qcom,scm-msm8953", .data = (void *)(SCM_HAS_CORE_CLK | - SCM_HAS_IFACE_CLK | - SCM_HAS_BUS_CLK) - }, - { .compatible = "qcom,scm-msm8974", .data = (void *)(SCM_HAS_CORE_CLK | - SCM_HAS_IFACE_CLK | - SCM_HAS_BUS_CLK) - }, - { .compatible = "qcom,scm-msm8976", .data = (void *)(SCM_HAS_CORE_CLK | - SCM_HAS_IFACE_CLK | - SCM_HAS_BUS_CLK) - }, + { .compatible = "qcom,scm-mdm9607" }, + { .compatible = "qcom,scm-msm8660" }, + { .compatible = "qcom,scm-msm8960" }, + { .compatible = "qcom,scm-msm8916" }, + { .compatible = "qcom,scm-msm8953" }, + { .compatible = "qcom,scm-msm8974" }, + { .compatible = "qcom,scm-msm8976" }, { .compatible = "qcom,scm-msm8994" }, { .compatible = "qcom,scm-msm8996" }, - { .compatible = "qcom,scm-sm6375", .data = (void *)SCM_HAS_CORE_CLK }, + { .compatible = "qcom,scm-sm6375" }, { .compatible = "qcom,scm" }, {} }; From ae76fd3f5554fe7b30207100ff002669714081ee Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 24 Jun 2023 14:23:46 +0200 Subject: [PATCH 041/136] firmware: qcom_scm: Always return devm_clk_get_optional errors If devm_clk_get_optional throws an error, something is really wrong. It may be a probe deferral, or it may be a problem with the clock provider. Regardless of what it may be, it should definitely not be ignored. Stop doing that. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230623-topic-scm_cleanup-v2-2-9db8c583138d@linaro.org Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom_scm.c | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index 237d05d6208b..b8398002205d 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1419,22 +1419,16 @@ static int qcom_scm_probe(struct platform_device *pdev) "failed to acquire interconnect path\n"); scm->core_clk = devm_clk_get_optional(&pdev->dev, "core"); - if (IS_ERR(scm->core_clk)) { - if (PTR_ERR(scm->core_clk) == -EPROBE_DEFER) - return PTR_ERR(scm->core_clk); - } + if (IS_ERR(scm->core_clk)) + return PTR_ERR(scm->core_clk); scm->iface_clk = devm_clk_get_optional(&pdev->dev, "iface"); - if (IS_ERR(scm->iface_clk)) { - if (PTR_ERR(scm->iface_clk) == -EPROBE_DEFER) - return PTR_ERR(scm->iface_clk); - } + if (IS_ERR(scm->iface_clk)) + return PTR_ERR(scm->iface_clk); scm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); - if (IS_ERR(scm->bus_clk)) { - if (PTR_ERR(scm->bus_clk) == -EPROBE_DEFER) - return PTR_ERR(scm->bus_clk); - } + if (IS_ERR(scm->bus_clk)) + return PTR_ERR(scm->bus_clk); scm->reset.ops = &qcom_scm_pas_reset_ops; scm->reset.nr_resets = 1; From 626237dbc9ff233cc51cc3313e5f41dfd79181bc Mon Sep 17 00:00:00 2001 From: Konrad Dybcio Date: Sat, 24 Jun 2023 14:23:47 +0200 Subject: [PATCH 042/136] firmware: qcom_scm: Drop useless compatibles There are three categories of compatibles within the driver: 1. Ones which were introduced without a qcom,scm fallback 2. Ones which were introduced with a qcom,scm fallback 3. Ones which were defined but never used Keep 1 for backwards compatibility and axe 2 & 3. Signed-off-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230623-topic-scm_cleanup-v2-3-9db8c583138d@linaro.org Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom_scm.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index b8398002205d..b6055b1c18d8 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -1478,20 +1478,15 @@ static void qcom_scm_shutdown(struct platform_device *pdev) } static const struct of_device_id qcom_scm_dt_match[] = { + { .compatible = "qcom,scm" }, + + /* Legacy entries kept for backwards compatibility */ { .compatible = "qcom,scm-apq8064" }, { .compatible = "qcom,scm-apq8084" }, { .compatible = "qcom,scm-ipq4019" }, - { .compatible = "qcom,scm-mdm9607" }, - { .compatible = "qcom,scm-msm8660" }, - { .compatible = "qcom,scm-msm8960" }, - { .compatible = "qcom,scm-msm8916" }, { .compatible = "qcom,scm-msm8953" }, { .compatible = "qcom,scm-msm8974" }, - { .compatible = "qcom,scm-msm8976" }, - { .compatible = "qcom,scm-msm8994" }, { .compatible = "qcom,scm-msm8996" }, - { .compatible = "qcom,scm-sm6375" }, - { .compatible = "qcom,scm" }, {} }; MODULE_DEVICE_TABLE(of, qcom_scm_dt_match); From 5542c7cfc1082608959b4317ab7c3867b5f4aa7c Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Wed, 5 Jul 2023 20:26:39 +0800 Subject: [PATCH 043/136] soc: ti: omap-prm: Use devm_platform_get_and_ioremap_resource() Convert platform_get_resource(), devm_ioremap_resource() to a single call to devm_platform_get_and_ioremap_resource(), as this is exactly what this function does. Signed-off-by: Yangtao Li Link: https://lore.kernel.org/r/20230705122644.32236-1-frank.li@vivo.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/omap_prm.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index ecd9a8bdd7c0..b2cf0a1810b9 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -943,10 +943,6 @@ static int omap_prm_probe(struct platform_device *pdev) struct omap_prm *prm; int ret; - res = platform_get_resource(pdev, IORESOURCE_MEM, 0); - if (!res) - return -ENODEV; - data = of_device_get_match_data(&pdev->dev); if (!data) return -ENOTSUPP; @@ -955,6 +951,10 @@ static int omap_prm_probe(struct platform_device *pdev) if (!prm) return -ENOMEM; + prm->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); + if (IS_ERR(prm->base)) + return PTR_ERR(prm->base); + while (data->base != res->start) { if (!data->base) return -EINVAL; @@ -963,10 +963,6 @@ static int omap_prm_probe(struct platform_device *pdev) prm->data = data; - prm->base = devm_ioremap_resource(&pdev->dev, res); - if (IS_ERR(prm->base)) - return PTR_ERR(prm->base); - ret = omap_prm_domain_init(&pdev->dev, prm); if (ret) return ret; From cdbab28c3728e6c47228585eb6e84669518a1e7d Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 14 Jul 2023 11:51:56 -0600 Subject: [PATCH 044/136] soc: ti: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230714175156.4068520-1-robh@kernel.org Signed-off-by: Nishanth Menon --- drivers/soc/ti/k3-ringacc.c | 1 - drivers/soc/ti/omap_prm.c | 1 - drivers/soc/ti/pruss.c | 4 +++- drivers/soc/ti/ti_sci_inta_msi.c | 3 ++- 4 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index 999403e1b9e0..c6fdf0ad3d33 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/soc/ti/omap_prm.c b/drivers/soc/ti/omap_prm.c index b2cf0a1810b9..c2feae3a634c 100644 --- a/drivers/soc/ti/omap_prm.c +++ b/drivers/soc/ti/omap_prm.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/soc/ti/pruss.c b/drivers/soc/ti/pruss.c index 7fdefee1ed87..f49f8492dde5 100644 --- a/drivers/soc/ti/pruss.c +++ b/drivers/soc/ti/pruss.c @@ -14,8 +14,10 @@ #include #include #include +#include #include -#include +#include +#include #include #include #include diff --git a/drivers/soc/ti/ti_sci_inta_msi.c b/drivers/soc/ti/ti_sci_inta_msi.c index b9251e1d9a5c..c36364522157 100644 --- a/drivers/soc/ti/ti_sci_inta_msi.c +++ b/drivers/soc/ti/ti_sci_inta_msi.c @@ -9,9 +9,10 @@ #include #include #include +#include #include -#include #include +#include #include #include From 6d0c4aa516280c3bab82cd3c53d142401eccab26 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Wed, 21 Jun 2023 19:13:57 +0530 Subject: [PATCH 045/136] memory: tegra: sort tegra234_mc_clients table as per register offsets Sort the MC client entries in "tegra234_mc_clients" table as per the override and security register offsets. This will help to avoid creating duplicate entries. Signed-off-by: Sumit Gupta Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20230621134400.23070-2-sumitg@nvidia.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra234.c | 524 ++++++++++++++++---------------- 1 file changed, 264 insertions(+), 260 deletions(-) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 8fb83b39f5f5..84f4d964d834 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -12,6 +12,10 @@ #include #include "mc.h" +/* + * MC Client entries are sorted in the increasing order of the + * override and security register offsets. + */ static const struct tegra_mc_client tegra234_mc_clients[] = { { .id = TEGRA234_MEMORY_CLIENT_HDAR, @@ -25,6 +29,106 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0xac, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AR, + .name = "pcie6ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x140, + .security = 0x144, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AW, + .name = "pcie6aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x148, + .security = 0x14c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AR, + .name = "pcie7ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x150, + .security = 0x154, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0RDB, + .name = "dla0rdb", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x160, + .security = 0x164, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1, + .name = "dla0rdb1", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x168, + .security = 0x16c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0WRB, + .name = "dla0wrb", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x170, + .security = 0x174, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1RDB, + .name = "dla0rdb", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x178, + .security = 0x17c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AW, + .name = "pcie7aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x180, + .security = 0x184, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE8AR, + .name = "pcie8ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE8, + .regs = { + .sid = { + .override = 0x190, + .security = 0x194, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_HDAW, .name = "hdaw", @@ -37,6 +141,102 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x1ac, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE8AW, + .name = "pcie8aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE8, + .regs = { + .sid = { + .override = 0x1d8, + .security = 0x1dc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE9AR, + .name = "pcie9ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE9, + .regs = { + .sid = { + .override = 0x1e0, + .security = 0x1e4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1, + .name = "pcie6ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE6, + .regs = { + .sid = { + .override = 0x1e8, + .security = 0x1ec, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE9AW, + .name = "pcie9aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE9, + .regs = { + .sid = { + .override = 0x1f0, + .security = 0x1f4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AR, + .name = "pcie10ar", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x1f8, + .security = 0x1fc, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AW, + .name = "pcie10aw", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x200, + .security = 0x204, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1, + .name = "pcie10ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE10, + .regs = { + .sid = { + .override = 0x240, + .security = 0x244, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1, + .name = "pcie7ar1", + .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_PCIE7, + .regs = { + .sid = { + .override = 0x248, + .security = 0x24c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_MGBEARD, .name = "mgbeard", @@ -157,6 +357,26 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x33c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1, + .name = "dla0rdb1", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x370, + .security = 0x374, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1WRB, + .name = "dla0wrb", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x378, + .security = 0x37c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_VI2W, .name = "vi2w", @@ -181,18 +401,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x38c, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_VI2FALW, - .name = "vi2falw", - .bpmp_id = TEGRA_ICC_BPMP_VI2FAL, - .type = TEGRA_ICC_ISO_VIFAL, - .sid = TEGRA234_SID_ISO_VI2FALC, - .regs = { - .sid = { - .override = 0x3e0, - .security = 0x3e4, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_APER, .name = "aper", @@ -217,6 +425,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x3dc, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_VI2FALW, + .name = "vi2falw", + .bpmp_id = TEGRA_ICC_BPMP_VI2FAL, + .type = TEGRA_ICC_ISO_VIFAL, + .sid = TEGRA234_SID_ISO_VI2FALC, + .regs = { + .sid = { + .override = 0x3e0, + .security = 0x3e4, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR, .name = "nvdisplayr", @@ -229,18 +449,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x494, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1, - .name = "nvdisplayr1", - .bpmp_id = TEGRA_ICC_BPMP_DISPLAY, - .type = TEGRA_ICC_ISO_DISPLAY, - .sid = TEGRA234_SID_ISO_NVDISPLAY, - .regs = { - .sid = { - .override = 0x508, - .security = 0x50c, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_BPMPR, .name = "bpmpr", @@ -305,6 +513,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x504, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR1, + .name = "nvdisplayr1", + .bpmp_id = TEGRA_ICC_BPMP_DISPLAY, + .type = TEGRA_ICC_ISO_DISPLAY, + .sid = TEGRA234_SID_ISO_NVDISPLAY, + .regs = { + .sid = { + .override = 0x508, + .security = 0x50c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA0RDA, .name = "dla0rda", @@ -335,26 +555,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x604, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA0RDB, - .name = "dla0rdb", - .sid = TEGRA234_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x160, - .security = 0x164, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1, - .name = "dla0rda1", - .sid = TEGRA234_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x748, - .security = 0x74c, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA0FALWRB, .name = "dla0falwrb", @@ -365,26 +565,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x60c, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA0RDB1, - .name = "dla0rdb1", - .sid = TEGRA234_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x168, - .security = 0x16c, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA0WRB, - .name = "dla0wrb", - .sid = TEGRA234_SID_NVDLA0, - .regs = { - .sid = { - .override = 0x170, - .security = 0x174, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA1RDA, .name = "dla0rda", @@ -415,26 +595,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x624, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA1RDB, - .name = "dla0rdb", - .sid = TEGRA234_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x178, - .security = 0x17c, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1, - .name = "dla0rda1", - .sid = TEGRA234_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x750, - .security = 0x754, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA1FALWRB, .name = "dla0falwrb", @@ -445,26 +605,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x62c, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1, - .name = "dla0rdb1", - .sid = TEGRA234_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x370, - .security = 0x374, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_DLA1WRB, - .name = "dla0wrb", - .sid = TEGRA234_SID_NVDLA1, - .regs = { - .sid = { - .override = 0x378, - .security = 0x37c, - }, - }, }, { .id = TEGRA234_MEMORY_CLIENT_PCIE0R, .name = "pcie0r", @@ -609,6 +749,26 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x71c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA0RDA1, + .name = "dla0rda1", + .sid = TEGRA234_SID_NVDLA0, + .regs = { + .sid = { + .override = 0x748, + .security = 0x74c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_DLA1RDA1, + .name = "dla0rda1", + .sid = TEGRA234_SID_NVDLA1, + .regs = { + .sid = { + .override = 0x750, + .security = 0x754, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_PCIE5R1, .name = "pcie5r1", @@ -621,162 +781,6 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x77c, }, }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE6AR, - .name = "pcie6ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE6, - .regs = { - .sid = { - .override = 0x140, - .security = 0x144, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE6AW, - .name = "pcie6aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE6, - .regs = { - .sid = { - .override = 0x148, - .security = 0x14c, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE6AR1, - .name = "pcie6ar1", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_6, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE6, - .regs = { - .sid = { - .override = 0x1e8, - .security = 0x1ec, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE7AR, - .name = "pcie7ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE7, - .regs = { - .sid = { - .override = 0x150, - .security = 0x154, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE7AW, - .name = "pcie7aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE7, - .regs = { - .sid = { - .override = 0x180, - .security = 0x184, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE7AR1, - .name = "pcie7ar1", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_7, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE7, - .regs = { - .sid = { - .override = 0x248, - .security = 0x24c, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE8AR, - .name = "pcie8ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE8, - .regs = { - .sid = { - .override = 0x190, - .security = 0x194, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE8AW, - .name = "pcie8aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_8, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE8, - .regs = { - .sid = { - .override = 0x1d8, - .security = 0x1dc, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE9AR, - .name = "pcie9ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE9, - .regs = { - .sid = { - .override = 0x1e0, - .security = 0x1e4, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE9AW, - .name = "pcie9aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_9, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE9, - .regs = { - .sid = { - .override = 0x1f0, - .security = 0x1f4, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE10AR, - .name = "pcie10ar", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE10, - .regs = { - .sid = { - .override = 0x1f8, - .security = 0x1fc, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE10AW, - .name = "pcie10aw", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE10, - .regs = { - .sid = { - .override = 0x200, - .security = 0x204, - }, - }, - }, { - .id = TEGRA234_MEMORY_CLIENT_PCIE10AR1, - .name = "pcie10ar1", - .bpmp_id = TEGRA_ICC_BPMP_PCIE_10, - .type = TEGRA_ICC_NISO, - .sid = TEGRA234_SID_PCIE10, - .regs = { - .sid = { - .override = 0x240, - .security = 0x244, - }, - }, }, { .id = TEGRA_ICC_MC_CPU_CLUSTER0, .name = "sw_cluster0", From b18e525990acb67f214f6b2528fae292ac9cf641 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Wed, 21 Jun 2023 19:13:58 +0530 Subject: [PATCH 046/136] memory: tegra: Add clients used by DRM in Tegra234 Add entries for VIC, NVDEC, NVENC, NVJPG memory controller clients into the 'tegra_234_mc_clients' table. Signed-off-by: Johnny Liu Signed-off-by: Sumit Gupta Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20230621134400.23070-3-sumitg@nvidia.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra234.c | 120 ++++++++++++++++++++++++++++++++ 1 file changed, 120 insertions(+) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 84f4d964d834..7954f339ca79 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -29,6 +29,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0xac, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVENCSRD, + .name = "nvencsrd", + .bpmp_id = TEGRA_ICC_BPMP_NVENC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVENC, + .regs = { + .sid = { + .override = 0xe0, + .security = 0xe4, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_PCIE6AR, .name = "pcie6ar", @@ -65,6 +77,18 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x154, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVENCSWR, + .name = "nvencswr", + .bpmp_id = TEGRA_ICC_BPMP_NVENC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVENC, + .regs = { + .sid = { + .override = 0x158, + .security = 0x15c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA0RDB, .name = "dla0rdb", @@ -357,6 +381,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x33c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_VICSRD, + .name = "vicsrd", + .bpmp_id = TEGRA_ICC_BPMP_VIC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_VIC, + .regs = { + .sid = { + .override = 0x360, + .security = 0x364, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_VICSWR, + .name = "vicswr", + .bpmp_id = TEGRA_ICC_BPMP_VIC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_VIC, + .regs = { + .sid = { + .override = 0x368, + .security = 0x36c, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_DLA1RDB1, .name = "dla0rdb1", @@ -401,6 +449,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x38c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVDECSRD, + .name = "nvdecsrd", + .bpmp_id = TEGRA_ICC_BPMP_NVDEC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVDEC, + .regs = { + .sid = { + .override = 0x3c0, + .security = 0x3c4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVDECSWR, + .name = "nvdecswr", + .bpmp_id = TEGRA_ICC_BPMP_NVDEC, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVDEC, + .regs = { + .sid = { + .override = 0x3c8, + .security = 0x3cc, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_APER, .name = "aper", @@ -437,6 +509,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x3e4, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVJPGSRD, + .name = "nvjpgsrd", + .bpmp_id = TEGRA_ICC_BPMP_NVJPG_0, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVJPG, + .regs = { + .sid = { + .override = 0x3f0, + .security = 0x3f4, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVJPGSWR, + .name = "nvjpgswr", + .bpmp_id = TEGRA_ICC_BPMP_NVJPG_0, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVJPG, + .regs = { + .sid = { + .override = 0x3f8, + .security = 0x3fc, + }, + }, }, { .id = TEGRA234_MEMORY_CLIENT_NVDISPLAYR, .name = "nvdisplayr", @@ -781,6 +877,30 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .security = 0x77c, }, }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVJPG1SRD, + .name = "nvjpg1srd", + .bpmp_id = TEGRA_ICC_BPMP_NVJPG_1, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVJPG1, + .regs = { + .sid = { + .override = 0x918, + .security = 0x91c, + }, + }, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVJPG1SWR, + .name = "nvjpg1swr", + .bpmp_id = TEGRA_ICC_BPMP_NVJPG_1, + .type = TEGRA_ICC_NISO, + .sid = TEGRA234_SID_NVJPG1, + .regs = { + .sid = { + .override = 0x920, + .security = 0x924, + }, + }, }, { .id = TEGRA_ICC_MC_CPU_CLUSTER0, .name = "sw_cluster0", From 0a7e4578567a3270ba35ebde4e0ce2795fa55384 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Wed, 21 Jun 2023 19:13:59 +0530 Subject: [PATCH 047/136] memory: tegra: add check if MRQ_EMC_DVFS_LATENCY is supported Add check to ensure that "MRQ_EMC_DVFS_LATENCY" is supported by the BPMP-FW before making the MRQ request. Currently, if the BPMP-FW doesn't support this MRQ, then the "tegra186_emc_probe" fails. Due to this the Memory Interconnect initialization also doesn't happen. Memory Interconnect is not dependent on this MRQ and can initialize even when this MRQ is not supported in any platform. The check ensures that the MRQ is called only when it is supported by the BPMP-FW and Interconnect initializes independent of this MRQ. Also, moved the code to new function for better readability. Signed-off-by: Sumit Gupta Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20230621134400.23070-4-sumitg@nvidia.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra186-emc.c | 136 +++++++++++++++------------- 1 file changed, 71 insertions(+), 65 deletions(-) diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c index 6ad8a4023dd7..83981ae3ea86 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -155,6 +155,73 @@ DEFINE_DEBUGFS_ATTRIBUTE(tegra186_emc_debug_max_rate_fops, tegra186_emc_debug_max_rate_get, tegra186_emc_debug_max_rate_set, "%llu\n"); +static int tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc *emc) +{ + struct mrq_emc_dvfs_latency_response response; + struct tegra_bpmp_message msg; + unsigned int i; + int err; + + memset(&msg, 0, sizeof(msg)); + msg.mrq = MRQ_EMC_DVFS_LATENCY; + msg.tx.data = NULL; + msg.tx.size = 0; + msg.rx.data = &response; + msg.rx.size = sizeof(response); + + err = tegra_bpmp_transfer(emc->bpmp, &msg); + if (err < 0) { + dev_err(emc->dev, "failed to EMC DVFS pairs: %d\n", err); + return err; + } + if (msg.rx.ret < 0) { + dev_err(emc->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret); + return -EINVAL; + } + + emc->debugfs.min_rate = ULONG_MAX; + emc->debugfs.max_rate = 0; + + emc->num_dvfs = response.num_pairs; + + emc->dvfs = devm_kmalloc_array(emc->dev, emc->num_dvfs, sizeof(*emc->dvfs), GFP_KERNEL); + if (!emc->dvfs) + return -ENOMEM; + + dev_dbg(emc->dev, "%u DVFS pairs:\n", emc->num_dvfs); + + for (i = 0; i < emc->num_dvfs; i++) { + emc->dvfs[i].rate = response.pairs[i].freq * 1000; + emc->dvfs[i].latency = response.pairs[i].latency; + + if (emc->dvfs[i].rate < emc->debugfs.min_rate) + emc->debugfs.min_rate = emc->dvfs[i].rate; + + if (emc->dvfs[i].rate > emc->debugfs.max_rate) + emc->debugfs.max_rate = emc->dvfs[i].rate; + + dev_dbg(emc->dev, " %2u: %lu Hz -> %lu us\n", i, + emc->dvfs[i].rate, emc->dvfs[i].latency); + } + + err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, emc->debugfs.max_rate); + if (err < 0) { + dev_err(emc->dev, "failed to set rate range [%lu-%lu] for %pC\n", + emc->debugfs.min_rate, emc->debugfs.max_rate, emc->clk); + return err; + } + + emc->debugfs.root = debugfs_create_dir("emc", NULL); + debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, + emc, &tegra186_emc_debug_available_rates_fops); + debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, + emc, &tegra186_emc_debug_min_rate_fops); + debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, + emc, &tegra186_emc_debug_max_rate_fops); + + return 0; +} + /* * tegra_emc_icc_set_bw() - Set BW api for EMC provider * @src: ICC node for External Memory Controller (EMC) @@ -251,10 +318,7 @@ err_msg: static int tegra186_emc_probe(struct platform_device *pdev) { struct tegra_mc *mc = dev_get_drvdata(pdev->dev.parent); - struct mrq_emc_dvfs_latency_response response; - struct tegra_bpmp_message msg; struct tegra186_emc *emc; - unsigned int i; int err; emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); @@ -275,69 +339,11 @@ static int tegra186_emc_probe(struct platform_device *pdev) platform_set_drvdata(pdev, emc); emc->dev = &pdev->dev; - memset(&msg, 0, sizeof(msg)); - msg.mrq = MRQ_EMC_DVFS_LATENCY; - msg.tx.data = NULL; - msg.tx.size = 0; - msg.rx.data = &response; - msg.rx.size = sizeof(response); - - err = tegra_bpmp_transfer(emc->bpmp, &msg); - if (err < 0) { - dev_err(&pdev->dev, "failed to EMC DVFS pairs: %d\n", err); - goto put_bpmp; + if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_EMC_DVFS_LATENCY)) { + err = tegra186_emc_get_emc_dvfs_latency(emc); + if (err) + goto put_bpmp; } - if (msg.rx.ret < 0) { - err = -EINVAL; - dev_err(&pdev->dev, "EMC DVFS MRQ failed: %d (BPMP error code)\n", msg.rx.ret); - goto put_bpmp; - } - - emc->debugfs.min_rate = ULONG_MAX; - emc->debugfs.max_rate = 0; - - emc->num_dvfs = response.num_pairs; - - emc->dvfs = devm_kmalloc_array(&pdev->dev, emc->num_dvfs, - sizeof(*emc->dvfs), GFP_KERNEL); - if (!emc->dvfs) { - err = -ENOMEM; - goto put_bpmp; - } - - dev_dbg(&pdev->dev, "%u DVFS pairs:\n", emc->num_dvfs); - - for (i = 0; i < emc->num_dvfs; i++) { - emc->dvfs[i].rate = response.pairs[i].freq * 1000; - emc->dvfs[i].latency = response.pairs[i].latency; - - if (emc->dvfs[i].rate < emc->debugfs.min_rate) - emc->debugfs.min_rate = emc->dvfs[i].rate; - - if (emc->dvfs[i].rate > emc->debugfs.max_rate) - emc->debugfs.max_rate = emc->dvfs[i].rate; - - dev_dbg(&pdev->dev, " %2u: %lu Hz -> %lu us\n", i, - emc->dvfs[i].rate, emc->dvfs[i].latency); - } - - err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, - emc->debugfs.max_rate); - if (err < 0) { - dev_err(&pdev->dev, - "failed to set rate range [%lu-%lu] for %pC\n", - emc->debugfs.min_rate, emc->debugfs.max_rate, - emc->clk); - goto put_bpmp; - } - - emc->debugfs.root = debugfs_create_dir("emc", NULL); - debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, - emc, &tegra186_emc_debug_available_rates_fops); - debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, - emc, &tegra186_emc_debug_min_rate_fops); - debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, - emc, &tegra186_emc_debug_max_rate_fops); if (mc && mc->soc->icc_ops) { if (tegra_bpmp_mrq_is_supported(emc->bpmp, MRQ_BWMGR_INT)) { From 6e1547f9873b0cea840625081ee4e5d7dd26661a Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Fri, 14 Jul 2023 17:01:16 +0200 Subject: [PATCH 048/136] memory: tegra: Prefer octal over symbolic permissions checkpatch recommends using octal permissions instead of symbolic permissions. Switch the debugfs files to use the former to silence these warnings. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20230714150116.2823766-1-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra186-emc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/memory/tegra/tegra186-emc.c b/drivers/memory/tegra/tegra186-emc.c index 83981ae3ea86..4007f4e16d74 100644 --- a/drivers/memory/tegra/tegra186-emc.c +++ b/drivers/memory/tegra/tegra186-emc.c @@ -212,12 +212,12 @@ static int tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc *emc) } emc->debugfs.root = debugfs_create_dir("emc", NULL); - debugfs_create_file("available_rates", S_IRUGO, emc->debugfs.root, - emc, &tegra186_emc_debug_available_rates_fops); - debugfs_create_file("min_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, - emc, &tegra186_emc_debug_min_rate_fops); - debugfs_create_file("max_rate", S_IRUGO | S_IWUSR, emc->debugfs.root, - emc, &tegra186_emc_debug_max_rate_fops); + debugfs_create_file("available_rates", 0444, emc->debugfs.root, emc, + &tegra186_emc_debug_available_rates_fops); + debugfs_create_file("min_rate", 0644, emc->debugfs.root, emc, + &tegra186_emc_debug_min_rate_fops); + debugfs_create_file("max_rate", 0644, emc->debugfs.root, emc, + &tegra186_emc_debug_max_rate_fops); return 0; } From 0b4838717fff5e24d97742e79ba1ee46cbfbf4b6 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 14 Jul 2023 11:47:16 -0600 Subject: [PATCH 049/136] memory: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230714174717.4059518-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski --- drivers/memory/brcmstb_dpfe.c | 3 +-- drivers/memory/da8xx-ddrctl.c | 1 - drivers/memory/fsl_ifc.c | 2 +- drivers/memory/jz4780-nemc.c | 1 - drivers/memory/pl353-smc.c | 1 + drivers/memory/renesas-rpc-if.c | 1 - drivers/memory/samsung/exynos5422-dmc.c | 2 +- drivers/memory/stm32-fmc2-ebi.c | 2 ++ drivers/memory/tegra/mc.c | 2 +- drivers/memory/tegra/tegra124.c | 2 +- drivers/memory/tegra/tegra186.c | 3 ++- drivers/memory/tegra/tegra20.c | 3 ++- drivers/memory/tegra/tegra210-emc-core.c | 4 ++-- drivers/memory/tegra/tegra30-emc.c | 2 +- drivers/memory/tegra/tegra30.c | 2 +- 15 files changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/memory/brcmstb_dpfe.c b/drivers/memory/brcmstb_dpfe.c index 9339f80b21c5..a7ab3d377206 100644 --- a/drivers/memory/brcmstb_dpfe.c +++ b/drivers/memory/brcmstb_dpfe.c @@ -32,8 +32,7 @@ #include #include #include -#include -#include +#include #include #define DRVNAME "brcmstb-dpfe" diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c index 0ef8cc878b95..2bf34da85d22 100644 --- a/drivers/memory/da8xx-ddrctl.c +++ b/drivers/memory/da8xx-ddrctl.c @@ -10,7 +10,6 @@ #include #include -#include #include #include diff --git a/drivers/memory/fsl_ifc.c b/drivers/memory/fsl_ifc.c index 9e8d8e9c5ad8..2509e5152036 100644 --- a/drivers/memory/fsl_ifc.c +++ b/drivers/memory/fsl_ifc.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/memory/jz4780-nemc.c b/drivers/memory/jz4780-nemc.c index 555f7ac3b7dd..e5a93e7da15f 100644 --- a/drivers/memory/jz4780-nemc.c +++ b/drivers/memory/jz4780-nemc.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/memory/pl353-smc.c b/drivers/memory/pl353-smc.c index d39ee7d06665..48540817e046 100644 --- a/drivers/memory/pl353-smc.c +++ b/drivers/memory/pl353-smc.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index 75fcba45ec1b..9695b2d3ae59 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include diff --git a/drivers/memory/samsung/exynos5422-dmc.c b/drivers/memory/samsung/exynos5422-dmc.c index c491cd549644..6d019dbd721c 100644 --- a/drivers/memory/samsung/exynos5422-dmc.c +++ b/drivers/memory/samsung/exynos5422-dmc.c @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/memory/stm32-fmc2-ebi.c b/drivers/memory/stm32-fmc2-ebi.c index ffec26a99313..9015e8277dc8 100644 --- a/drivers/memory/stm32-fmc2-ebi.c +++ b/drivers/memory/stm32-fmc2-ebi.c @@ -7,8 +7,10 @@ #include #include #include +#include #include #include +#include #include #include diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c index deb6e65b59af..67d6e70b4eab 100644 --- a/drivers/memory/tegra/mc.c +++ b/drivers/memory/tegra/mc.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/memory/tegra/tegra124.c b/drivers/memory/tegra/tegra124.c index d780a84241fe..470b7dbab2c2 100644 --- a/drivers/memory/tegra/tegra124.c +++ b/drivers/memory/tegra/tegra124.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c index 7bb73f06fad3..533f85a4b2bd 100644 --- a/drivers/memory/tegra/tegra186.c +++ b/drivers/memory/tegra/tegra186.c @@ -7,7 +7,8 @@ #include #include #include -#include +#include +#include #include #include diff --git a/drivers/memory/tegra/tegra20.c b/drivers/memory/tegra/tegra20.c index fcd7738fcb53..544bfd216a22 100644 --- a/drivers/memory/tegra/tegra20.c +++ b/drivers/memory/tegra/tegra20.c @@ -5,8 +5,9 @@ #include #include +#include #include -#include +#include #include #include diff --git a/drivers/memory/tegra/tegra210-emc-core.c b/drivers/memory/tegra/tegra210-emc-core.c index ae5f982f861b..3300bde47c13 100644 --- a/drivers/memory/tegra/tegra210-emc-core.c +++ b/drivers/memory/tegra/tegra210-emc-core.c @@ -9,10 +9,10 @@ #include #include #include +#include #include -#include -#include #include +#include #include #include #include diff --git a/drivers/memory/tegra/tegra30-emc.c b/drivers/memory/tegra/tegra30-emc.c index c91e9b7e2e01..9eae25c57ec6 100644 --- a/drivers/memory/tegra/tegra30-emc.c +++ b/drivers/memory/tegra/tegra30-emc.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/memory/tegra/tegra30.c b/drivers/memory/tegra/tegra30.c index 84316357513d..06f8b35e0a14 100644 --- a/drivers/memory/tegra/tegra30.c +++ b/drivers/memory/tegra/tegra30.c @@ -3,8 +3,8 @@ * Copyright (C) 2014 NVIDIA CORPORATION. All rights reserved. */ +#include #include -#include #include #include From eb6bb73f5762cd4eb1eadc42a357f8f13b0f37ef Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 13 Jul 2023 17:28:46 +0200 Subject: [PATCH 050/136] dt-bindings: memory-controllers: ingenic,nemc: reference peripheral properties Ingenic NAND / External Memory Controller has children with peripheral properties, so it should reference the Memory Controller bus Peripheral-specific schema. Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230713152848.82752-2-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../devicetree/bindings/memory-controllers/ingenic,nemc.yaml | 1 + .../bindings/memory-controllers/mc-peripheral-props.yaml | 1 + 2 files changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml b/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml index a02724221ff3..b40cec0eb651 100644 --- a/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/ingenic,nemc.yaml @@ -39,6 +39,7 @@ properties: patternProperties: ".*@[0-9]+$": type: object + $ref: mc-peripheral-props.yaml# required: - compatible diff --git a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml index 5acfcad12bb7..5ff8cc26962a 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml @@ -34,6 +34,7 @@ required: # The controller specific properties go here. allOf: - $ref: st,stm32-fmc2-ebi-props.yaml# + - $ref: ingenic,nemc-peripherals.yaml# - $ref: intel,ixp4xx-expansion-peripheral-props.yaml# additionalProperties: true From a98dcaaa019996e52244feee54a043ddfb4050cd Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 13 Jul 2023 17:28:47 +0200 Subject: [PATCH 051/136] dt-bindings: memory-controllers: reference TI GPMC peripheral properties Reference the Texas Instruments GPMC Bus Child Nodes schema with peripheral properties, in common Memory Controller bus Peripheral-specific schema, to allow properly validate devices like davicom,dm9000. Acked-by: Conor Dooley Link: https://lore.kernel.org/r/20230713152848.82752-3-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/memory-controllers/mc-peripheral-props.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml index 5ff8cc26962a..8d9dae15ade0 100644 --- a/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/mc-peripheral-props.yaml @@ -36,5 +36,6 @@ allOf: - $ref: st,stm32-fmc2-ebi-props.yaml# - $ref: ingenic,nemc-peripherals.yaml# - $ref: intel,ixp4xx-expansion-peripheral-props.yaml# + - $ref: ti,gpmc-child.yaml# additionalProperties: true From f7812cdabb82b2b143bba7cb1736889cd56d2092 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Thu, 13 Jul 2023 17:28:48 +0200 Subject: [PATCH 052/136] dt-bindings: net: davicom,dm9000: convert to DT schema Convert the Davicom DM9000 Fast Ethernet Controller bindings to DT schema. Reviewed-by: Conor Dooley Link: https://lore.kernel.org/r/20230713152848.82752-4-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- .../bindings/net/davicom,dm9000.yaml | 59 +++++++++++++++++++ .../bindings/net/davicom-dm9000.txt | 27 --------- 2 files changed, 59 insertions(+), 27 deletions(-) create mode 100644 Documentation/devicetree/bindings/net/davicom,dm9000.yaml delete mode 100644 Documentation/devicetree/bindings/net/davicom-dm9000.txt diff --git a/Documentation/devicetree/bindings/net/davicom,dm9000.yaml b/Documentation/devicetree/bindings/net/davicom,dm9000.yaml new file mode 100644 index 000000000000..66a7c6eec767 --- /dev/null +++ b/Documentation/devicetree/bindings/net/davicom,dm9000.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/davicom,dm9000.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Davicom DM9000 Fast Ethernet Controller + +maintainers: + - Paul Cercueil + +properties: + compatible: + const: davicom,dm9000 + + reg: + items: + - description: Address registers + - description: Data registers + + interrupts: + maxItems: 1 + + davicom,no-eeprom: + type: boolean + description: Configuration EEPROM is not available + + davicom,ext-phy: + type: boolean + description: Use external PHY + + reset-gpios: + maxItems: 1 + + vcc-supply: true + +required: + - compatible + - reg + - interrupts + +allOf: + - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml# + - $ref: /schemas/net/ethernet-controller.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + ethernet@a8000000 { + compatible = "davicom,dm9000"; + reg = <0xa8000000 0x2>, <0xa8000002 0x2>; + interrupt-parent = <&gph1>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; + local-mac-address = [00 00 de ad be ef]; + davicom,no-eeprom; + }; diff --git a/Documentation/devicetree/bindings/net/davicom-dm9000.txt b/Documentation/devicetree/bindings/net/davicom-dm9000.txt deleted file mode 100644 index 64c159e9cbf7..000000000000 --- a/Documentation/devicetree/bindings/net/davicom-dm9000.txt +++ /dev/null @@ -1,27 +0,0 @@ -Davicom DM9000 Fast Ethernet controller - -Required properties: -- compatible = "davicom,dm9000"; -- reg : physical addresses and sizes of registers, must contain 2 entries: - first entry : address register, - second entry : data register. -- interrupts : interrupt specifier specific to interrupt controller - -Optional properties: -- davicom,no-eeprom : Configuration EEPROM is not available -- davicom,ext-phy : Use external PHY -- reset-gpios : phandle of gpio that will be used to reset chip during probe -- vcc-supply : phandle of regulator that will be used to enable power to chip - -Example: - - ethernet@18000000 { - compatible = "davicom,dm9000"; - reg = <0x18000000 0x2 0x18000004 0x2>; - interrupt-parent = <&gpn>; - interrupts = <7 4>; - local-mac-address = [00 00 de ad be ef]; - davicom,no-eeprom; - reset-gpios = <&gpf 12 GPIO_ACTIVE_LOW>; - vcc-supply = <ð0_power>; - }; From 2f17bea81aff53155689de776e52328f82bf603c Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Mon, 24 Jul 2023 11:01:09 +0200 Subject: [PATCH 053/136] dt-bindings: arm: msm: kpss-acc: Revert "dt-bindings: arm: msm: kpss-acc: Make the optional reg truly optional" This reverts commit 981be238e1d28e156aa9da2a8722f86f02fd0453 because it was totally bogus and duplicated existing minItems: ruamel.yaml.constructor.DuplicateKeyError: while constructing a mapping Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml: ignoring, error parsing file Signed-off-by: Krzysztof Kozlowski Acked-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230724090109.19489-1-krzysztof.kozlowski@linaro.org Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml b/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml index facaafefb441..202a5d51ee88 100644 --- a/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml +++ b/Documentation/devicetree/bindings/power/qcom,kpss-acc-v2.yaml @@ -21,7 +21,6 @@ properties: const: qcom,kpss-acc-v2 reg: - minItems: 1 items: - description: Base address and size of the register region - description: Optional base address and size of the alias register region From ac60f06215fda9ea10ac0b2a3bc3a1e7ba4a8fd1 Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Thu, 27 Jul 2023 16:32:46 +0200 Subject: [PATCH 054/136] soc/tegra: fuse: Sort includes alphabetically The includes were slightly out of order, so sort them correctly. Signed-off-by: Thierry Reding --- drivers/soc/tegra/fuse/tegra-apbmisc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/fuse/tegra-apbmisc.c b/drivers/soc/tegra/fuse/tegra-apbmisc.c index eb0a1d924526..da970f3dbf35 100644 --- a/drivers/soc/tegra/fuse/tegra-apbmisc.c +++ b/drivers/soc/tegra/fuse/tegra-apbmisc.c @@ -4,13 +4,13 @@ */ #include +#include #include #include #include -#include -#include #include +#include #include "fuse.h" From 10f975f8b0e8e563bf1e5c2f5e4ebada29fa7edc Mon Sep 17 00:00:00 2001 From: Jiapeng Chong Date: Sat, 6 May 2023 17:07:35 +0800 Subject: [PATCH 055/136] soc/tegra: cbb: Remove unnecessary print function dev_err() The print function dev_err() is redundant because platform_get_irq() already prints an error. ./drivers/soc/tegra/cbb/tegra-cbb.c:130:3-10: line 130 is redundant because platform_get_irq() already prints an error. ./drivers/soc/tegra/cbb/tegra-cbb.c:140:2-9: line 140 is redundant because platform_get_irq() already prints an error. Reported-by: Abaci Robot Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4879 Signed-off-by: Jiapeng Chong Signed-off-by: Thierry Reding --- drivers/soc/tegra/cbb/tegra-cbb.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/soc/tegra/cbb/tegra-cbb.c b/drivers/soc/tegra/cbb/tegra-cbb.c index be76c6aa131c..84ab46c9d9f5 100644 --- a/drivers/soc/tegra/cbb/tegra-cbb.c +++ b/drivers/soc/tegra/cbb/tegra-cbb.c @@ -122,20 +122,16 @@ int tegra_cbb_get_irq(struct platform_device *pdev, unsigned int *nonsec_irq, if (num_intr == 2) { irq = platform_get_irq(pdev, index); - if (irq <= 0) { - dev_err(&pdev->dev, "failed to get non-secure IRQ: %d\n", irq); + if (irq <= 0) return -ENOENT; - } *nonsec_irq = irq; index++; } irq = platform_get_irq(pdev, index); - if (irq <= 0) { - dev_err(&pdev->dev, "failed to get secure IRQ: %d\n", irq); + if (irq <= 0) return -ENOENT; - } *sec_irq = irq; From 2784e3b0cc028f5f996e7b86ea6fbaf13b5f23d8 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Thu, 27 Jul 2023 17:42:48 -0700 Subject: [PATCH 056/136] firmware: qcom_scm: Convert all symbols to EXPORT_SYMBOL_GPL The `qcom_scm` module is GPL v2-licenced and so there is no reason why the APIs it exports should not be, too. Signed-off-by: Guru Das Srinagesh Reviewed-by: Trilok Soni Link: https://lore.kernel.org/r/19d9ac0bf79f957574ef9b3b73246ea0113cc0fd.1690503893.git.quic_gurus@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/firmware/qcom_scm.c | 66 ++++++++++++++++++------------------- 1 file changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index b6055b1c18d8..06fe8aca870d 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -347,7 +347,7 @@ int qcom_scm_set_warm_boot_addr(void *entry) return qcom_scm_set_boot_addr(entry, qcom_scm_cpu_warm_bits); return 0; } -EXPORT_SYMBOL(qcom_scm_set_warm_boot_addr); +EXPORT_SYMBOL_GPL(qcom_scm_set_warm_boot_addr); /** * qcom_scm_set_cold_boot_addr() - Set the cold boot address for all cpus @@ -360,7 +360,7 @@ int qcom_scm_set_cold_boot_addr(void *entry) return qcom_scm_set_boot_addr(entry, qcom_scm_cpu_cold_bits); return 0; } -EXPORT_SYMBOL(qcom_scm_set_cold_boot_addr); +EXPORT_SYMBOL_GPL(qcom_scm_set_cold_boot_addr); /** * qcom_scm_cpu_power_down() - Power down the cpu @@ -382,7 +382,7 @@ void qcom_scm_cpu_power_down(u32 flags) qcom_scm_call_atomic(__scm ? __scm->dev : NULL, &desc, NULL); } -EXPORT_SYMBOL(qcom_scm_cpu_power_down); +EXPORT_SYMBOL_GPL(qcom_scm_cpu_power_down); int qcom_scm_set_remote_state(u32 state, u32 id) { @@ -401,7 +401,7 @@ int qcom_scm_set_remote_state(u32 state, u32 id) return ret ? : res.result[0]; } -EXPORT_SYMBOL(qcom_scm_set_remote_state); +EXPORT_SYMBOL_GPL(qcom_scm_set_remote_state); static int __qcom_scm_set_dload_mode(struct device *dev, bool enable) { @@ -511,7 +511,7 @@ out: return ret ? : res.result[0]; } -EXPORT_SYMBOL(qcom_scm_pas_init_image); +EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image); /** * qcom_scm_pas_metadata_release() - release metadata context @@ -528,7 +528,7 @@ void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx) ctx->phys = 0; ctx->size = 0; } -EXPORT_SYMBOL(qcom_scm_pas_metadata_release); +EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release); /** * qcom_scm_pas_mem_setup() - Prepare the memory related to a given peripheral @@ -567,7 +567,7 @@ int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size) return ret ? : res.result[0]; } -EXPORT_SYMBOL(qcom_scm_pas_mem_setup); +EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup); /** * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmware @@ -602,7 +602,7 @@ int qcom_scm_pas_auth_and_reset(u32 peripheral) return ret ? : res.result[0]; } -EXPORT_SYMBOL(qcom_scm_pas_auth_and_reset); +EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset); /** * qcom_scm_pas_shutdown() - Shut down the remote processor @@ -637,7 +637,7 @@ int qcom_scm_pas_shutdown(u32 peripheral) return ret ? : res.result[0]; } -EXPORT_SYMBOL(qcom_scm_pas_shutdown); +EXPORT_SYMBOL_GPL(qcom_scm_pas_shutdown); /** * qcom_scm_pas_supported() - Check if the peripheral authentication service is @@ -666,7 +666,7 @@ bool qcom_scm_pas_supported(u32 peripheral) return ret ? false : !!res.result[0]; } -EXPORT_SYMBOL(qcom_scm_pas_supported); +EXPORT_SYMBOL_GPL(qcom_scm_pas_supported); static int __qcom_scm_pas_mss_reset(struct device *dev, bool reset) { @@ -728,7 +728,7 @@ int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val) return ret < 0 ? ret : 0; } -EXPORT_SYMBOL(qcom_scm_io_readl); +EXPORT_SYMBOL_GPL(qcom_scm_io_readl); int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) { @@ -743,7 +743,7 @@ int qcom_scm_io_writel(phys_addr_t addr, unsigned int val) return qcom_scm_call_atomic(__scm->dev, &desc, NULL); } -EXPORT_SYMBOL(qcom_scm_io_writel); +EXPORT_SYMBOL_GPL(qcom_scm_io_writel); /** * qcom_scm_restore_sec_cfg_available() - Check if secure environment @@ -756,7 +756,7 @@ bool qcom_scm_restore_sec_cfg_available(void) return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_MP, QCOM_SCM_MP_RESTORE_SEC_CFG); } -EXPORT_SYMBOL(qcom_scm_restore_sec_cfg_available); +EXPORT_SYMBOL_GPL(qcom_scm_restore_sec_cfg_available); int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { @@ -775,7 +775,7 @@ int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) return ret ? : res.result[0]; } -EXPORT_SYMBOL(qcom_scm_restore_sec_cfg); +EXPORT_SYMBOL_GPL(qcom_scm_restore_sec_cfg); int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { @@ -796,7 +796,7 @@ int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) return ret ? : res.result[1]; } -EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_size); +EXPORT_SYMBOL_GPL(qcom_scm_iommu_secure_ptbl_size); int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { @@ -820,7 +820,7 @@ int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) return ret; } -EXPORT_SYMBOL(qcom_scm_iommu_secure_ptbl_init); +EXPORT_SYMBOL_GPL(qcom_scm_iommu_secure_ptbl_init); int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size) { @@ -835,7 +835,7 @@ int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size) return qcom_scm_call(__scm->dev, &desc, NULL); } -EXPORT_SYMBOL(qcom_scm_iommu_set_cp_pool_size); +EXPORT_SYMBOL_GPL(qcom_scm_iommu_set_cp_pool_size); int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, u32 cp_nonpixel_start, @@ -859,7 +859,7 @@ int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, return ret ? : res.result[0]; } -EXPORT_SYMBOL(qcom_scm_mem_protect_video_var); +EXPORT_SYMBOL_GPL(qcom_scm_mem_protect_video_var); static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, size_t mem_sz, phys_addr_t src, size_t src_sz, @@ -968,7 +968,7 @@ int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, *srcvm = next_vm; return 0; } -EXPORT_SYMBOL(qcom_scm_assign_mem); +EXPORT_SYMBOL_GPL(qcom_scm_assign_mem); /** * qcom_scm_ocmem_lock_available() - is OCMEM lock/unlock interface available @@ -978,7 +978,7 @@ bool qcom_scm_ocmem_lock_available(void) return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_OCMEM, QCOM_SCM_OCMEM_LOCK_CMD); } -EXPORT_SYMBOL(qcom_scm_ocmem_lock_available); +EXPORT_SYMBOL_GPL(qcom_scm_ocmem_lock_available); /** * qcom_scm_ocmem_lock() - call OCMEM lock interface to assign an OCMEM @@ -1004,7 +1004,7 @@ int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size, return qcom_scm_call(__scm->dev, &desc, NULL); } -EXPORT_SYMBOL(qcom_scm_ocmem_lock); +EXPORT_SYMBOL_GPL(qcom_scm_ocmem_lock); /** * qcom_scm_ocmem_unlock() - call OCMEM unlock interface to release an OCMEM @@ -1027,7 +1027,7 @@ int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size) return qcom_scm_call(__scm->dev, &desc, NULL); } -EXPORT_SYMBOL(qcom_scm_ocmem_unlock); +EXPORT_SYMBOL_GPL(qcom_scm_ocmem_unlock); /** * qcom_scm_ice_available() - Is the ICE key programming interface available? @@ -1042,7 +1042,7 @@ bool qcom_scm_ice_available(void) __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_ES, QCOM_SCM_ES_CONFIG_SET_ICE_KEY); } -EXPORT_SYMBOL(qcom_scm_ice_available); +EXPORT_SYMBOL_GPL(qcom_scm_ice_available); /** * qcom_scm_ice_invalidate_key() - Invalidate an inline encryption key @@ -1068,7 +1068,7 @@ int qcom_scm_ice_invalidate_key(u32 index) return qcom_scm_call(__scm->dev, &desc, NULL); } -EXPORT_SYMBOL(qcom_scm_ice_invalidate_key); +EXPORT_SYMBOL_GPL(qcom_scm_ice_invalidate_key); /** * qcom_scm_ice_set_key() - Set an inline encryption key @@ -1134,7 +1134,7 @@ int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size, dma_free_coherent(__scm->dev, key_size, keybuf, key_phys); return ret; } -EXPORT_SYMBOL(qcom_scm_ice_set_key); +EXPORT_SYMBOL_GPL(qcom_scm_ice_set_key); /** * qcom_scm_hdcp_available() - Check if secure environment supports HDCP. @@ -1156,7 +1156,7 @@ bool qcom_scm_hdcp_available(void) return avail; } -EXPORT_SYMBOL(qcom_scm_hdcp_available); +EXPORT_SYMBOL_GPL(qcom_scm_hdcp_available); /** * qcom_scm_hdcp_req() - Send HDCP request. @@ -1203,7 +1203,7 @@ int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp) return ret; } -EXPORT_SYMBOL(qcom_scm_hdcp_req); +EXPORT_SYMBOL_GPL(qcom_scm_hdcp_req); int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt) { @@ -1219,7 +1219,7 @@ int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt) return qcom_scm_call(__scm->dev, &desc, NULL); } -EXPORT_SYMBOL(qcom_scm_iommu_set_pt_format); +EXPORT_SYMBOL_GPL(qcom_scm_iommu_set_pt_format); int qcom_scm_qsmmu500_wait_safe_toggle(bool en) { @@ -1235,13 +1235,13 @@ int qcom_scm_qsmmu500_wait_safe_toggle(bool en) return qcom_scm_call_atomic(__scm->dev, &desc, NULL); } -EXPORT_SYMBOL(qcom_scm_qsmmu500_wait_safe_toggle); +EXPORT_SYMBOL_GPL(qcom_scm_qsmmu500_wait_safe_toggle); bool qcom_scm_lmh_dcvsh_available(void) { return __qcom_scm_is_call_available(__scm->dev, QCOM_SCM_SVC_LMH, QCOM_SCM_LMH_LIMIT_DCVSH); } -EXPORT_SYMBOL(qcom_scm_lmh_dcvsh_available); +EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh_available); int qcom_scm_lmh_profile_change(u32 profile_id) { @@ -1255,7 +1255,7 @@ int qcom_scm_lmh_profile_change(u32 profile_id) return qcom_scm_call(__scm->dev, &desc, NULL); } -EXPORT_SYMBOL(qcom_scm_lmh_profile_change); +EXPORT_SYMBOL_GPL(qcom_scm_lmh_profile_change); int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, u64 limit_node, u32 node_id, u64 version) @@ -1293,7 +1293,7 @@ int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, dma_free_coherent(__scm->dev, payload_size, payload_buf, payload_phys); return ret; } -EXPORT_SYMBOL(qcom_scm_lmh_dcvsh); +EXPORT_SYMBOL_GPL(qcom_scm_lmh_dcvsh); static int qcom_scm_find_dload_address(struct device *dev, u64 *addr) { @@ -1328,7 +1328,7 @@ bool qcom_scm_is_available(void) { return !!__scm; } -EXPORT_SYMBOL(qcom_scm_is_available); +EXPORT_SYMBOL_GPL(qcom_scm_is_available); static int qcom_scm_assert_valid_wq_ctx(u32 wq_ctx) { From d5d9bca2219d78c652d340079945f0f2071e1219 Mon Sep 17 00:00:00 2001 From: Guru Das Srinagesh Date: Thu, 27 Jul 2023 17:42:49 -0700 Subject: [PATCH 057/136] firmware: qcom_scm: Add missing extern specifier Commit 3a99f121fe0b ("firmware: qcom: scm: Introduce pas_metadata context") left out the `extern` specifier for the API it introduced, so add it. Signed-off-by: Guru Das Srinagesh Link: https://lore.kernel.org/r/bce25c8e215f7cfc7b0780d6965d09f5efe1cc5f.1690503893.git.quic_gurus@quicinc.com Signed-off-by: Bjorn Andersson --- include/linux/firmware/qcom/qcom_scm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h index 250ea4efb7cb..0c091a3f6d49 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -75,7 +75,7 @@ struct qcom_scm_pas_metadata { extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size, struct qcom_scm_pas_metadata *ctx); -void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx); +extern void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx); extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size); extern int qcom_scm_pas_auth_and_reset(u32 peripheral); From eecff3319287179032600eeec5fa357a53ae0fe1 Mon Sep 17 00:00:00 2001 From: Krzysztof Kozlowski Date: Fri, 14 Jul 2023 07:03:13 +0200 Subject: [PATCH 058/136] MAINTAINERS: mfd: Un-support Maxim and Samsung PMIC drivers Since few years no one is really paid to support drivers for: Maxim MUICs/PMICs for Exynos based boards and Samsung PMICs. Correct the status to keep them as maintained. Acked-by: Sebastian Reichel Link: https://lore.kernel.org/r/20230714050313.8424-1-krzysztof.kozlowski@linaro.org Signed-off-by: Krzysztof Kozlowski --- MAINTAINERS | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index ae2f478c0bac..cfd5c6124e6e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12817,7 +12817,7 @@ F: drivers/power/supply/max77976_charger.c MAXIM MUIC CHARGER DRIVERS FOR EXYNOS BASED BOARDS M: Krzysztof Kozlowski L: linux-pm@vger.kernel.org -S: Supported +S: Maintained B: mailto:linux-samsung-soc@vger.kernel.org F: Documentation/devicetree/bindings/power/supply/maxim,max14577.yaml F: Documentation/devicetree/bindings/power/supply/maxim,max77693.yaml @@ -12828,7 +12828,7 @@ MAXIM PMIC AND MUIC DRIVERS FOR EXYNOS BASED BOARDS M: Chanwoo Choi M: Krzysztof Kozlowski L: linux-kernel@vger.kernel.org -S: Supported +S: Maintained B: mailto:linux-samsung-soc@vger.kernel.org F: Documentation/devicetree/bindings/*/maxim,max14577.yaml F: Documentation/devicetree/bindings/*/maxim,max77686.yaml @@ -18777,7 +18777,7 @@ SAMSUNG MULTIFUNCTION PMIC DEVICE DRIVERS M: Krzysztof Kozlowski L: linux-kernel@vger.kernel.org L: linux-samsung-soc@vger.kernel.org -S: Supported +S: Maintained B: mailto:linux-samsung-soc@vger.kernel.org F: Documentation/devicetree/bindings/clock/samsung,s2mps11.yaml F: Documentation/devicetree/bindings/mfd/samsung,s2m*.yaml From bad8a8afe19f43641a15a9540c56f80f1de50f63 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 14 Jul 2023 11:49:37 -0600 Subject: [PATCH 059/136] reset: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Reviewed-by: Damien Le Moal Acked-by: Steen Hegelund Link: https://lore.kernel.org/r/20230714174939.4063667-1-robh@kernel.org Signed-off-by: Philipp Zabel --- drivers/reset/hisilicon/hi6220_reset.c | 1 - drivers/reset/hisilicon/reset-hi3660.c | 2 +- drivers/reset/reset-imx7.c | 2 +- drivers/reset/reset-intel-gw.c | 2 +- drivers/reset/reset-k210.c | 1 - drivers/reset/reset-meson-audio-arb.c | 3 ++- drivers/reset/reset-meson.c | 1 - drivers/reset/reset-microchip-sparx5.c | 3 ++- drivers/reset/reset-mpfs.c | 1 + drivers/reset/reset-qcom-aoss.c | 2 +- drivers/reset/reset-qcom-pdc.c | 2 +- drivers/reset/reset-simple.c | 1 - drivers/reset/reset-uniphier-glue.c | 2 +- drivers/reset/reset-uniphier.c | 1 - drivers/reset/reset-zynqmp.c | 1 - 15 files changed, 11 insertions(+), 14 deletions(-) diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c index 5ca145b64e63..8d1fce18ded7 100644 --- a/drivers/reset/hisilicon/hi6220_reset.c +++ b/drivers/reset/hisilicon/hi6220_reset.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/reset/hisilicon/reset-hi3660.c b/drivers/reset/hisilicon/reset-hi3660.c index 965f5ceba7d8..087f28e326ee 100644 --- a/drivers/reset/hisilicon/reset-hi3660.c +++ b/drivers/reset/hisilicon/reset-hi3660.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/reset/reset-imx7.c b/drivers/reset/reset-imx7.c index d2408725eb2c..dd01fe11c5cb 100644 --- a/drivers/reset/reset-imx7.c +++ b/drivers/reset/reset-imx7.c @@ -9,7 +9,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/reset/reset-intel-gw.c b/drivers/reset/reset-intel-gw.c index effc177db80a..a5a01388ae7f 100644 --- a/drivers/reset/reset-intel-gw.c +++ b/drivers/reset/reset-intel-gw.c @@ -6,7 +6,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/reset/reset-k210.c b/drivers/reset/reset-k210.c index 1b6e03522b40..b62a2fd44e4e 100644 --- a/drivers/reset/reset-k210.c +++ b/drivers/reset/reset-k210.c @@ -3,7 +3,6 @@ * Copyright (c) 2020 Western Digital Corporation or its affiliates. */ #include -#include #include #include #include diff --git a/drivers/reset/reset-meson-audio-arb.c b/drivers/reset/reset-meson-audio-arb.c index 6a3f6a6a3bbf..7e46dbc04998 100644 --- a/drivers/reset/reset-meson-audio-arb.c +++ b/drivers/reset/reset-meson-audio-arb.c @@ -5,7 +5,8 @@ #include #include #include -#include +#include +#include #include #include diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index 13878ca2779d..89ac99789a3c 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -14,7 +14,6 @@ #include #include #include -#include #define BITS_PER_REG 32 diff --git a/drivers/reset/reset-microchip-sparx5.c b/drivers/reset/reset-microchip-sparx5.c index ead25942061d..636e85c388b0 100644 --- a/drivers/reset/reset-microchip-sparx5.c +++ b/drivers/reset/reset-microchip-sparx5.c @@ -7,9 +7,10 @@ * https://github.com/microchip-ung/sparx-5_reginfo */ #include -#include +#include #include #include +#include #include #include diff --git a/drivers/reset/reset-mpfs.c b/drivers/reset/reset-mpfs.c index e71ab73092ab..7f3fb2d472f4 100644 --- a/drivers/reset/reset-mpfs.c +++ b/drivers/reset/reset-mpfs.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/reset/reset-qcom-aoss.c b/drivers/reset/reset-qcom-aoss.c index 9333b923dda0..f52e90e36194 100644 --- a/drivers/reset/reset-qcom-aoss.c +++ b/drivers/reset/reset-qcom-aoss.c @@ -8,7 +8,7 @@ #include #include #include -#include +#include #include struct qcom_aoss_reset_map { diff --git a/drivers/reset/reset-qcom-pdc.c b/drivers/reset/reset-qcom-pdc.c index f22bb49a4ac8..a3aae3f902e6 100644 --- a/drivers/reset/reset-qcom-pdc.c +++ b/drivers/reset/reset-qcom-pdc.c @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include #include diff --git a/drivers/reset/reset-simple.c b/drivers/reset/reset-simple.c index 361a68314265..7ea5adbf2097 100644 --- a/drivers/reset/reset-simple.c +++ b/drivers/reset/reset-simple.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/reset/reset-uniphier-glue.c b/drivers/reset/reset-uniphier-glue.c index 15abac9fc72c..38aa953855aa 100644 --- a/drivers/reset/reset-uniphier-glue.c +++ b/drivers/reset/reset-uniphier-glue.c @@ -6,7 +6,7 @@ #include #include -#include +#include #include #include #include diff --git a/drivers/reset/reset-uniphier.c b/drivers/reset/reset-uniphier.c index ff7580f38056..79c43c204d46 100644 --- a/drivers/reset/reset-uniphier.c +++ b/drivers/reset/reset-uniphier.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c index 59dc0ff9af9e..f0f64ad3472b 100644 --- a/drivers/reset/reset-zynqmp.c +++ b/drivers/reset/reset-zynqmp.c @@ -9,7 +9,6 @@ #include #include #include -#include #define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START) #define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START From 737af37e9c060f6e865090b885c1d6e3fe0f4d40 Mon Sep 17 00:00:00 2001 From: Piyush Mehta Date: Fri, 21 Jul 2023 09:41:18 +0530 Subject: [PATCH 060/136] dt-bindings: reset: Updated binding for Versal-NET reset driver Added dt-binding documentation for Versal NET platforms. Versal Net is a new AMD/Xilinx SoC. The SoC and its architecture is based on the Versal ACAP device. The Versal Net device includes more security features in the platform management controller (PMC) and increases the number of CPUs in the application processing unit (APU) and the real-time processing unit (RPU). Signed-off-by: Piyush Mehta Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230721041119.4058430-2-piyush.mehta@amd.com Signed-off-by: Philipp Zabel --- Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml index 0d50f6a54af3..49db66801429 100644 --- a/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml +++ b/Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.yaml @@ -32,6 +32,7 @@ properties: enum: - xlnx,zynqmp-reset - xlnx,versal-reset + - xlnx,versal-net-reset "#reset-cells": const: 1 From f7cb24e466ee939e70e986e14db8338ab44b177c Mon Sep 17 00:00:00 2001 From: Piyush Mehta Date: Fri, 21 Jul 2023 09:41:19 +0530 Subject: [PATCH 061/136] reset: reset-zynqmp: add support for Versal NET platform Updated the reset driver to support Versal NET platform. As part of adding support for versal NET: - Added Versal NET specific compatible string. - Reset Id and number of resets. Signed-off-by: Piyush Mehta Link: https://lore.kernel.org/r/20230721041119.4058430-3-piyush.mehta@amd.com Signed-off-by: Philipp Zabel --- drivers/reset/reset-zynqmp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c index f0f64ad3472b..72546b4844d5 100644 --- a/drivers/reset/reset-zynqmp.c +++ b/drivers/reset/reset-zynqmp.c @@ -13,6 +13,7 @@ #define ZYNQMP_NR_RESETS (ZYNQMP_PM_RESET_END - ZYNQMP_PM_RESET_START) #define ZYNQMP_RESET_ID ZYNQMP_PM_RESET_START #define VERSAL_NR_RESETS 95 +#define VERSAL_NET_NR_RESETS 176 struct zynqmp_reset_soc_data { u32 reset_id; @@ -87,6 +88,11 @@ static const struct zynqmp_reset_soc_data versal_reset_data = { .num_resets = VERSAL_NR_RESETS, }; +static const struct zynqmp_reset_soc_data versal_net_reset_data = { + .reset_id = 0, + .num_resets = VERSAL_NET_NR_RESETS, +}; + static const struct reset_control_ops zynqmp_reset_ops = { .reset = zynqmp_reset_reset, .assert = zynqmp_reset_assert, @@ -121,6 +127,7 @@ static int zynqmp_reset_probe(struct platform_device *pdev) static const struct of_device_id zynqmp_reset_dt_ids[] = { { .compatible = "xlnx,zynqmp-reset", .data = &zynqmp_reset_data, }, { .compatible = "xlnx,versal-reset", .data = &versal_reset_data, }, + { .compatible = "xlnx,versal-net-reset", .data = &versal_net_reset_data, }, { /* sentinel */ }, }; From 38d09b989721ad14cbbeb82a28c1c6978438bcce Mon Sep 17 00:00:00 2001 From: Wang Ming Date: Wed, 26 Jul 2023 19:45:45 +0800 Subject: [PATCH 062/136] reset: hisilicon: Use dev_err_probe instead of dev_err The probe process may generate EPROBE_DEFER. In this case, dev_err_probe can still record err information. This helps simplify code and standardize error output. Signed-off-by: Wang Ming Link: https://lore.kernel.org/r/20230726114555.5011-1-machel@vivo.com Signed-off-by: Philipp Zabel --- drivers/reset/hisilicon/reset-hi3660.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/reset/hisilicon/reset-hi3660.c b/drivers/reset/hisilicon/reset-hi3660.c index 087f28e326ee..1beb275275ad 100644 --- a/drivers/reset/hisilicon/reset-hi3660.c +++ b/drivers/reset/hisilicon/reset-hi3660.c @@ -90,8 +90,8 @@ static int hi3660_reset_probe(struct platform_device *pdev) "hisi,rst-syscon"); } if (IS_ERR(rc->map)) { - dev_err(dev, "failed to get hisilicon,rst-syscon\n"); - return PTR_ERR(rc->map); + return dev_err_probe(dev, PTR_ERR(rc->map), + "failed to get hisilicon,rst-syscon\n"); } rc->rst.ops = &hi3660_reset_ops, From 57e493aff59529b0ed503ec1540e6125c84f9053 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 26 Jul 2023 17:31:29 -0600 Subject: [PATCH 063/136] soc: bcm: Explicitly include correct DT includes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it was merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230726233130.3811017-1-robh@kernel.org Signed-off-by: Florian Fainelli --- drivers/soc/bcm/bcm63xx/bcm-pmb.c | 1 - drivers/soc/bcm/bcm63xx/bcm63xx-power.c | 1 - drivers/soc/bcm/raspberrypi-power.c | 2 +- 3 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/soc/bcm/bcm63xx/bcm-pmb.c b/drivers/soc/bcm/bcm63xx/bcm-pmb.c index 9407cac47fdb..a72ba26ecf9d 100644 --- a/drivers/soc/bcm/bcm63xx/bcm-pmb.c +++ b/drivers/soc/bcm/bcm63xx/bcm-pmb.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/soc/bcm/bcm63xx/bcm63xx-power.c b/drivers/soc/bcm/bcm63xx/bcm63xx-power.c index aa72e13d5d0e..98b0c2430dbc 100644 --- a/drivers/soc/bcm/bcm63xx/bcm63xx-power.c +++ b/drivers/soc/bcm/bcm63xx/bcm63xx-power.c @@ -14,7 +14,6 @@ #include #include #include -#include struct bcm63xx_power_dev { struct generic_pm_domain genpd; diff --git a/drivers/soc/bcm/raspberrypi-power.c b/drivers/soc/bcm/raspberrypi-power.c index 58175af982a0..06196ebfe03b 100644 --- a/drivers/soc/bcm/raspberrypi-power.c +++ b/drivers/soc/bcm/raspberrypi-power.c @@ -7,7 +7,7 @@ */ #include -#include +#include #include #include #include From 01b76ae654da42c7ee5ffc7347bfafd6b6fd9dd9 Mon Sep 17 00:00:00 2001 From: Yangtao Li Date: Thu, 6 Jul 2023 15:20:36 +0800 Subject: [PATCH 064/136] bus: sunxi-rsb: Convert to devm_platform_ioremap_resource() Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230706072042.31296-1-frank.li@vivo.com Signed-off-by: Jernej Skrabec --- drivers/bus/sunxi-rsb.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/bus/sunxi-rsb.c b/drivers/bus/sunxi-rsb.c index 696c0aefb0ca..2aefd5dde3c9 100644 --- a/drivers/bus/sunxi-rsb.c +++ b/drivers/bus/sunxi-rsb.c @@ -746,7 +746,6 @@ static int sunxi_rsb_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; - struct resource *r; struct sunxi_rsb *rsb; u32 clk_freq = 3000000; int irq, ret; @@ -766,8 +765,7 @@ static int sunxi_rsb_probe(struct platform_device *pdev) rsb->dev = dev; rsb->clk_freq = clk_freq; platform_set_drvdata(pdev, rsb); - r = platform_get_resource(pdev, IORESOURCE_MEM, 0); - rsb->regs = devm_ioremap_resource(dev, r); + rsb->regs = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(rsb->regs)) return PTR_ERR(rsb->regs); From fadf18180022743ff74b1f6ca4f3cff462ddaddb Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Fri, 7 Jul 2023 08:37:07 +0800 Subject: [PATCH 065/136] soc: amlogic: use name instead of index as criterion The variate 'index' could be equal to zero in some SoCs. Such as C3 SoC, PWRC_C3_NNA_ID be defined zero. Use 'name' instead of 'index' as criterion. Signed-off-by: Xianwei Zhao Reviewed-by: Neil Armstrong Reviewed-by: Dmitry Rokosov Link: https://lore.kernel.org/r/20230707003710.2667989-2-xianwei.zhao@amlogic.com Signed-off-by: Neil Armstrong --- drivers/soc/amlogic/meson-secure-pwrc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/amlogic/meson-secure-pwrc.c b/drivers/soc/amlogic/meson-secure-pwrc.c index 25b4b71df9b8..c11d65a3e3d9 100644 --- a/drivers/soc/amlogic/meson-secure-pwrc.c +++ b/drivers/soc/amlogic/meson-secure-pwrc.c @@ -179,7 +179,7 @@ static int meson_secure_pwrc_probe(struct platform_device *pdev) for (i = 0 ; i < match->count ; ++i) { struct meson_secure_pwrc_domain *dom = &pwrc->domains[i]; - if (!match->domains[i].index) + if (!match->domains[i].name) continue; dom->pwrc = pwrc; From 83b03d62939c46c118a8d722f07ae03a87967b00 Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Fri, 7 Jul 2023 08:37:08 +0800 Subject: [PATCH 066/136] dt-bindings: power: add Amlogic C3 power domains Add devicetree binding document and related header file for Amlogic C3 secure power domains. Signed-off-by: Xianwei Zhao Acked-by: Rob Herring Link: https://lore.kernel.org/r/20230707003710.2667989-3-xianwei.zhao@amlogic.com Signed-off-by: Neil Armstrong --- .../power/amlogic,meson-sec-pwrc.yaml | 3 ++- include/dt-bindings/power/amlogic,c3-pwrc.h | 25 +++++++++++++++++++ 2 files changed, 27 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/power/amlogic,c3-pwrc.h diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml index eab21bb2050a..d80bbedfe3aa 100644 --- a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml +++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml @@ -12,7 +12,7 @@ maintainers: - Jianxin Pan description: |+ - Secure Power Domains used in Meson A1/C1/S4 SoCs, and should be the child node + Secure Power Domains used in Meson A1/C1/S4 & C3 SoCs, and should be the child node of secure-monitor. properties: @@ -20,6 +20,7 @@ properties: enum: - amlogic,meson-a1-pwrc - amlogic,meson-s4-pwrc + - amlogic,c3-pwrc "#power-domain-cells": const: 1 diff --git a/include/dt-bindings/power/amlogic,c3-pwrc.h b/include/dt-bindings/power/amlogic,c3-pwrc.h new file mode 100644 index 000000000000..1d98a25b08a4 --- /dev/null +++ b/include/dt-bindings/power/amlogic,c3-pwrc.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0+ or MIT) */ +/* + * Copyright (c) 2023 Amlogic, Inc. + * Author: hongyu chen1 + */ +#ifndef _DT_BINDINGS_AMLOGIC_C3_POWER_H +#define _DT_BINDINGS_AMLOGIC_C3_POWER_H + +#define PWRC_C3_NNA_ID 0 +#define PWRC_C3_AUDIO_ID 1 +#define PWRC_C3_RESV_SEC_ID 2 +#define PWRC_C3_SDIOA_ID 3 +#define PWRC_C3_EMMC_ID 4 +#define PWRC_C3_USB_COMB_ID 5 +#define PWRC_C3_SDCARD_ID 6 +#define PWRC_C3_ETH_ID 7 +#define PWRC_C3_RESV0_ID 8 +#define PWRC_C3_GE2D_ID 9 +#define PWRC_C3_CVE_ID 10 +#define PWRC_C3_GDC_WRAP_ID 11 +#define PWRC_C3_ISP_TOP_ID 12 +#define PWRC_C3_MIPI_ISP_WRAP_ID 13 +#define PWRC_C3_VCODEC_ID 14 + +#endif From 77e2f4e3cbd5cde442d05a7bdb6cd01565bead6d Mon Sep 17 00:00:00 2001 From: Xianwei Zhao Date: Fri, 7 Jul 2023 08:37:09 +0800 Subject: [PATCH 067/136] soc: c3: Add support for power domains controller Add support for C3 Power controller. C3 power control registers are in secure domain, and should be accessed by SMC. Signed-off-by: Xianwei Zhao Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230707003710.2667989-4-xianwei.zhao@amlogic.com Signed-off-by: Neil Armstrong --- drivers/soc/amlogic/meson-secure-pwrc.c | 26 +++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/soc/amlogic/meson-secure-pwrc.c b/drivers/soc/amlogic/meson-secure-pwrc.c index c11d65a3e3d9..a1ffebf70de3 100644 --- a/drivers/soc/amlogic/meson-secure-pwrc.c +++ b/drivers/soc/amlogic/meson-secure-pwrc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -120,6 +121,22 @@ static struct meson_secure_pwrc_domain_desc a1_pwrc_domains[] = { SEC_PD(RSA, 0), }; +static struct meson_secure_pwrc_domain_desc c3_pwrc_domains[] = { + SEC_PD(C3_NNA, 0), + SEC_PD(C3_AUDIO, GENPD_FLAG_ALWAYS_ON), + SEC_PD(C3_SDIOA, GENPD_FLAG_ALWAYS_ON), + SEC_PD(C3_EMMC, GENPD_FLAG_ALWAYS_ON), + SEC_PD(C3_USB_COMB, GENPD_FLAG_ALWAYS_ON), + SEC_PD(C3_SDCARD, GENPD_FLAG_ALWAYS_ON), + SEC_PD(C3_ETH, GENPD_FLAG_ALWAYS_ON), + SEC_PD(C3_GE2D, GENPD_FLAG_ALWAYS_ON), + SEC_PD(C3_CVE, GENPD_FLAG_ALWAYS_ON), + SEC_PD(C3_GDC_WRAP, GENPD_FLAG_ALWAYS_ON), + SEC_PD(C3_ISP_TOP, GENPD_FLAG_ALWAYS_ON), + SEC_PD(C3_MIPI_ISP_WRAP, GENPD_FLAG_ALWAYS_ON), + SEC_PD(C3_VCODEC, 0), +}; + static struct meson_secure_pwrc_domain_desc s4_pwrc_domains[] = { SEC_PD(S4_DOS_HEVC, 0), SEC_PD(S4_DOS_VDEC, 0), @@ -202,6 +219,11 @@ static struct meson_secure_pwrc_domain_data meson_secure_a1_pwrc_data = { .count = ARRAY_SIZE(a1_pwrc_domains), }; +static struct meson_secure_pwrc_domain_data amlogic_secure_c3_pwrc_data = { + .domains = c3_pwrc_domains, + .count = ARRAY_SIZE(c3_pwrc_domains), +}; + static struct meson_secure_pwrc_domain_data meson_secure_s4_pwrc_data = { .domains = s4_pwrc_domains, .count = ARRAY_SIZE(s4_pwrc_domains), @@ -212,6 +234,10 @@ static const struct of_device_id meson_secure_pwrc_match_table[] = { .compatible = "amlogic,meson-a1-pwrc", .data = &meson_secure_a1_pwrc_data, }, + { + .compatible = "amlogic,c3-pwrc", + .data = &amlogic_secure_c3_pwrc_data, + }, { .compatible = "amlogic,meson-s4-pwrc", .data = &meson_secure_s4_pwrc_data, From 0b9d94e1f19acd19613386096d924af2333b620a Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 31 Jul 2023 17:00:06 +0530 Subject: [PATCH 068/136] dt-bindings: power: qcom,rpmpd: Add compatible for sdx75 Add a compatible string for power domains in sdx75. Signed-off-by: Rohit Agarwal Acked-by: Conor Dooley Link: https://lore.kernel.org/r/1690803007-8640-2-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index f9c211a9a938..9b03c41d3604 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -41,6 +41,7 @@ properties: - qcom,sdm845-rpmhpd - qcom,sdx55-rpmhpd - qcom,sdx65-rpmhpd + - qcom,sdx75-rpmhpd - qcom,sm6115-rpmpd - qcom,sm6125-rpmpd - qcom,sm6350-rpmhpd From 668e08c2e7b02124da573e29a67e013627ebf9ea Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Mon, 31 Jul 2023 17:00:07 +0530 Subject: [PATCH 069/136] soc: qcom: rpmhpd: Add SDX75 power domains Add the power domains exposed by RPMH in the Qualcomm SDX75 platform. Signed-off-by: Rohit Agarwal Link: https://lore.kernel.org/r/1690803007-8640-3-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/rpmhpd.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index 6641d5228bc6..a87e336d5e33 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -307,6 +307,21 @@ static const struct rpmhpd_desc sdx65_desc = { .num_pds = ARRAY_SIZE(sdx65_rpmhpds), }; +/* SDX75 RPMH powerdomains */ +static struct rpmhpd *sdx75_rpmhpds[] = { + [RPMHPD_CX] = &cx, + [RPMHPD_CX_AO] = &cx_ao, + [RPMHPD_MSS] = &mss, + [RPMHPD_MX] = &mx, + [RPMHPD_MX_AO] = &mx_ao, + [RPMHPD_MXC] = &mxc, +}; + +static const struct rpmhpd_desc sdx75_desc = { + .rpmhpds = sdx75_rpmhpds, + .num_pds = ARRAY_SIZE(sdx75_rpmhpds), +}; + /* SM6350 RPMH powerdomains */ static struct rpmhpd *sm6350_rpmhpds[] = { [SM6350_CX] = &cx_w_mx_parent, @@ -545,6 +560,7 @@ static const struct of_device_id rpmhpd_match_table[] = { { .compatible = "qcom,sdm845-rpmhpd", .data = &sdm845_desc }, { .compatible = "qcom,sdx55-rpmhpd", .data = &sdx55_desc}, { .compatible = "qcom,sdx65-rpmhpd", .data = &sdx65_desc}, + { .compatible = "qcom,sdx75-rpmhpd", .data = &sdx75_desc}, { .compatible = "qcom,sm6350-rpmhpd", .data = &sm6350_desc }, { .compatible = "qcom,sm8150-rpmhpd", .data = &sm8150_desc }, { .compatible = "qcom,sm8250-rpmhpd", .data = &sm8250_desc }, From 1beecfe68f802e5d4218bb7c5a728f2f38c979c7 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 19 Jun 2023 10:07:13 +0200 Subject: [PATCH 070/136] soc: qcom: pmic_glink_altmode: handle safe mode when disconnect On some Qcom SoCs, the Altmode event mode is set to 0xff when the Type-C port is disconnected. Handle this specific mode and translate it as the SAFE mode. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-type-c-v5-1-9221cd300903@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/pmic_glink_altmode.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/pmic_glink_altmode.c b/drivers/soc/qcom/pmic_glink_altmode.c index 1dedacc52aea..297d5821c784 100644 --- a/drivers/soc/qcom/pmic_glink_altmode.c +++ b/drivers/soc/qcom/pmic_glink_altmode.c @@ -174,6 +174,20 @@ static void pmic_glink_altmode_enable_usb(struct pmic_glink_altmode *altmode, dev_err(altmode->dev, "failed to switch mux to USB\n"); } +static void pmic_glink_altmode_safe(struct pmic_glink_altmode *altmode, + struct pmic_glink_altmode_port *port) +{ + int ret; + + port->state.alt = NULL; + port->state.data = NULL; + port->state.mode = TYPEC_STATE_SAFE; + + ret = typec_mux_set(port->typec_mux, &port->state); + if (ret) + dev_err(altmode->dev, "failed to switch mux to safe mode\n"); +} + static void pmic_glink_altmode_worker(struct work_struct *work) { struct pmic_glink_altmode_port *alt_port = work_to_altmode_port(work); @@ -181,7 +195,9 @@ static void pmic_glink_altmode_worker(struct work_struct *work) typec_switch_set(alt_port->typec_switch, alt_port->orientation); - if (alt_port->svid == USB_TYPEC_DP_SID) + if (alt_port->svid == USB_TYPEC_DP_SID && alt_port->mode == 0xff) + pmic_glink_altmode_safe(altmode, alt_port); + else if (alt_port->svid == USB_TYPEC_DP_SID) pmic_glink_altmode_enable_dp(altmode, alt_port, alt_port->mode, alt_port->hpd_state, alt_port->hpd_irq); else From 0549bc385f3534c380acbd7722cb6e14cca8c580 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 19 Jun 2023 10:07:14 +0200 Subject: [PATCH 071/136] soc: qcom: pmic_glink_altmode: add retimer-switch support Some boards have a retimer/redriver between the SuperSpeed PHY and the USB-C connector to compensates signal integrity losses mainly due to PCB & transmission cables. Add support for an optional retimer-switch in the USB-C connector graph. Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-type-c-v5-2-9221cd300903@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/pmic_glink_altmode.c | 43 +++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/soc/qcom/pmic_glink_altmode.c b/drivers/soc/qcom/pmic_glink_altmode.c index 297d5821c784..d05e0d6edf49 100644 --- a/drivers/soc/qcom/pmic_glink_altmode.c +++ b/drivers/soc/qcom/pmic_glink_altmode.c @@ -16,6 +16,7 @@ #include #include #include +#include #include @@ -69,6 +70,8 @@ struct pmic_glink_altmode_port { struct typec_switch *typec_switch; struct typec_mux *typec_mux; struct typec_mux_state state; + struct typec_retimer *typec_retimer; + struct typec_retimer_state retimer_state; struct typec_altmode dp_alt; struct work_struct work; @@ -158,6 +161,14 @@ static void pmic_glink_altmode_enable_dp(struct pmic_glink_altmode *altmode, ret = typec_mux_set(port->typec_mux, &port->state); if (ret) dev_err(altmode->dev, "failed to switch mux to DP\n"); + + port->retimer_state.alt = &port->dp_alt; + port->retimer_state.data = &dp_data; + port->retimer_state.mode = TYPEC_MODAL_STATE(mode); + + ret = typec_retimer_set(port->typec_retimer, &port->retimer_state); + if (ret) + dev_err(altmode->dev, "failed to setup retimer to DP\n"); } static void pmic_glink_altmode_enable_usb(struct pmic_glink_altmode *altmode, @@ -172,6 +183,14 @@ static void pmic_glink_altmode_enable_usb(struct pmic_glink_altmode *altmode, ret = typec_mux_set(port->typec_mux, &port->state); if (ret) dev_err(altmode->dev, "failed to switch mux to USB\n"); + + port->retimer_state.alt = NULL; + port->retimer_state.data = NULL; + port->retimer_state.mode = TYPEC_STATE_USB; + + ret = typec_retimer_set(port->typec_retimer, &port->retimer_state); + if (ret) + dev_err(altmode->dev, "failed to setup retimer to USB\n"); } static void pmic_glink_altmode_safe(struct pmic_glink_altmode *altmode, @@ -186,6 +205,14 @@ static void pmic_glink_altmode_safe(struct pmic_glink_altmode *altmode, ret = typec_mux_set(port->typec_mux, &port->state); if (ret) dev_err(altmode->dev, "failed to switch mux to safe mode\n"); + + port->retimer_state.alt = NULL; + port->retimer_state.data = NULL; + port->retimer_state.mode = TYPEC_STATE_SAFE; + + ret = typec_retimer_set(port->typec_retimer, &port->retimer_state); + if (ret) + dev_err(altmode->dev, "failed to setup retimer to USB\n"); } static void pmic_glink_altmode_worker(struct work_struct *work) @@ -348,6 +375,11 @@ static const struct drm_bridge_funcs pmic_glink_altmode_bridge_funcs = { .attach = pmic_glink_altmode_attach, }; +static void pmic_glink_altmode_put_retimer(void *data) +{ + typec_retimer_put(data); +} + static void pmic_glink_altmode_put_mux(void *data) { typec_mux_put(data); @@ -454,6 +486,17 @@ static int pmic_glink_altmode_probe(struct auxiliary_device *adev, if (ret) return ret; + alt_port->typec_retimer = fwnode_typec_retimer_get(fwnode); + if (IS_ERR(alt_port->typec_retimer)) + return dev_err_probe(dev, PTR_ERR(alt_port->typec_retimer), + "failed to acquire retimer-switch for port: %d\n", + port); + + ret = devm_add_action_or_reset(dev, pmic_glink_altmode_put_retimer, + alt_port->typec_retimer); + if (ret) + return ret; + alt_port->typec_switch = fwnode_typec_switch_get(fwnode); if (IS_ERR(alt_port->typec_switch)) return dev_err_probe(dev, PTR_ERR(alt_port->typec_switch), From 7daada8630eb49cd841c0fd022fadd52da100bce Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 19 Jun 2023 10:07:15 +0200 Subject: [PATCH 072/136] soc: qcom: pmic_glink: enable altmode for SM8550 Altmode is also supported for SM8550, allow it. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20230601-topic-sm8550-upstream-type-c-v5-3-9221cd300903@linaro.org Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/pmic_glink.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index 264e63493bfe..61c89ddfc75b 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -342,13 +342,9 @@ static const unsigned long pmic_glink_sm8450_client_mask = BIT(PMIC_GLINK_CLIENT BIT(PMIC_GLINK_CLIENT_ALTMODE) | BIT(PMIC_GLINK_CLIENT_UCSI); -/* Do not handle altmode for now on those platforms */ -static const unsigned long pmic_glink_sm8550_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | - BIT(PMIC_GLINK_CLIENT_UCSI); - static const struct of_device_id pmic_glink_of_match[] = { { .compatible = "qcom,sm8450-pmic-glink", .data = &pmic_glink_sm8450_client_mask }, - { .compatible = "qcom,sm8550-pmic-glink", .data = &pmic_glink_sm8550_client_mask }, + { .compatible = "qcom,sm8550-pmic-glink", .data = &pmic_glink_sm8450_client_mask }, { .compatible = "qcom,pmic-glink" }, {} }; From 4d641d2fafbb4470f6c765b8cb92c0e1073f1f03 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Mon, 31 Jul 2023 16:00:42 +0800 Subject: [PATCH 073/136] dt-bindings: arm: qcom,ids: add SoC ID for SM4450 Add the ID for the Qualcomm SM4450 SoC. Signed-off-by: Tengfei Fan Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230731080043.38552-6-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index bcbe9ee2cdaf..b8cdb0813f78 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -249,6 +249,7 @@ #define QCOM_ID_SA8775P 534 #define QCOM_ID_QRU1000 539 #define QCOM_ID_QDU1000 545 +#define QCOM_ID_SM4450 568 #define QCOM_ID_QDU1010 587 #define QCOM_ID_IPQ5019 569 #define QCOM_ID_QRU1032 588 From 42618de085cc305a5a03bb16a5965f8413944843 Mon Sep 17 00:00:00 2001 From: Tengfei Fan Date: Mon, 31 Jul 2023 16:00:43 +0800 Subject: [PATCH 074/136] soc: qcom: socinfo: add SM4450 ID Add the ID for the Qualcomm SM4450 SoC. Signed-off-by: Tengfei Fan Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230731080043.38552-7-quic_tengfan@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 4d49945b3a35..441a40f58838 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -405,6 +405,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SA8775P) }, { qcom_board_id(QRU1000) }, { qcom_board_id(QDU1000) }, + { qcom_board_id(SM4450) }, { qcom_board_id(QDU1010) }, { qcom_board_id(IPQ5019) }, { qcom_board_id(QRU1032) }, From 90158bc118f6f09fd5cd412c5954a40fd032aeff Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 24 Jul 2023 14:07:44 +0530 Subject: [PATCH 075/136] soc: qcom: socinfo: drop the IPQ5019 SoC ID IPQ5019 SoC is never productized. So lets drop it. Signed-off-by: Kathiravan T Link: https://lore.kernel.org/r/20230724083745.1015321-2-quic_kathirav@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 441a40f58838..1055b2e0bf96 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -407,7 +407,6 @@ static const struct soc_id soc_id[] = { { qcom_board_id(QDU1000) }, { qcom_board_id(SM4450) }, { qcom_board_id(QDU1010) }, - { qcom_board_id(IPQ5019) }, { qcom_board_id(QRU1032) }, { qcom_board_id(QRU1052) }, { qcom_board_id(QRU1062) }, From cb160cd7b11d0080d6bd21f1ea97c6edd2ae295a Mon Sep 17 00:00:00 2001 From: Kathiravan T Date: Mon, 24 Jul 2023 14:07:45 +0530 Subject: [PATCH 076/136] dt-bindings: arm: qcom,ids: drop the IPQ5019 SoC ID IPQ5019 SoC is never productized. So lets drop it. Signed-off-by: Kathiravan T Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230724083745.1015321-3-quic_kathirav@quicinc.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/arm/qcom,ids.h | 1 - 1 file changed, 1 deletion(-) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index b8cdb0813f78..48a1b0f63b77 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -251,7 +251,6 @@ #define QCOM_ID_QDU1000 545 #define QCOM_ID_SM4450 568 #define QCOM_ID_QDU1010 587 -#define QCOM_ID_IPQ5019 569 #define QCOM_ID_QRU1032 588 #define QCOM_ID_QRU1052 589 #define QCOM_ID_QRU1062 590 From b1b52717beb1e2cbb905e09f0d83a58323baec40 Mon Sep 17 00:00:00 2001 From: David Wronek Date: Sun, 23 Jul 2023 21:05:03 +0200 Subject: [PATCH 077/136] dt-bindings: arm: qcom,ids: Add SoC ID for SM7125 Add the SoC ID for Qualcomm SM7125. Signed-off-by: David Wronek Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230723190725.1619193-3-davidwronek@gmail.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/arm/qcom,ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/arm/qcom,ids.h b/include/dt-bindings/arm/qcom,ids.h index 48a1b0f63b77..be12e1dd1f38 100644 --- a/include/dt-bindings/arm/qcom,ids.h +++ b/include/dt-bindings/arm/qcom,ids.h @@ -215,6 +215,7 @@ #define QCOM_ID_SDA429W 437 #define QCOM_ID_SM8350 439 #define QCOM_ID_QCM2290 441 +#define QCOM_ID_SM7125 443 #define QCOM_ID_SM6115 444 #define QCOM_ID_IPQ5010 446 #define QCOM_ID_IPQ5018 447 From 23b45f8aab49f97b0c32bdc6331c0baf7337c48a Mon Sep 17 00:00:00 2001 From: David Wronek Date: Sun, 23 Jul 2023 21:05:05 +0200 Subject: [PATCH 078/136] soc: qcom: socinfo: Add SoC ID for SM7125 Add the SoC ID entry for Qualcomm SM7125. Signed-off-by: David Wronek Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230723190725.1619193-5-davidwronek@gmail.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 1055b2e0bf96..497cfb720fcb 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -371,6 +371,7 @@ static const struct soc_id soc_id[] = { { qcom_board_id(SDA429W) }, { qcom_board_id(SM8350) }, { qcom_board_id(QCM2290) }, + { qcom_board_id(SM7125) }, { qcom_board_id(SM6115) }, { qcom_board_id(IPQ5010) }, { qcom_board_id(IPQ5018) }, From e50a76355c1d8581673bda987688d59e7da33928 Mon Sep 17 00:00:00 2001 From: Jayesh Choudhary Date: Fri, 28 Jul 2023 11:03:56 +0530 Subject: [PATCH 079/136] soc: ti: k3-ringacc: remove non-fatal probe deferral log Drop the non-fatal probe deferral log for getting MSI domain. This makes the kernel log clean and we do not get recurring logs stating: "Failed to get MSI domain". Signed-off-by: Jayesh Choudhary Link: https://lore.kernel.org/r/20230728053356.31044-1-j-choudhary@ti.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/k3-ringacc.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index c6fdf0ad3d33..4c1353616b72 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -1373,10 +1373,8 @@ static int k3_ringacc_init(struct platform_device *pdev, dev->msi.domain = of_msi_get_domain(dev, dev->of_node, DOMAIN_BUS_TI_SCI_INTA_MSI); - if (!dev->msi.domain) { - dev_err(dev, "Failed to get MSI domain\n"); + if (!dev->msi.domain) return -EPROBE_DEFER; - } ret = k3_ringacc_probe_dt(ringacc); if (ret) From 4d6e0a1bf8f7a6b44d20162e29a87d0bd9526bb0 Mon Sep 17 00:00:00 2001 From: Yang Yingliang Date: Wed, 2 Aug 2023 10:48:55 +0800 Subject: [PATCH 080/136] soc: qcom: ocmem: add missing clk_disable_unprepare() in ocmem_dev_probe() Add clk_disable_unprepare(core_clk) when enable iface_clk failed. Fixes: a7e12e7bda08 ("soc: qcom: ocmem: make iface clock optional") Signed-off-by: Yang Yingliang Link: https://lore.kernel.org/r/20230802024855.2521895-1-yangyingliang@huawei.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/ocmem.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/ocmem.c b/drivers/soc/qcom/ocmem.c index 6edc18b211aa..20f5461d46b9 100644 --- a/drivers/soc/qcom/ocmem.c +++ b/drivers/soc/qcom/ocmem.c @@ -343,8 +343,10 @@ static int ocmem_dev_probe(struct platform_device *pdev) return dev_err_probe(ocmem->dev, ret, "Failed to enable core clock\n"); ret = clk_prepare_enable(ocmem->iface_clk); - if (ret) + if (ret) { + clk_disable_unprepare(ocmem->core_clk); return dev_err_probe(ocmem->dev, ret, "Failed to enable iface clock\n"); + } if (qcom_scm_restore_sec_cfg_available()) { dev_dbg(dev, "configuring scm\n"); From 5f908786cf44fcb397cfe0f322ef2f41b0909e2a Mon Sep 17 00:00:00 2001 From: Chen Jiahao Date: Tue, 1 Aug 2023 17:48:07 +0800 Subject: [PATCH 081/136] soc: qcom: smem: Fix incompatible types in comparison This patch fixes the following sparse error: drivers/soc/qcom/smem.c:738:30: error: incompatible types in comparison expression (different add ress spaces): drivers/soc/qcom/smem.c:738:30: void * drivers/soc/qcom/smem.c:738:30: void [noderef] __iomem * In addr_in_range(), "base" is of type void __iomem *, converting void *addr to the same type to fix above sparse error. Fixes: 20bb6c9de1b7 ("soc: qcom: smem: map only partitions used by local HOST") Signed-off-by: Chen Jiahao Link: https://lore.kernel.org/r/20230801094807.4146779-1-chenjiahao16@huawei.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/smem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/qcom/smem.c b/drivers/soc/qcom/smem.c index aa4a199efefb..d4a89d2bb43b 100644 --- a/drivers/soc/qcom/smem.c +++ b/drivers/soc/qcom/smem.c @@ -735,7 +735,7 @@ EXPORT_SYMBOL_GPL(qcom_smem_get_free_space); static bool addr_in_range(void __iomem *base, size_t size, void *addr) { - return base && (addr >= base && addr < base + size); + return base && ((void __iomem *)addr >= base && (void __iomem *)addr < base + size); } /** From 8d207400fd6b79c92aeb2f33bb79f62dff904ea2 Mon Sep 17 00:00:00 2001 From: Chris Lew Date: Tue, 1 Aug 2023 12:17:12 +0530 Subject: [PATCH 082/136] soc: qcom: qmi_encdec: Restrict string length in decode The QMI TLV value for strings in a lot of qmi element info structures account for null terminated strings with MAX_LEN + 1. If a string is actually MAX_LEN + 1 length, this will cause an out of bounds access when the NULL character is appended in decoding. Fixes: 9b8a11e82615 ("soc: qcom: Introduce QMI encoder/decoder") Cc: stable@vger.kernel.org Signed-off-by: Chris Lew Signed-off-by: Praveenkumar I Link: https://lore.kernel.org/r/20230801064712.3590128-1-quic_ipkumar@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qmi_encdec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/qmi_encdec.c b/drivers/soc/qcom/qmi_encdec.c index b7158e3c3a0b..5c7161b18b72 100644 --- a/drivers/soc/qcom/qmi_encdec.c +++ b/drivers/soc/qcom/qmi_encdec.c @@ -534,8 +534,8 @@ static int qmi_decode_string_elem(const struct qmi_elem_info *ei_array, decoded_bytes += rc; } - if (string_len > temp_ei->elem_len) { - pr_err("%s: String len %d > Max Len %d\n", + if (string_len >= temp_ei->elem_len) { + pr_err("%s: String len %d >= Max Len %d\n", __func__, string_len, temp_ei->elem_len); return -ETOOSMALL; } else if (string_len > tlv_len) { From 014f3272af3778cf8344fe92a153ab3d27011a3e Mon Sep 17 00:00:00 2001 From: Rohit Agarwal Date: Thu, 27 Jul 2023 18:13:33 +0530 Subject: [PATCH 083/136] dt-bindings: qcom: Update RPMHPD entries for some SoCs Update the RPMHPD references with new bindings defined in rpmhpd.h for Qualcomm SoCs SM8[2345]50. Signed-off-by: Rohit Agarwal Link: https://lore.kernel.org/r/1690461813-22564-1-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Bjorn Andersson --- .../devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml | 4 ++-- .../devicetree/bindings/clock/qcom,sm8350-videocc.yaml | 4 ++-- .../devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 4 ++-- .../devicetree/bindings/clock/qcom,sm8450-dispcc.yaml | 4 ++-- .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml | 4 ++-- .../devicetree/bindings/clock/qcom,sm8550-dispcc.yaml | 4 ++-- Documentation/devicetree/bindings/clock/qcom,videocc.yaml | 4 ++-- .../devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml | 4 ++-- .../devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml | 8 ++++---- .../devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml | 4 ++-- .../devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml | 6 +++--- .../devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml | 4 ++-- .../devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml | 8 ++++---- .../devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml | 4 ++-- .../devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml | 8 ++++---- .../devicetree/bindings/media/qcom,sm8250-venus.yaml | 4 ++-- Documentation/devicetree/bindings/mmc/sdhci-msm.yaml | 4 ++-- .../devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml | 6 +++--- 18 files changed, 44 insertions(+), 44 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml index d6774db257f0..59cc88a52f6b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml @@ -82,7 +82,7 @@ additionalProperties: false examples: - | #include - #include + #include clock-controller@af00000 { compatible = "qcom,sm8250-dispcc"; reg = <0x0af00000 0x10000>; @@ -103,7 +103,7 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml index 23505c8c3dbd..d723bb11d947 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8350-videocc.yaml @@ -51,7 +51,7 @@ unevaluatedProperties: false examples: - | #include - #include + #include clock-controller@abf0000 { compatible = "qcom,sm8350-videocc"; @@ -59,7 +59,7 @@ examples: clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml index 87ae74166807..8178c35bc348 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml @@ -64,7 +64,7 @@ examples: - | #include #include - #include + #include clock-controller@ade0000 { compatible = "qcom,sm8450-camcc"; reg = <0xade0000 0x20000>; @@ -72,7 +72,7 @@ examples: <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml index 1dd1f696dcd3..2f22310b08a9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml @@ -76,7 +76,7 @@ examples: - | #include #include - #include + #include clock-controller@af00000 { compatible = "qcom,sm8450-dispcc"; reg = <0x0af00000 0x10000>; @@ -91,7 +91,7 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index f1c6dd50f184..bad8f019a8d3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -64,13 +64,13 @@ examples: - | #include #include - #include + #include videocc: clock-controller@aaf0000 { compatible = "qcom,sm8450-videocc"; reg = <0x0aaf0000 0x10000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; #clock-cells = <1>; #reset-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml index ab25f7cbaa2e..c129f8c16b50 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml @@ -76,7 +76,7 @@ examples: - | #include #include - #include + #include clock-controller@af00000 { compatible = "qcom,sm8550-dispcc"; reg = <0x0af00000 0x10000>; @@ -99,7 +99,7 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 2b07146161b4..6de01cf3259d 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -124,7 +124,7 @@ additionalProperties: false examples: - | #include - #include + #include clock-controller@ab00000 { compatible = "qcom,sdm845-videocc"; reg = <0x0ab00000 0x10000>; @@ -133,7 +133,7 @@ examples: #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; required-opps = <&rpmhpd_opp_low_svs>; }; ... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml index 687c8c170cd4..acd2ed391b2f 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-dpu.yaml @@ -54,7 +54,7 @@ examples: #include #include #include - #include + #include display-controller@ae01000 { compatible = "qcom,sm8250-dpu"; @@ -72,7 +72,7 @@ examples: assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml index 368d3db0ce96..5cfb9b917e90 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8250-mdss.yaml @@ -76,7 +76,7 @@ examples: #include #include #include - #include + #include display-subsystem@ae00000 { compatible = "qcom,sm8250-mdss"; @@ -121,7 +121,7 @@ examples: assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; @@ -196,7 +196,7 @@ examples: assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&dsi0_phy>; phy-names = "dsi"; @@ -286,7 +286,7 @@ examples: assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SM8250_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&dsi1_phy>; phy-names = "dsi"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml index 120500395c9a..1a4e03531a1b 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-dpu.yaml @@ -51,7 +51,7 @@ examples: #include #include #include - #include + #include display-controller@ae01000 { compatible = "qcom,sm8350-dpu"; @@ -76,7 +76,7 @@ examples: assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml index 79a226e4cc6a..1056bed1272c 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8350-mdss.yaml @@ -75,7 +75,7 @@ examples: #include #include #include - #include + #include display-subsystem@ae00000 { compatible = "qcom,sm8350-mdss"; @@ -128,7 +128,7 @@ examples: assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; @@ -197,7 +197,7 @@ examples: <&mdss_dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SM8350_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&mdss_dsi0_phy>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml index 0d17ece1c453..da3fd66c564f 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-dpu.yaml @@ -58,7 +58,7 @@ examples: #include #include #include - #include + #include display-controller@ae01000 { compatible = "qcom,sm8450-dpu"; @@ -83,7 +83,7 @@ examples: assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml index f26eb5643aed..6dd21afd5226 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8450-mdss.yaml @@ -68,7 +68,7 @@ examples: #include #include #include - #include + #include display-subsystem@ae00000 { compatible = "qcom,sm8450-mdss"; @@ -122,7 +122,7 @@ examples: assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; @@ -202,7 +202,7 @@ examples: assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&dsi0_phy>; phy-names = "dsi"; @@ -297,7 +297,7 @@ examples: assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SM8450_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&dsi1_phy>; phy-names = "dsi"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml index ff58a747bb6f..99908fbe74f0 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-dpu.yaml @@ -57,7 +57,7 @@ examples: #include #include #include - #include + #include display-controller@ae01000 { compatible = "qcom,sm8550-dpu"; @@ -82,7 +82,7 @@ examples: assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml index 887be33ba108..a4643129972e 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8550-mdss.yaml @@ -68,7 +68,7 @@ examples: #include #include #include - #include + #include display-subsystem@ae00000 { compatible = "qcom,sm8550-mdss"; @@ -122,7 +122,7 @@ examples: assigned-clock-rates = <19200000>; operating-points-v2 = <&mdp_opp_table>; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; interrupt-parent = <&mdss>; interrupts = <0>; @@ -197,7 +197,7 @@ examples: assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&dsi0_phy>; phy-names = "dsi"; @@ -286,7 +286,7 @@ examples: assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; operating-points-v2 = <&dsi_opp_table>; - power-domains = <&rpmhpd SM8550_MMCX>; + power-domains = <&rpmhpd RPMHPD_MMCX>; phys = <&dsi1_phy>; phy-names = "dsi"; diff --git a/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml index 7915dcd2d99f..f66033ae8b59 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml @@ -106,7 +106,7 @@ examples: #include #include #include - #include + #include venus: video-codec@aa00000 { compatible = "qcom,sm8250-venus"; @@ -114,7 +114,7 @@ examples: interrupts = ; power-domains = <&videocc MVS0C_GDSC>, <&videocc MVS0_GDSC>, - <&rpmhpd SM8250_MX>; + <&rpmhpd RPMHPD_MX>; power-domain-names = "venus", "vcodec0", "mx"; clocks = <&gcc GCC_VIDEO_AXI0_CLK>, diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index 6da28e630577..80141eb7fc6b 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -215,7 +215,7 @@ examples: #include #include #include - #include + #include sdhc_2: mmc@8804000 { compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; @@ -232,7 +232,7 @@ examples: iommus = <&apps_smmu 0x4a0 0x0>; qcom,dll-config = <0x0007642c>; qcom,ddr-config = <0x80040868>; - power-domains = <&rpmhpd SM8250_CX>; + power-domains = <&rpmhpd RPMHPD_CX>; operating-points-v2 = <&sdhc2_opp_table>; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml index af24f9a3cdf1..9a04d192e7e4 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8350-pas.yaml @@ -139,7 +139,7 @@ examples: #include #include #include - #include + #include remoteproc@30000000 { compatible = "qcom,sm8450-adsp-pas"; @@ -160,8 +160,8 @@ examples: memory-region = <&adsp_mem>; - power-domains = <&rpmhpd SM8450_LCX>, - <&rpmhpd SM8450_LMX>; + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; power-domain-names = "lcx", "lmx"; qcom,qmp = <&aoss_qmp>; From c6cb31b9f61c5261f9a0d7dc38b8f84a850bfcee Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 3 Aug 2023 16:43:02 -0600 Subject: [PATCH 084/136] soc: xilinx: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230803-dt-header-cleanups-for-soc-v2-22-d8de2cc88bff@kernel.org Signed-off-by: Michal Simek --- drivers/soc/xilinx/zynqmp_power.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/xilinx/zynqmp_power.c b/drivers/soc/xilinx/zynqmp_power.c index 641dcc958911..913417506468 100644 --- a/drivers/soc/xilinx/zynqmp_power.c +++ b/drivers/soc/xilinx/zynqmp_power.c @@ -11,6 +11,7 @@ #include #include +#include #include #include #include From 746db5d0b6d2a4bce0bc972bffd8428c606106cd Mon Sep 17 00:00:00 2001 From: Ruan Jinjie Date: Thu, 3 Aug 2023 18:48:07 +0800 Subject: [PATCH 085/136] soc: xilinx: Do not check for 0 return after calling platform_get_irq() There is no possible for platform_get_irq() to return 0. Use the return value from platform_get_irq(). Signed-off-by: Ruan Jinjie Link: https://lore.kernel.org/r/20230803104807.814005-3-ruanjinjie@huawei.com Signed-off-by: Michal Simek --- drivers/soc/xilinx/zynqmp_power.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/xilinx/zynqmp_power.c b/drivers/soc/xilinx/zynqmp_power.c index 913417506468..c2c819701eec 100644 --- a/drivers/soc/xilinx/zynqmp_power.c +++ b/drivers/soc/xilinx/zynqmp_power.c @@ -243,8 +243,8 @@ static int zynqmp_pm_probe(struct platform_device *pdev) } } else if (of_property_present(pdev->dev.of_node, "interrupts")) { irq = platform_get_irq(pdev, 0); - if (irq <= 0) - return -ENXIO; + if (irq < 0) + return irq; ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, zynqmp_pm_isr, From ebd4f6102fbc2c5a7560ad5256a71696ab136ce6 Mon Sep 17 00:00:00 2001 From: Sudeep Holla Date: Thu, 27 Jul 2023 14:35:51 +0100 Subject: [PATCH 086/136] MAINTAINERS: Simplify entries for Arm Vexpress platform and related drivers Currently the entries have regexs but in absolute paths. The "N:" entries can deal with all files and directories irrespective of the depth/path matching the regex patterns. Simplifies the entry by making using "N:" and dropping "F:" with absolute paths. Cc: Liviu Dudau Cc: Lorenzo Pieralisi Suggested-by: Tom Rini Acked-by: Liviu Dudau Link: https://lore.kernel.org/r/20230727133551.648390-1-sudeep.holla@arm.com Signed-off-by: Sudeep Holla --- MAINTAINERS | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 3be1bdfe8ecc..ef8ac28b098a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2927,14 +2927,13 @@ M: Sudeep Holla M: Lorenzo Pieralisi L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -F: */*/*/vexpress* -F: */*/vexpress* -F: arch/arm/boot/dts/arm/vexpress* +N: mps2 +N: vexpress F: arch/arm/mach-versatile/ F: arch/arm64/boot/dts/arm/ -F: drivers/clk/versatile/clk-vexpress-osc.c F: drivers/clocksource/timer-versatile.c -N: mps2 +X: drivers/cpufreq/vexpress-spc-cpufreq.c +X: Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml ARM/VFP SUPPORT M: Russell King From 3da82112355bba263597fcbb24d275fc57e69e7e Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Mon, 17 Jul 2023 17:12:45 +0100 Subject: [PATCH 087/136] firmware: arm_scmi: Harden perf domain info access Harden internal accesses to domain info in the SCMI perf protocol. Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20230717161246.1761777-2-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/perf.c | 89 +++++++++++++++++++++++--------- 1 file changed, 64 insertions(+), 25 deletions(-) diff --git a/drivers/firmware/arm_scmi/perf.c b/drivers/firmware/arm_scmi/perf.c index ecf5c4de851b..43dd242ecc49 100644 --- a/drivers/firmware/arm_scmi/perf.c +++ b/drivers/firmware/arm_scmi/perf.c @@ -139,7 +139,7 @@ struct perf_dom_info { struct scmi_perf_info { u32 version; - int num_domains; + u16 num_domains; enum scmi_power_scale power_scale; u64 stats_addr; u32 stats_size; @@ -356,11 +356,26 @@ static int scmi_perf_mb_limits_set(const struct scmi_protocol_handle *ph, return ret; } +static inline struct perf_dom_info * +scmi_perf_domain_lookup(const struct scmi_protocol_handle *ph, u32 domain) +{ + struct scmi_perf_info *pi = ph->get_priv(ph); + + if (domain >= pi->num_domains) + return ERR_PTR(-EINVAL); + + return pi->dom_info + domain; +} + static int scmi_perf_limits_set(const struct scmi_protocol_handle *ph, u32 domain, u32 max_perf, u32 min_perf) { struct scmi_perf_info *pi = ph->get_priv(ph); - struct perf_dom_info *dom = pi->dom_info + domain; + struct perf_dom_info *dom; + + dom = scmi_perf_domain_lookup(ph, domain); + if (IS_ERR(dom)) + return PTR_ERR(dom); if (PROTOCOL_REV_MAJOR(pi->version) >= 0x3 && !max_perf && !min_perf) return -EINVAL; @@ -408,8 +423,11 @@ static int scmi_perf_mb_limits_get(const struct scmi_protocol_handle *ph, static int scmi_perf_limits_get(const struct scmi_protocol_handle *ph, u32 domain, u32 *max_perf, u32 *min_perf) { - struct scmi_perf_info *pi = ph->get_priv(ph); - struct perf_dom_info *dom = pi->dom_info + domain; + struct perf_dom_info *dom; + + dom = scmi_perf_domain_lookup(ph, domain); + if (IS_ERR(dom)) + return PTR_ERR(dom); if (dom->fc_info && dom->fc_info[PERF_FC_LIMIT].get_addr) { struct scmi_fc_info *fci = &dom->fc_info[PERF_FC_LIMIT]; @@ -449,8 +467,11 @@ static int scmi_perf_mb_level_set(const struct scmi_protocol_handle *ph, static int scmi_perf_level_set(const struct scmi_protocol_handle *ph, u32 domain, u32 level, bool poll) { - struct scmi_perf_info *pi = ph->get_priv(ph); - struct perf_dom_info *dom = pi->dom_info + domain; + struct perf_dom_info *dom; + + dom = scmi_perf_domain_lookup(ph, domain); + if (IS_ERR(dom)) + return PTR_ERR(dom); if (dom->fc_info && dom->fc_info[PERF_FC_LEVEL].set_addr) { struct scmi_fc_info *fci = &dom->fc_info[PERF_FC_LEVEL]; @@ -490,8 +511,11 @@ static int scmi_perf_mb_level_get(const struct scmi_protocol_handle *ph, static int scmi_perf_level_get(const struct scmi_protocol_handle *ph, u32 domain, u32 *level, bool poll) { - struct scmi_perf_info *pi = ph->get_priv(ph); - struct perf_dom_info *dom = pi->dom_info + domain; + struct perf_dom_info *dom; + + dom = scmi_perf_domain_lookup(ph, domain); + if (IS_ERR(dom)) + return PTR_ERR(dom); if (dom->fc_info && dom->fc_info[PERF_FC_LEVEL].get_addr) { *level = ioread32(dom->fc_info[PERF_FC_LEVEL].get_addr); @@ -574,13 +598,14 @@ static int scmi_dvfs_device_opps_add(const struct scmi_protocol_handle *ph, unsigned long freq; struct scmi_opp *opp; struct perf_dom_info *dom; - struct scmi_perf_info *pi = ph->get_priv(ph); domain = scmi_dev_domain_id(dev); if (domain < 0) - return domain; + return -EINVAL; - dom = pi->dom_info + domain; + dom = scmi_perf_domain_lookup(ph, domain); + if (IS_ERR(dom)) + return PTR_ERR(dom); for (opp = dom->opp, idx = 0; idx < dom->opp_count; idx++, opp++) { freq = opp->perf * dom->mult_factor; @@ -603,14 +628,17 @@ static int scmi_dvfs_transition_latency_get(const struct scmi_protocol_handle *ph, struct device *dev) { + int domain; struct perf_dom_info *dom; - struct scmi_perf_info *pi = ph->get_priv(ph); - int domain = scmi_dev_domain_id(dev); + domain = scmi_dev_domain_id(dev); if (domain < 0) - return domain; + return -EINVAL; + + dom = scmi_perf_domain_lookup(ph, domain); + if (IS_ERR(dom)) + return PTR_ERR(dom); - dom = pi->dom_info + domain; /* uS to nS */ return dom->opp[dom->opp_count - 1].trans_latency_us * 1000; } @@ -618,8 +646,11 @@ scmi_dvfs_transition_latency_get(const struct scmi_protocol_handle *ph, static int scmi_dvfs_freq_set(const struct scmi_protocol_handle *ph, u32 domain, unsigned long freq, bool poll) { - struct scmi_perf_info *pi = ph->get_priv(ph); - struct perf_dom_info *dom = pi->dom_info + domain; + struct perf_dom_info *dom; + + dom = scmi_perf_domain_lookup(ph, domain); + if (IS_ERR(dom)) + return PTR_ERR(dom); return scmi_perf_level_set(ph, domain, freq / dom->mult_factor, poll); } @@ -630,11 +661,14 @@ static int scmi_dvfs_freq_get(const struct scmi_protocol_handle *ph, u32 domain, int ret; u32 level; struct scmi_perf_info *pi = ph->get_priv(ph); - struct perf_dom_info *dom = pi->dom_info + domain; ret = scmi_perf_level_get(ph, domain, &level, poll); - if (!ret) + if (!ret) { + struct perf_dom_info *dom = pi->dom_info + domain; + + /* Note domain is validated implicitly by scmi_perf_level_get */ *freq = level * dom->mult_factor; + } return ret; } @@ -643,15 +677,14 @@ static int scmi_dvfs_est_power_get(const struct scmi_protocol_handle *ph, u32 domain, unsigned long *freq, unsigned long *power) { - struct scmi_perf_info *pi = ph->get_priv(ph); struct perf_dom_info *dom; unsigned long opp_freq; int idx, ret = -EINVAL; struct scmi_opp *opp; - dom = pi->dom_info + domain; - if (!dom) - return -EIO; + dom = scmi_perf_domain_lookup(ph, domain); + if (IS_ERR(dom)) + return PTR_ERR(dom); for (opp = dom->opp, idx = 0; idx < dom->opp_count; idx++, opp++) { opp_freq = opp->perf * dom->mult_factor; @@ -670,10 +703,16 @@ static int scmi_dvfs_est_power_get(const struct scmi_protocol_handle *ph, static bool scmi_fast_switch_possible(const struct scmi_protocol_handle *ph, struct device *dev) { + int domain; struct perf_dom_info *dom; - struct scmi_perf_info *pi = ph->get_priv(ph); - dom = pi->dom_info + scmi_dev_domain_id(dev); + domain = scmi_dev_domain_id(dev); + if (domain < 0) + return false; + + dom = scmi_perf_domain_lookup(ph, domain); + if (IS_ERR(dom)) + return false; return dom->fc_info && dom->fc_info[PERF_FC_LEVEL].set_addr; } From 31c7c1397a33d4c7ad1e06aa6ea9fc6148554b29 Mon Sep 17 00:00:00 2001 From: Cristian Marussi Date: Mon, 17 Jul 2023 17:12:46 +0100 Subject: [PATCH 088/136] firmware: arm_scmi: Add v3.2 perf level indexing mode support SCMI v3.2 adds PERF protocol support to optionally define performance domains that cannot be represented on a linear scale; the platform firmware can declare the performance levels of a domain as being 'level indexed' and provide an indicative frequency associated to each of those levels, with such indexes not required anymore to be contiguous nor to satisfy any linear-scaling constraint: when level-indexing is available for a domain, the platform will expect to deal with SCMI requests using indexes instead of performance levels for that domain. Add level-indexing mode support to the PERF protocol implementation while maintaining unchanged the protocol operations interface exposed by PERF; all the required mapping from performamce levels/frequencies to the corresponding level indexes is carried out transparently by the core PERF protocol support: as a consequence no change is either required in any SCMI driver using the PERF protocol, even when using level indexing. Signed-off-by: Cristian Marussi Link: https://lore.kernel.org/r/20230717161246.1761777-3-cristian.marussi@arm.com Signed-off-by: Sudeep Holla --- drivers/firmware/arm_scmi/perf.c | 371 +++++++++++++++++++++++++------ 1 file changed, 299 insertions(+), 72 deletions(-) diff --git a/drivers/firmware/arm_scmi/perf.c b/drivers/firmware/arm_scmi/perf.c index 43dd242ecc49..c0cd556fbaae 100644 --- a/drivers/firmware/arm_scmi/perf.c +++ b/drivers/firmware/arm_scmi/perf.c @@ -2,19 +2,22 @@ /* * System Control and Management Interface (SCMI) Performance Protocol * - * Copyright (C) 2018-2022 ARM Ltd. + * Copyright (C) 2018-2023 ARM Ltd. */ #define pr_fmt(fmt) "SCMI Notifications PERF - " fmt #include -#include +#include #include +#include #include +#include #include #include #include #include +#include #include @@ -46,6 +49,9 @@ struct scmi_opp { u32 perf; u32 power; u32 trans_latency_us; + u32 indicative_freq; + u32 level_index; + struct hlist_node hash; }; struct scmi_msg_resp_perf_attributes { @@ -66,6 +72,7 @@ struct scmi_msg_resp_perf_domain_attributes { #define SUPPORTS_PERF_LEVEL_NOTIFY(x) ((x) & BIT(28)) #define SUPPORTS_PERF_FASTCHANNELS(x) ((x) & BIT(27)) #define SUPPORTS_EXTENDED_NAMES(x) ((x) & BIT(26)) +#define SUPPORTS_LEVEL_INDEXING(x) ((x) & BIT(25)) __le32 rate_limit_us; __le32 sustained_freq_khz; __le32 sustained_perf_level; @@ -122,12 +129,27 @@ struct scmi_msg_resp_perf_describe_levels { } opp[]; }; +struct scmi_msg_resp_perf_describe_levels_v4 { + __le16 num_returned; + __le16 num_remaining; + struct { + __le32 perf_val; + __le32 power; + __le16 transition_latency_us; + __le16 reserved; + __le32 indicative_freq; + __le32 level_index; + } opp[]; +}; + struct perf_dom_info { + u32 id; bool set_limits; bool set_perf; bool perf_limit_notify; bool perf_level_notify; bool perf_fastchannels; + bool level_indexing_mode; u32 opp_count; u32 sustained_freq_khz; u32 sustained_perf_level; @@ -135,8 +157,23 @@ struct perf_dom_info { char name[SCMI_MAX_STR_SIZE]; struct scmi_opp opp[MAX_OPPS]; struct scmi_fc_info *fc_info; + struct xarray opps_by_idx; + struct xarray opps_by_lvl; + DECLARE_HASHTABLE(opps_by_freq, ilog2(MAX_OPPS)); }; +#define LOOKUP_BY_FREQ(__htp, __freq) \ +({ \ + /* u32 cast is needed to pick right hash func */ \ + u32 f_ = (u32)(__freq); \ + struct scmi_opp *_opp; \ + \ + hash_for_each_possible((__htp), _opp, hash, f_) \ + if (_opp->indicative_freq == f_) \ + break; \ + _opp; \ +}) + struct scmi_perf_info { u32 version; u16 num_domains; @@ -186,9 +223,20 @@ static int scmi_perf_attributes_get(const struct scmi_protocol_handle *ph, return ret; } +static void scmi_perf_xa_destroy(void *data) +{ + int domain; + struct scmi_perf_info *pinfo = data; + + for (domain = 0; domain < pinfo->num_domains; domain++) { + xa_destroy(&((pinfo->dom_info + domain)->opps_by_idx)); + xa_destroy(&((pinfo->dom_info + domain)->opps_by_lvl)); + } +} + static int scmi_perf_domain_attributes_get(const struct scmi_protocol_handle *ph, - u32 domain, struct perf_dom_info *dom_info, + struct perf_dom_info *dom_info, u32 version) { int ret; @@ -197,11 +245,11 @@ scmi_perf_domain_attributes_get(const struct scmi_protocol_handle *ph, struct scmi_msg_resp_perf_domain_attributes *attr; ret = ph->xops->xfer_get_init(ph, PERF_DOMAIN_ATTRIBUTES, - sizeof(domain), sizeof(*attr), &t); + sizeof(dom_info->id), sizeof(*attr), &t); if (ret) return ret; - put_unaligned_le32(domain, t->tx.buf); + put_unaligned_le32(dom_info->id, t->tx.buf); attr = t->rx.buf; ret = ph->xops->do_xfer(ph, t); @@ -213,6 +261,9 @@ scmi_perf_domain_attributes_get(const struct scmi_protocol_handle *ph, dom_info->perf_limit_notify = SUPPORTS_PERF_LIMIT_NOTIFY(flags); dom_info->perf_level_notify = SUPPORTS_PERF_LEVEL_NOTIFY(flags); dom_info->perf_fastchannels = SUPPORTS_PERF_FASTCHANNELS(flags); + if (PROTOCOL_REV_MAJOR(version) >= 0x4) + dom_info->level_indexing_mode = + SUPPORTS_LEVEL_INDEXING(flags); dom_info->sustained_freq_khz = le32_to_cpu(attr->sustained_freq_khz); dom_info->sustained_perf_level = @@ -236,8 +287,15 @@ scmi_perf_domain_attributes_get(const struct scmi_protocol_handle *ph, */ if (!ret && PROTOCOL_REV_MAJOR(version) >= 0x3 && SUPPORTS_EXTENDED_NAMES(flags)) - ph->hops->extended_name_get(ph, PERF_DOMAIN_NAME_GET, domain, - dom_info->name, SCMI_MAX_STR_SIZE); + ph->hops->extended_name_get(ph, PERF_DOMAIN_NAME_GET, + dom_info->id, dom_info->name, + SCMI_MAX_STR_SIZE); + + if (dom_info->level_indexing_mode) { + xa_init(&dom_info->opps_by_idx); + xa_init(&dom_info->opps_by_lvl); + hash_init(dom_info->opps_by_freq); + } return ret; } @@ -250,7 +308,7 @@ static int opp_cmp_func(const void *opp1, const void *opp2) } struct scmi_perf_ipriv { - u32 domain; + u32 version; struct perf_dom_info *perf_dom; }; @@ -261,7 +319,7 @@ static void iter_perf_levels_prepare_message(void *message, struct scmi_msg_perf_describe_levels *msg = message; const struct scmi_perf_ipriv *p = priv; - msg->domain = cpu_to_le32(p->domain); + msg->domain = cpu_to_le32(p->perf_dom->id); /* Set the number of OPPs to be skipped/already read */ msg->level_index = cpu_to_le32(desc_index); } @@ -277,31 +335,63 @@ static int iter_perf_levels_update_state(struct scmi_iterator_state *st, return 0; } +static inline void +process_response_opp(struct scmi_opp *opp, unsigned int loop_idx, + const struct scmi_msg_resp_perf_describe_levels *r) +{ + opp->perf = le32_to_cpu(r->opp[loop_idx].perf_val); + opp->power = le32_to_cpu(r->opp[loop_idx].power); + opp->trans_latency_us = + le16_to_cpu(r->opp[loop_idx].transition_latency_us); +} + +static inline void +process_response_opp_v4(struct perf_dom_info *dom, struct scmi_opp *opp, + unsigned int loop_idx, + const struct scmi_msg_resp_perf_describe_levels_v4 *r) +{ + opp->perf = le32_to_cpu(r->opp[loop_idx].perf_val); + opp->power = le32_to_cpu(r->opp[loop_idx].power); + opp->trans_latency_us = + le16_to_cpu(r->opp[loop_idx].transition_latency_us); + + /* Note that PERF v4 reports always five 32-bit words */ + opp->indicative_freq = le32_to_cpu(r->opp[loop_idx].indicative_freq); + if (dom->level_indexing_mode) { + opp->level_index = le32_to_cpu(r->opp[loop_idx].level_index); + + xa_store(&dom->opps_by_idx, opp->level_index, opp, GFP_KERNEL); + xa_store(&dom->opps_by_lvl, opp->perf, opp, GFP_KERNEL); + hash_add(dom->opps_by_freq, &opp->hash, opp->indicative_freq); + } +} + static int iter_perf_levels_process_response(const struct scmi_protocol_handle *ph, const void *response, struct scmi_iterator_state *st, void *priv) { struct scmi_opp *opp; - const struct scmi_msg_resp_perf_describe_levels *r = response; struct scmi_perf_ipriv *p = priv; opp = &p->perf_dom->opp[st->desc_index + st->loop_idx]; - opp->perf = le32_to_cpu(r->opp[st->loop_idx].perf_val); - opp->power = le32_to_cpu(r->opp[st->loop_idx].power); - opp->trans_latency_us = - le16_to_cpu(r->opp[st->loop_idx].transition_latency_us); + if (PROTOCOL_REV_MAJOR(p->version) <= 0x3) + process_response_opp(opp, st->loop_idx, response); + else + process_response_opp_v4(p->perf_dom, opp, st->loop_idx, + response); p->perf_dom->opp_count++; - dev_dbg(ph->dev, "Level %d Power %d Latency %dus\n", - opp->perf, opp->power, opp->trans_latency_us); + dev_dbg(ph->dev, "Level %d Power %d Latency %dus Ifreq %d Index %d\n", + opp->perf, opp->power, opp->trans_latency_us, + opp->indicative_freq, opp->level_index); return 0; } static int -scmi_perf_describe_levels_get(const struct scmi_protocol_handle *ph, u32 domain, - struct perf_dom_info *perf_dom) +scmi_perf_describe_levels_get(const struct scmi_protocol_handle *ph, + struct perf_dom_info *perf_dom, u32 version) { int ret; void *iter; @@ -311,7 +401,7 @@ scmi_perf_describe_levels_get(const struct scmi_protocol_handle *ph, u32 domain, .process_response = iter_perf_levels_process_response, }; struct scmi_perf_ipriv ppriv = { - .domain = domain, + .version = version, .perf_dom = perf_dom, }; @@ -333,8 +423,8 @@ scmi_perf_describe_levels_get(const struct scmi_protocol_handle *ph, u32 domain, return ret; } -static int scmi_perf_mb_limits_set(const struct scmi_protocol_handle *ph, - u32 domain, u32 max_perf, u32 min_perf) +static int scmi_perf_msg_limits_set(const struct scmi_protocol_handle *ph, + u32 domain, u32 max_perf, u32 min_perf) { int ret; struct scmi_xfer *t; @@ -367,6 +457,24 @@ scmi_perf_domain_lookup(const struct scmi_protocol_handle *ph, u32 domain) return pi->dom_info + domain; } +static int __scmi_perf_limits_set(const struct scmi_protocol_handle *ph, + struct perf_dom_info *dom, u32 max_perf, + u32 min_perf) +{ + if (dom->fc_info && dom->fc_info[PERF_FC_LIMIT].set_addr) { + struct scmi_fc_info *fci = &dom->fc_info[PERF_FC_LIMIT]; + + trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LIMITS_SET, + dom->id, min_perf, max_perf); + iowrite32(max_perf, fci->set_addr); + iowrite32(min_perf, fci->set_addr + 4); + ph->hops->fastchannel_db_ring(fci->set_db); + return 0; + } + + return scmi_perf_msg_limits_set(ph, dom->id, max_perf, min_perf); +} + static int scmi_perf_limits_set(const struct scmi_protocol_handle *ph, u32 domain, u32 max_perf, u32 min_perf) { @@ -380,22 +488,31 @@ static int scmi_perf_limits_set(const struct scmi_protocol_handle *ph, if (PROTOCOL_REV_MAJOR(pi->version) >= 0x3 && !max_perf && !min_perf) return -EINVAL; - if (dom->fc_info && dom->fc_info[PERF_FC_LIMIT].set_addr) { - struct scmi_fc_info *fci = &dom->fc_info[PERF_FC_LIMIT]; + if (dom->level_indexing_mode) { + struct scmi_opp *opp; - trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LIMITS_SET, - domain, min_perf, max_perf); - iowrite32(max_perf, fci->set_addr); - iowrite32(min_perf, fci->set_addr + 4); - ph->hops->fastchannel_db_ring(fci->set_db); - return 0; + if (min_perf) { + opp = xa_load(&dom->opps_by_lvl, min_perf); + if (!opp) + return -EIO; + + min_perf = opp->level_index; + } + + if (max_perf) { + opp = xa_load(&dom->opps_by_lvl, max_perf); + if (!opp) + return -EIO; + + max_perf = opp->level_index; + } } - return scmi_perf_mb_limits_set(ph, domain, max_perf, min_perf); + return __scmi_perf_limits_set(ph, dom, max_perf, min_perf); } -static int scmi_perf_mb_limits_get(const struct scmi_protocol_handle *ph, - u32 domain, u32 *max_perf, u32 *min_perf) +static int scmi_perf_msg_limits_get(const struct scmi_protocol_handle *ph, + u32 domain, u32 *max_perf, u32 *min_perf) { int ret; struct scmi_xfer *t; @@ -420,30 +537,58 @@ static int scmi_perf_mb_limits_get(const struct scmi_protocol_handle *ph, return ret; } -static int scmi_perf_limits_get(const struct scmi_protocol_handle *ph, - u32 domain, u32 *max_perf, u32 *min_perf) +static int __scmi_perf_limits_get(const struct scmi_protocol_handle *ph, + struct perf_dom_info *dom, u32 *max_perf, + u32 *min_perf) { - struct perf_dom_info *dom; - - dom = scmi_perf_domain_lookup(ph, domain); - if (IS_ERR(dom)) - return PTR_ERR(dom); - if (dom->fc_info && dom->fc_info[PERF_FC_LIMIT].get_addr) { struct scmi_fc_info *fci = &dom->fc_info[PERF_FC_LIMIT]; *max_perf = ioread32(fci->get_addr); *min_perf = ioread32(fci->get_addr + 4); trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LIMITS_GET, - domain, *min_perf, *max_perf); + dom->id, *min_perf, *max_perf); return 0; } - return scmi_perf_mb_limits_get(ph, domain, max_perf, min_perf); + return scmi_perf_msg_limits_get(ph, dom->id, max_perf, min_perf); } -static int scmi_perf_mb_level_set(const struct scmi_protocol_handle *ph, - u32 domain, u32 level, bool poll) +static int scmi_perf_limits_get(const struct scmi_protocol_handle *ph, + u32 domain, u32 *max_perf, u32 *min_perf) +{ + int ret; + struct perf_dom_info *dom; + + dom = scmi_perf_domain_lookup(ph, domain); + if (IS_ERR(dom)) + return PTR_ERR(dom); + + ret = __scmi_perf_limits_get(ph, dom, max_perf, min_perf); + if (ret) + return ret; + + if (dom->level_indexing_mode) { + struct scmi_opp *opp; + + opp = xa_load(&dom->opps_by_idx, *min_perf); + if (!opp) + return -EIO; + + *min_perf = opp->perf; + + opp = xa_load(&dom->opps_by_idx, *max_perf); + if (!opp) + return -EIO; + + *max_perf = opp->perf; + } + + return 0; +} + +static int scmi_perf_msg_level_set(const struct scmi_protocol_handle *ph, + u32 domain, u32 level, bool poll) { int ret; struct scmi_xfer *t; @@ -464,6 +609,23 @@ static int scmi_perf_mb_level_set(const struct scmi_protocol_handle *ph, return ret; } +static int __scmi_perf_level_set(const struct scmi_protocol_handle *ph, + struct perf_dom_info *dom, u32 level, + bool poll) +{ + if (dom->fc_info && dom->fc_info[PERF_FC_LEVEL].set_addr) { + struct scmi_fc_info *fci = &dom->fc_info[PERF_FC_LEVEL]; + + trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LEVEL_SET, + dom->id, level, 0); + iowrite32(level, fci->set_addr); + ph->hops->fastchannel_db_ring(fci->set_db); + return 0; + } + + return scmi_perf_msg_level_set(ph, dom->id, level, poll); +} + static int scmi_perf_level_set(const struct scmi_protocol_handle *ph, u32 domain, u32 level, bool poll) { @@ -473,21 +635,21 @@ static int scmi_perf_level_set(const struct scmi_protocol_handle *ph, if (IS_ERR(dom)) return PTR_ERR(dom); - if (dom->fc_info && dom->fc_info[PERF_FC_LEVEL].set_addr) { - struct scmi_fc_info *fci = &dom->fc_info[PERF_FC_LEVEL]; + if (dom->level_indexing_mode) { + struct scmi_opp *opp; - trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LEVEL_SET, - domain, level, 0); - iowrite32(level, fci->set_addr); - ph->hops->fastchannel_db_ring(fci->set_db); - return 0; + opp = xa_load(&dom->opps_by_lvl, level); + if (!opp) + return -EIO; + + level = opp->level_index; } - return scmi_perf_mb_level_set(ph, domain, level, poll); + return __scmi_perf_level_set(ph, dom, level, poll); } -static int scmi_perf_mb_level_get(const struct scmi_protocol_handle *ph, - u32 domain, u32 *level, bool poll) +static int scmi_perf_msg_level_get(const struct scmi_protocol_handle *ph, + u32 domain, u32 *level, bool poll) { int ret; struct scmi_xfer *t; @@ -508,23 +670,45 @@ static int scmi_perf_mb_level_get(const struct scmi_protocol_handle *ph, return ret; } +static int __scmi_perf_level_get(const struct scmi_protocol_handle *ph, + struct perf_dom_info *dom, u32 *level, + bool poll) +{ + if (dom->fc_info && dom->fc_info[PERF_FC_LEVEL].get_addr) { + *level = ioread32(dom->fc_info[PERF_FC_LEVEL].get_addr); + trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LEVEL_GET, + dom->id, *level, 0); + return 0; + } + + return scmi_perf_msg_level_get(ph, dom->id, level, poll); +} + static int scmi_perf_level_get(const struct scmi_protocol_handle *ph, u32 domain, u32 *level, bool poll) { + int ret; struct perf_dom_info *dom; dom = scmi_perf_domain_lookup(ph, domain); if (IS_ERR(dom)) return PTR_ERR(dom); - if (dom->fc_info && dom->fc_info[PERF_FC_LEVEL].get_addr) { - *level = ioread32(dom->fc_info[PERF_FC_LEVEL].get_addr); - trace_scmi_fc_call(SCMI_PROTOCOL_PERF, PERF_LEVEL_GET, - domain, *level, 0); - return 0; + ret = __scmi_perf_level_get(ph, dom, level, poll); + if (ret) + return ret; + + if (dom->level_indexing_mode) { + struct scmi_opp *opp; + + opp = xa_load(&dom->opps_by_idx, *level); + if (!opp) + return -EIO; + + *level = opp->perf; } - return scmi_perf_mb_level_get(ph, domain, level, poll); + return 0; } static int scmi_perf_level_limits_notify(const struct scmi_protocol_handle *ph, @@ -608,18 +792,27 @@ static int scmi_dvfs_device_opps_add(const struct scmi_protocol_handle *ph, return PTR_ERR(dom); for (opp = dom->opp, idx = 0; idx < dom->opp_count; idx++, opp++) { - freq = opp->perf * dom->mult_factor; + if (!dom->level_indexing_mode) + freq = opp->perf * dom->mult_factor; + else + freq = opp->indicative_freq * 1000; ret = dev_pm_opp_add(dev, freq, 0); if (ret) { dev_warn(dev, "failed to add opp %luHz\n", freq); while (idx-- > 0) { - freq = (--opp)->perf * dom->mult_factor; + if (!dom->level_indexing_mode) + freq = (--opp)->perf * dom->mult_factor; + else + freq = (--opp)->indicative_freq * 1000; dev_pm_opp_remove(dev, freq); } return ret; } + + dev_dbg(dev, "[%d][%s]:: Registered OPP[%d] %lu\n", + domain, dom->name, idx, freq); } return 0; } @@ -646,13 +839,26 @@ scmi_dvfs_transition_latency_get(const struct scmi_protocol_handle *ph, static int scmi_dvfs_freq_set(const struct scmi_protocol_handle *ph, u32 domain, unsigned long freq, bool poll) { + unsigned int level; struct perf_dom_info *dom; dom = scmi_perf_domain_lookup(ph, domain); if (IS_ERR(dom)) return PTR_ERR(dom); - return scmi_perf_level_set(ph, domain, freq / dom->mult_factor, poll); + if (!dom->level_indexing_mode) { + level = freq / dom->mult_factor; + } else { + struct scmi_opp *opp; + + opp = LOOKUP_BY_FREQ(dom->opps_by_freq, freq / 1000); + if (!opp) + return -EIO; + + level = opp->level_index; + } + + return __scmi_perf_level_set(ph, dom, level, poll); } static int scmi_dvfs_freq_get(const struct scmi_protocol_handle *ph, u32 domain, @@ -660,14 +866,26 @@ static int scmi_dvfs_freq_get(const struct scmi_protocol_handle *ph, u32 domain, { int ret; u32 level; - struct scmi_perf_info *pi = ph->get_priv(ph); + struct perf_dom_info *dom; - ret = scmi_perf_level_get(ph, domain, &level, poll); - if (!ret) { - struct perf_dom_info *dom = pi->dom_info + domain; + dom = scmi_perf_domain_lookup(ph, domain); + if (IS_ERR(dom)) + return PTR_ERR(dom); - /* Note domain is validated implicitly by scmi_perf_level_get */ + ret = __scmi_perf_level_get(ph, dom, &level, poll); + if (ret) + return ret; + + if (!dom->level_indexing_mode) { *freq = level * dom->mult_factor; + } else { + struct scmi_opp *opp; + + opp = xa_load(&dom->opps_by_idx, level); + if (!opp) + return -EIO; + + *freq = opp->indicative_freq * 1000; } return ret; @@ -687,7 +905,11 @@ static int scmi_dvfs_est_power_get(const struct scmi_protocol_handle *ph, return PTR_ERR(dom); for (opp = dom->opp, idx = 0; idx < dom->opp_count; idx++, opp++) { - opp_freq = opp->perf * dom->mult_factor; + if (!dom->level_indexing_mode) + opp_freq = opp->perf * dom->mult_factor; + else + opp_freq = opp->indicative_freq * 1000; + if (opp_freq < *freq) continue; @@ -870,13 +1092,18 @@ static int scmi_perf_protocol_init(const struct scmi_protocol_handle *ph) for (domain = 0; domain < pinfo->num_domains; domain++) { struct perf_dom_info *dom = pinfo->dom_info + domain; - scmi_perf_domain_attributes_get(ph, domain, dom, version); - scmi_perf_describe_levels_get(ph, domain, dom); + dom->id = domain; + scmi_perf_domain_attributes_get(ph, dom, version); + scmi_perf_describe_levels_get(ph, dom, version); if (dom->perf_fastchannels) - scmi_perf_domain_init_fc(ph, domain, &dom->fc_info); + scmi_perf_domain_init_fc(ph, dom->id, &dom->fc_info); } + ret = devm_add_action_or_reset(ph->dev, scmi_perf_xa_destroy, pinfo); + if (ret) + return ret; + pinfo->version = version; return ph->set_priv(ph, pinfo); From 584ed6d4afca4824f3bf18e588cc0cb555278bff Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Fri, 14 Jul 2023 11:51:23 -0600 Subject: [PATCH 089/136] soc: amlogic: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/20230714175124.4066972-1-robh@kernel.org Signed-off-by: Neil Armstrong --- drivers/genpd/amlogic/meson-ee-pwrc.c | 3 +-- drivers/genpd/amlogic/meson-gx-pwrc-vpu.c | 3 +-- drivers/genpd/amlogic/meson-secure-pwrc.c | 2 +- drivers/soc/amlogic/meson-canvas.c | 1 + 4 files changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/genpd/amlogic/meson-ee-pwrc.c b/drivers/genpd/amlogic/meson-ee-pwrc.c index f54acffc83f9..cfb796d40d9d 100644 --- a/drivers/genpd/amlogic/meson-ee-pwrc.c +++ b/drivers/genpd/amlogic/meson-ee-pwrc.c @@ -4,13 +4,12 @@ * Author: Neil Armstrong */ -#include #include #include #include #include #include -#include +#include #include #include #include diff --git a/drivers/genpd/amlogic/meson-gx-pwrc-vpu.c b/drivers/genpd/amlogic/meson-gx-pwrc-vpu.c index 5d4f12800d93..33df520eab95 100644 --- a/drivers/genpd/amlogic/meson-gx-pwrc-vpu.c +++ b/drivers/genpd/amlogic/meson-gx-pwrc-vpu.c @@ -5,13 +5,12 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include #include #include #include #include #include -#include +#include #include #include #include diff --git a/drivers/genpd/amlogic/meson-secure-pwrc.c b/drivers/genpd/amlogic/meson-secure-pwrc.c index a1ffebf70de3..89c881c56cd7 100644 --- a/drivers/genpd/amlogic/meson-secure-pwrc.c +++ b/drivers/genpd/amlogic/meson-secure-pwrc.c @@ -7,7 +7,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt #include -#include +#include #include #include #include diff --git a/drivers/soc/amlogic/meson-canvas.c b/drivers/soc/amlogic/meson-canvas.c index 383b0cfc584e..b6e06c4d2117 100644 --- a/drivers/soc/amlogic/meson-canvas.c +++ b/drivers/soc/amlogic/meson-canvas.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include From f2ed165619c16577c02b703a114a1f6b52026df4 Mon Sep 17 00:00:00 2001 From: Zhang Shurong Date: Sat, 15 Jul 2023 22:13:38 +0800 Subject: [PATCH 090/136] firmware: meson_sm: fix to avoid potential NULL pointer dereference of_match_device() may fail and returns a NULL pointer. Fix this by checking the return value of of_match_device. Fixes: 8cde3c2153e8 ("firmware: meson_sm: Rework driver as a proper platform driver") Signed-off-by: Zhang Shurong Reviewed-by: Neil Armstrong Link: https://lore.kernel.org/r/tencent_AA08AAA6C4F34D53ADCE962E188A879B8206@qq.com Signed-off-by: Neil Armstrong --- drivers/firmware/meson/meson_sm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/firmware/meson/meson_sm.c b/drivers/firmware/meson/meson_sm.c index 798bcdb05d84..9a2656d73600 100644 --- a/drivers/firmware/meson/meson_sm.c +++ b/drivers/firmware/meson/meson_sm.c @@ -292,6 +292,8 @@ static int __init meson_sm_probe(struct platform_device *pdev) return -ENOMEM; chip = of_match_device(meson_sm_ids, dev)->data; + if (!chip) + return -EINVAL; if (chip->cmd_shmem_in_base) { fw->sm_shmem_in_base = meson_sm_map_shmem(chip->cmd_shmem_in_base, From 35bd78cf252245f11dd1c9d5f1b414c25e727b5a Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Tue, 1 Aug 2023 17:40:23 +0530 Subject: [PATCH 091/136] memory: tegra: add MC client for Tegra234 GPU Add the Non-ISO MC client for the Tegra234 GPU to the tegra234_mc_clients table. Signed-off-by: Sumit Gupta Link: https://lore.kernel.org/r/20230801121023.27841-1-sumitg@nvidia.com Signed-off-by: Krzysztof Kozlowski --- drivers/memory/tegra/tegra234.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c index 7954f339ca79..9e5b5dbd9c8d 100644 --- a/drivers/memory/tegra/tegra234.c +++ b/drivers/memory/tegra/tegra234.c @@ -916,6 +916,16 @@ static const struct tegra_mc_client tegra234_mc_clients[] = { .name = "sw_cluster2", .bpmp_id = TEGRA_ICC_BPMP_CPU_CLUSTER2, .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVL1R, + .name = "nvl1r", + .bpmp_id = TEGRA_ICC_BPMP_GPU, + .type = TEGRA_ICC_NISO, + }, { + .id = TEGRA234_MEMORY_CLIENT_NVL1W, + .name = "nvl1w", + .bpmp_id = TEGRA_ICC_BPMP_GPU, + .type = TEGRA_ICC_NISO, }, }; From 23e9bf8e78ba2ed32e9bf5a37c5074b9dfc29110 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Thu, 3 Aug 2023 16:43:01 -0600 Subject: [PATCH 092/136] soc: sunxi: Explicitly include correct DT includes The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Acked-by: Jernej Skrabec Link: https://lore.kernel.org/r/20230803-dt-header-cleanups-for-soc-v2-21-d8de2cc88bff@kernel.org Signed-off-by: Jernej Skrabec --- drivers/soc/sunxi/sunxi_sram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c index 4c4864cd2342..4458b2e0562b 100644 --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -15,7 +15,7 @@ #include #include #include -#include +#include #include #include From 886bdf9c883bcc9bfb0a0bc0ed27680e68c8b6c2 Mon Sep 17 00:00:00 2001 From: Huisong Li Date: Tue, 8 Aug 2023 10:36:38 +0800 Subject: [PATCH 093/136] soc: hisilicon: Support HCCS driver on Kunpeng SoC The Huawei Cache Coherence System (HCCS) is a multi-chip interconnection bus protocol. This driver is aimed to support some features about HCCS on Kunpeng SoC, like, querying the health status of HCCS. This patch adds the probing of HCCS driver, and obtains all HCCS port information by the dimension of chip and die on platform. Signed-off-by: Huisong Li Signed-off-by: Wei Xu --- MAINTAINERS | 6 + drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/hisilicon/Kconfig | 20 + drivers/soc/hisilicon/Makefile | 2 + drivers/soc/hisilicon/kunpeng_hccs.c | 637 +++++++++++++++++++++++++++ drivers/soc/hisilicon/kunpeng_hccs.h | 169 +++++++ 7 files changed, 836 insertions(+) create mode 100644 drivers/soc/hisilicon/Kconfig create mode 100644 drivers/soc/hisilicon/Makefile create mode 100644 drivers/soc/hisilicon/kunpeng_hccs.c create mode 100644 drivers/soc/hisilicon/kunpeng_hccs.h diff --git a/MAINTAINERS b/MAINTAINERS index 3be1bdfe8ecc..8607360e77b7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9307,6 +9307,12 @@ W: https://www.hisilicon.com F: Documentation/devicetree/bindings/i2c/hisilicon,ascend910-i2c.yaml F: drivers/i2c/busses/i2c-hisi.c +HISILICON KUNPENG SOC HCCS DRIVER +M: Huisong Li +S: Maintained +F: drivers/soc/hisilicon/kunpeng_hccs.c +F: drivers/soc/hisilicon/kunpeng_hccs.h + HISILICON LPC BUS DRIVER M: Jay Fang S: Maintained diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig index 4e176280113a..d21e75d69294 100644 --- a/drivers/soc/Kconfig +++ b/drivers/soc/Kconfig @@ -10,6 +10,7 @@ source "drivers/soc/bcm/Kconfig" source "drivers/soc/canaan/Kconfig" source "drivers/soc/fsl/Kconfig" source "drivers/soc/fujitsu/Kconfig" +source "drivers/soc/hisilicon/Kconfig" source "drivers/soc/imx/Kconfig" source "drivers/soc/ixp4xx/Kconfig" source "drivers/soc/litex/Kconfig" diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile index 3b0f9fb3b5c8..531f46f3ad98 100644 --- a/drivers/soc/Makefile +++ b/drivers/soc/Makefile @@ -14,6 +14,7 @@ obj-$(CONFIG_MACH_DOVE) += dove/ obj-y += fsl/ obj-y += fujitsu/ obj-$(CONFIG_ARCH_GEMINI) += gemini/ +obj-y += hisilicon/ obj-y += imx/ obj-y += ixp4xx/ obj-$(CONFIG_SOC_XWAY) += lantiq/ diff --git a/drivers/soc/hisilicon/Kconfig b/drivers/soc/hisilicon/Kconfig new file mode 100644 index 000000000000..7c84dd4da0f8 --- /dev/null +++ b/drivers/soc/hisilicon/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0-only + +menu "Hisilicon SoC drivers" + depends on ARCH_HISI || COMPILE_TEST + +config KUNPENG_HCCS + tristate "HCCS driver on Kunpeng SoC" + depends on ACPI + depends on ARM64 || COMPILE_TEST + help + The Huawei Cache Coherence System (HCCS) is a multi-chip + interconnection bus protocol. + The performance of application may be affected if some HCCS + ports are not in full lane status, have a large number of CRC + errors and so on. + + Say M here if you want to include support for querying the + health status and port information of HCCS on Kunpeng SoC. + +endmenu diff --git a/drivers/soc/hisilicon/Makefile b/drivers/soc/hisilicon/Makefile new file mode 100644 index 000000000000..226e747e70d6 --- /dev/null +++ b/drivers/soc/hisilicon/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-$(CONFIG_KUNPENG_HCCS) += kunpeng_hccs.o diff --git a/drivers/soc/hisilicon/kunpeng_hccs.c b/drivers/soc/hisilicon/kunpeng_hccs.c new file mode 100644 index 000000000000..b61de32ce00c --- /dev/null +++ b/drivers/soc/hisilicon/kunpeng_hccs.c @@ -0,0 +1,637 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * The Huawei Cache Coherence System (HCCS) is a multi-chip interconnection + * bus protocol. + * + * Copyright (c) 2023 Hisilicon Limited. + * Author: Huisong Li + */ +#include +#include +#include + +#include + +#include "kunpeng_hccs.h" + +/* PCC defines */ +#define HCCS_PCC_SIGNATURE_MASK 0x50434300 +#define HCCS_PCC_STATUS_CMD_COMPLETE BIT(0) + +/* + * Arbitrary retries in case the remote processor is slow to respond + * to PCC commands + */ +#define HCCS_PCC_CMD_WAIT_RETRIES_NUM 500ULL +#define HCCS_POLL_STATUS_TIME_INTERVAL_US 3 + +struct hccs_register_ctx { + struct device *dev; + u8 chan_id; + int err; +}; + +static acpi_status hccs_get_register_cb(struct acpi_resource *ares, + void *context) +{ + struct acpi_resource_generic_register *reg; + struct hccs_register_ctx *ctx = context; + + if (ares->type != ACPI_RESOURCE_TYPE_GENERIC_REGISTER) + return AE_OK; + + reg = &ares->data.generic_reg; + if (reg->space_id != ACPI_ADR_SPACE_PLATFORM_COMM) { + dev_err(ctx->dev, "Bad register resource.\n"); + ctx->err = -EINVAL; + return AE_ERROR; + } + ctx->chan_id = reg->access_size; + + return AE_OK; +} + +static int hccs_get_pcc_chan_id(struct hccs_dev *hdev) +{ + acpi_handle handle = ACPI_HANDLE(hdev->dev); + struct hccs_register_ctx ctx = {0}; + acpi_status status; + + if (!acpi_has_method(handle, METHOD_NAME__CRS)) + return -ENODEV; + + ctx.dev = hdev->dev; + status = acpi_walk_resources(handle, METHOD_NAME__CRS, + hccs_get_register_cb, &ctx); + if (ACPI_FAILURE(status)) + return ctx.err; + hdev->chan_id = ctx.chan_id; + + return 0; +} + +static void hccs_chan_tx_done(struct mbox_client *cl, void *msg, int ret) +{ + if (ret < 0) + pr_debug("TX did not complete: CMD sent:0x%x, ret:%d\n", + *(u8 *)msg, ret); + else + pr_debug("TX completed. CMD sent:0x%x, ret:%d\n", + *(u8 *)msg, ret); +} + +static void hccs_unregister_pcc_channel(struct hccs_dev *hdev) +{ + struct hccs_mbox_client_info *cl_info = &hdev->cl_info; + + if (cl_info->pcc_comm_addr) + iounmap(cl_info->pcc_comm_addr); + pcc_mbox_free_channel(hdev->cl_info.pcc_chan); +} + +static int hccs_register_pcc_channel(struct hccs_dev *hdev) +{ + struct hccs_mbox_client_info *cl_info = &hdev->cl_info; + struct mbox_client *cl = &cl_info->client; + struct pcc_mbox_chan *pcc_chan; + struct device *dev = hdev->dev; + int rc; + + cl->dev = dev; + cl->tx_block = false; + cl->knows_txdone = true; + cl->tx_done = hccs_chan_tx_done; + pcc_chan = pcc_mbox_request_channel(cl, hdev->chan_id); + if (IS_ERR(pcc_chan)) { + dev_err(dev, "PPC channel request failed.\n"); + rc = -ENODEV; + goto out; + } + cl_info->pcc_chan = pcc_chan; + cl_info->mbox_chan = pcc_chan->mchan; + + /* + * pcc_chan->latency is just a nominal value. In reality the remote + * processor could be much slower to reply. So add an arbitrary amount + * of wait on top of nominal. + */ + cl_info->deadline_us = + HCCS_PCC_CMD_WAIT_RETRIES_NUM * pcc_chan->latency; + if (cl_info->mbox_chan->mbox->txdone_irq) { + dev_err(dev, "PCC IRQ in PCCT is enabled.\n"); + rc = -EINVAL; + goto err_mbx_channel_free; + } + + if (pcc_chan->shmem_base_addr) { + cl_info->pcc_comm_addr = (void __force *)ioremap( + pcc_chan->shmem_base_addr, pcc_chan->shmem_size); + if (!cl_info->pcc_comm_addr) { + dev_err(dev, "Failed to ioremap PCC communication region for channel-%d.\n", + hdev->chan_id); + rc = -ENOMEM; + goto err_mbx_channel_free; + } + } + + return 0; + +err_mbx_channel_free: + pcc_mbox_free_channel(cl_info->pcc_chan); +out: + return rc; +} + +static int hccs_check_chan_cmd_complete(struct hccs_dev *hdev) +{ + struct hccs_mbox_client_info *cl_info = &hdev->cl_info; + struct acpi_pcct_shared_memory *comm_base = cl_info->pcc_comm_addr; + u16 status; + int ret; + + /* + * Poll PCC status register every 3us(delay_us) for maximum of + * deadline_us(timeout_us) until PCC command complete bit is set(cond) + */ + ret = readw_poll_timeout(&comm_base->status, status, + status & HCCS_PCC_STATUS_CMD_COMPLETE, + HCCS_POLL_STATUS_TIME_INTERVAL_US, + cl_info->deadline_us); + if (unlikely(ret)) + dev_err(hdev->dev, "poll PCC status failed, ret = %d.\n", ret); + + return ret; +} + +static int hccs_pcc_cmd_send(struct hccs_dev *hdev, u8 cmd, + struct hccs_desc *desc) +{ + struct hccs_mbox_client_info *cl_info = &hdev->cl_info; + struct acpi_pcct_shared_memory *comm_base = cl_info->pcc_comm_addr; + void *comm_space = (void *)(comm_base + 1); + struct hccs_fw_inner_head *fw_inner_head; + struct acpi_pcct_shared_memory tmp = {0}; + u16 comm_space_size; + int ret; + + /* Write signature for this subspace */ + tmp.signature = HCCS_PCC_SIGNATURE_MASK | hdev->chan_id; + /* Write to the shared command region */ + tmp.command = cmd; + /* Clear cmd complete bit */ + tmp.status = 0; + memcpy_toio(comm_base, (void *)&tmp, + sizeof(struct acpi_pcct_shared_memory)); + + /* Copy the message to the PCC comm space */ + comm_space_size = HCCS_PCC_SHARE_MEM_BYTES - + sizeof(struct acpi_pcct_shared_memory); + memcpy_toio(comm_space, (void *)desc, comm_space_size); + + /* Ring doorbell */ + ret = mbox_send_message(cl_info->mbox_chan, &cmd); + if (ret < 0) { + dev_err(hdev->dev, "Send PCC mbox message failed, ret = %d.\n", + ret); + goto end; + } + + /* Wait for completion */ + ret = hccs_check_chan_cmd_complete(hdev); + if (ret) + goto end; + + /* Copy response data */ + memcpy_fromio((void *)desc, comm_space, comm_space_size); + fw_inner_head = &desc->rsp.fw_inner_head; + if (fw_inner_head->retStatus) { + dev_err(hdev->dev, "Execute PCC command failed, error code = %u.\n", + fw_inner_head->retStatus); + ret = -EIO; + } + +end: + mbox_client_txdone(cl_info->mbox_chan, ret); + return ret; +} + +static void hccs_init_req_desc(struct hccs_desc *desc) +{ + struct hccs_req_desc *req = &desc->req; + + memset(desc, 0, sizeof(*desc)); + req->req_head.module_code = HCCS_SERDES_MODULE_CODE; +} + +static int hccs_get_dev_caps(struct hccs_dev *hdev) +{ + struct hccs_desc desc; + int ret; + + hccs_init_req_desc(&desc); + ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DEV_CAP, &desc); + if (ret) { + dev_err(hdev->dev, "Get device capabilities failed, ret = %d.\n", + ret); + return ret; + } + memcpy(&hdev->caps, desc.rsp.data, sizeof(hdev->caps)); + + return 0; +} + +static int hccs_query_chip_num_on_platform(struct hccs_dev *hdev) +{ + struct hccs_desc desc; + int ret; + + hccs_init_req_desc(&desc); + ret = hccs_pcc_cmd_send(hdev, HCCS_GET_CHIP_NUM, &desc); + if (ret) { + dev_err(hdev->dev, "query system chip number failed, ret = %d.\n", + ret); + return ret; + } + + hdev->chip_num = *((u8 *)&desc.rsp.data); + if (!hdev->chip_num) { + dev_err(hdev->dev, "chip num obtained from firmware is zero.\n"); + return -EINVAL; + } + + return 0; +} + +static int hccs_get_chip_info(struct hccs_dev *hdev, + struct hccs_chip_info *chip) +{ + struct hccs_die_num_req_param *req_param; + struct hccs_desc desc; + int ret; + + hccs_init_req_desc(&desc); + req_param = (struct hccs_die_num_req_param *)desc.req.data; + req_param->chip_id = chip->chip_id; + ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_NUM, &desc); + if (ret) + return ret; + + chip->die_num = *((u8 *)&desc.rsp.data); + + return 0; +} + +static int hccs_query_chip_info_on_platform(struct hccs_dev *hdev) +{ + struct hccs_chip_info *chip; + int ret; + u8 idx; + + ret = hccs_query_chip_num_on_platform(hdev); + if (ret) { + dev_err(hdev->dev, "query chip number on platform failed, ret = %d.\n", + ret); + return ret; + } + + hdev->chips = devm_kzalloc(hdev->dev, + hdev->chip_num * sizeof(struct hccs_chip_info), + GFP_KERNEL); + if (!hdev->chips) { + dev_err(hdev->dev, "allocate all chips memory failed.\n"); + return -ENOMEM; + } + + for (idx = 0; idx < hdev->chip_num; idx++) { + chip = &hdev->chips[idx]; + chip->chip_id = idx; + ret = hccs_get_chip_info(hdev, chip); + if (ret) { + dev_err(hdev->dev, "get chip%u info failed, ret = %d.\n", + idx, ret); + return ret; + } + chip->hdev = hdev; + } + + return 0; +} + +static int hccs_query_die_info_on_chip(struct hccs_dev *hdev, u8 chip_id, + u8 die_idx, struct hccs_die_info *die) +{ + struct hccs_die_info_req_param *req_param; + struct hccs_die_info_rsp_data *rsp_data; + struct hccs_desc desc; + int ret; + + hccs_init_req_desc(&desc); + req_param = (struct hccs_die_info_req_param *)desc.req.data; + req_param->chip_id = chip_id; + req_param->die_idx = die_idx; + ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_INFO, &desc); + if (ret) + return ret; + + rsp_data = (struct hccs_die_info_rsp_data *)desc.rsp.data; + die->die_id = rsp_data->die_id; + die->port_num = rsp_data->port_num; + die->min_port_id = rsp_data->min_port_id; + die->max_port_id = rsp_data->max_port_id; + if (die->min_port_id > die->max_port_id) { + dev_err(hdev->dev, "min port id(%u) > max port id(%u) on die_idx(%u).\n", + die->min_port_id, die->max_port_id, die_idx); + return -EINVAL; + } + if (die->max_port_id > HCCS_DIE_MAX_PORT_ID) { + dev_err(hdev->dev, "max port id(%u) on die_idx(%u) is too big.\n", + die->max_port_id, die_idx); + return -EINVAL; + } + + return 0; +} + +static int hccs_query_all_die_info_on_platform(struct hccs_dev *hdev) +{ + struct device *dev = hdev->dev; + struct hccs_chip_info *chip; + struct hccs_die_info *die; + u8 i, j; + int ret; + + for (i = 0; i < hdev->chip_num; i++) { + chip = &hdev->chips[i]; + if (!chip->die_num) + continue; + + chip->dies = devm_kzalloc(hdev->dev, + chip->die_num * sizeof(struct hccs_die_info), + GFP_KERNEL); + if (!chip->dies) { + dev_err(dev, "allocate all dies memory on chip%u failed.\n", + i); + return -ENOMEM; + } + + for (j = 0; j < chip->die_num; j++) { + die = &chip->dies[j]; + ret = hccs_query_die_info_on_chip(hdev, i, j, die); + if (ret) { + dev_err(dev, "get die idx (%u) info on chip%u failed, ret = %d.\n", + j, i, ret); + return ret; + } + die->chip = chip; + } + } + + return 0; +} + +static int hccs_get_bd_info(struct hccs_dev *hdev, u8 opcode, + struct hccs_desc *desc, + void *buf, size_t buf_len, + struct hccs_rsp_head *rsp_head) +{ + struct hccs_rsp_head *head; + struct hccs_rsp_desc *rsp; + int ret; + + ret = hccs_pcc_cmd_send(hdev, opcode, desc); + if (ret) + return ret; + + rsp = &desc->rsp; + head = &rsp->rsp_head; + if (head->data_len > buf_len) { + dev_err(hdev->dev, + "buffer overflow (buf_len = %lu, data_len = %u)!\n", + buf_len, head->data_len); + return -ENOMEM; + } + + memcpy(buf, rsp->data, head->data_len); + *rsp_head = *head; + + return 0; +} + +static int hccs_get_all_port_attr(struct hccs_dev *hdev, + struct hccs_die_info *die, + struct hccs_port_attr *attrs, u16 size) +{ + struct hccs_die_comm_req_param *req_param; + struct hccs_req_head *req_head; + struct hccs_rsp_head rsp_head; + struct hccs_desc desc; + size_t left_buf_len; + u32 data_len = 0; + u8 start_id; + u8 *buf; + int ret; + + buf = (u8 *)attrs; + left_buf_len = sizeof(struct hccs_port_attr) * size; + start_id = die->min_port_id; + while (start_id <= die->max_port_id) { + hccs_init_req_desc(&desc); + req_head = &desc.req.req_head; + req_head->start_id = start_id; + req_param = (struct hccs_die_comm_req_param *)desc.req.data; + req_param->chip_id = die->chip->chip_id; + req_param->die_id = die->die_id; + + ret = hccs_get_bd_info(hdev, HCCS_GET_DIE_PORT_INFO, &desc, + buf + data_len, left_buf_len, &rsp_head); + if (ret) { + dev_err(hdev->dev, + "get the information of port%u on die%u failed, ret = %d.\n", + start_id, die->die_id, ret); + return ret; + } + + data_len += rsp_head.data_len; + left_buf_len -= rsp_head.data_len; + if (unlikely(rsp_head.next_id <= start_id)) { + dev_err(hdev->dev, + "next port id (%u) is not greater than last start id (%u) on die%u.\n", + rsp_head.next_id, start_id, die->die_id); + return -EINVAL; + } + start_id = rsp_head.next_id; + } + + return 0; +} + +static int hccs_get_all_port_info_on_die(struct hccs_dev *hdev, + struct hccs_die_info *die) +{ + struct hccs_port_attr *attrs; + struct hccs_port_info *port; + int ret; + u8 i; + + attrs = kcalloc(die->port_num, sizeof(struct hccs_port_attr), + GFP_KERNEL); + if (!attrs) + return -ENOMEM; + + ret = hccs_get_all_port_attr(hdev, die, attrs, die->port_num); + if (ret) + goto out; + + for (i = 0; i < die->port_num; i++) { + port = &die->ports[i]; + port->port_id = attrs[i].port_id; + port->port_type = attrs[i].port_type; + port->lane_mode = attrs[i].lane_mode; + port->enable = attrs[i].enable; + port->die = die; + } + +out: + kfree(attrs); + return ret; +} + +static int hccs_query_all_port_info_on_platform(struct hccs_dev *hdev) +{ + + struct device *dev = hdev->dev; + struct hccs_chip_info *chip; + struct hccs_die_info *die; + u8 i, j; + int ret; + + for (i = 0; i < hdev->chip_num; i++) { + chip = &hdev->chips[i]; + for (j = 0; j < chip->die_num; j++) { + die = &chip->dies[j]; + if (!die->port_num) + continue; + + die->ports = devm_kzalloc(dev, + die->port_num * sizeof(struct hccs_port_info), + GFP_KERNEL); + if (!die->ports) { + dev_err(dev, "allocate ports memory on chip%u/die%u failed.\n", + i, die->die_id); + return -ENOMEM; + } + + ret = hccs_get_all_port_info_on_die(hdev, die); + if (ret) { + dev_err(dev, "get all port info on chip%u/die%u failed, ret = %d.\n", + i, die->die_id, ret); + return ret; + } + } + } + + return 0; +} + +static int hccs_get_hw_info(struct hccs_dev *hdev) +{ + int ret; + + ret = hccs_query_chip_info_on_platform(hdev); + if (ret) { + dev_err(hdev->dev, "query chip info on platform failed, ret = %d.\n", + ret); + return ret; + } + + ret = hccs_query_all_die_info_on_platform(hdev); + if (ret) { + dev_err(hdev->dev, "query all die info on platform failed, ret = %d.\n", + ret); + return ret; + } + + ret = hccs_query_all_port_info_on_platform(hdev); + if (ret) { + dev_err(hdev->dev, "query all port info on platform failed, ret = %d.\n", + ret); + return ret; + } + + return 0; +} + +static int hccs_probe(struct platform_device *pdev) +{ + struct acpi_device *acpi_dev; + struct hccs_dev *hdev; + int rc; + + if (acpi_disabled) { + dev_err(&pdev->dev, "acpi is disabled.\n"); + return -ENODEV; + } + acpi_dev = ACPI_COMPANION(&pdev->dev); + if (!acpi_dev) + return -ENODEV; + + hdev = devm_kzalloc(&pdev->dev, sizeof(*hdev), GFP_KERNEL); + if (!hdev) + return -ENOMEM; + hdev->acpi_dev = acpi_dev; + hdev->dev = &pdev->dev; + platform_set_drvdata(pdev, hdev); + + mutex_init(&hdev->lock); + rc = hccs_get_pcc_chan_id(hdev); + if (rc) + return rc; + rc = hccs_register_pcc_channel(hdev); + if (rc) + return rc; + + rc = hccs_get_dev_caps(hdev); + if (rc) + goto unregister_pcc_chan; + + rc = hccs_get_hw_info(hdev); + if (rc) + goto unregister_pcc_chan; + + return 0; + +unregister_pcc_chan: + hccs_unregister_pcc_channel(hdev); + + return rc; +} + +static int hccs_remove(struct platform_device *pdev) +{ + struct hccs_dev *hdev = platform_get_drvdata(pdev); + + hccs_unregister_pcc_channel(hdev); + + return 0; +} + +static const struct acpi_device_id hccs_acpi_match[] = { + { "HISI04B1"}, + { ""}, +}; +MODULE_DEVICE_TABLE(acpi, hccs_acpi_match); + +static struct platform_driver hccs_driver = { + .probe = hccs_probe, + .remove = hccs_remove, + .driver = { + .name = "kunpeng_hccs", + .acpi_match_table = hccs_acpi_match, + }, +}; + +module_platform_driver(hccs_driver); + +MODULE_DESCRIPTION("Kunpeng SoC HCCS driver"); +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Huisong Li "); diff --git a/drivers/soc/hisilicon/kunpeng_hccs.h b/drivers/soc/hisilicon/kunpeng_hccs.h new file mode 100644 index 000000000000..fcc95e7e2a60 --- /dev/null +++ b/drivers/soc/hisilicon/kunpeng_hccs.h @@ -0,0 +1,169 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* Copyright (c) 2023 Hisilicon Limited. */ + +#ifndef __KUNPENG_HCCS_H__ +#define __KUNPENG_HCCS_H__ + +/* + * |--------------- Chip0 ---------------|---------------- ChipN -------------| + * |--------Die0-------|--------DieN-------|--------Die0-------|-------DieN-------| + * | P0 | P1 | P2 | P3 | P0 | P1 | P2 | P3 | P0 | P1 | P2 | P3 |P0 | P1 | P2 | P3 | + */ + +/* + * This value cannot be 255, otherwise the loop of the multi-BD communication + * case cannot end. + */ +#define HCCS_DIE_MAX_PORT_ID 254 + +struct hccs_port_info { + u8 port_id; + u8 port_type; + u8 lane_mode; + bool enable; /* if the port is enabled */ + struct hccs_die_info *die; /* point to the die the port is located */ +}; + +struct hccs_die_info { + u8 die_id; + u8 port_num; + u8 min_port_id; + u8 max_port_id; + struct hccs_port_info *ports; + struct hccs_chip_info *chip; /* point to the chip the die is located */ +}; + +struct hccs_chip_info { + u8 chip_id; + u8 die_num; + struct hccs_die_info *dies; + struct hccs_dev *hdev; +}; + +struct hccs_mbox_client_info { + struct mbox_client client; + struct mbox_chan *mbox_chan; + struct pcc_mbox_chan *pcc_chan; + u64 deadline_us; + void *pcc_comm_addr; +}; + +struct hccs_dev { + struct device *dev; + struct acpi_device *acpi_dev; + u64 caps; + u8 chip_num; + struct hccs_chip_info *chips; + u8 chan_id; + struct mutex lock; + struct hccs_mbox_client_info cl_info; +}; + +#define HCCS_SERDES_MODULE_CODE 0x32 +enum hccs_subcmd_type { + HCCS_GET_CHIP_NUM = 0x1, + HCCS_GET_DIE_NUM, + HCCS_GET_DIE_INFO, + HCCS_GET_DIE_PORT_INFO, + HCCS_GET_DEV_CAP, + HCCS_GET_PORT_LINK_STATUS, + HCCS_GET_PORT_CRC_ERR_CNT, + HCCS_GET_DIE_PORTS_LANE_STA, + HCCS_GET_DIE_PORTS_LINK_STA, + HCCS_GET_DIE_PORTS_CRC_ERR_CNT, + HCCS_SUB_CMD_MAX = 255, +}; + +struct hccs_die_num_req_param { + u8 chip_id; +}; + +struct hccs_die_info_req_param { + u8 chip_id; + u8 die_idx; +}; + +struct hccs_die_info_rsp_data { + u8 die_id; + u8 port_num; + u8 min_port_id; + u8 max_port_id; +}; + +struct hccs_port_attr { + u8 port_id; + u8 port_type; + u8 lane_mode; + u8 enable : 1; /* if the port is enabled */ + u16 rsv[2]; +}; + +/* + * The common command request for getting the information of all HCCS port on + * specified DIE. + */ +struct hccs_die_comm_req_param { + u8 chip_id; + u8 die_id; /* id in hardware */ +}; + +struct hccs_req_head { + u8 module_code; /* set to 0x32 for serdes */ + u8 start_id; + u8 rsv[2]; +}; + +struct hccs_rsp_head { + u8 data_len; + u8 next_id; + u8 rsv[2]; +}; + +struct hccs_fw_inner_head { + u8 retStatus; /* 0: success, other: failure */ + u8 rsv[7]; +}; + +#define HCCS_PCC_SHARE_MEM_BYTES 64 +#define HCCS_FW_INNER_HEAD_BYTES 8 +#define HCCS_RSP_HEAD_BYTES 4 + +#define HCCS_MAX_RSP_DATA_BYTES (HCCS_PCC_SHARE_MEM_BYTES - \ + HCCS_FW_INNER_HEAD_BYTES - \ + HCCS_RSP_HEAD_BYTES) +#define HCCS_MAX_RSP_DATA_SIZE_MAX (HCCS_MAX_RSP_DATA_BYTES / 4) + +/* + * Note: Actual available size of data field also depands on the PCC header + * bytes of the specific type. Driver needs to copy the response data in the + * communication space based on the real length. + */ +struct hccs_rsp_desc { + struct hccs_fw_inner_head fw_inner_head; /* 8 Bytes */ + struct hccs_rsp_head rsp_head; /* 4 Bytes */ + u32 data[HCCS_MAX_RSP_DATA_SIZE_MAX]; +}; + +#define HCCS_REQ_HEAD_BYTES 4 +#define HCCS_MAX_REQ_DATA_BYTES (HCCS_PCC_SHARE_MEM_BYTES - \ + HCCS_REQ_HEAD_BYTES) +#define HCCS_MAX_REQ_DATA_SIZE_MAX (HCCS_MAX_REQ_DATA_BYTES / 4) + +/* + * Note: Actual available size of data field also depands on the PCC header + * bytes of the specific type. Driver needs to copy the request data to the + * communication space based on the real length. + */ +struct hccs_req_desc { + struct hccs_req_head req_head; /* 4 Bytes */ + u32 data[HCCS_MAX_REQ_DATA_SIZE_MAX]; +}; + +struct hccs_desc { + union { + struct hccs_req_desc req; + struct hccs_rsp_desc rsp; + }; +}; + +#endif /* __KUNPENG_HCCS_H__ */ From 47f7a25533cea268e663be7b84fef933e40692c4 Mon Sep 17 00:00:00 2001 From: Huisong Li Date: Tue, 8 Aug 2023 10:36:39 +0800 Subject: [PATCH 094/136] soc: hisilicon: add sysfs entry to query information of HCCS This patch creates chip, die and port directory based on the actual hardware implementation of platform. Some sysfs entries under these directories are created to query the health status and port information of HCCS. Signed-off-by: Huisong Li Signed-off-by: Wei Xu --- drivers/soc/hisilicon/kunpeng_hccs.c | 638 +++++++++++++++++++++++++++ drivers/soc/hisilicon/kunpeng_hccs.h | 22 + 2 files changed, 660 insertions(+) diff --git a/drivers/soc/hisilicon/kunpeng_hccs.c b/drivers/soc/hisilicon/kunpeng_hccs.c index b61de32ce00c..6864d203c678 100644 --- a/drivers/soc/hisilicon/kunpeng_hccs.c +++ b/drivers/soc/hisilicon/kunpeng_hccs.c @@ -5,10 +5,27 @@ * * Copyright (c) 2023 Hisilicon Limited. * Author: Huisong Li + * + * HCCS driver for Kunpeng SoC provides the following features: + * - Retrieve the following information about each port: + * - port type + * - lane mode + * - enable + * - current lane mode + * - link finite state machine + * - lane mask + * - CRC error count + * + * - Retrieve the following information about all the ports on the chip or + * the die: + * - if all enabled ports are in linked + * - if all linked ports are in full lane + * - CRC error count sum */ #include #include #include +#include #include @@ -25,6 +42,21 @@ #define HCCS_PCC_CMD_WAIT_RETRIES_NUM 500ULL #define HCCS_POLL_STATUS_TIME_INTERVAL_US 3 +static struct hccs_port_info *kobj_to_port_info(struct kobject *k) +{ + return container_of(k, struct hccs_port_info, kobj); +} + +static struct hccs_die_info *kobj_to_die_info(struct kobject *k) +{ + return container_of(k, struct hccs_die_info, kobj); +} + +static struct hccs_chip_info *kobj_to_chip_info(struct kobject *k) +{ + return container_of(k, struct hccs_chip_info, kobj); +} + struct hccs_register_ctx { struct device *dev; u8 chan_id; @@ -561,6 +593,607 @@ static int hccs_get_hw_info(struct hccs_dev *hdev) return 0; } +static int hccs_query_port_link_status(struct hccs_dev *hdev, + const struct hccs_port_info *port, + struct hccs_link_status *link_status) +{ + const struct hccs_die_info *die = port->die; + const struct hccs_chip_info *chip = die->chip; + struct hccs_port_comm_req_param *req_param; + struct hccs_desc desc; + int ret; + + hccs_init_req_desc(&desc); + req_param = (struct hccs_port_comm_req_param *)desc.req.data; + req_param->chip_id = chip->chip_id; + req_param->die_id = die->die_id; + req_param->port_id = port->port_id; + ret = hccs_pcc_cmd_send(hdev, HCCS_GET_PORT_LINK_STATUS, &desc); + if (ret) { + dev_err(hdev->dev, + "get port link status info failed, ret = %d.\n", ret); + return ret; + } + + *link_status = *((struct hccs_link_status *)desc.rsp.data); + + return 0; +} + +static int hccs_query_port_crc_err_cnt(struct hccs_dev *hdev, + const struct hccs_port_info *port, + u64 *crc_err_cnt) +{ + const struct hccs_die_info *die = port->die; + const struct hccs_chip_info *chip = die->chip; + struct hccs_port_comm_req_param *req_param; + struct hccs_desc desc; + int ret; + + hccs_init_req_desc(&desc); + req_param = (struct hccs_port_comm_req_param *)desc.req.data; + req_param->chip_id = chip->chip_id; + req_param->die_id = die->die_id; + req_param->port_id = port->port_id; + ret = hccs_pcc_cmd_send(hdev, HCCS_GET_PORT_CRC_ERR_CNT, &desc); + if (ret) { + dev_err(hdev->dev, + "get port crc error count failed, ret = %d.\n", ret); + return ret; + } + + memcpy(crc_err_cnt, &desc.rsp.data, sizeof(u64)); + + return 0; +} + +static int hccs_get_die_all_link_status(struct hccs_dev *hdev, + const struct hccs_die_info *die, + u8 *all_linked) +{ + struct hccs_die_comm_req_param *req_param; + struct hccs_desc desc; + int ret; + + if (die->port_num == 0) { + *all_linked = 1; + return 0; + } + + hccs_init_req_desc(&desc); + req_param = (struct hccs_die_comm_req_param *)desc.req.data; + req_param->chip_id = die->chip->chip_id; + req_param->die_id = die->die_id; + ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_PORTS_LINK_STA, &desc); + if (ret) { + dev_err(hdev->dev, + "get link status of all ports failed on die%u, ret = %d.\n", + die->die_id, ret); + return ret; + } + + *all_linked = *((u8 *)&desc.rsp.data); + + return 0; +} + +static int hccs_get_die_all_port_lane_status(struct hccs_dev *hdev, + const struct hccs_die_info *die, + u8 *full_lane) +{ + struct hccs_die_comm_req_param *req_param; + struct hccs_desc desc; + int ret; + + if (die->port_num == 0) { + *full_lane = 1; + return 0; + } + + hccs_init_req_desc(&desc); + req_param = (struct hccs_die_comm_req_param *)desc.req.data; + req_param->chip_id = die->chip->chip_id; + req_param->die_id = die->die_id; + ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_PORTS_LANE_STA, &desc); + if (ret) { + dev_err(hdev->dev, "get lane status of all ports failed on die%u, ret = %d.\n", + die->die_id, ret); + return ret; + } + + *full_lane = *((u8 *)&desc.rsp.data); + + return 0; +} + +static int hccs_get_die_total_crc_err_cnt(struct hccs_dev *hdev, + const struct hccs_die_info *die, + u64 *total_crc_err_cnt) +{ + struct hccs_die_comm_req_param *req_param; + struct hccs_desc desc; + int ret; + + if (die->port_num == 0) { + *total_crc_err_cnt = 0; + return 0; + } + + hccs_init_req_desc(&desc); + req_param = (struct hccs_die_comm_req_param *)desc.req.data; + req_param->chip_id = die->chip->chip_id; + req_param->die_id = die->die_id; + ret = hccs_pcc_cmd_send(hdev, HCCS_GET_DIE_PORTS_CRC_ERR_CNT, &desc); + if (ret) { + dev_err(hdev->dev, "get crc error count sum failed on die%u, ret = %d.\n", + die->die_id, ret); + return ret; + } + + memcpy(total_crc_err_cnt, &desc.rsp.data, sizeof(u64)); + + return 0; +} + +static ssize_t hccs_show(struct kobject *k, struct attribute *attr, char *buf) +{ + struct kobj_attribute *kobj_attr; + + kobj_attr = container_of(attr, struct kobj_attribute, attr); + + return kobj_attr->show(k, kobj_attr, buf); +} + +static const struct sysfs_ops hccs_comm_ops = { + .show = hccs_show, +}; + +static ssize_t type_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + const struct hccs_port_info *port = kobj_to_port_info(kobj); + + return sysfs_emit(buf, "HCCS-v%u\n", port->port_type); +} +static struct kobj_attribute hccs_type_attr = __ATTR_RO(type); + +static ssize_t lane_mode_show(struct kobject *kobj, struct kobj_attribute *attr, + char *buf) +{ + const struct hccs_port_info *port = kobj_to_port_info(kobj); + + return sysfs_emit(buf, "x%u\n", port->lane_mode); +} +static struct kobj_attribute lane_mode_attr = __ATTR_RO(lane_mode); + +static ssize_t enable_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + const struct hccs_port_info *port = kobj_to_port_info(kobj); + + return sysfs_emit(buf, "%u\n", port->enable); +} +static struct kobj_attribute port_enable_attr = __ATTR_RO(enable); + +static ssize_t cur_lane_num_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + const struct hccs_port_info *port = kobj_to_port_info(kobj); + struct hccs_dev *hdev = port->die->chip->hdev; + struct hccs_link_status link_status = {0}; + int ret; + + mutex_lock(&hdev->lock); + ret = hccs_query_port_link_status(hdev, port, &link_status); + mutex_unlock(&hdev->lock); + if (ret) + return ret; + + return sysfs_emit(buf, "%u\n", link_status.lane_num); +} +static struct kobj_attribute cur_lane_num_attr = __ATTR_RO(cur_lane_num); + +static ssize_t link_fsm_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + const struct hccs_port_info *port = kobj_to_port_info(kobj); + struct hccs_dev *hdev = port->die->chip->hdev; + struct hccs_link_status link_status = {0}; + const struct { + u8 link_fsm; + char *str; + } link_fsm_map[] = { + {HCCS_PORT_RESET, "reset"}, + {HCCS_PORT_SETUP, "setup"}, + {HCCS_PORT_CONFIG, "config"}, + {HCCS_PORT_READY, "link-up"}, + }; + const char *link_fsm_str = "unknown"; + size_t i; + int ret; + + mutex_lock(&hdev->lock); + ret = hccs_query_port_link_status(hdev, port, &link_status); + mutex_unlock(&hdev->lock); + if (ret) + return ret; + + for (i = 0; i < ARRAY_SIZE(link_fsm_map); i++) { + if (link_fsm_map[i].link_fsm == link_status.link_fsm) { + link_fsm_str = link_fsm_map[i].str; + break; + } + } + + return sysfs_emit(buf, "%s\n", link_fsm_str); +} +static struct kobj_attribute link_fsm_attr = __ATTR_RO(link_fsm); + +static ssize_t lane_mask_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + const struct hccs_port_info *port = kobj_to_port_info(kobj); + struct hccs_dev *hdev = port->die->chip->hdev; + struct hccs_link_status link_status = {0}; + int ret; + + mutex_lock(&hdev->lock); + ret = hccs_query_port_link_status(hdev, port, &link_status); + mutex_unlock(&hdev->lock); + if (ret) + return ret; + + return sysfs_emit(buf, "0x%x\n", link_status.lane_mask); +} +static struct kobj_attribute lane_mask_attr = __ATTR_RO(lane_mask); + +static ssize_t crc_err_cnt_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + const struct hccs_port_info *port = kobj_to_port_info(kobj); + struct hccs_dev *hdev = port->die->chip->hdev; + u64 crc_err_cnt; + int ret; + + mutex_lock(&hdev->lock); + ret = hccs_query_port_crc_err_cnt(hdev, port, &crc_err_cnt); + mutex_unlock(&hdev->lock); + if (ret) + return ret; + + return sysfs_emit(buf, "%llu\n", crc_err_cnt); +} +static struct kobj_attribute crc_err_cnt_attr = __ATTR_RO(crc_err_cnt); + +static struct attribute *hccs_port_default_attrs[] = { + &hccs_type_attr.attr, + &lane_mode_attr.attr, + &port_enable_attr.attr, + &cur_lane_num_attr.attr, + &link_fsm_attr.attr, + &lane_mask_attr.attr, + &crc_err_cnt_attr.attr, + NULL, +}; +ATTRIBUTE_GROUPS(hccs_port_default); + +static const struct kobj_type hccs_port_type = { + .sysfs_ops = &hccs_comm_ops, + .default_groups = hccs_port_default_groups, +}; + +static ssize_t all_linked_on_die_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + const struct hccs_die_info *die = kobj_to_die_info(kobj); + struct hccs_dev *hdev = die->chip->hdev; + u8 all_linked; + int ret; + + mutex_lock(&hdev->lock); + ret = hccs_get_die_all_link_status(hdev, die, &all_linked); + mutex_unlock(&hdev->lock); + if (ret) + return ret; + + return sysfs_emit(buf, "%u\n", all_linked); +} +static struct kobj_attribute all_linked_on_die_attr = + __ATTR(all_linked, 0444, all_linked_on_die_show, NULL); + +static ssize_t linked_full_lane_on_die_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + const struct hccs_die_info *die = kobj_to_die_info(kobj); + struct hccs_dev *hdev = die->chip->hdev; + u8 full_lane; + int ret; + + mutex_lock(&hdev->lock); + ret = hccs_get_die_all_port_lane_status(hdev, die, &full_lane); + mutex_unlock(&hdev->lock); + if (ret) + return ret; + + return sysfs_emit(buf, "%u\n", full_lane); +} +static struct kobj_attribute linked_full_lane_on_die_attr = + __ATTR(linked_full_lane, 0444, linked_full_lane_on_die_show, NULL); + +static ssize_t crc_err_cnt_sum_on_die_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + const struct hccs_die_info *die = kobj_to_die_info(kobj); + struct hccs_dev *hdev = die->chip->hdev; + u64 total_crc_err_cnt; + int ret; + + mutex_lock(&hdev->lock); + ret = hccs_get_die_total_crc_err_cnt(hdev, die, &total_crc_err_cnt); + mutex_unlock(&hdev->lock); + if (ret) + return ret; + + return sysfs_emit(buf, "%llu\n", total_crc_err_cnt); +} +static struct kobj_attribute crc_err_cnt_sum_on_die_attr = + __ATTR(crc_err_cnt, 0444, crc_err_cnt_sum_on_die_show, NULL); + +static struct attribute *hccs_die_default_attrs[] = { + &all_linked_on_die_attr.attr, + &linked_full_lane_on_die_attr.attr, + &crc_err_cnt_sum_on_die_attr.attr, + NULL, +}; +ATTRIBUTE_GROUPS(hccs_die_default); + +static const struct kobj_type hccs_die_type = { + .sysfs_ops = &hccs_comm_ops, + .default_groups = hccs_die_default_groups, +}; + +static ssize_t all_linked_on_chip_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + const struct hccs_chip_info *chip = kobj_to_chip_info(kobj); + struct hccs_dev *hdev = chip->hdev; + const struct hccs_die_info *die; + u8 all_linked = 1; + u8 i, tmp; + int ret; + + mutex_lock(&hdev->lock); + for (i = 0; i < chip->die_num; i++) { + die = &chip->dies[i]; + ret = hccs_get_die_all_link_status(hdev, die, &tmp); + if (ret) { + mutex_unlock(&hdev->lock); + return ret; + } + if (tmp != all_linked) { + all_linked = 0; + break; + } + } + mutex_unlock(&hdev->lock); + + return sysfs_emit(buf, "%u\n", all_linked); +} +static struct kobj_attribute all_linked_on_chip_attr = + __ATTR(all_linked, 0444, all_linked_on_chip_show, NULL); + +static ssize_t linked_full_lane_on_chip_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + const struct hccs_chip_info *chip = kobj_to_chip_info(kobj); + struct hccs_dev *hdev = chip->hdev; + const struct hccs_die_info *die; + u8 full_lane = 1; + u8 i, tmp; + int ret; + + mutex_lock(&hdev->lock); + for (i = 0; i < chip->die_num; i++) { + die = &chip->dies[i]; + ret = hccs_get_die_all_port_lane_status(hdev, die, &tmp); + if (ret) { + mutex_unlock(&hdev->lock); + return ret; + } + if (tmp != full_lane) { + full_lane = 0; + break; + } + } + mutex_unlock(&hdev->lock); + + return sysfs_emit(buf, "%u\n", full_lane); +} +static struct kobj_attribute linked_full_lane_on_chip_attr = + __ATTR(linked_full_lane, 0444, linked_full_lane_on_chip_show, NULL); + +static ssize_t crc_err_cnt_sum_on_chip_show(struct kobject *kobj, + struct kobj_attribute *attr, + char *buf) +{ + const struct hccs_chip_info *chip = kobj_to_chip_info(kobj); + u64 crc_err_cnt, total_crc_err_cnt = 0; + struct hccs_dev *hdev = chip->hdev; + const struct hccs_die_info *die; + int ret; + u16 i; + + mutex_lock(&hdev->lock); + for (i = 0; i < chip->die_num; i++) { + die = &chip->dies[i]; + ret = hccs_get_die_total_crc_err_cnt(hdev, die, &crc_err_cnt); + if (ret) { + mutex_unlock(&hdev->lock); + return ret; + } + + total_crc_err_cnt += crc_err_cnt; + } + mutex_unlock(&hdev->lock); + + return sysfs_emit(buf, "%llu\n", total_crc_err_cnt); +} +static struct kobj_attribute crc_err_cnt_sum_on_chip_attr = + __ATTR(crc_err_cnt, 0444, crc_err_cnt_sum_on_chip_show, NULL); + +static struct attribute *hccs_chip_default_attrs[] = { + &all_linked_on_chip_attr.attr, + &linked_full_lane_on_chip_attr.attr, + &crc_err_cnt_sum_on_chip_attr.attr, + NULL, +}; +ATTRIBUTE_GROUPS(hccs_chip_default); + +static const struct kobj_type hccs_chip_type = { + .sysfs_ops = &hccs_comm_ops, + .default_groups = hccs_chip_default_groups, +}; + +static void hccs_remove_die_dir(struct hccs_die_info *die) +{ + struct hccs_port_info *port; + u8 i; + + for (i = 0; i < die->port_num; i++) { + port = &die->ports[i]; + if (port->dir_created) + kobject_put(&port->kobj); + } + + kobject_put(&die->kobj); +} + +static void hccs_remove_chip_dir(struct hccs_chip_info *chip) +{ + struct hccs_die_info *die; + u8 i; + + for (i = 0; i < chip->die_num; i++) { + die = &chip->dies[i]; + if (die->dir_created) + hccs_remove_die_dir(die); + } + + kobject_put(&chip->kobj); +} + +static void hccs_remove_topo_dirs(struct hccs_dev *hdev) +{ + u8 i; + + for (i = 0; i < hdev->chip_num; i++) + hccs_remove_chip_dir(&hdev->chips[i]); +} + +static int hccs_create_hccs_dir(struct hccs_dev *hdev, + struct hccs_die_info *die, + struct hccs_port_info *port) +{ + int ret; + + ret = kobject_init_and_add(&port->kobj, &hccs_port_type, + &die->kobj, "hccs%d", port->port_id); + if (ret) { + kobject_put(&port->kobj); + return ret; + } + + return 0; +} + +static int hccs_create_die_dir(struct hccs_dev *hdev, + struct hccs_chip_info *chip, + struct hccs_die_info *die) +{ + struct hccs_port_info *port; + int ret; + u16 i; + + ret = kobject_init_and_add(&die->kobj, &hccs_die_type, + &chip->kobj, "die%d", die->die_id); + if (ret) { + kobject_put(&die->kobj); + return ret; + } + + for (i = 0; i < die->port_num; i++) { + port = &die->ports[i]; + ret = hccs_create_hccs_dir(hdev, die, port); + if (ret) { + dev_err(hdev->dev, "create hccs%d dir failed.\n", + port->port_id); + goto err; + } + port->dir_created = true; + } + + return 0; +err: + hccs_remove_die_dir(die); + + return ret; +} + +static int hccs_create_chip_dir(struct hccs_dev *hdev, + struct hccs_chip_info *chip) +{ + struct hccs_die_info *die; + int ret; + u16 id; + + ret = kobject_init_and_add(&chip->kobj, &hccs_chip_type, + &hdev->dev->kobj, "chip%d", chip->chip_id); + if (ret) { + kobject_put(&chip->kobj); + return ret; + } + + for (id = 0; id < chip->die_num; id++) { + die = &chip->dies[id]; + ret = hccs_create_die_dir(hdev, chip, die); + if (ret) + goto err; + die->dir_created = true; + } + + return 0; +err: + hccs_remove_chip_dir(chip); + + return ret; +} + +static int hccs_create_topo_dirs(struct hccs_dev *hdev) +{ + struct hccs_chip_info *chip; + u8 id, k; + int ret; + + for (id = 0; id < hdev->chip_num; id++) { + chip = &hdev->chips[id]; + ret = hccs_create_chip_dir(hdev, chip); + if (ret) { + dev_err(hdev->dev, "init chip%d dir failed!\n", id); + goto err; + } + } + + return 0; +err: + for (k = 0; k < id; k++) + hccs_remove_chip_dir(&hdev->chips[k]); + + return ret; +} + static int hccs_probe(struct platform_device *pdev) { struct acpi_device *acpi_dev; @@ -598,6 +1231,10 @@ static int hccs_probe(struct platform_device *pdev) if (rc) goto unregister_pcc_chan; + rc = hccs_create_topo_dirs(hdev); + if (rc) + goto unregister_pcc_chan; + return 0; unregister_pcc_chan: @@ -610,6 +1247,7 @@ static int hccs_remove(struct platform_device *pdev) { struct hccs_dev *hdev = platform_get_drvdata(pdev); + hccs_remove_topo_dirs(hdev); hccs_unregister_pcc_channel(hdev); return 0; diff --git a/drivers/soc/hisilicon/kunpeng_hccs.h b/drivers/soc/hisilicon/kunpeng_hccs.h index fcc95e7e2a60..9d71fb78443f 100644 --- a/drivers/soc/hisilicon/kunpeng_hccs.h +++ b/drivers/soc/hisilicon/kunpeng_hccs.h @@ -21,6 +21,8 @@ struct hccs_port_info { u8 port_type; u8 lane_mode; bool enable; /* if the port is enabled */ + struct kobject kobj; + bool dir_created; struct hccs_die_info *die; /* point to the die the port is located */ }; @@ -30,6 +32,8 @@ struct hccs_die_info { u8 min_port_id; u8 max_port_id; struct hccs_port_info *ports; + struct kobject kobj; + bool dir_created; struct hccs_chip_info *chip; /* point to the chip the die is located */ }; @@ -37,6 +41,7 @@ struct hccs_chip_info { u8 chip_id; u8 die_num; struct hccs_die_info *dies; + struct kobject kobj; struct hccs_dev *hdev; }; @@ -107,6 +112,23 @@ struct hccs_die_comm_req_param { u8 die_id; /* id in hardware */ }; +/* The common command request for getting the information of a specific port */ +struct hccs_port_comm_req_param { + u8 chip_id; + u8 die_id; + u8 port_id; +}; + +#define HCCS_PORT_RESET 1 +#define HCCS_PORT_SETUP 2 +#define HCCS_PORT_CONFIG 3 +#define HCCS_PORT_READY 4 +struct hccs_link_status { + u8 lane_mask; /* indicate which lanes are used. */ + u8 link_fsm : 3; /* link fsm, 1: reset 2: setup 3: config 4: link-up */ + u8 lane_num : 5; /* current lane number */ +}; + struct hccs_req_head { u8 module_code; /* set to 0x32 for serdes */ u8 start_id; From b51022b416f5be113cd5345a2cab287d78e6b74c Mon Sep 17 00:00:00 2001 From: Huisong Li Date: Tue, 8 Aug 2023 10:36:40 +0800 Subject: [PATCH 095/136] doc: soc: hisilicon: Add Kunpeng HCCS driver documentation Document the sysfs attributes description provided by HCCS driver on Kunpeng SoC. Signed-off-by: Huisong Li Signed-off-by: Wei Xu --- .../sysfs-devices-platform-kunpeng_hccs | 81 +++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 82 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs diff --git a/Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs b/Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs new file mode 100644 index 000000000000..fdb4e36310fb --- /dev/null +++ b/Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs @@ -0,0 +1,81 @@ +What: /sys/devices/platform/HISI04Bx:00/chipX/all_linked +What: /sys/devices/platform/HISI04Bx:00/chipX/linked_full_lane +What: /sys/devices/platform/HISI04Bx:00/chipX/crc_err_cnt +Date: November 2023 +KernelVersion: 6.6 +Contact: Huisong Li +Description: + The /sys/devices/platform/HISI04Bx:00/chipX/ directory + contains read-only attributes exposing some summarization + information of all HCCS ports under a specified chip. + The X in 'chipX' indicates the Xth chip on platform. + + There are following attributes in this directory: + + ================= ==== ========================================= + all_linked: (RO) if all enabled ports on this chip are + linked (bool). + linked_full_lane: (RO) if all linked ports on this chip are full + lane (bool). + crc_err_cnt: (RO) total CRC err count for all ports on this + chip. + ================= ==== ========================================= + +What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/all_linked +What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/linked_full_lane +What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/crc_err_cnt +Date: November 2023 +KernelVersion: 6.6 +Contact: Huisong Li +Description: + The /sys/devices/platform/HISI04Bx:00/chipX/dieY/ directory + contains read-only attributes exposing some summarization + information of all HCCS ports under a specified die. + The Y in 'dieY' indicates the hardware id of the die on chip who + has chip id X. + + There are following attributes in this directory: + + ================= ==== ========================================= + all_linked: (RO) if all enabled ports on this die are + linked (bool). + linked_full_lane: (RO) if all linked ports on this die are full + lane (bool). + crc_err_cnt: (RO) total CRC err count for all ports on this + die. + ================= ==== ========================================= + +What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/type +What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mode +What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/enable +What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/cur_lane_num +What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/link_fsm +What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mask +What: /sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/crc_err_cnt +Date: November 2023 +KernelVersion: 6.6 +Contact: Huisong Li +Description: + The /sys/devices/platform/HISI04Bx/chipX/dieX/hccsN/ directory + contains read-only attributes exposing information about + a HCCS port. The N value in 'hccsN' indicates this port id. + The X in 'chipX' indicates the ID of the chip to which the + HCCS port belongs. For example, X ranges from to 'n - 1' if the + chip number on platform is n. + The Y in 'dieY' indicates the hardware id of the die to which + the hccs port belongs. + Note: type, lane_mode and enable are fixed attributes on running + platform. + + The HCCS port have the following attributes: + + ============= ==== ============================================= + type: (RO) port type (string), e.g. HCCS-v1 -> H32 + lane_mode: (RO) the lane mode of this port (string), e.g. x8 + enable: (RO) indicate if this port is enabled (bool). + cur_lane_num: (RO) current lane number of this port. + link_fsm: (RO) link finite state machine of this port. + lane_mask: (RO) current lane mask of this port, every bit + indicates a lane. + crc_err_cnt: (RO) CRC err count on this port. + ============= ==== ============================================= diff --git a/MAINTAINERS b/MAINTAINERS index 8607360e77b7..7e26ed6f8499 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -9310,6 +9310,7 @@ F: drivers/i2c/busses/i2c-hisi.c HISILICON KUNPENG SOC HCCS DRIVER M: Huisong Li S: Maintained +F: Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs F: drivers/soc/hisilicon/kunpeng_hccs.c F: drivers/soc/hisilicon/kunpeng_hccs.h From 5eddff6add4feebac625f256d2fe292935351ce3 Mon Sep 17 00:00:00 2001 From: Andrei Coardos Date: Thu, 3 Aug 2023 13:41:02 +0300 Subject: [PATCH 096/136] reset: ath79: remove unneeded call to platform_set_drvdata() This function call was found to be unnecessary as there is no equivalent platform_get_drvdata() call to access the private data of the driver. Also, the private data is defined in this driver, so there is no risk of it being accessed outside of this driver file. Reviewed-by: Alexandru Ardelean Signed-off-by: Andrei Coardos Link: https://lore.kernel.org/r/20230803104102.29647-1-aboutphysycs@gmail.com Signed-off-by: Philipp Zabel --- drivers/reset/reset-ath79.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/reset/reset-ath79.c b/drivers/reset/reset-ath79.c index a8b8f5ea77ec..b5d620132052 100644 --- a/drivers/reset/reset-ath79.c +++ b/drivers/reset/reset-ath79.c @@ -93,8 +93,6 @@ static int ath79_reset_probe(struct platform_device *pdev) if (!ath79_reset) return -ENOMEM; - platform_set_drvdata(pdev, ath79_reset); - ath79_reset->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(ath79_reset->base)) return PTR_ERR(ath79_reset->base); From 7640e58d40bc360db010ceeb3185dea411269a16 Mon Sep 17 00:00:00 2001 From: Andrei Coardos Date: Thu, 3 Aug 2023 13:41:42 +0300 Subject: [PATCH 097/136] reset: bcm6345: remove unneeded call to platform_set_drvdata() This function call was found to be unnecessary as there is no equivalent platform_get_drvdata() call to access the private data of the driver. Also, the private data is defined in this driver, so there is no risk of it being accessed outside of this driver file. Reviewed-by: Alexandru Ardelean Signed-off-by: Andrei Coardos Link: https://lore.kernel.org/r/20230803104142.29694-1-aboutphysycs@gmail.com Signed-off-by: Philipp Zabel --- drivers/reset/reset-bcm6345.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/reset/reset-bcm6345.c b/drivers/reset/reset-bcm6345.c index ac6c7ad1deda..aa9353439e70 100644 --- a/drivers/reset/reset-bcm6345.c +++ b/drivers/reset/reset-bcm6345.c @@ -102,8 +102,6 @@ static int bcm6345_reset_probe(struct platform_device *pdev) if (!bcm6345_reset) return -ENOMEM; - platform_set_drvdata(pdev, bcm6345_reset); - bcm6345_reset->base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(bcm6345_reset->base)) return PTR_ERR(bcm6345_reset->base); From 41bbf70471a251f6c553855260c3408d8b4d83c3 Mon Sep 17 00:00:00 2001 From: Andrei Coardos Date: Thu, 3 Aug 2023 13:42:25 +0300 Subject: [PATCH 098/136] reset: lantiq: remove unneeded call to platform_set_drvdata() This function call was found to be unnecessary as there is no equivalent platform_get_drvdata() call to access the private data of the driver. Also, the private data is defined in this driver, so there is no risk of it being accessed outside of this driver file. Reviewed-by: Alexandru Ardelean Signed-off-by: Andrei Coardos Link: https://lore.kernel.org/r/20230803104225.29740-1-aboutphysycs@gmail.com Signed-off-by: Philipp Zabel --- drivers/reset/reset-lantiq.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/reset/reset-lantiq.c b/drivers/reset/reset-lantiq.c index 549ba45d8597..652a45890cb2 100644 --- a/drivers/reset/reset-lantiq.c +++ b/drivers/reset/reset-lantiq.c @@ -173,7 +173,6 @@ static int lantiq_rcu_reset_probe(struct platform_device *pdev) return -ENOMEM; priv->dev = &pdev->dev; - platform_set_drvdata(pdev, priv); err = lantiq_rcu_reset_of_parse(pdev, priv); if (err) From fdc670acf62ccbd3adadf8bd4be2175e1c3a648d Mon Sep 17 00:00:00 2001 From: Andrei Coardos Date: Mon, 7 Aug 2023 13:45:49 +0300 Subject: [PATCH 099/136] reset: lpc18xx: remove unneeded call to platform_set_drvdata() This function call was found to be unnecessary as there is no equivalent platform_get_drvdata() call to access the private data of the driver. Also, the private data is defined in this driver, so there is no risk of it being accessed outside of this driver file. Reviewed-by: Alexandru Ardelean Signed-off-by: Andrei Coardos Link: https://lore.kernel.org/r/20230807104549.11225-1-aboutphysycs@gmail.com Signed-off-by: Philipp Zabel --- drivers/reset/reset-lpc18xx.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/reset/reset-lpc18xx.c b/drivers/reset/reset-lpc18xx.c index 36ec95518905..28fb85772b3e 100644 --- a/drivers/reset/reset-lpc18xx.c +++ b/drivers/reset/reset-lpc18xx.c @@ -188,8 +188,6 @@ static int lpc18xx_rgu_probe(struct platform_device *pdev) rc->rcdev.ops = &lpc18xx_rgu_ops; rc->rcdev.of_node = pdev->dev.of_node; - platform_set_drvdata(pdev, rc); - ret = reset_controller_register(&rc->rcdev); if (ret) { dev_err(&pdev->dev, "unable to register device\n"); From 1b5adb40cd9bdb7b835dbafffef00bd9dd5ae19e Mon Sep 17 00:00:00 2001 From: Andrei Coardos Date: Mon, 7 Aug 2023 13:54:00 +0300 Subject: [PATCH 100/136] reset: meson: remove unneeded call to platform_set_drvdata() This function call was found to be unnecessary as there is no equivalent platform_get_drvdata() call to access the private data of the driver. Also, the private data is defined in this driver, so there is no risk of it being accessed outside of this driver file. Reviewed-by: Alexandru Ardelean Signed-off-by: Andrei Coardos Link: https://lore.kernel.org/r/20230807105400.11560-1-aboutphysycs@gmail.com Signed-off-by: Philipp Zabel --- drivers/reset/reset-meson.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c index 89ac99789a3c..a7af051b17fb 100644 --- a/drivers/reset/reset-meson.c +++ b/drivers/reset/reset-meson.c @@ -128,8 +128,6 @@ static int meson_reset_probe(struct platform_device *pdev) if (!data->param) return -ENODEV; - platform_set_drvdata(pdev, data); - spin_lock_init(&data->lock); data->rcdev.owner = THIS_MODULE; From 00e1b4427daf3739cdcb644b72ee94fb41913447 Mon Sep 17 00:00:00 2001 From: Andrei Coardos Date: Mon, 7 Aug 2023 13:56:30 +0300 Subject: [PATCH 101/136] reset: npcm: remove unneeded call to platform_set_drvdata() This function call was found to be unnecessary as there is no equivalent platform_get_drvdata() call to access the private data of the driver. Also, the private data is defined in this driver, so there is no risk of it being accessed outside of this driver file. Reviewed-by: Alexandru Ardelean Signed-off-by: Andrei Coardos Link: https://lore.kernel.org/r/20230807105630.11638-1-aboutphysycs@gmail.com Signed-off-by: Philipp Zabel --- drivers/reset/reset-npcm.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/reset/reset-npcm.c b/drivers/reset/reset-npcm.c index f2333506b0a6..f6c4f854f2be 100644 --- a/drivers/reset/reset-npcm.c +++ b/drivers/reset/reset-npcm.c @@ -394,8 +394,6 @@ static int npcm_rc_probe(struct platform_device *pdev) rc->rcdev.of_reset_n_cells = 2; rc->rcdev.of_xlate = npcm_reset_xlate; - platform_set_drvdata(pdev, rc); - ret = devm_reset_controller_register(&pdev->dev, &rc->rcdev); if (ret) { dev_err(&pdev->dev, "unable to register device\n"); From 38f190f9410e2a4cc478897860324fde0cc99174 Mon Sep 17 00:00:00 2001 From: Andrei Coardos Date: Mon, 7 Aug 2023 14:27:05 +0300 Subject: [PATCH 102/136] reset: uniphier-glue: remove unneeded call to platform_set_drvdata() This function call was found to be unnecessary as there is no equivalent platform_get_drvdata() call to access the private data of the driver. Also, the private data is defined in this driver, so there is no risk of it being accessed outside of this driver file. Signed-off-by: Andrei Coardos Reviewed-by: Alexandru Ardelean Link: https://lore.kernel.org/r/20230807112705.12862-1-aboutphysycs@gmail.com Signed-off-by: Philipp Zabel --- drivers/reset/reset-uniphier-glue.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/reset/reset-uniphier-glue.c b/drivers/reset/reset-uniphier-glue.c index 38aa953855aa..97b3ddcdade1 100644 --- a/drivers/reset/reset-uniphier-glue.c +++ b/drivers/reset/reset-uniphier-glue.c @@ -99,8 +99,6 @@ static int uniphier_glue_reset_probe(struct platform_device *pdev) priv->rdata.rcdev.of_node = dev->of_node; priv->rdata.active_low = true; - platform_set_drvdata(pdev, priv); - return devm_reset_controller_register(dev, &priv->rdata.rcdev); } From 877fbf320a582bc5286994875128b12f959cd6fc Mon Sep 17 00:00:00 2001 From: Andrei Coardos Date: Mon, 7 Aug 2023 14:35:45 +0300 Subject: [PATCH 103/136] reset: zynq: remove unneeded call to platfrom_set_drvdata() This function call was found to be unnecessary as there is no equivalent platform_get_drvdata() call to access the private data of the driver. Also, the private data is defined in this driver, so there is no risk of it being accessed outside of this driver file. Signed-off-by: Andrei Coardos Reviewed-by: Alexandru Ardelean Link: https://lore.kernel.org/r/20230807113545.14743-1-aboutphysycs@gmail.com Signed-off-by: Philipp Zabel --- drivers/reset/reset-zynq.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/reset/reset-zynq.c b/drivers/reset/reset-zynq.c index 706bbbbb4ec7..688b512882ec 100644 --- a/drivers/reset/reset-zynq.c +++ b/drivers/reset/reset-zynq.c @@ -94,7 +94,6 @@ static int zynq_reset_probe(struct platform_device *pdev) priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) return -ENOMEM; - platform_set_drvdata(pdev, priv); priv->slcr = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, "syscon"); From 0c8603cd3031eed1ba95e4998c280dbfb12b55c4 Mon Sep 17 00:00:00 2001 From: Andrei Coardos Date: Mon, 7 Aug 2023 14:43:44 +0300 Subject: [PATCH 104/136] reset: zynqmp: removed unneeded call to platform_set_drvdata() This function call was found to be unnecessary as there is no equivalent platform_get_drvdata() call to access the private data of the driver. Also, the private data is defined in this driver, so there is no risk of it being accessed outside of this driver file. Signed-off-by: Andrei Coardos Reviewed-by: Alexandru Ardelean Link: https://lore.kernel.org/r/20230807114344.15076-1-aboutphysycs@gmail.com Signed-off-by: Philipp Zabel --- drivers/reset/reset-zynqmp.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c index 72546b4844d5..c770ea3a1894 100644 --- a/drivers/reset/reset-zynqmp.c +++ b/drivers/reset/reset-zynqmp.c @@ -112,8 +112,6 @@ static int zynqmp_reset_probe(struct platform_device *pdev) if (!priv->data) return -EINVAL; - platform_set_drvdata(pdev, priv); - priv->rcdev.ops = &zynqmp_reset_ops; priv->rcdev.owner = THIS_MODULE; priv->rcdev.of_node = pdev->dev.of_node; From 417a3a5ae44a14b4eeb3df514b2c006b19771f82 Mon Sep 17 00:00:00 2001 From: Andrei Coardos Date: Mon, 7 Aug 2023 14:15:34 +0300 Subject: [PATCH 105/136] reset: ti: syscon: remove unneeded call to platform_set_drvdata() This function call was found to be unnecessary as there is no equivalent platform_get_drvdata() call to access the private data of the driver. Also, the private data is defined in this driver, so there is no risk of it being accessed outside of this driver file. Signed-off-by: Andrei Coardos Acked-by: Andrew Davis Reviewed-by: Alexandru Ardelean Link: https://lore.kernel.org/r/20230807111534.12392-1-aboutphysycs@gmail.com Signed-off-by: Philipp Zabel --- drivers/reset/reset-ti-syscon.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/reset/reset-ti-syscon.c b/drivers/reset/reset-ti-syscon.c index f0dd7ffc3b72..23f86ddb8668 100644 --- a/drivers/reset/reset-ti-syscon.c +++ b/drivers/reset/reset-ti-syscon.c @@ -204,8 +204,6 @@ static int ti_syscon_reset_probe(struct platform_device *pdev) data->controls = controls; data->nr_controls = nr_controls; - platform_set_drvdata(pdev, data); - return devm_reset_controller_register(dev, &data->rcdev); } From 99f13d7a1686b9ec69fa4d4be4fd43757fa7aed9 Mon Sep 17 00:00:00 2001 From: "Sicelo A. Mhlongo" Date: Tue, 1 Aug 2023 21:22:40 +0200 Subject: [PATCH 106/136] bus: omap_l3_smx: identify timeout cause before rebooting Identify and print the error source before rebooting the board due to an l3 timeout error. This is helpful when debugging, e.g. via serial. Signed-off-by: Sicelo A. Mhlongo Reviewed-by: Sebastian Reichel Message-ID: <20230801192240.1063764-1-absicsz@gmail.com> Signed-off-by: Tony Lindgren --- drivers/bus/omap_l3_smx.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/bus/omap_l3_smx.c b/drivers/bus/omap_l3_smx.c index bb1606f5ce2d..8e1a38bfcd8b 100644 --- a/drivers/bus/omap_l3_smx.c +++ b/drivers/bus/omap_l3_smx.c @@ -166,19 +166,10 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3) irqreturn_t ret = IRQ_NONE; int_type = irq == l3->app_irq ? L3_APPLICATION_ERROR : L3_DEBUG_ERROR; - if (!int_type) { + if (!int_type) status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_0); - /* - * if we have a timeout error, there's nothing we can - * do besides rebooting the board. So let's BUG on any - * of such errors and handle the others. timeout error - * is severe and not expected to occur. - */ - BUG_ON(status & L3_STATUS_0_TIMEOUT_MASK); - } else { + else status = omap3_l3_readll(l3->rt, L3_SI_FLAG_STATUS_1); - /* No timeout error for debug sources */ - } /* identify the error source */ err_source = __ffs(status); @@ -190,6 +181,14 @@ static irqreturn_t omap3_l3_app_irq(int irq, void *_l3) ret |= omap3_l3_block_irq(l3, error, error_addr); } + /* + * if we have a timeout error, there's nothing we can + * do besides rebooting the board. So let's BUG on any + * of such errors and handle the others. timeout error + * is severe and not expected to occur. + */ + BUG_ON(!int_type && status & L3_STATUS_0_TIMEOUT_MASK); + /* Clear the status register */ clear = (L3_AGENT_STATUS_CLEAR_IA << int_type) | L3_AGENT_STATUS_CLEAR_TA; From f9dbb99748bab004663e349498c24edbb2368f70 Mon Sep 17 00:00:00 2001 From: Zhang Zekun Date: Wed, 9 Aug 2023 16:15:23 +0800 Subject: [PATCH 107/136] soc: ti: Use devm_platform_ioremap_resource_byname simplify logic platform_get_resource_byname() and devm_ioremap_resource() can be replaced by devm_platform_ioremap_resource_byname(), which can simplify the code logic a bit, No functional change here. Signed-off-by: Zhang Zekun Reviewed-by: Dhruva Gole Link: https://lore.kernel.org/r/20230809081523.26196-1-zhangzekun11@huawei.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/k3-ringacc.c | 19 ++++++------------- 1 file changed, 6 insertions(+), 13 deletions(-) diff --git a/drivers/soc/ti/k3-ringacc.c b/drivers/soc/ti/k3-ringacc.c index 4c1353616b72..148f54d9691d 100644 --- a/drivers/soc/ti/k3-ringacc.c +++ b/drivers/soc/ti/k3-ringacc.c @@ -1368,7 +1368,6 @@ static int k3_ringacc_init(struct platform_device *pdev, const struct soc_device_attribute *soc; void __iomem *base_fifo, *base_rt; struct device *dev = &pdev->dev; - struct resource *res; int ret, i; dev->msi.domain = of_msi_get_domain(dev, dev->of_node, @@ -1387,24 +1386,20 @@ static int k3_ringacc_init(struct platform_device *pdev, ringacc->dma_ring_reset_quirk = soc_data->dma_ring_reset_quirk; } - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rt"); - base_rt = devm_ioremap_resource(dev, res); + base_rt = devm_platform_ioremap_resource_byname(pdev, "rt"); if (IS_ERR(base_rt)) return PTR_ERR(base_rt); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fifos"); - base_fifo = devm_ioremap_resource(dev, res); + base_fifo = devm_platform_ioremap_resource_byname(pdev, "fifos"); if (IS_ERR(base_fifo)) return PTR_ERR(base_fifo); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "proxy_gcfg"); - ringacc->proxy_gcfg = devm_ioremap_resource(dev, res); + ringacc->proxy_gcfg = devm_platform_ioremap_resource_byname(pdev, "proxy_gcfg"); if (IS_ERR(ringacc->proxy_gcfg)) return PTR_ERR(ringacc->proxy_gcfg); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, - "proxy_target"); - ringacc->proxy_target_base = devm_ioremap_resource(dev, res); + ringacc->proxy_target_base = devm_platform_ioremap_resource_byname(pdev, + "proxy_target"); if (IS_ERR(ringacc->proxy_target_base)) return PTR_ERR(ringacc->proxy_target_base); @@ -1471,7 +1466,6 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev, struct device *dev = &pdev->dev; struct k3_ringacc *ringacc; void __iomem *base_rt; - struct resource *res; int i; ringacc = devm_kzalloc(dev, sizeof(*ringacc), GFP_KERNEL); @@ -1486,8 +1480,7 @@ struct k3_ringacc *k3_ringacc_dmarings_init(struct platform_device *pdev, mutex_init(&ringacc->req_lock); - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ringrt"); - base_rt = devm_ioremap_resource(dev, res); + base_rt = devm_platform_ioremap_resource_byname(pdev, "ringrt"); if (IS_ERR(base_rt)) return ERR_CAST(base_rt); From e1e1e9bb9d943ec690670a609a5f660ca10eaf85 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Aug 2023 13:38:01 +0300 Subject: [PATCH 108/136] bus: ti-sysc: Fix build warning for 64-bit build Fix "warning: cast from pointer to integer of different size" on 64-bit builds. Note that this is a cosmetic fix at this point as the driver is not yet used for 64-bit systems. Fixes: feaa8baee82a ("bus: ti-sysc: Implement SoC revision handling") Reviewed-by: Dhruva Gole Reviewed-by: Nishanth Menon Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 21fe9854703f..e9bc3894a1ec 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -3104,7 +3104,7 @@ static int sysc_init_static_data(struct sysc *ddata) match = soc_device_match(sysc_soc_match); if (match && match->data) - sysc_soc->soc = (int)match->data; + sysc_soc->soc = (enum sysc_soc)match->data; /* * Check and warn about possible old incomplete dtb. We now want to see From 063dc0622705623b3a70739b9f33d5ea019882e6 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Aug 2023 13:38:01 +0300 Subject: [PATCH 109/136] bus: ti-sysc: Build driver for TI K3 SoCs Allow building ti-sysc also for K3 SoCs. This allows configuring the wkup domain devices for SYSCONFIG register wake-up events in a generic way. As this is an interconnect level driver, default to built-in on K3 SoCs to probe the devices connected to the wkup domain like gpio, uart and timers. Reviewed-by: Dhruva Gole Reviewed-by: Nishanth Menon Signed-off-by: Tony Lindgren --- drivers/bus/Kconfig | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig index fcfa280df98a..c98dd6ca2629 100644 --- a/drivers/bus/Kconfig +++ b/drivers/bus/Kconfig @@ -210,7 +210,8 @@ config TI_PWMSS config TI_SYSC bool "TI sysc interconnect target module driver" - depends on ARCH_OMAP2PLUS + depends on ARCH_OMAP2PLUS || ARCH_K3 + default y help Generic driver for Texas Instruments interconnect target module found on many TI SoCs. From 03a711d3cb83692733f865312f49e665c49de6de Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Fri, 4 Aug 2023 13:38:01 +0300 Subject: [PATCH 110/136] bus: ti-sysc: Configure uart quirks for k3 SoC Enable the uart quirks similar to the earlier SoCs. Let's assume we are likely going to need a k3 specific quirk mask separate from the earlier SoCs, so let's not start changing the revision register mask at this point. Note that SYSC_QUIRK_LEGACY_IDLE will be needed until we can remove the need for pm_runtime_irq_safe() from 8250_omap driver. Reviewed-by: Nishanth Menon Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index e9bc3894a1ec..2e983e9492d9 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -1525,6 +1525,8 @@ static const struct sysc_revision_quirk sysc_revision_quirks[] = { SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47422e03, 0xffffffff, SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), + SYSC_QUIRK("uart", 0, 0x50, 0x54, 0x58, 0x47424e03, 0xffffffff, + SYSC_QUIRK_SWSUP_SIDLE | SYSC_QUIRK_LEGACY_IDLE), /* Quirks that need to be set based on the module address */ SYSC_QUIRK("mcpdm", 0x40132000, 0, 0x10, -ENODEV, 0x50000800, 0xffffffff, From 40a4f49cd32dbc641c706215c1fa6c5bd051428c Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Wed, 9 Aug 2023 12:53:23 +0300 Subject: [PATCH 111/136] bus: ti-sysc: Fix a build warning with W=1 for sysconfig Dhruva reported a build warning with W=1 for "Function parameter or member 'sysconfig' not described in 'sysc'". Let's document sysconfig to fix this. Reported-by: Dhruva Gole Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 2e983e9492d9..9c00802e0c20 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -109,6 +109,7 @@ static const char * const clock_names[SYSC_MAX_CLOCKS] = { * @cookie: data used by legacy platform callbacks * @name: name if available * @revision: interconnect target module revision + * @sysconfig: saved sysconfig register value * @reserved: target module is reserved and already in use * @enabled: sysc runtime enabled status * @needs_resume: runtime resume needed on resume from suspend From 22420dc71e8d735799cdadf106a420b3ce25aca3 Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Mon, 7 Aug 2023 20:14:25 +0800 Subject: [PATCH 112/136] firmware: imx: scu: change init level to subsys_initcall_sync Change firmware init level to subsys_initcall_sync to ensure it's probed before most devices to avoid unnecessary defer probe. Signed-off-by: Dong Aisheng Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/firmware/imx/imx-scu.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/imx/imx-scu.c b/drivers/firmware/imx/imx-scu.c index 47db49911e7b..2d24359420d8 100644 --- a/drivers/firmware/imx/imx-scu.c +++ b/drivers/firmware/imx/imx-scu.c @@ -353,7 +353,12 @@ static struct platform_driver imx_scu_driver = { }, .probe = imx_scu_probe, }; -builtin_platform_driver(imx_scu_driver); + +static int __init imx_scu_driver_init(void) +{ + return platform_driver_register(&imx_scu_driver); +} +subsys_initcall_sync(imx_scu_driver_init); MODULE_AUTHOR("Dong Aisheng "); MODULE_DESCRIPTION("IMX SCU firmware protocol driver"); From 4b9ccf041e3971427784870ac5b607a5cb38d43a Mon Sep 17 00:00:00 2001 From: Dong Aisheng Date: Mon, 7 Aug 2023 20:14:26 +0800 Subject: [PATCH 113/136] firmware: imx: scu: increase RPC timeout When system loading is high, we can meet some command timeout issue occasionally, so increase the timeout to a safe value. Signed-off-by: Dong Aisheng Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/firmware/imx/imx-scu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/imx/imx-scu.c b/drivers/firmware/imx/imx-scu.c index 2d24359420d8..14ff9d3504bf 100644 --- a/drivers/firmware/imx/imx-scu.c +++ b/drivers/firmware/imx/imx-scu.c @@ -20,7 +20,7 @@ #include #define SCU_MU_CHAN_NUM 8 -#define MAX_RX_TIMEOUT (msecs_to_jiffies(30)) +#define MAX_RX_TIMEOUT (msecs_to_jiffies(3000)) struct imx_sc_chan { struct imx_sc_ipc *sc_ipc; From 150019dea22afa2ea9ebe28078fe36271defa9c4 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Aug 2023 20:14:27 +0800 Subject: [PATCH 114/136] firmware: imx: scu: use soc name for soc_id Same as soc-imx8m and soc-imx driver, use soc name for soc_id which is user friendly. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/firmware/imx/imx-scu-soc.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/firmware/imx/imx-scu-soc.c b/drivers/firmware/imx/imx-scu-soc.c index 2f32353de2c9..497192320562 100644 --- a/drivers/firmware/imx/imx-scu-soc.c +++ b/drivers/firmware/imx/imx-scu-soc.c @@ -78,6 +78,22 @@ static int imx_scu_soc_id(void) return msg.data.resp.id; } +static const char *imx_scu_soc_name(u32 id) +{ + switch (id) { + case 0x1: + return "i.MX8QM"; + case 0x2: + return "i.MX8QXP"; + case 0xe: + return "i.MX8DXL"; + default: + break; + } + + return "NULL"; +} + int imx_scu_soc_init(struct device *dev) { struct soc_device_attribute *soc_dev_attr; @@ -113,9 +129,7 @@ int imx_scu_soc_init(struct device *dev) /* format soc_id value passed from SCU firmware */ val = id & 0x1f; - soc_dev_attr->soc_id = devm_kasprintf(dev, GFP_KERNEL, "0x%x", val); - if (!soc_dev_attr->soc_id) - return -ENOMEM; + soc_dev_attr->soc_id = imx_scu_soc_name(val); /* format revision value passed from SCU firmware */ val = (id >> 5) & 0xf; From 8314aa8af4f9905dded47e53b3e283e632736d41 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Aug 2023 20:14:28 +0800 Subject: [PATCH 115/136] firmware: imx: scu: use EOPNOTSUPP Per checkpatch.pl, "ENOTSUPP is not a SUSV4 error code, prefer EOPNOTSUPP" So use EOPNOTSUPP to replace ENOTSUPP. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- include/linux/firmware/imx/sci.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/linux/firmware/imx/sci.h b/include/linux/firmware/imx/sci.h index 5cc63fe7e84d..7fa0f3b329b5 100644 --- a/include/linux/firmware/imx/sci.h +++ b/include/linux/firmware/imx/sci.h @@ -25,27 +25,27 @@ int imx_scu_soc_init(struct device *dev); #else static inline int imx_scu_soc_init(struct device *dev) { - return -ENOTSUPP; + return -EOPNOTSUPP; } static inline int imx_scu_enable_general_irq_channel(struct device *dev) { - return -ENOTSUPP; + return -EOPNOTSUPP; } static inline int imx_scu_irq_register_notifier(struct notifier_block *nb) { - return -ENOTSUPP; + return -EOPNOTSUPP; } static inline int imx_scu_irq_unregister_notifier(struct notifier_block *nb) { - return -ENOTSUPP; + return -EOPNOTSUPP; } static inline int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable) { - return -ENOTSUPP; + return -EOPNOTSUPP; } #endif #endif /* _SC_SCI_H */ From 19a72e0cb06de380c6259d1ca02aea2c99c1e175 Mon Sep 17 00:00:00 2001 From: Robin Gong Date: Mon, 7 Aug 2023 20:14:29 +0800 Subject: [PATCH 116/136] firmware: imx: scu-irq: fix RCU complaint after M4 partition reset Use blocking_notifier_chain instead of atomic_notifier_chain, otherwise there will be RCU complaint, because unregister/register_virtio_device() will issue mbox message. mbox_send_message() is blocking again after received M4 partition reset. Actually, no need atomic notifier for scu irq notification since this notifier is called in worker instead of interrupt handler. [ 389.706645] i2c-rpmsg virtio0.rpmsg-i2c-channel.-1.2: i2c rpmsg driver is removed [ 389.767362] Wait for remote ready timeout, use first_notify. [ 389.774084] ------------[ cut here ]------------ [ 389.778729] WARNING: CPU: 0 PID: 397 at kernel/rcu/tree_plugin.h:293 rcu_note_context_switch+0x34/0x338 [ 389.788131] Modules linked in: [ 389.791195] CPU: 0 PID: 397 Comm: kworker/0:13 Not tainted 5.4.0-rc5-02977-g08f78722f07b #26 [ 389.799633] Hardware name: Freescale i.MX8DXL MEK (DT) [ 389.805481] Workqueue: events imx_scu_irq_work_handler Signed-off-by: Robin Gong Reviewed-by: Dong Aisheng Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/firmware/imx/imx-scu-irq.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/firmware/imx/imx-scu-irq.c b/drivers/firmware/imx/imx-scu-irq.c index d9dcc20945c6..4408f150b3d5 100644 --- a/drivers/firmware/imx/imx-scu-irq.c +++ b/drivers/firmware/imx/imx-scu-irq.c @@ -42,25 +42,25 @@ struct imx_sc_msg_irq_enable { static struct imx_sc_ipc *imx_sc_irq_ipc_handle; static struct work_struct imx_sc_irq_work; -static ATOMIC_NOTIFIER_HEAD(imx_scu_irq_notifier_chain); +static BLOCKING_NOTIFIER_HEAD(imx_scu_irq_notifier_chain); int imx_scu_irq_register_notifier(struct notifier_block *nb) { - return atomic_notifier_chain_register( + return blocking_notifier_chain_register( &imx_scu_irq_notifier_chain, nb); } EXPORT_SYMBOL(imx_scu_irq_register_notifier); int imx_scu_irq_unregister_notifier(struct notifier_block *nb) { - return atomic_notifier_chain_unregister( + return blocking_notifier_chain_unregister( &imx_scu_irq_notifier_chain, nb); } EXPORT_SYMBOL(imx_scu_irq_unregister_notifier); static int imx_scu_irq_notifier_call_chain(unsigned long status, u8 *group) { - return atomic_notifier_call_chain(&imx_scu_irq_notifier_chain, + return blocking_notifier_call_chain(&imx_scu_irq_notifier_chain, status, (void *)group); } From d2bd250cefabd2ce51a77bf69435e28f1fa47176 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Aug 2023 20:14:30 +0800 Subject: [PATCH 117/136] firmware: imx: scu-irq: add imx_scu_irq_get_status Extract the scu irq get status code from imx_scu_irq_work_handler and make into a new function imx_scu_irq_get_status which could be used by others, such as SECO. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/firmware/imx/imx-scu-irq.c | 40 ++++++++++++++++++++---------- include/linux/firmware/imx/sci.h | 6 +++++ 2 files changed, 33 insertions(+), 13 deletions(-) diff --git a/drivers/firmware/imx/imx-scu-irq.c b/drivers/firmware/imx/imx-scu-irq.c index 4408f150b3d5..6549f3792a0f 100644 --- a/drivers/firmware/imx/imx-scu-irq.c +++ b/drivers/firmware/imx/imx-scu-irq.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2019 NXP + * Copyright 2019,2023 NXP * * Implementation of the SCU IRQ functions using MU. * @@ -66,29 +66,18 @@ static int imx_scu_irq_notifier_call_chain(unsigned long status, u8 *group) static void imx_scu_irq_work_handler(struct work_struct *work) { - struct imx_sc_msg_irq_get_status msg; - struct imx_sc_rpc_msg *hdr = &msg.hdr; u32 irq_status; int ret; u8 i; for (i = 0; i < IMX_SC_IRQ_NUM_GROUP; i++) { - hdr->ver = IMX_SC_RPC_VERSION; - hdr->svc = IMX_SC_RPC_SVC_IRQ; - hdr->func = IMX_SC_IRQ_FUNC_STATUS; - hdr->size = 2; - - msg.data.req.resource = mu_resource_id; - msg.data.req.group = i; - - ret = imx_scu_call_rpc(imx_sc_irq_ipc_handle, &msg, true); + ret = imx_scu_irq_get_status(i, &irq_status); if (ret) { pr_err("get irq group %d status failed, ret %d\n", i, ret); return; } - irq_status = msg.data.resp.status; if (!irq_status) continue; @@ -97,6 +86,31 @@ static void imx_scu_irq_work_handler(struct work_struct *work) } } +int imx_scu_irq_get_status(u8 group, u32 *irq_status) +{ + struct imx_sc_msg_irq_get_status msg; + struct imx_sc_rpc_msg *hdr = &msg.hdr; + int ret; + + hdr->ver = IMX_SC_RPC_VERSION; + hdr->svc = IMX_SC_RPC_SVC_IRQ; + hdr->func = IMX_SC_IRQ_FUNC_STATUS; + hdr->size = 2; + + msg.data.req.resource = mu_resource_id; + msg.data.req.group = group; + + ret = imx_scu_call_rpc(imx_sc_irq_ipc_handle, &msg, true); + if (ret) + return ret; + + if (irq_status) + *irq_status = msg.data.resp.status; + + return 0; +} +EXPORT_SYMBOL(imx_scu_irq_get_status); + int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable) { struct imx_sc_msg_irq_enable msg; diff --git a/include/linux/firmware/imx/sci.h b/include/linux/firmware/imx/sci.h index 7fa0f3b329b5..df17196df5ff 100644 --- a/include/linux/firmware/imx/sci.h +++ b/include/linux/firmware/imx/sci.h @@ -21,6 +21,7 @@ int imx_scu_enable_general_irq_channel(struct device *dev); int imx_scu_irq_register_notifier(struct notifier_block *nb); int imx_scu_irq_unregister_notifier(struct notifier_block *nb); int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable); +int imx_scu_irq_get_status(u8 group, u32 *irq_status); int imx_scu_soc_init(struct device *dev); #else static inline int imx_scu_soc_init(struct device *dev) @@ -47,5 +48,10 @@ static inline int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable) { return -EOPNOTSUPP; } + +static inline int imx_scu_irq_get_status(u8 group, u32 *irq_status) +{ + return -EOPNOTSUPP; +} #endif #endif /* _SC_SCI_H */ From 6c59ce485fd0015db160b913903c5f1e8c586d38 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 7 Aug 2023 20:14:31 +0800 Subject: [PATCH 118/136] firmware: imx: scu-irq: enlarge the IMX_SC_IRQ_NUM_GROUP Per SCFW update, update the IMX_SC_IRQ_NUM_GROUP to 9. Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/firmware/imx/imx-scu-irq.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/firmware/imx/imx-scu-irq.c b/drivers/firmware/imx/imx-scu-irq.c index 6549f3792a0f..8d902db1daf2 100644 --- a/drivers/firmware/imx/imx-scu-irq.c +++ b/drivers/firmware/imx/imx-scu-irq.c @@ -14,7 +14,7 @@ #define IMX_SC_IRQ_FUNC_ENABLE 1 #define IMX_SC_IRQ_FUNC_STATUS 2 -#define IMX_SC_IRQ_NUM_GROUP 4 +#define IMX_SC_IRQ_NUM_GROUP 9 static u32 mu_resource_id; From c081197a33a2813881b534c44666024c97fb025d Mon Sep 17 00:00:00 2001 From: Ranjani Vaidyanathan Date: Mon, 7 Aug 2023 20:14:32 +0800 Subject: [PATCH 119/136] firmware: imx: scu-irq: support identifying SCU wakeup source from sysfs Record SCU wakeup interrupt in /sys/power/pm_wakeup_irq The user can further identify the exact wakeup source by using the following interface: cat /sys/firmware/scu_wakeup_source/wakeup_src The above will print the wake groups and the irqs that could have contributed to waking up the kernel. For example if ON/OFF button was the wakeup source: cat /sys/firmware/scu_wakeup_source/wakeup_src Wakeup source group = 3, irq = 0x1 The user can refer to the SCFW API documentation to identify all the wake groups and irqs. Signed-off-by: Ranjani Vaidyanathan Signed-off-by: Peng Fan Signed-off-by: Shawn Guo --- drivers/firmware/imx/imx-scu-irq.c | 70 ++++++++++++++++++++++++++++++ 1 file changed, 70 insertions(+) diff --git a/drivers/firmware/imx/imx-scu-irq.c b/drivers/firmware/imx/imx-scu-irq.c index 8d902db1daf2..7cc0dec04587 100644 --- a/drivers/firmware/imx/imx-scu-irq.c +++ b/drivers/firmware/imx/imx-scu-irq.c @@ -9,8 +9,10 @@ #include #include #include +#include #include #include +#include #define IMX_SC_IRQ_FUNC_ENABLE 1 #define IMX_SC_IRQ_FUNC_STATUS 2 @@ -40,6 +42,20 @@ struct imx_sc_msg_irq_enable { u8 enable; } __packed; +struct scu_wakeup { + u32 mask; + u32 wakeup_src; + bool valid; +}; + +/* Sysfs functions */ +static struct kobject *wakeup_obj; +static ssize_t wakeup_source_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf); +static struct kobj_attribute wakeup_source_attr = + __ATTR(wakeup_src, 0660, wakeup_source_show, NULL); + +static struct scu_wakeup scu_irq_wakeup[IMX_SC_IRQ_NUM_GROUP]; + static struct imx_sc_ipc *imx_sc_irq_ipc_handle; static struct work_struct imx_sc_irq_work; static BLOCKING_NOTIFIER_HEAD(imx_scu_irq_notifier_chain); @@ -71,6 +87,11 @@ static void imx_scu_irq_work_handler(struct work_struct *work) u8 i; for (i = 0; i < IMX_SC_IRQ_NUM_GROUP; i++) { + if (scu_irq_wakeup[i].mask) { + scu_irq_wakeup[i].valid = false; + scu_irq_wakeup[i].wakeup_src = 0; + } + ret = imx_scu_irq_get_status(i, &irq_status); if (ret) { pr_err("get irq group %d status failed, ret %d\n", @@ -80,6 +101,12 @@ static void imx_scu_irq_work_handler(struct work_struct *work) if (!irq_status) continue; + if (scu_irq_wakeup[i].mask & irq_status) { + scu_irq_wakeup[i].valid = true; + scu_irq_wakeup[i].wakeup_src = irq_status & scu_irq_wakeup[i].mask; + } else { + scu_irq_wakeup[i].wakeup_src = irq_status; + } pm_system_wakeup(); imx_scu_irq_notifier_call_chain(irq_status, &i); @@ -135,6 +162,11 @@ int imx_scu_irq_group_enable(u8 group, u32 mask, u8 enable) pr_err("enable irq failed, group %d, mask %d, ret %d\n", group, mask, ret); + if (enable) + scu_irq_wakeup[group].mask |= mask; + else + scu_irq_wakeup[group].mask &= ~mask; + return ret; } EXPORT_SYMBOL(imx_scu_irq_group_enable); @@ -144,6 +176,25 @@ static void imx_scu_irq_callback(struct mbox_client *c, void *msg) schedule_work(&imx_sc_irq_work); } +static ssize_t wakeup_source_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) +{ + int i; + + for (i = 0; i < IMX_SC_IRQ_NUM_GROUP; i++) { + if (!scu_irq_wakeup[i].wakeup_src) + continue; + + if (scu_irq_wakeup[i].valid) + sprintf(buf, "Wakeup source group = %d, irq = 0x%x\n", + i, scu_irq_wakeup[i].wakeup_src); + else + sprintf(buf, "Spurious SCU wakeup, group = %d, irq = 0x%x\n", + i, scu_irq_wakeup[i].wakeup_src); + } + + return strlen(buf); +} + int imx_scu_enable_general_irq_channel(struct device *dev) { struct of_phandle_args spec; @@ -183,6 +234,25 @@ int imx_scu_enable_general_irq_channel(struct device *dev) mu_resource_id = IMX_SC_R_MU_0A + i; + /* Create directory under /sysfs/firmware */ + wakeup_obj = kobject_create_and_add("scu_wakeup_source", firmware_kobj); + if (!wakeup_obj) { + ret = -ENOMEM; + goto free_ch; + } + + ret = sysfs_create_file(wakeup_obj, &wakeup_source_attr.attr); + if (ret) { + dev_err(dev, "Cannot create wakeup source src file......\n"); + kobject_put(wakeup_obj); + goto free_ch; + } + + return 0; + +free_ch: + mbox_free_channel(ch); + return ret; } EXPORT_SYMBOL(imx_scu_enable_general_irq_channel); From f9eac7e0298ff9df9ae10a579a620d07453845d4 Mon Sep 17 00:00:00 2001 From: Gokul krishna Krishnakumar Date: Mon, 3 Apr 2023 13:44:55 -0700 Subject: [PATCH 120/136] dt-bindings: firmware: qcom: scm: Updating VMID list Adding the full list of VMID's, which are used by different clients to pass to the secure world. Signed-off-by: Gokul krishna Krishnakumar Acked-by: Rob Herring Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20230403204455.6758-1-quic_gokukris@quicinc.com Signed-off-by: Bjorn Andersson --- include/dt-bindings/firmware/qcom,scm.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/include/dt-bindings/firmware/qcom,scm.h b/include/dt-bindings/firmware/qcom,scm.h index d1dc09e72923..6de8b08e1e79 100644 --- a/include/dt-bindings/firmware/qcom,scm.h +++ b/include/dt-bindings/firmware/qcom,scm.h @@ -2,17 +2,38 @@ /* * Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved. * Copyright (C) 2015 Linaro Ltd. + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. */ #ifndef _DT_BINDINGS_FIRMWARE_QCOM_SCM_H #define _DT_BINDINGS_FIRMWARE_QCOM_SCM_H +#define QCOM_SCM_VMID_TZ 0x1 #define QCOM_SCM_VMID_HLOS 0x3 #define QCOM_SCM_VMID_SSC_Q6 0x5 #define QCOM_SCM_VMID_ADSP_Q6 0x6 +#define QCOM_SCM_VMID_CP_TOUCH 0x8 +#define QCOM_SCM_VMID_CP_BITSTREAM 0x9 +#define QCOM_SCM_VMID_CP_PIXEL 0xA +#define QCOM_SCM_VMID_CP_NON_PIXEL 0xB +#define QCOM_SCM_VMID_CP_CAMERA 0xD +#define QCOM_SCM_VMID_HLOS_FREE 0xE #define QCOM_SCM_VMID_MSS_MSA 0xF +#define QCOM_SCM_VMID_MSS_NONMSA 0x10 +#define QCOM_SCM_VMID_CP_SEC_DISPLAY 0x11 +#define QCOM_SCM_VMID_CP_APP 0x12 +#define QCOM_SCM_VMID_LPASS 0x16 #define QCOM_SCM_VMID_WLAN 0x18 #define QCOM_SCM_VMID_WLAN_CE 0x19 +#define QCOM_SCM_VMID_CP_SPSS_SP 0x1A +#define QCOM_SCM_VMID_CP_CAMERA_PREVIEW 0x1D +#define QCOM_SCM_VMID_CDSP 0x1E +#define QCOM_SCM_VMID_CP_SPSS_SP_SHARED 0x22 +#define QCOM_SCM_VMID_CP_SPSS_HLOS_SHARED 0x24 +#define QCOM_SCM_VMID_ADSP_HEAP 0x25 +#define QCOM_SCM_VMID_CP_CDSP 0x2A #define QCOM_SCM_VMID_NAV 0x2B +#define QCOM_SCM_VMID_TVM 0x2D +#define QCOM_SCM_VMID_OEMVM 0x31 #endif From 443012dd31e5939cb53bc9c5713d32d87321b0d8 Mon Sep 17 00:00:00 2001 From: Vignesh Raghavendra Date: Fri, 11 Aug 2023 22:31:27 +0530 Subject: [PATCH 121/136] soc: ti: k3-socinfo.c: Add JTAG ID for AM62PX This adds JTAG ID info for the AM62PX so as to enable SoC detection in kernel. Signed-off-by: Vignesh Raghavendra Reviewed-by: Praneeth Bajjuri Link: https://lore.kernel.org/r/20230811170127.250733-1-vigneshr@ti.com Signed-off-by: Nishanth Menon --- drivers/soc/ti/k3-socinfo.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/ti/k3-socinfo.c b/drivers/soc/ti/k3-socinfo.c index ad97e08a25f6..6ea9b8c7d335 100644 --- a/drivers/soc/ti/k3-socinfo.c +++ b/drivers/soc/ti/k3-socinfo.c @@ -45,6 +45,7 @@ static const struct k3_soc_id { { 0xBB7E, "AM62X" }, { 0xBB80, "J784S4" }, { 0xBB8D, "AM62AX" }, + { 0xBB9D, "AM62PX" }, }; static int From 37696fa746731ce137f07b03443eec79bba07794 Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 12 Aug 2023 19:17:58 +0200 Subject: [PATCH 122/136] soc: kunpeng_hccs: fix size_t format string Printing a size_t using the %lu format string causes a warning on architectures that define the type as 'unsigned int': In file included from include/linux/device.h:15, from include/linux/acpi.h:14, from drivers/soc/hisilicon/kunpeng_hccs.c:25: drivers/soc/hisilicon/kunpeng_hccs.c: In function 'hccs_get_bd_info': drivers/soc/hisilicon/kunpeng_hccs.c:441:25: error: format '%lu' expects argument of type 'long unsigned int', but argument 3 has type 'size_t' {aka 'unsigned int'} [-Werror=format=] Use the correct %zu format instead. Fixes: 886bdf9c883bc ("soc: hisilicon: Support HCCS driver on Kunpeng SoC") Signed-off-by: Arnd Bergmann --- drivers/soc/hisilicon/kunpeng_hccs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/soc/hisilicon/kunpeng_hccs.c b/drivers/soc/hisilicon/kunpeng_hccs.c index 6864d203c678..0d6f6bacd3f6 100644 --- a/drivers/soc/hisilicon/kunpeng_hccs.c +++ b/drivers/soc/hisilicon/kunpeng_hccs.c @@ -438,7 +438,7 @@ static int hccs_get_bd_info(struct hccs_dev *hdev, u8 opcode, head = &rsp->rsp_head; if (head->data_len > buf_len) { dev_err(hdev->dev, - "buffer overflow (buf_len = %lu, data_len = %u)!\n", + "buffer overflow (buf_len = %zu, data_len = %u)!\n", buf_len, head->data_len); return -ENOMEM; } From 59e09100836fdb618b107c37189d6001b5825872 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 11 Aug 2023 13:58:36 -0700 Subject: [PATCH 123/136] soc: qcom: aoss: Move length requirements from caller The existing implementation of qmp_send() requires the caller to provide a buffer which is of word-aligned. The underlying reason for this is that message ram only supports word accesses, but pushing this requirement onto the clients results in the same boiler plate code sprinkled in every call site. By using a temporary buffer in qmp_send() we can hide the underlying hardware limitations from the clients and allow them to pass their NUL-terminates C string directly. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230811205839.727373-2-quic_bjorande@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/net/ipa/ipa_power.c | 2 +- drivers/remoteproc/qcom_q6v5.c | 2 +- drivers/soc/qcom/qcom_aoss.c | 25 ++++++++++++------------- include/linux/soc/qcom/qcom_aoss.h | 4 ++-- 4 files changed, 16 insertions(+), 17 deletions(-) diff --git a/drivers/net/ipa/ipa_power.c b/drivers/net/ipa/ipa_power.c index 921eecf3eff6..26181eeed975 100644 --- a/drivers/net/ipa/ipa_power.c +++ b/drivers/net/ipa/ipa_power.c @@ -332,7 +332,7 @@ void ipa_power_retention(struct ipa *ipa, bool enable) (void)snprintf(buf, sizeof(buf), fmt, enable ? '1' : '0'); - ret = qmp_send(power->qmp, buf, sizeof(buf)); + ret = qmp_send(power->qmp, buf); if (ret) dev_err(power->dev, "error %d sending QMP %sable request\n", ret, enable ? "en" : "dis"); diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c index 192c7aa0e39e..8b41a73fa4d1 100644 --- a/drivers/remoteproc/qcom_q6v5.c +++ b/drivers/remoteproc/qcom_q6v5.c @@ -35,7 +35,7 @@ static int q6v5_load_state_toggle(struct qcom_q6v5 *q6v5, bool enable) WARN_ON(ret >= Q6V5_LOAD_STATE_MSG_LEN); - ret = qmp_send(q6v5->qmp, buf, sizeof(buf)); + ret = qmp_send(q6v5->qmp, buf); if (ret) dev_err(q6v5->dev, "failed to toggle load state\n"); diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index e376c32cc16e..880fe234ca0a 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -206,36 +206,35 @@ static bool qmp_message_empty(struct qmp *qmp) * qmp_send() - send a message to the AOSS * @qmp: qmp context * @data: message to be sent - * @len: length of the message * * Transmit @data to AOSS and wait for the AOSS to acknowledge the message. - * @len must be a multiple of 4 and not longer than the mailbox size. Access is - * synchronized by this implementation. + * data must not be longer than the mailbox size. Access is synchronized by + * this implementation. * * Return: 0 on success, negative errno on failure */ -int qmp_send(struct qmp *qmp, const void *data, size_t len) +int qmp_send(struct qmp *qmp, const void *data) { + char buf[QMP_MSG_LEN]; long time_left; int ret; if (WARN_ON(IS_ERR_OR_NULL(qmp) || !data)) return -EINVAL; - if (WARN_ON(len + sizeof(u32) > qmp->size)) + if (WARN_ON(strlen(data) >= sizeof(buf))) return -EINVAL; - if (WARN_ON(len % sizeof(u32))) - return -EINVAL; + strscpy_pad(buf, data, sizeof(buf)); mutex_lock(&qmp->tx_lock); /* The message RAM only implements 32-bit accesses */ __iowrite32_copy(qmp->msgram + qmp->offset + sizeof(u32), - data, len / sizeof(u32)); - writel(len, qmp->msgram + qmp->offset); + buf, sizeof(buf) / sizeof(u32)); + writel(sizeof(buf), qmp->msgram + qmp->offset); - /* Read back len to confirm data written in message RAM */ + /* Read back length to confirm data written in message RAM */ readl(qmp->msgram + qmp->offset); qmp_kick(qmp); @@ -262,7 +261,7 @@ static int qmp_qdss_clk_prepare(struct clk_hw *hw) static const char buf[QMP_MSG_LEN] = "{class: clock, res: qdss, val: 1}"; struct qmp *qmp = container_of(hw, struct qmp, qdss_clk); - return qmp_send(qmp, buf, sizeof(buf)); + return qmp_send(qmp, buf); } static void qmp_qdss_clk_unprepare(struct clk_hw *hw) @@ -270,7 +269,7 @@ static void qmp_qdss_clk_unprepare(struct clk_hw *hw) static const char buf[QMP_MSG_LEN] = "{class: clock, res: qdss, val: 0}"; struct qmp *qmp = container_of(hw, struct qmp, qdss_clk); - qmp_send(qmp, buf, sizeof(buf)); + qmp_send(qmp, buf); } static const struct clk_ops qmp_qdss_clk_ops = { @@ -344,7 +343,7 @@ static int qmp_cdev_set_cur_state(struct thermal_cooling_device *cdev, qmp_cdev->name, cdev_state ? "on" : "off"); - ret = qmp_send(qmp_cdev->qmp, buf, sizeof(buf)); + ret = qmp_send(qmp_cdev->qmp, buf); if (!ret) qmp_cdev->state = cdev_state; diff --git a/include/linux/soc/qcom/qcom_aoss.h b/include/linux/soc/qcom/qcom_aoss.h index 3c2a82e606f8..7a71406b6050 100644 --- a/include/linux/soc/qcom/qcom_aoss.h +++ b/include/linux/soc/qcom/qcom_aoss.h @@ -13,13 +13,13 @@ struct qmp; #if IS_ENABLED(CONFIG_QCOM_AOSS_QMP) -int qmp_send(struct qmp *qmp, const void *data, size_t len); +int qmp_send(struct qmp *qmp, const void *data); struct qmp *qmp_get(struct device *dev); void qmp_put(struct qmp *qmp); #else -static inline int qmp_send(struct qmp *qmp, const void *data, size_t len) +static inline int qmp_send(struct qmp *qmp, const void *data) { return -ENODEV; } From 8873d1e2f88afbe89c99d8f49f88934a2da2991f Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 11 Aug 2023 13:58:38 -0700 Subject: [PATCH 124/136] soc: qcom: aoss: Format string in qmp_send() The majority of callers to qmp_send() composes the message dynamically using some form of sprintf(), resulting in unnecessary complication and stack usage. By changing the interface of qmp_send() to take a format string and arguments, the duplicated composition of the commands can be moved to a single location. Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230811205839.727373-4-quic_bjorande@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/soc/qcom/qcom_aoss.c | 20 +++++++++++++------- include/linux/soc/qcom/qcom_aoss.h | 4 ++-- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 880fe234ca0a..8424d1da4db9 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -205,27 +205,33 @@ static bool qmp_message_empty(struct qmp *qmp) /** * qmp_send() - send a message to the AOSS * @qmp: qmp context - * @data: message to be sent + * @fmt: format string for message to be sent + * @...: arguments for the format string * - * Transmit @data to AOSS and wait for the AOSS to acknowledge the message. + * Transmit message to AOSS and wait for the AOSS to acknowledge the message. * data must not be longer than the mailbox size. Access is synchronized by * this implementation. * * Return: 0 on success, negative errno on failure */ -int qmp_send(struct qmp *qmp, const void *data) +int qmp_send(struct qmp *qmp, const char *fmt, ...) { char buf[QMP_MSG_LEN]; long time_left; + va_list args; + int len; int ret; - if (WARN_ON(IS_ERR_OR_NULL(qmp) || !data)) + if (WARN_ON(IS_ERR_OR_NULL(qmp) || !fmt)) return -EINVAL; - if (WARN_ON(strlen(data) >= sizeof(buf))) - return -EINVAL; + memset(buf, 0, sizeof(buf)); + va_start(args, fmt); + len = vsnprintf(buf, sizeof(buf), fmt, args); + va_end(args); - strscpy_pad(buf, data, sizeof(buf)); + if (WARN_ON(len >= sizeof(buf))) + return -EINVAL; mutex_lock(&qmp->tx_lock); diff --git a/include/linux/soc/qcom/qcom_aoss.h b/include/linux/soc/qcom/qcom_aoss.h index 7a71406b6050..7361ca028752 100644 --- a/include/linux/soc/qcom/qcom_aoss.h +++ b/include/linux/soc/qcom/qcom_aoss.h @@ -13,13 +13,13 @@ struct qmp; #if IS_ENABLED(CONFIG_QCOM_AOSS_QMP) -int qmp_send(struct qmp *qmp, const void *data); +int qmp_send(struct qmp *qmp, const char *fmt, ...); struct qmp *qmp_get(struct device *dev); void qmp_put(struct qmp *qmp); #else -static inline int qmp_send(struct qmp *qmp, const void *data) +static inline int qmp_send(struct qmp *qmp, const char *fmt, ...) { return -ENODEV; } From b4f63bbff96e4510676b1e78b00d14baaee9ad29 Mon Sep 17 00:00:00 2001 From: Bjorn Andersson Date: Fri, 11 Aug 2023 13:58:39 -0700 Subject: [PATCH 125/136] soc: qcom: aoss: Tidy up qmp_send() callers With qmp_send() handling variable length messages and string formatting he callers of qmp_send() can be cleaned up to not care about these things. Drop the QMP_MSG_LEN sized buffers and use the message formatting, as appropriate. Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230811205839.727373-5-quic_bjorande@quicinc.com Signed-off-by: Bjorn Andersson --- drivers/net/ipa/ipa_power.c | 5 +---- drivers/remoteproc/qcom_q6v5.c | 8 +------- drivers/soc/qcom/qcom_aoss.c | 14 ++++---------- 3 files changed, 6 insertions(+), 21 deletions(-) diff --git a/drivers/net/ipa/ipa_power.c b/drivers/net/ipa/ipa_power.c index 26181eeed975..0eaa7a7f3343 100644 --- a/drivers/net/ipa/ipa_power.c +++ b/drivers/net/ipa/ipa_power.c @@ -324,15 +324,12 @@ void ipa_power_retention(struct ipa *ipa, bool enable) { static const char fmt[] = "{ class: bcm, res: ipa_pc, val: %c }"; struct ipa_power *power = ipa->power; - char buf[36]; /* Exactly enough for fmt[]; size a multiple of 4 */ int ret; if (!power->qmp) return; /* Not needed on this platform */ - (void)snprintf(buf, sizeof(buf), fmt, enable ? '1' : '0'); - - ret = qmp_send(power->qmp, buf); + ret = qmp_send(power->qmp, fmt, enable ? '1' : '0'); if (ret) dev_err(power->dev, "error %d sending QMP %sable request\n", ret, enable ? "en" : "dis"); diff --git a/drivers/remoteproc/qcom_q6v5.c b/drivers/remoteproc/qcom_q6v5.c index 8b41a73fa4d1..4ee5e67a9f03 100644 --- a/drivers/remoteproc/qcom_q6v5.c +++ b/drivers/remoteproc/qcom_q6v5.c @@ -23,19 +23,13 @@ static int q6v5_load_state_toggle(struct qcom_q6v5 *q6v5, bool enable) { - char buf[Q6V5_LOAD_STATE_MSG_LEN]; int ret; if (!q6v5->qmp) return 0; - ret = snprintf(buf, sizeof(buf), - "{class: image, res: load_state, name: %s, val: %s}", + ret = qmp_send(q6v5->qmp, "{class: image, res: load_state, name: %s, val: %s}", q6v5->load_state, enable ? "on" : "off"); - - WARN_ON(ret >= Q6V5_LOAD_STATE_MSG_LEN); - - ret = qmp_send(q6v5->qmp, buf); if (ret) dev_err(q6v5->dev, "failed to toggle load state\n"); diff --git a/drivers/soc/qcom/qcom_aoss.c b/drivers/soc/qcom/qcom_aoss.c index 8424d1da4db9..77f0cf126629 100644 --- a/drivers/soc/qcom/qcom_aoss.c +++ b/drivers/soc/qcom/qcom_aoss.c @@ -264,7 +264,7 @@ EXPORT_SYMBOL(qmp_send); static int qmp_qdss_clk_prepare(struct clk_hw *hw) { - static const char buf[QMP_MSG_LEN] = "{class: clock, res: qdss, val: 1}"; + static const char *buf = "{class: clock, res: qdss, val: 1}"; struct qmp *qmp = container_of(hw, struct qmp, qdss_clk); return qmp_send(qmp, buf); @@ -272,7 +272,7 @@ static int qmp_qdss_clk_prepare(struct clk_hw *hw) static void qmp_qdss_clk_unprepare(struct clk_hw *hw) { - static const char buf[QMP_MSG_LEN] = "{class: clock, res: qdss, val: 0}"; + static const char *buf = "{class: clock, res: qdss, val: 0}"; struct qmp *qmp = container_of(hw, struct qmp, qdss_clk); qmp_send(qmp, buf); @@ -334,7 +334,6 @@ static int qmp_cdev_set_cur_state(struct thermal_cooling_device *cdev, unsigned long state) { struct qmp_cooling_device *qmp_cdev = cdev->devdata; - char buf[QMP_MSG_LEN] = {}; bool cdev_state; int ret; @@ -344,13 +343,8 @@ static int qmp_cdev_set_cur_state(struct thermal_cooling_device *cdev, if (qmp_cdev->state == state) return 0; - snprintf(buf, sizeof(buf), - "{class: volt_flr, event:zero_temp, res:%s, value:%s}", - qmp_cdev->name, - cdev_state ? "on" : "off"); - - ret = qmp_send(qmp_cdev->qmp, buf); - + ret = qmp_send(qmp_cdev->qmp, "{class: volt_flr, event:zero_temp, res:%s, value:%s}", + qmp_cdev->name, cdev_state ? "on" : "off"); if (!ret) qmp_cdev->state = cdev_state; From 33e839adabedb3a958efe5d974e38e868f7a8584 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 14 Aug 2023 10:19:52 +0200 Subject: [PATCH 126/136] irqchip: irq-versatile-fpga: remove obsolete oxnas compatible Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove support for OX810 and OX820 IRQ controller. Acked-by: Krzysztof Kozlowski Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Acked-by: Marc Zyngier Acked-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230814-topic-oxnas-upstream-remove-v3-1-e2ba579a49d3@linaro.org Signed-off-by: Neil Armstrong --- drivers/irqchip/irq-versatile-fpga.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c index ba543ed9c154..5018a06060e6 100644 --- a/drivers/irqchip/irq-versatile-fpga.c +++ b/drivers/irqchip/irq-versatile-fpga.c @@ -242,5 +242,4 @@ static int __init fpga_irq_of_init(struct device_node *node, } IRQCHIP_DECLARE(arm_fpga, "arm,versatile-fpga-irq", fpga_irq_of_init); IRQCHIP_DECLARE(arm_fpga_sic, "arm,versatile-sic", fpga_irq_of_init); -IRQCHIP_DECLARE(ox810se_rps, "oxsemi,ox810se-rps-irq", fpga_irq_of_init); #endif From 5f784ff8376dd519bbe317174972423508b627c4 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 14 Aug 2023 10:19:53 +0200 Subject: [PATCH 127/136] dt-bindings: interrupt-controller: arm,versatile-fpga-irq: mark oxnas compatible as deprecated Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, mark the OX810 and OX820 IRQ compatible as deprecated. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Acked-by: Conor Dooley Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230814-topic-oxnas-upstream-remove-v3-2-e2ba579a49d3@linaro.org Signed-off-by: Neil Armstrong --- .../bindings/interrupt-controller/arm,versatile-fpga-irq.txt | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt index 2a1d16bdf834..ea939f54c5eb 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,versatile-fpga-irq.txt @@ -6,7 +6,7 @@ controllers are OR:ed together and fed to the CPU tile's IRQ input. Each instance can handle up to 32 interrupts. Required properties: -- compatible: "arm,versatile-fpga-irq" or "oxsemi,ox810se-rps-irq" +- compatible: "arm,versatile-fpga-irq" - interrupt-controller: Identifies the node as an interrupt controller - #interrupt-cells: The number of cells to define the interrupts. Must be 1 as the FPGA IRQ controller has no configuration options for interrupt @@ -19,6 +19,8 @@ Required properties: the system till not make it possible for devices to request these interrupts. +The "oxsemi,ox810se-rps-irq" compatible is deprecated. + Example: pic: pic@14000000 { From b1627ad5f457c8cea08bb2ab6b24d1c0381fbe30 Mon Sep 17 00:00:00 2001 From: Neil Armstrong Date: Mon, 14 Aug 2023 10:19:54 +0200 Subject: [PATCH 128/136] MAINTAINERS: remove OXNAS entry Due to lack of maintenance and stall of development for a few years now, and since no new features will ever be added upstream, remove MAINTAINERS entry for OXNAS files. Acked-by: Linus Walleij Acked-by: Arnd Bergmann Acked-by: Daniel Golle Acked-by: Andy Shevchenko Link: https://lore.kernel.org/r/20230814-topic-oxnas-upstream-remove-v3-3-e2ba579a49d3@linaro.org Signed-off-by: Neil Armstrong --- MAINTAINERS | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 3be1bdfe8ecc..52530b8684c6 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2491,16 +2491,6 @@ S: Maintained W: http://www.digriz.org.uk/ts78xx/kernel F: arch/arm/mach-orion5x/ts78xx-* -ARM/OXNAS platform support -M: Neil Armstrong -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -L: linux-oxnas@groups.io (moderated for non-subscribers) -S: Maintained -F: arch/arm/boot/dts/ox8*.dts* -F: arch/arm/mach-oxnas/ -F: drivers/power/reset/oxnas-restart.c -N: oxnas - ARM/QUALCOMM CHROMEBOOK SUPPORT R: cros-qcom-dts-watchers@chromium.org F: arch/arm64/boot/dts/qcom/sc7180* From a90d34afee25e8e2753859b2e00d83f6b9bf410a Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Sat, 12 Aug 2023 19:17:58 +0200 Subject: [PATCH 129/136] soc: kunpeng_hccs: add MAILBOX dependency When the mailbox subsystem is disabled, the driver fails to link, so add an explicit dependency. Some other drivers use 'select' here, but the dependency seems more logical and more common. Fixes: 886bdf9c883bc ("soc: hisilicon: Support HCCS driver on Kunpeng SoC") Signed-off-by: Arnd Bergmann --- drivers/soc/hisilicon/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/soc/hisilicon/Kconfig b/drivers/soc/hisilicon/Kconfig index 7c84dd4da0f8..0ab688af308f 100644 --- a/drivers/soc/hisilicon/Kconfig +++ b/drivers/soc/hisilicon/Kconfig @@ -6,6 +6,7 @@ menu "Hisilicon SoC drivers" config KUNPENG_HCCS tristate "HCCS driver on Kunpeng SoC" depends on ACPI + depends on MAILBOX depends on ARM64 || COMPILE_TEST help The Huawei Cache Coherence System (HCCS) is a multi-chip From de44bf2f7683347f75690ef6cf61a1d5ba8f0891 Mon Sep 17 00:00:00 2001 From: Tony Lindgren Date: Tue, 15 Aug 2023 08:49:05 +0300 Subject: [PATCH 130/136] bus: ti-sysc: Fix cast to enum warning Fix warning for "cast to smaller integer type 'enum sysc_soc' from 'const void *'". Cc: Nishanth Menon Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202308150723.ziuGCdM3-lkp@intel.com/ Fixes: e1e1e9bb9d94 ("bus: ti-sysc: Fix build warning for 64-bit build") Signed-off-by: Tony Lindgren --- drivers/bus/ti-sysc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/bus/ti-sysc.c b/drivers/bus/ti-sysc.c index 9c00802e0c20..962cdbad7573 100644 --- a/drivers/bus/ti-sysc.c +++ b/drivers/bus/ti-sysc.c @@ -3107,7 +3107,7 @@ static int sysc_init_static_data(struct sysc *ddata) match = soc_device_match(sysc_soc_match); if (match && match->data) - sysc_soc->soc = (enum sysc_soc)match->data; + sysc_soc->soc = (enum sysc_soc)(uintptr_t)match->data; /* * Check and warn about possible old incomplete dtb. We now want to see From 480a5794949cb853b933193f99df4f59bcb9d336 Mon Sep 17 00:00:00 2001 From: Jagan Teki Date: Mon, 31 Jul 2023 16:29:59 +0530 Subject: [PATCH 131/136] genpd: rockchip: Add PD_VO entry for rv1126 PD_VO power-domain entry in RV1126 are connected to - BIU_VO - VOP - RGA - IEP - DSIHOST Add an entry for it. Signed-off-by: Jagan Teki Reviewed-by: Heiko Stuebner Link: https://lore.kernel.org/r/20230731110012.2913742-2-jagan@edgeble.ai Signed-off-by: Heiko Stuebner --- drivers/genpd/rockchip/pm-domains.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/genpd/rockchip/pm-domains.c b/drivers/genpd/rockchip/pm-domains.c index e3de49e671dc..d5d3ecb38283 100644 --- a/drivers/genpd/rockchip/pm-domains.c +++ b/drivers/genpd/rockchip/pm-domains.c @@ -976,6 +976,7 @@ static const struct rockchip_domain_info px30_pm_domains[] = { static const struct rockchip_domain_info rv1126_pm_domains[] = { [RV1126_PD_VEPU] = DOMAIN_RV1126("vepu", BIT(2), BIT(9), BIT(9), false), [RV1126_PD_VI] = DOMAIN_RV1126("vi", BIT(4), BIT(6), BIT(6), false), + [RV1126_PD_VO] = DOMAIN_RV1126("vo", BIT(5), BIT(7), BIT(7), false), [RV1126_PD_ISPP] = DOMAIN_RV1126("ispp", BIT(1), BIT(8), BIT(8), false), [RV1126_PD_VDPU] = DOMAIN_RV1126("vdpu", BIT(3), BIT(10), BIT(10), false), [RV1126_PD_NVM] = DOMAIN_RV1126("nvm", BIT(7), BIT(11), BIT(11), false), From 6f6878ec6faf16a5f36761c93da6ea9cf09adb33 Mon Sep 17 00:00:00 2001 From: Ondrej Jirman Date: Mon, 19 Jun 2023 03:09:58 +0200 Subject: [PATCH 132/136] soc: rockchip: grf: Fix SDMMC not working on RK3588 with bus-width > 1 RK3588 has the same issue as other earlier RK SoCs. JTAG functionality muxed to some SDMMC data pins causes issues with SDMMC interface. Without this patch, I can only use SDMMC inteface with bus-width = <1>. (JTAG is muxed to data pins D2 and D3) Signed-off-by: Ondrej Jirman Link: https://lore.kernel.org/r/20230619011002.2249960-1-megi@xff.cz Signed-off-by: Heiko Stuebner --- drivers/soc/rockchip/grf.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/soc/rockchip/grf.c b/drivers/soc/rockchip/grf.c index 15a3970e3509..d768c5a70174 100644 --- a/drivers/soc/rockchip/grf.c +++ b/drivers/soc/rockchip/grf.c @@ -121,6 +121,17 @@ static const struct rockchip_grf_info rk3566_pipegrf __initconst = { .num_values = ARRAY_SIZE(rk3566_defaults), }; +#define RK3588_GRF_SOC_CON6 0x0318 + +static const struct rockchip_grf_value rk3588_defaults[] __initconst = { + { "jtag switching", RK3588_GRF_SOC_CON6, HIWORD_UPDATE(0, 1, 14) }, +}; + +static const struct rockchip_grf_info rk3588_sysgrf __initconst = { + .values = rk3588_defaults, + .num_values = ARRAY_SIZE(rk3588_defaults), +}; + static const struct of_device_id rockchip_grf_dt_match[] __initconst = { { @@ -147,6 +158,9 @@ static const struct of_device_id rockchip_grf_dt_match[] __initconst = { }, { .compatible = "rockchip,rk3566-pipe-grf", .data = (void *)&rk3566_pipegrf, + }, { + .compatible = "rockchip,rk3588-sys-grf", + .data = (void *)&rk3588_sysgrf, }, { /* sentinel */ }, }; From 6054a676e969b4bbf69be3f1dd7aba2443102848 Mon Sep 17 00:00:00 2001 From: Yinbo Zhu Date: Thu, 3 Aug 2023 14:37:02 +0800 Subject: [PATCH 133/136] soc: dt-bindings: add loongson-2 pm Add the Loongson-2 SoC Power Management Controller binding with DT schema format using json-schema. Signed-off-by: Yinbo Zhu Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230803063703.5659-2-zhuyinbo@loongson.cn Signed-off-by: Arnd Bergmann --- .../soc/loongson/loongson,ls2k-pmc.yaml | 52 +++++++++++++++++++ MAINTAINERS | 6 +++ 2 files changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/loongson/loongson,ls2k-pmc.yaml diff --git a/Documentation/devicetree/bindings/soc/loongson/loongson,ls2k-pmc.yaml b/Documentation/devicetree/bindings/soc/loongson/loongson,ls2k-pmc.yaml new file mode 100644 index 000000000000..da2dcfeebf12 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/loongson/loongson,ls2k-pmc.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/loongson/loongson,ls2k-pmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Loongson-2 Power Manager controller + +maintainers: + - Yinbo Zhu + +properties: + compatible: + items: + - enum: + - loongson,ls2k0500-pmc + - loongson,ls2k1000-pmc + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + loongson,suspend-address: + $ref: /schemas/types.yaml#/definitions/uint64 + description: + The "loongson,suspend-address" is a deep sleep state (Suspend To + RAM) firmware entry address which was jumped from kernel and it's + value was dependent on specific platform firmware code. In + addition, the PM need according to it to indicate that current + SoC whether support Suspend To RAM. + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + + power-management@1fe27000 { + compatible = "loongson,ls2k1000-pmc", "syscon"; + reg = <0x1fe27000 0x58>; + interrupt-parent = <&liointc1>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + loongson,suspend-address = <0x0 0x1c000500>; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 4ec7e6739470..d398892548dc 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12282,6 +12282,12 @@ S: Maintained F: Documentation/devicetree/bindings/hwinfo/loongson,ls2k-chipid.yaml F: drivers/soc/loongson/loongson2_guts.c +LOONGSON-2 SOC SERIES PM DRIVER +M: Yinbo Zhu +L: linux-pm@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/soc/loongson/loongson,ls2k-pmc.yaml + LOONGSON-2 SOC SERIES PINCTRL DRIVER M: zhanghongchen M: Yinbo Zhu From 67694c076bd7d6b8b73c59d4881822f0493caf35 Mon Sep 17 00:00:00 2001 From: Yinbo Zhu Date: Thu, 3 Aug 2023 14:37:03 +0800 Subject: [PATCH 134/136] soc: loongson2_pm: add power management support The Loongson-2's power management controller was ACPI, supports ACPI S2Idle (Suspend To Idle), ACPI S3 (Suspend To RAM), ACPI S4 (Suspend To Disk), ACPI S5 (Soft Shutdown) and supports multiple wake-up methods (USB, GMAC, PWRBTN, etc.). This driver was to add power management controller support that base on dts for Loongson-2 series SoCs. Co-developed-by: Liu Yun Signed-off-by: Liu Yun Co-developed-by: Liu Peibao Signed-off-by: Liu Peibao Cc: soc@kernel.org Cc: Ulf Hansson Signed-off-by: Yinbo Zhu Link: https://lore.kernel.org/r/20230803063703.5659-3-zhuyinbo@loongson.cn Signed-off-by: Arnd Bergmann --- MAINTAINERS | 1 + drivers/soc/loongson/Kconfig | 10 ++ drivers/soc/loongson/Makefile | 1 + drivers/soc/loongson/loongson2_pm.c | 215 ++++++++++++++++++++++++++++ 4 files changed, 227 insertions(+) create mode 100644 drivers/soc/loongson/loongson2_pm.c diff --git a/MAINTAINERS b/MAINTAINERS index d398892548dc..54da9567d7cf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12287,6 +12287,7 @@ M: Yinbo Zhu L: linux-pm@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/soc/loongson/loongson,ls2k-pmc.yaml +F: drivers/soc/loongson/loongson2_pm.c LOONGSON-2 SOC SERIES PINCTRL DRIVER M: zhanghongchen diff --git a/drivers/soc/loongson/Kconfig b/drivers/soc/loongson/Kconfig index 707f56358dc4..314e13bb3e01 100644 --- a/drivers/soc/loongson/Kconfig +++ b/drivers/soc/loongson/Kconfig @@ -16,3 +16,13 @@ config LOONGSON2_GUTS SoCs. Initially only reading SVR and registering soc device are supported. Other guts accesses, such as reading firmware configuration by default, should eventually be added into this driver as well. + +config LOONGSON2_PM + bool "Loongson-2 SoC Power Management Controller Driver" + depends on LOONGARCH && OF + help + The Loongson-2's power management controller was ACPI, supports ACPI + S2Idle (Suspend To Idle), ACPI S3 (Suspend To RAM), ACPI S4 (Suspend To + Disk), ACPI S5 (Soft Shutdown) and supports multiple wake-up methods + (USB, GMAC, PWRBTN, etc.). This driver was to add power management + controller support that base on dts for Loongson-2 series SoCs. diff --git a/drivers/soc/loongson/Makefile b/drivers/soc/loongson/Makefile index 263c486df638..4118f50f55e2 100644 --- a/drivers/soc/loongson/Makefile +++ b/drivers/soc/loongson/Makefile @@ -4,3 +4,4 @@ # obj-$(CONFIG_LOONGSON2_GUTS) += loongson2_guts.o +obj-$(CONFIG_LOONGSON2_PM) += loongson2_pm.o diff --git a/drivers/soc/loongson/loongson2_pm.c b/drivers/soc/loongson/loongson2_pm.c new file mode 100644 index 000000000000..796add6e8b63 --- /dev/null +++ b/drivers/soc/loongson/loongson2_pm.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Loongson-2 PM Support + * + * Copyright (C) 2023 Loongson Technology Corporation Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define LOONGSON2_PM1_CNT_REG 0x14 +#define LOONGSON2_PM1_STS_REG 0x0c +#define LOONGSON2_PM1_ENA_REG 0x10 +#define LOONGSON2_GPE0_STS_REG 0x28 +#define LOONGSON2_GPE0_ENA_REG 0x2c + +#define LOONGSON2_PM1_PWRBTN_STS BIT(8) +#define LOONGSON2_PM1_PCIEXP_WAKE_STS BIT(14) +#define LOONGSON2_PM1_WAKE_STS BIT(15) +#define LOONGSON2_PM1_CNT_INT_EN BIT(0) +#define LOONGSON2_PM1_PWRBTN_EN LOONGSON2_PM1_PWRBTN_STS + +static struct loongson2_pm { + void __iomem *base; + struct input_dev *dev; + bool suspended; +} loongson2_pm; + +#define loongson2_pm_readw(reg) readw(loongson2_pm.base + reg) +#define loongson2_pm_readl(reg) readl(loongson2_pm.base + reg) +#define loongson2_pm_writew(val, reg) writew(val, loongson2_pm.base + reg) +#define loongson2_pm_writel(val, reg) writel(val, loongson2_pm.base + reg) + +static void loongson2_pm_status_clear(void) +{ + u16 value; + + value = loongson2_pm_readw(LOONGSON2_PM1_STS_REG); + value |= (LOONGSON2_PM1_PWRBTN_STS | LOONGSON2_PM1_PCIEXP_WAKE_STS | + LOONGSON2_PM1_WAKE_STS); + loongson2_pm_writew(value, LOONGSON2_PM1_STS_REG); + loongson2_pm_writel(loongson2_pm_readl(LOONGSON2_GPE0_STS_REG), LOONGSON2_GPE0_STS_REG); +} + +static void loongson2_pm_irq_enable(void) +{ + u16 value; + + value = loongson2_pm_readw(LOONGSON2_PM1_CNT_REG); + value |= LOONGSON2_PM1_CNT_INT_EN; + loongson2_pm_writew(value, LOONGSON2_PM1_CNT_REG); + + value = loongson2_pm_readw(LOONGSON2_PM1_ENA_REG); + value |= LOONGSON2_PM1_PWRBTN_EN; + loongson2_pm_writew(value, LOONGSON2_PM1_ENA_REG); +} + +static int loongson2_suspend_enter(suspend_state_t state) +{ + loongson2_pm_status_clear(); + loongarch_common_suspend(); + loongarch_suspend_enter(); + loongarch_common_resume(); + loongson2_pm_irq_enable(); + pm_set_resume_via_firmware(); + + return 0; +} + +static int loongson2_suspend_begin(suspend_state_t state) +{ + pm_set_suspend_via_firmware(); + + return 0; +} + +static int loongson2_suspend_valid_state(suspend_state_t state) +{ + return (state == PM_SUSPEND_MEM); +} + +static const struct platform_suspend_ops loongson2_suspend_ops = { + .valid = loongson2_suspend_valid_state, + .begin = loongson2_suspend_begin, + .enter = loongson2_suspend_enter, +}; + +static int loongson2_power_button_init(struct device *dev, int irq) +{ + int ret; + struct input_dev *button; + + button = input_allocate_device(); + if (!dev) + return -ENOMEM; + + button->name = "Power Button"; + button->phys = "pm/button/input0"; + button->id.bustype = BUS_HOST; + button->dev.parent = NULL; + input_set_capability(button, EV_KEY, KEY_POWER); + + ret = input_register_device(button); + if (ret) + goto free_dev; + + dev_pm_set_wake_irq(&button->dev, irq); + device_set_wakeup_capable(&button->dev, true); + device_set_wakeup_enable(&button->dev, true); + + loongson2_pm.dev = button; + dev_info(dev, "Power Button: Init successful!\n"); + + return 0; + +free_dev: + input_free_device(button); + + return ret; +} + +static irqreturn_t loongson2_pm_irq_handler(int irq, void *dev_id) +{ + u16 status = loongson2_pm_readw(LOONGSON2_PM1_STS_REG); + + if (!loongson2_pm.suspended && (status & LOONGSON2_PM1_PWRBTN_STS)) { + pr_info("Power Button pressed...\n"); + input_report_key(loongson2_pm.dev, KEY_POWER, 1); + input_sync(loongson2_pm.dev); + input_report_key(loongson2_pm.dev, KEY_POWER, 0); + input_sync(loongson2_pm.dev); + } + + loongson2_pm_status_clear(); + + return IRQ_HANDLED; +} + +static int __maybe_unused loongson2_pm_suspend(struct device *dev) +{ + loongson2_pm.suspended = true; + + return 0; +} + +static int __maybe_unused loongson2_pm_resume(struct device *dev) +{ + loongson2_pm.suspended = false; + + return 0; +} +static SIMPLE_DEV_PM_OPS(loongson2_pm_ops, loongson2_pm_suspend, loongson2_pm_resume); + +static int loongson2_pm_probe(struct platform_device *pdev) +{ + int irq, retval; + u64 suspend_addr; + struct device *dev = &pdev->dev; + + loongson2_pm.base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(loongson2_pm.base)) + return PTR_ERR(loongson2_pm.base); + + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + if (!device_property_read_u64(dev, "loongson,suspend-address", &suspend_addr)) + loongson_sysconf.suspend_addr = (u64)phys_to_virt(suspend_addr); + else + dev_err(dev, "No loongson,suspend-address, could not support S3!\n"); + + if (loongson2_power_button_init(dev, irq)) + return -EINVAL; + + retval = devm_request_irq(&pdev->dev, irq, loongson2_pm_irq_handler, + IRQF_SHARED, "pm_irq", &loongson2_pm); + if (retval) + return retval; + + loongson2_pm_irq_enable(); + loongson2_pm_status_clear(); + + if (loongson_sysconf.suspend_addr) + suspend_set_ops(&loongson2_suspend_ops); + + return 0; +} + +static const struct of_device_id loongson2_pm_match[] = { + { .compatible = "loongson,ls2k0500-pmc", }, + { .compatible = "loongson,ls2k1000-pmc", }, + {}, +}; + +static struct platform_driver loongson2_pm_driver = { + .driver = { + .name = "ls2k-pm", + .pm = &loongson2_pm_ops, + .of_match_table = loongson2_pm_match, + }, + .probe = loongson2_pm_probe, +}; +module_platform_driver(loongson2_pm_driver); + +MODULE_DESCRIPTION("Loongson-2 PM driver"); +MODULE_LICENSE("GPL"); From 7d6612834d176a1343aea4b2f01efa94f1cea68f Mon Sep 17 00:00:00 2001 From: Huisong Li Date: Wed, 16 Aug 2023 15:37:06 +0800 Subject: [PATCH 135/136] soc: kunpeng_hccs: fix some sparse warnings about incorrect type This patch fixes some sparse warnings about incorrect type. The address about PCC communication space should use '__iomem' tag. Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202308151142.dH5Muhva-lkp@intel.com/ Fixes: 886bdf9c883b ("soc: hisilicon: Support HCCS driver on Kunpeng SoC") Signed-off-by: Huisong Li Link: https://lore.kernel.org/r/20230816073706.33297-1-lihuisong@huawei.com Signed-off-by: Arnd Bergmann --- drivers/soc/hisilicon/kunpeng_hccs.c | 13 +++++++------ drivers/soc/hisilicon/kunpeng_hccs.h | 2 +- 2 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/soc/hisilicon/kunpeng_hccs.c b/drivers/soc/hisilicon/kunpeng_hccs.c index 0d6f6bacd3f6..f3810d9d1caa 100644 --- a/drivers/soc/hisilicon/kunpeng_hccs.c +++ b/drivers/soc/hisilicon/kunpeng_hccs.c @@ -156,8 +156,8 @@ static int hccs_register_pcc_channel(struct hccs_dev *hdev) } if (pcc_chan->shmem_base_addr) { - cl_info->pcc_comm_addr = (void __force *)ioremap( - pcc_chan->shmem_base_addr, pcc_chan->shmem_size); + cl_info->pcc_comm_addr = ioremap(pcc_chan->shmem_base_addr, + pcc_chan->shmem_size); if (!cl_info->pcc_comm_addr) { dev_err(dev, "Failed to ioremap PCC communication region for channel-%d.\n", hdev->chan_id); @@ -177,7 +177,8 @@ out: static int hccs_check_chan_cmd_complete(struct hccs_dev *hdev) { struct hccs_mbox_client_info *cl_info = &hdev->cl_info; - struct acpi_pcct_shared_memory *comm_base = cl_info->pcc_comm_addr; + struct acpi_pcct_shared_memory __iomem *comm_base = + cl_info->pcc_comm_addr; u16 status; int ret; @@ -199,8 +200,8 @@ static int hccs_pcc_cmd_send(struct hccs_dev *hdev, u8 cmd, struct hccs_desc *desc) { struct hccs_mbox_client_info *cl_info = &hdev->cl_info; - struct acpi_pcct_shared_memory *comm_base = cl_info->pcc_comm_addr; - void *comm_space = (void *)(comm_base + 1); + void __iomem *comm_space = cl_info->pcc_comm_addr + + sizeof(struct acpi_pcct_shared_memory); struct hccs_fw_inner_head *fw_inner_head; struct acpi_pcct_shared_memory tmp = {0}; u16 comm_space_size; @@ -212,7 +213,7 @@ static int hccs_pcc_cmd_send(struct hccs_dev *hdev, u8 cmd, tmp.command = cmd; /* Clear cmd complete bit */ tmp.status = 0; - memcpy_toio(comm_base, (void *)&tmp, + memcpy_toio(cl_info->pcc_comm_addr, (void *)&tmp, sizeof(struct acpi_pcct_shared_memory)); /* Copy the message to the PCC comm space */ diff --git a/drivers/soc/hisilicon/kunpeng_hccs.h b/drivers/soc/hisilicon/kunpeng_hccs.h index 9d71fb78443f..6012d2776028 100644 --- a/drivers/soc/hisilicon/kunpeng_hccs.h +++ b/drivers/soc/hisilicon/kunpeng_hccs.h @@ -50,7 +50,7 @@ struct hccs_mbox_client_info { struct mbox_chan *mbox_chan; struct pcc_mbox_chan *pcc_chan; u64 deadline_us; - void *pcc_comm_addr; + void __iomem *pcc_comm_addr; }; struct hccs_dev { From 09959520d2b0853a16962d245acfdc995d1b0da9 Mon Sep 17 00:00:00 2001 From: Rob Herring Date: Wed, 23 Aug 2023 14:09:42 -0500 Subject: [PATCH 136/136] bus: fsl-mc: Use common ranges functions Since commit 3d5089c4263d ("of/address: Add support for 3 address cell bus"), the DT address functions can handle translating buses with 3 address cells. Replace the custom code with the for_each_of_range() iterator. The original code had fallbacks to get "#address-cells"/"#size-cells" from the bus parent node if they are missing. This is non-standard behavior, and AFAICT the upstream .dts files never relied on that. Reviewed-by: Laurentiu Tudor Tested-by: Laurentiu Tudor Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230823190958.2717267-1-robh@kernel.org Signed-off-by: Arnd Bergmann --- drivers/bus/fsl-mc/fsl-mc-bus.c | 90 +++++---------------------------- 1 file changed, 13 insertions(+), 77 deletions(-) diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c index 4352745a923c..e2c30b4c9aa6 100644 --- a/drivers/bus/fsl-mc/fsl-mc-bus.c +++ b/drivers/bus/fsl-mc/fsl-mc-bus.c @@ -994,75 +994,18 @@ struct fsl_mc_device *fsl_mc_get_endpoint(struct fsl_mc_device *mc_dev, } EXPORT_SYMBOL_GPL(fsl_mc_get_endpoint); -static int parse_mc_ranges(struct device *dev, - int *paddr_cells, - int *mc_addr_cells, - int *mc_size_cells, - const __be32 **ranges_start) -{ - const __be32 *prop; - int range_tuple_cell_count; - int ranges_len; - int tuple_len; - struct device_node *mc_node = dev->of_node; - - *ranges_start = of_get_property(mc_node, "ranges", &ranges_len); - if (!(*ranges_start) || !ranges_len) { - dev_warn(dev, - "missing or empty ranges property for device tree node '%pOFn'\n", - mc_node); - return 0; - } - - *paddr_cells = of_n_addr_cells(mc_node); - - prop = of_get_property(mc_node, "#address-cells", NULL); - if (prop) - *mc_addr_cells = be32_to_cpup(prop); - else - *mc_addr_cells = *paddr_cells; - - prop = of_get_property(mc_node, "#size-cells", NULL); - if (prop) - *mc_size_cells = be32_to_cpup(prop); - else - *mc_size_cells = of_n_size_cells(mc_node); - - range_tuple_cell_count = *paddr_cells + *mc_addr_cells + - *mc_size_cells; - - tuple_len = range_tuple_cell_count * sizeof(__be32); - if (ranges_len % tuple_len != 0) { - dev_err(dev, "malformed ranges property '%pOFn'\n", mc_node); - return -EINVAL; - } - - return ranges_len / tuple_len; -} - static int get_mc_addr_translation_ranges(struct device *dev, struct fsl_mc_addr_translation_range **ranges, u8 *num_ranges) { - int ret; - int paddr_cells; - int mc_addr_cells; - int mc_size_cells; - int i; - const __be32 *ranges_start; - const __be32 *cell; + struct fsl_mc_addr_translation_range *r; + struct of_range_parser parser; + struct of_range range; - ret = parse_mc_ranges(dev, - &paddr_cells, - &mc_addr_cells, - &mc_size_cells, - &ranges_start); - if (ret < 0) - return ret; - - *num_ranges = ret; - if (!ret) { + of_range_parser_init(&parser, dev->of_node); + *num_ranges = of_range_count(&parser); + if (!*num_ranges) { /* * Missing or empty ranges property ("ranges;") for the * 'fsl,qoriq-mc' node. In this case, identity mapping @@ -1078,20 +1021,13 @@ static int get_mc_addr_translation_ranges(struct device *dev, if (!(*ranges)) return -ENOMEM; - cell = ranges_start; - for (i = 0; i < *num_ranges; ++i) { - struct fsl_mc_addr_translation_range *range = &(*ranges)[i]; - - range->mc_region_type = of_read_number(cell, 1); - range->start_mc_offset = of_read_number(cell + 1, - mc_addr_cells - 1); - cell += mc_addr_cells; - range->start_phys_addr = of_read_number(cell, paddr_cells); - cell += paddr_cells; - range->end_mc_offset = range->start_mc_offset + - of_read_number(cell, mc_size_cells); - - cell += mc_size_cells; + r = *ranges; + for_each_of_range(&parser, &range) { + r->mc_region_type = range.flags; + r->start_mc_offset = range.bus_addr; + r->end_mc_offset = range.bus_addr + range.size; + r->start_phys_addr = range.cpu_addr; + r++; } return 0;