From 06f799fa0334ff1ca043fa402e5c93ffeaf4e223 Mon Sep 17 00:00:00 2001 From: Jean-Baptiste Maneyrol Date: Fri, 7 Jun 2024 08:10:39 +0000 Subject: [PATCH] iio: imu: inv_icm42600: add register caching in the regmap BugLink: https://bugs.launchpad.net/bugs/2106770 Register caching is improving bus access a lot because of the register window bank setting. Previously, bank register was set for every register access. Now with caching, it happens only when changing bank which is very infrequent. Signed-off-by: Jean-Baptiste Maneyrol Link: https://lore.kernel.org/r/20240607081039.789079-1-inv.git-commit@tdk.com Signed-off-by: Jonathan Cameron (cherry picked from commit 50cfe81b71e50d7a7f6afb84d5dbe084ed4ea174) [diewald: prerequisite for c0f866de4ce4 iio: imu: inv_icm42600: fix spi burst write not supported] Signed-off-by: Manuel Diewald Signed-off-by: Mehmet Basaran --- .../iio/imu/inv_icm42600/inv_icm42600_core.c | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c b/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c index d938bc454397..29a896bb1f7f 100644 --- a/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c +++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_core.c @@ -35,12 +35,56 @@ static const struct regmap_range_cfg inv_icm42600_regmap_ranges[] = { }, }; +static const struct regmap_range inv_icm42600_regmap_volatile_yes_ranges[] = { + /* Sensor data registers */ + regmap_reg_range(0x001D, 0x002A), + /* INT status, FIFO, APEX data */ + regmap_reg_range(0x002D, 0x0038), + /* Signal path reset */ + regmap_reg_range(0x004B, 0x004B), + /* FIFO lost packets */ + regmap_reg_range(0x006C, 0x006D), + /* Timestamp value */ + regmap_reg_range(0x1062, 0x1064), +}; + +static const struct regmap_range inv_icm42600_regmap_volatile_no_ranges[] = { + regmap_reg_range(0x0000, 0x001C), + regmap_reg_range(0x006E, 0x1061), + regmap_reg_range(0x1065, 0x4FFF), +}; + +static const struct regmap_access_table inv_icm42600_regmap_volatile_accesses[] = { + { + .yes_ranges = inv_icm42600_regmap_volatile_yes_ranges, + .n_yes_ranges = ARRAY_SIZE(inv_icm42600_regmap_volatile_yes_ranges), + .no_ranges = inv_icm42600_regmap_volatile_no_ranges, + .n_no_ranges = ARRAY_SIZE(inv_icm42600_regmap_volatile_no_ranges), + }, +}; + +static const struct regmap_range inv_icm42600_regmap_rd_noinc_no_ranges[] = { + regmap_reg_range(0x0000, INV_ICM42600_REG_FIFO_DATA - 1), + regmap_reg_range(INV_ICM42600_REG_FIFO_DATA + 1, 0x4FFF), +}; + +static const struct regmap_access_table inv_icm42600_regmap_rd_noinc_accesses[] = { + { + .no_ranges = inv_icm42600_regmap_rd_noinc_no_ranges, + .n_no_ranges = ARRAY_SIZE(inv_icm42600_regmap_rd_noinc_no_ranges), + }, +}; + const struct regmap_config inv_icm42600_regmap_config = { + .name = "inv_icm42600", .reg_bits = 8, .val_bits = 8, .max_register = 0x4FFF, .ranges = inv_icm42600_regmap_ranges, .num_ranges = ARRAY_SIZE(inv_icm42600_regmap_ranges), + .volatile_table = inv_icm42600_regmap_volatile_accesses, + .rd_noinc_table = inv_icm42600_regmap_rd_noinc_accesses, + .cache_type = REGCACHE_RBTREE, }; EXPORT_SYMBOL_NS_GPL(inv_icm42600_regmap_config, IIO_ICM42600);