tmakin/tegra-linux-noble
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

net/wan/fsl_ucc_hdlc: add hdlc-bus support

Browse Source 
This adds support for hdlc-bus mode to the fsl_ucc_hdlc driver. This can
be enabled with the "fsl,hdlc-bus" property in the DTS node of the
corresponding ucc.

This aligns the configuration of the UPSMR and GUMR registers to what is
done in our ucc_hdlc driver (that only support hdlc-bus mode) and with
the QuickEngine's documentation for hdlc-bus mode.

GUMR/SYNL is set to AUTO for the busmode as in this case the CD signal
is ignored. The brkpt_support is enabled to set the HBM1 bit in the
CMXUCR register to configure an open-drain connected HDLC bus.

Signed-off-by: Holger Brunck <holger.brunck@keymile.com>
Cc: Zhao Qiang <qiang.zhao@nxp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Holger Brunck
2017-05-17 17:24:38 +02:00
committed by David S. Miller
parent c7f235a7c2
commit 067bb938da
3 changed files with 38 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/soc/fsl/qe/qe.h
+5
View File
@@ -789,6 +789,11 @@ struct ucc_slow_pram {
#define UCC_GETH_UPSMR_SMM 0x00000080
#define UCC_GETH_UPSMR_SGMM 0x00000020
/* UCC Protocol Specific Mode Register (UPSMR), when used for HDLC */
#define UCC_HDLC_UPSMR_RTE 0x02000000
#define UCC_HDLC_UPSMR_BUS 0x00200000
#define UCC_HDLC_UPSMR_CW8 0x00007000
/* UCC Transmit On Demand Register (UTODR) */
#define UCC_SLOW_TOD 0x8000
#define UCC_FAST_TOD 0x8000