From 03986412c48df62cfdec5cee98b7423fcf8d6550 Mon Sep 17 00:00:00 2001 From: Sumit Gupta Date: Wed, 10 Jan 2024 13:35:15 +0530 Subject: [PATCH] NVIDIA: SAUCE: soc: tegra: cbb: update register offsets for NET10 CBB register offsets have changed in header files for NET10. Update those as per the CL 71970723 used for NET10. http://nvbugs/4136792 Signed-off-by: Sumit Gupta Signed-off-by: Laxman Dewangan Acked-by: Noah Wager Acked-by: Jacob Martin Signed-off-by: Noah Wager --- drivers/soc/tegra/cbb/tegra234-cbb.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/soc/tegra/cbb/tegra234-cbb.c b/drivers/soc/tegra/cbb/tegra234-cbb.c index da8ac23dfabe..bb9aeda0644d 100644 --- a/drivers/soc/tegra/cbb/tegra234-cbb.c +++ b/drivers/soc/tegra/cbb/tegra234-cbb.c @@ -1150,8 +1150,8 @@ static const struct tegra234_cbb_fabric tegra264_top0_cbb_fabric = { .notifier_offset = 0x90000, .off_mask_erd = 0x4a004, .firewall_base = 0x3c0000, - .firewall_ctl = 0x610, - .firewall_wr_ctl = 0x608, + .firewall_ctl = 0x5b0, + .firewall_wr_ctl = 0x5a8, }; /* To be filled later when address map is more stabilized */ @@ -1210,8 +1210,8 @@ static const struct tegra234_cbb_fabric tegra264_vision_cbb_fabric = { .err_status_clr = 0x1ff007f, .notifier_offset = 0x80000, .firewall_base = 0x290000, - .firewall_ctl = 0x630, - .firewall_wr_ctl = 0x628, + .firewall_ctl = 0x5d0, + .firewall_wr_ctl = 0x5c8, }; static const struct of_device_id tegra234_cbb_dt_ids[] = {