diff --git a/tegra210-odin-prods.dtsi b/tegra210-odin-prods.dtsi deleted file mode 100644 index f8683ea..0000000 --- a/tegra210-odin-prods.dtsi +++ /dev/null @@ -1,131 +0,0 @@ -/* - * Copyright (c) 2019-2020, Billy Laws - * Copyright (c) 2019-2022, CTCaer - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - */ - -/ { - host1x@50000000 { - sor@54580000 { - prod-settings { - #prod-cells = <3>; - prod_list_hdmi_board = "prod_c_hdmi_54m_75m", "prod_c_hdmi_75m_150m", - "prod_c_hdmi_150m_300m", "prod_c_hdmi_300m_600m"; - prod_c_hdmi_54m_75m { - board { - prod = < - 0x000003a0 0x00000002 0x00000002 // SOR_NV_PDISP_INPUT_CONTROL 01:01=ARM_VIDEO_RANGE 0x1 - 0x0000005c 0x0f000700 0x01000300 // SOR_NV_PDISP_SOR_PLL0_0 11:08=VCOCAP 0x3 - // 27:24=ICHPMP 0x1 - 0x00000060 0x00f01f00 0x00301300 // SOR_NV_PDISP_SOR_PLL1_0 08:08=TMDS_TERM 0x1 - // 12:09=TMDS_TERMADJ 0x9 - // 23:20=LOADADJ 0x3 - 0x00000068 0x0f000000 0x08000000 // SOR_NV_PSIDP_SOR_PLL3_0 27:24=BG_VREF_LEVEL 0x8 - 0x00000138 0xffffffff 0x29292929 // SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0 - // 31:24=LANE3_DP_LANE3 0x29 - // 23:16=LANE2_DP_LANE0 0x29 - // 15:08=LANE1_DP_LANE1 0x29 - // 07:00=LANE0_DP_LANE2 0x29 - 0x00000148 0xffffffff 0x00000000 // SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0 - // 31:24=LANE3_DP_LANE3 0x00 - // 23:16=LANE2_DP_LANE0 0x00 - // 15:08=LANE1_DP_LANE1 0x00 - // 07:00=LANE0_DP_LANE2 0x00 - 0x00000170 0x0040ff00 0x00404000 // SOR_NV_PDISP_SOR_DP_PADCTL0_0 - // 22:22=TX_PU 0x1 - // 15:08=TX_PU_VALUE 0x40 - - >; - }; - }; - prod_c_hdmi_75m_150m { - board { - prod = < - 0x000003a0 0x00000002 0x00000000 // SOR_NV_PDISP_INPUT_CONTROL 01:01=ARM_VIDEO_RANGE 0x0 - 0x0000005c 0x0f000700 0x01000300 // SOR_NV_PDISP_SOR_PLL0_0 11:08=VCOCAP 0x3 - // 27:24=ICHPMP 0x1 - 0x00000060 0x00f01f00 0x00301300 // SOR_NV_PDISP_SOR_PLL1_0 08:08=TMDS_TERM 0x1 - // 12:09=TMDS_TERMADJ 0x9 - // 23:20=LOADADJ 0x3 - 0x00000068 0x0f000000 0x08000000 // SOR_NV_PSIDP_SOR_PLL3_0 27:24=BG_VREF_LEVEL 0x8 - 0x00000138 0xffffffff 0x30373737 // SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0 - // 31:24=LANE3_DP_LANE3 0x30 - // 23:16=LANE2_DP_LANE0 0x37 - // 15:08=LANE1_DP_LANE1 0x37 - // 07:00=LANE0_DP_LANE2 0x37 - 0x00000148 0xffffffff 0x01020202 // SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0 - // 31:24=LANE3_DP_LANE3 0x01 - // 23:16=LANE2_DP_LANE0 0x02 - // 15:08=LANE1_DP_LANE1 0x02 - // 07:00=LANE0_DP_LANE2 0x02 - 0x00000170 0x0040ff00 0x00406600 // SOR_NV_PDISP_SOR_DP_PADCTL0_0 - // 22:22=TX_PU 0x1 - // 15:08=TX_PU_VALUE 0x66 - >; - }; - }; - prod_c_hdmi_150m_300m { - board { - prod = < - 0x000003a0 0x00000002 0x00000000 // SOR_NV_PDISP_INPUT_CONTROL 01:01=ARM_VIDEO_RANGE 0x0 - 0x0000005c 0x0f000700 0x06000300 // SOR_NV_PDISP_SOR_PLL0_0 11:08=VCOCAP 0x3 - // 27:24=ICHPMP 0x6 - 0x00000060 0x00f01f00 0x00301300 // SOR_NV_PDISP_SOR_PLL1_0 08:08=TMDS_TERM 0x1 - // 12:09=TMDS_TERMADJ 0x9 - // 23:20=LOADADJ 0x3 - 0x00000068 0x0f000000 0x0F000000 // SOR_NV_PSIDP_SOR_PLL3_0 27:24=BG_VREF_LEVEL 0xF - 0x00000138 0xffffffff 0x30373737 // SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0 - // 31:24=LANE3_DP_LANE3 0x30 - // 23:16=LANE2_DP_LANE0 0x37 - // 15:08=LANE1_DP_LANE1 0x37 - // 07:00=LANE0_DP_LANE2 0x37 - 0x00000148 0xffffffff 0x103E3E3E // SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0 - // 31:24=LANE3_DP_LANE3 0x10 - // 23:16=LANE2_DP_LANE0 0x3E - // 15:08=LANE1_DP_LANE1 0x3E - // 07:00=LANE0_DP_LANE2 0x3E - 0x00000170 0x0040ff00 0x00406600 // SOR_NV_PDISP_SOR_DP_PADCTL0_0 - // 22:22=TX_PU 0x1 - // 15:08=TX_PU_VALUE 0x66 - >; - }; - }; - prod_c_hdmi_300m_600m { - board { - prod = < - 0x000003a0 0x00000002 0x00000002 // SOR_NV_PDISP_INPUT_CONTROL 01:01=ARM_VIDEO_RANGE 0x1 - 0x0000005c 0x0f000700 0x0A000300 // SOR_NV_PDISP_SOR_PLL0_0 11:08=VCOCAP 0x3 - // 27:24=ICHPMP 0xA - 0x00000060 0x00f01f00 0x00301700 // SOR_NV_PDISP_SOR_PLL1_0 08:08=TMDS_TERM 0x1 - // 12:09=TMDS_TERMADJ 0xB - // 23:20=LOADADJ 0x3 - 0x00000068 0x0f000000 0x0E000000 // SOR_NV_PSIDP_SOR_PLL3_0 27:24=BG_VREF_LEVEL 0xE - 0x00000138 0xffffffff 0x353E3E3E // SOR_NV_PDISP_SOR_LANE_DRIVE_CURRENT0_0 - // 31:24=LANE3_DP_LANE3 0x35 - // 23:16=LANE2_DP_LANE0 0x3E - // 15:08=LANE1_DP_LANE1 0x3E - // 07:00=LANE0_DP_LANE2 0x3E - 0x00000148 0xffffffff 0x023F3F3F // SOR_NV_PDISP_SOR_LANE_PREEMPHASIS0_0 - // 31:24=LANE3_DP_LANE3 0x02 - // 23:16=LANE2_DP_LANE0 0x3F - // 15:08=LANE1_DP_LANE1 0x3F - // 07:00=LANE0_DP_LANE2 0x3F - 0x00000170 0x0040ff00 0x00406600 // SOR_NV_PDISP_SOR_DP_PADCTL0_0 - // 22:22=TX_PU 0x1 - // 15:08=TX_PU_VALUE 0x66 - >; - }; - }; - }; - }; - }; -}; diff --git a/tegra210-odin.dts b/tegra210-odin.dts index 8bceba6..3569df4 100644 --- a/tegra210-odin.dts +++ b/tegra210-odin.dts @@ -2,7 +2,6 @@ /dts-v1/; #include "tegra210-nx.dtsi" -#include "tegra210-odin-prods.dtsi" / { model = "Nintendo Switch (2017)"; @@ -71,6 +70,11 @@ avdd_dsi_csi-supply = <&max77620_gpio7>; }; + sor1: sor@54580000 { + /* use odin hdmi defaults */ + compatible = "nvidia,tegra210-sor1-odin"; + }; + vi: i2c@546c0000 { avdd_dsi_csi-supply = <&max77620_gpio7>; };