Peter De Schrijver fd2bf45a19 clk: tegra: apply regulator align to Vmin ...

Apply regulator alignment when using Vmin to determine the lowest possible
rate generated by the DFLL.

Change-Id: I169528614871733e4a7568f3ec740079b0e9d097
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1584439
GVS: Gerrit_Virtual_Submit
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

2026-08-28 19:17:10 -05:00

..

clk-audio-sync.c

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-21 17:09:51 -08:00

clk-bpmp.c

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-21 17:09:51 -08:00

clk-device.c

clk: tegra: Adjust callbacks in tegra_clock_pm

2026-01-17 01:13:24 +01:00

clk-dfll.c

clk: tegra: apply regulator align to Vmin

2026-08-28 19:17:10 -05:00

clk-dfll.h

clk: soc: tegra: Add DFLL tune high margin voltage

2026-08-28 19:17:10 -05:00

clk-divider.c

Revert "mmc: sdhci: pedantic clock rate debug logging"

2026-08-24 18:39:43 -05:00

clk-id.h

clk: tegra: Fix duplicated SE clock entry

2020-12-10 12:51:59 -08:00

clk-periph-fixed.c

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-21 17:09:51 -08:00

clk-periph-gate.c

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-21 17:09:51 -08:00

clk-periph.c

clk: tegra: periph: divider: convert from round_rate() to determine_rate()

2025-09-08 12:50:41 -04:00

clk-pll-out.c

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-21 17:09:51 -08:00

clk-pll.c

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-21 17:09:51 -08:00

clk-sdmmc-mux.c

Revert "mmc: sdhci: pedantic clock rate debug logging"

2026-08-24 18:39:43 -05:00

clk-super.c

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-21 17:09:51 -08:00

clk-tegra20-emc.c

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-21 17:09:51 -08:00

clk-tegra20.c

clk: tegra: Set CSUS as vi_sensor's gate for Tegra20, Tegra30 and Tegra114

2026-01-17 01:32:18 +01:00

clk-tegra30.c

clk: tegra30: Add CSI pad clock gates

2026-01-17 01:33:18 +01:00

clk-tegra114.c

clk: tegra: Set CSUS as vi_sensor's gate for Tegra20, Tegra30 and Tegra114

2026-01-17 01:32:18 +01:00

clk-tegra124-dfll-fcpu.c

soc: tegra: Add support for DFLL Vmin CVB

2026-08-28 19:17:10 -05:00

clk-tegra124-emc.c

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-21 17:09:51 -08:00

clk-tegra124.c

clk: tegra: Fix Tegra PWM parent clock

2022-10-14 13:44:24 -07:00

clk-tegra210-emc.c

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-21 17:09:51 -08:00

clk-tegra210.c

clk changes, test later

2026-08-24 18:39:42 -05:00

clk-tegra210b01.c

clk changes, test later

2026-08-24 18:39:42 -05:00

clk-tegra-audio.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201

2019-05-30 11:29:52 -07:00

clk-tegra-fixed.c

clk: tegra: Remove CLK_M_DIV fixed clocks

2020-03-12 11:33:32 +01:00

clk-tegra-periph.c

clk: tegra: Add Tegra210B01 support

2026-07-24 02:44:54 -05:00

clk-tegra-super-cclk.c

Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

2026-02-21 17:09:51 -08:00

clk-tegra-super-gen4.c

clk: tegra: clk-super: Fix to enable PLLP branches to CPU

2019-11-11 14:53:03 +01:00

clk-utils.c

Revert "mmc: sdhci: pedantic clock rate debug logging"

2026-08-24 18:39:43 -05:00

clk.c

clk: tegra: Add Tegra210B01 support

2026-07-24 02:44:54 -05:00

clk.h

clk: tegra: Add Tegra210B01 support

2026-07-24 02:44:54 -05:00

cvb.c

soc: tegra: Add support for DFLL Vmin CVB

2026-08-28 19:17:10 -05:00

cvb.h

soc: tegra: Add support for DFLL Vmin CVB

2026-08-28 19:17:10 -05:00

Kconfig

clk: tegra: dfll: Add CVB tables for Tegra114

2025-09-14 08:23:28 +02:00

Makefile

clk: tegra: Add Tegra210B01 support

2026-07-24 02:44:54 -05:00