Files
ack-tegra/drivers/clk/tegra/clk-utils.c
T
tmakin 2458ea9a04 Revert "mmc: sdhci: pedantic clock rate debug logging"
This reverts commit 17bfd541f2b904f4ba87f0fcb3e2d3b4332d1802.
2026-08-24 18:39:43 -05:00

44 lines
840 B
C

// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
*/
#include <asm/div64.h>
#include "clk.h"
#define div_mask(w) ((1 << (w)) - 1)
int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
u8 frac_width, u8 flags)
{
s64 divider_ux1 = parent_rate;
int mul;
if (!rate)
return div_mask(width);
mul = 1 << frac_width;
if (!(flags & TEGRA_DIVIDER_INT))
divider_ux1 *= mul;
if (flags & TEGRA_DIVIDER_ROUND_UP)
divider_ux1 += rate - 1;
do_div(divider_ux1, rate);
if (flags & TEGRA_DIVIDER_INT)
divider_ux1 *= mul;
divider_ux1 -= mul;
if (divider_ux1 > div_mask(width))
return div_mask(width);
if (div1_5_not_allowed && (divider_ux1 > 0) && (divider_ux1 < mul))
divider_ux1 = (flags & TEGRA_DIVIDER_ROUND_UP) ? mul : 0;
return divider_ux1;
}