tmakin
d786880067
Add pr_info-level logging across the SDHCI subsystem and the Tegra
SDMMC clock providers so clock rate calculation, rounding, assigned
clocks and parents are visible in dmesg without needing dynamic_debug.
- sdhci-tegra: log curr_clk_rate/max_clk/clock on set_clock entry and
after clk_get_rate(), the requested host_clk, the rounded
get_max_clock value, and dump regs before hw tuning.
- sdhci: promote the DBG() macro from pr_debug to pr_info and log
host->clock/max_clk/clock plus the computed divider/actual clock
in sdhci_calc_clk() and sdhci_set_clock().
- clk-sdmmc-mux / clk-divider / clk-utils: log div, mul, parent_rate,
rounded rate and recalc_rate results in round_rate/recalc_rate/
set_rate/div_frac_get so the full rate decision path is traceable.
- mmc core: log the requested speed in mmc_set_clock() and the
tuning entry/host-exec points in mmc_execute_tuning().
Change-Id: I4d569a01da8355db3319e82de942f1401dfac911
49 lines
996 B
C
49 lines
996 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
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*/
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#include <asm/div64.h>
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#include "clk.h"
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#define DRIVER_NAME "sdhci"
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#define div_mask(w) ((1 << (w)) - 1)
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int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,
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u8 frac_width, u8 flags)
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{
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s64 divider_ux1 = parent_rate;
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int mul;
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if (!rate)
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return div_mask(width);
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mul = 1 << frac_width;
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if (!(flags & TEGRA_DIVIDER_INT))
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divider_ux1 *= mul;
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if (flags & TEGRA_DIVIDER_ROUND_UP)
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divider_ux1 += rate - 1;
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do_div(divider_ux1, rate);
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if (flags & TEGRA_DIVIDER_INT)
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divider_ux1 *= mul;
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divider_ux1 -= mul;
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if (divider_ux1 > div_mask(width))
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return div_mask(width);
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if (div1_5_not_allowed && (divider_ux1 > 0) && (divider_ux1 < mul))
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divider_ux1 = (flags & TEGRA_DIVIDER_ROUND_UP) ? mul : 0;
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pr_info("(" DRIVER_NAME ") div_frac_get: rate=%lu parent_rate=%u div=%lld mul=%d\n",
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rate, parent_rate, divider_ux1, mul);
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return divider_ux1;
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}
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