Ivan Mikhaylov
50f01c57d7
TVSENSE(temperature and voltage sensors) reset is blocked (clock gated) by the POR default of the TVS sleep config bit. As a consequence, TVSENSE will provide erratic sensor values, which may result in spurious (parity) errors recorded in the CMU FIR and leading to erroneous interrupt requests once the CMU interrupt is unmasked. Purpose of this to set up CMU in working state in any cases even in case of parity errors. Reviewed-by: Alistair Popple <alistair@popple.id.au> Signed-off-by: Ivan Mikhaylov <ivan@de.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
117 lines
3.1 KiB
C
117 lines
3.1 KiB
C
/*
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* FSP-2 board specific routines
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*
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* Based on earlier code:
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* Matt Porter <mporter@kernel.crashing.org>
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* Copyright 2002-2005 MontaVista Software Inc.
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*
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* Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
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* Copyright (c) 2003-2005 Zultys Technologies
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*
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* Rewritten and ported to the merged powerpc tree:
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* Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/of_platform.h>
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#include <linux/rtc.h>
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#include <asm/machdep.h>
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#include <asm/prom.h>
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#include <asm/udbg.h>
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#include <asm/time.h>
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#include <asm/uic.h>
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#include <asm/ppc4xx.h>
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#include <asm/dcr.h>
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#include "fsp2.h"
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static __initdata struct of_device_id fsp2_of_bus[] = {
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{ .compatible = "ibm,plb4", },
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{ .compatible = "ibm,plb6", },
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{ .compatible = "ibm,opb", },
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{},
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};
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static int __init fsp2_device_probe(void)
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{
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of_platform_bus_probe(NULL, fsp2_of_bus, NULL);
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return 0;
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}
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machine_device_initcall(fsp2, fsp2_device_probe);
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static int __init fsp2_probe(void)
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{
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u32 val;
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unsigned long root = of_get_flat_dt_root();
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if (!of_flat_dt_is_compatible(root, "ibm,fsp2"))
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return 0;
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/* Clear BC_ERR and mask snoopable request plb errors. */
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val = mfdcr(DCRN_PLB6_CR0);
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val |= 0x20000000;
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mtdcr(DCRN_PLB6_BASE, val);
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mtdcr(DCRN_PLB6_HD, 0xffff0000);
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mtdcr(DCRN_PLB6_SHD, 0xffff0000);
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/* TVSENSE reset is blocked (clock gated) by the POR default of the TVS
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* sleep config bit. As a consequence, TVSENSE will provide erratic
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* sensor values, which may result in spurious (parity) errors
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* recorded in the CMU FIR and leading to erroneous interrupt requests
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* once the CMU interrupt is unmasked.
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*/
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/* 1. set TVS1[UNDOZE] */
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val = mfcmu(CMUN_TVS1);
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val |= 0x4;
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mtcmu(CMUN_TVS1, val);
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/* 2. clear FIR[TVS] and FIR[TVSPAR] */
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val = mfcmu(CMUN_FIR0);
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val |= 0x30000000;
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mtcmu(CMUN_FIR0, val);
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/* L2 machine checks */
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mtl2(L2PLBMCKEN0, 0xffffffff);
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mtl2(L2PLBMCKEN1, 0x0000ffff);
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mtl2(L2ARRMCKEN0, 0xffffffff);
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mtl2(L2ARRMCKEN1, 0xffffffff);
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mtl2(L2ARRMCKEN2, 0xfffff000);
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mtl2(L2CPUMCKEN, 0xffffffff);
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mtl2(L2RACMCKEN0, 0xffffffff);
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mtl2(L2WACMCKEN0, 0xffffffff);
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mtl2(L2WACMCKEN1, 0xffffffff);
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mtl2(L2WACMCKEN2, 0xffffffff);
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mtl2(L2WDFMCKEN, 0xffffffff);
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/* L2 interrupts */
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mtl2(L2PLBINTEN1, 0xffff0000);
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/*
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* At a global level, enable all L2 machine checks and interrupts
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* reported by the L2 subsystems, except for the external machine check
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* input (UIC0.1).
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*/
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mtl2(L2MCKEN, 0x000007ff);
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mtl2(L2INTEN, 0x000004ff);
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/* Enable FSP-2 configuration logic parity errors */
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mtdcr(DCRN_CONF_EIR_RS, 0x80000000);
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return 1;
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}
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define_machine(fsp2) {
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.name = "FSP-2",
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.probe = fsp2_probe,
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.progress = udbg_progress,
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.init_IRQ = uic_init_tree,
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.get_irq = uic_get_irq,
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.restart = ppc4xx_reset_system,
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.calibrate_decr = generic_calibrate_decr,
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};
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