Taniya Das
06498d59bb
Add device tree bindings for the global clock controller on Qualcomm Nord platform. The global clock controller on Nord SoC is divided into multiple clock controllers (GCC,SE_GCC,NE_GCC and NW_GCC). Add each of the bindings to define the clock controllers. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260403-nord-clks-v1-3-018af14979fd@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
99 lines
3.5 KiB
C
99 lines
3.5 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H
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#define _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H
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/* SE_GCC clocks */
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#define SE_GCC_EEE_EMAC0_CLK 0
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#define SE_GCC_EEE_EMAC0_CLK_SRC 1
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#define SE_GCC_EEE_EMAC1_CLK 2
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#define SE_GCC_EEE_EMAC1_CLK_SRC 3
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#define SE_GCC_EMAC0_AXI_CLK 4
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#define SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK 5
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#define SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK 6
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#define SE_GCC_EMAC0_PHY_AUX_CLK 7
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#define SE_GCC_EMAC0_PHY_AUX_CLK_SRC 8
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#define SE_GCC_EMAC0_PTP_CLK 9
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#define SE_GCC_EMAC0_PTP_CLK_SRC 10
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#define SE_GCC_EMAC0_RGMII_CLK 11
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#define SE_GCC_EMAC0_RGMII_CLK_SRC 12
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#define SE_GCC_EMAC0_RPCS_RX_CLK 13
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#define SE_GCC_EMAC0_RPCS_TX_CLK 14
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#define SE_GCC_EMAC0_XGXS_RX_CLK 15
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#define SE_GCC_EMAC0_XGXS_TX_CLK 16
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#define SE_GCC_EMAC1_AXI_CLK 17
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#define SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK 18
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#define SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK 19
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#define SE_GCC_EMAC1_PHY_AUX_CLK 20
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#define SE_GCC_EMAC1_PHY_AUX_CLK_SRC 21
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#define SE_GCC_EMAC1_PTP_CLK 22
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#define SE_GCC_EMAC1_PTP_CLK_SRC 23
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#define SE_GCC_EMAC1_RGMII_CLK 24
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#define SE_GCC_EMAC1_RGMII_CLK_SRC 25
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#define SE_GCC_EMAC1_RPCS_RX_CLK 26
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#define SE_GCC_EMAC1_RPCS_TX_CLK 27
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#define SE_GCC_EMAC1_XGXS_RX_CLK 28
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#define SE_GCC_EMAC1_XGXS_TX_CLK 29
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#define SE_GCC_FRQ_MEASURE_REF_CLK 30
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#define SE_GCC_GP1_CLK 31
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#define SE_GCC_GP1_CLK_SRC 32
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#define SE_GCC_GP2_CLK 33
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#define SE_GCC_GP2_CLK_SRC 34
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#define SE_GCC_GPLL0 35
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#define SE_GCC_GPLL0_OUT_EVEN 36
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#define SE_GCC_GPLL2 37
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#define SE_GCC_GPLL4 38
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#define SE_GCC_GPLL5 39
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#define SE_GCC_MMU_2_TCU_VOTE_CLK 40
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#define SE_GCC_QUPV3_WRAP0_CORE_2X_CLK 41
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#define SE_GCC_QUPV3_WRAP0_CORE_CLK 42
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#define SE_GCC_QUPV3_WRAP0_M_AHB_CLK 43
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#define SE_GCC_QUPV3_WRAP0_S0_CLK 44
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#define SE_GCC_QUPV3_WRAP0_S0_CLK_SRC 45
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#define SE_GCC_QUPV3_WRAP0_S1_CLK 46
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#define SE_GCC_QUPV3_WRAP0_S1_CLK_SRC 47
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#define SE_GCC_QUPV3_WRAP0_S2_CLK 48
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#define SE_GCC_QUPV3_WRAP0_S2_CLK_SRC 49
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#define SE_GCC_QUPV3_WRAP0_S3_CLK 50
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#define SE_GCC_QUPV3_WRAP0_S3_CLK_SRC 51
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#define SE_GCC_QUPV3_WRAP0_S4_CLK 52
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#define SE_GCC_QUPV3_WRAP0_S4_CLK_SRC 53
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#define SE_GCC_QUPV3_WRAP0_S5_CLK 54
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#define SE_GCC_QUPV3_WRAP0_S5_CLK_SRC 55
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#define SE_GCC_QUPV3_WRAP0_S6_CLK 56
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#define SE_GCC_QUPV3_WRAP0_S6_CLK_SRC 57
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#define SE_GCC_QUPV3_WRAP0_S_AHB_CLK 58
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#define SE_GCC_QUPV3_WRAP1_CORE_2X_CLK 59
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#define SE_GCC_QUPV3_WRAP1_CORE_CLK 60
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#define SE_GCC_QUPV3_WRAP1_M_AHB_CLK 61
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#define SE_GCC_QUPV3_WRAP1_S0_CLK 62
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#define SE_GCC_QUPV3_WRAP1_S0_CLK_SRC 63
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#define SE_GCC_QUPV3_WRAP1_S1_CLK 64
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#define SE_GCC_QUPV3_WRAP1_S1_CLK_SRC 65
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#define SE_GCC_QUPV3_WRAP1_S2_CLK 66
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#define SE_GCC_QUPV3_WRAP1_S2_CLK_SRC 67
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#define SE_GCC_QUPV3_WRAP1_S3_CLK 68
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#define SE_GCC_QUPV3_WRAP1_S3_CLK_SRC 69
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#define SE_GCC_QUPV3_WRAP1_S4_CLK 70
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#define SE_GCC_QUPV3_WRAP1_S4_CLK_SRC 71
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#define SE_GCC_QUPV3_WRAP1_S5_CLK 72
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#define SE_GCC_QUPV3_WRAP1_S5_CLK_SRC 73
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#define SE_GCC_QUPV3_WRAP1_S6_CLK 74
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#define SE_GCC_QUPV3_WRAP1_S6_CLK_SRC 75
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#define SE_GCC_QUPV3_WRAP1_S_AHB_CLK 76
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/* SE_GCC power domains */
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#define SE_GCC_EMAC0_GDSC 0
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#define SE_GCC_EMAC1_GDSC 1
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/* SE_GCC resets */
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#define SE_GCC_EMAC0_BCR 0
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#define SE_GCC_EMAC1_BCR 1
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#define SE_GCC_QUPV3_WRAPPER_0_BCR 2
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#define SE_GCC_QUPV3_WRAPPER_1_BCR 3
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#endif
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