Files
SylveonDeko 53d6115483 phy: tegra: xusb: add the Tegra210B01 USB3 lane tuning
- Write the Tegra210B01 per-lane UPHY settings into UPHY_MISC_PAD_PX_CTL8
  for every lane used as USB3
- Skip the Tegra210 PLL calibration and DCO values on B01, which has its
  own PLL table and was having it overwritten
- USB3 device mode now links at SuperSpeed on Mariko units instead of
  falling back to USB2
2026-10-16 18:03:38 -05:00
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