xusb: bulk commit to split

Tegra210b01 uses tegra186-emc driver as emc clock is controlled by BPMP.
However, this driver expects emc as subnode of mc. Adjust Tegra30 mc
probe routine to populate subnodes.

arch/arm64/boot/dts/nvidia/tegra210-nx.dtsi

@@ -51,12 +51,37 @@
 		vdd-supply = <&gpu_max_reg>;
 	};
 
+	pcie@1003000 {
+		status = "okay";
+
+		avdd-pll-uerefe-supply = <&max77620_ldo1>;
+		hvddio-pex-supply = <&max77620_sd3>;
+		dvddio-pex-supply = <&max77620_ldo1>;
+		dvdd-pex-pll-supply = <&max77620_ldo1>;
+		hvdd-pex-pll-e-supply = <&max77620_sd3>;
+		vddio-pex-ctl-supply = <&max77620_sd3>;
+
+		pci@1,0 {
+			phys =	<&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>, /* Referred to plat config */
+				<&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
+			phy-names = "pcie-0", "pcie-1";
+			nvidia,num-lanes = <2>;
+			status = "disabled";
+		};
+
+		pci@2,0 {
+			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
+			phy-names = "pcie-0";
+			status = "okay";
+		};
+	};
+
 	host1x@50000000 {
 		dsia: dsi@54300000 {
 			status = "okay";
 
 			panel@0 {
-				compatible = "jdi,lpm062m326a";
+				compatible = "nintendo,panel-nx-dsi";
 				reset-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 				backlight = <&backlight>;
 				vdd1-supply = <&v_pavdd_5v0>;

arch/arm64/boot/dts/nvidia/tegra210b01-nx.dtsi

@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 #include <dt-bindings/mfd/max77620.h>
+#include <dt-bindings/thermal/tegra210b01-trips.h>
+#include <dt-bindings/thermal/thermal.h>
 
 #include "tegra210b01.dtsi"
 
@@ -17,12 +19,725 @@
 		reg = <0x0 0x80000000 0x0 0xc0000000>;
 	};
 
+	pwm@7000a000 {
+		status = "okay";
+		#pwm-cells = <2>;
+	};
+
 	serial@70006000 {
 		/delete-property/ dmas;
 		/delete-property/ dma-names;
 		status = "okay";
 	};
 
+	/* SDMMC4 for EMMC */
+	mmc@700b0600 {
+		status = "disabled";
+		bus-width = <8>;
+		max-frequency = <200000000>;
+
+		cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_HIGH>;
+
+		cap-mmc-highspeed;
+		mmc-ddr-1_8v;
+		mmc-hs200-1_8v;
+		mmc-hs400-1_8v;
+		non-removable;
+
+		vqmmc-supply = <&max77620_sd3>;
+		vmmc-supply = <&vdd_3v3>;
+	};
+
+	/* SDMMC3 Not Used */
+	mmc@700b0400 {
+		status = "disabled";
+	};
+
+	/* SDMMC2 for Gamecard */
+	mmc@700b0200 {
+		status = "disabled";
+		bus-width = <8>;
+		max-frequency = <200000000>;
+
+		mmc-ddr-1_8v;
+		mmc-hs400-1_8v;
+		mmc-hs200-1_8v;
+		cap-mmc-highspeed;
+		cap-sd-highspeed;
+		non-removable;
+
+		vqmmc-supply = <&max77620_sd3>;
+		vmmc-supply = <&vdd_3v3>;
+	};
+
+	/* SDMMC1 for SD Card */
+	mmc@700b0000 {
+		status = "okay";
+		bus-width = <4>;
+		max-frequency = <200000000>;
+
+		cap-sd-highspeed;
+		sd-uhs-sdr12;
+		sd-uhs-sdr50;
+		sd-uhs-sdr104;
+
+		vmmc-supply = <&en_vdd_sd>;
+		vqmmc-supply = <&max77620_ldo2>;
+	};
+
+	i2c@7000c000 {
+		status = "okay";
+		clock-frequency = <100000>;
+
+		bq24193@6b {
+			compatible = "ti,bq24193";
+			reg = <0x6b>;
+
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(Z, 0) IRQ_TYPE_LEVEL_LOW>;
+
+			monitored-battery = <&fuel_gauge>;
+			#extcon-cells = <1>;
+
+			omit-battery-class;
+
+			battery_charger: charger {
+				regulator-name = "batt_regulator";
+				regulator-max-microamp = <4500000>;
+			};
+
+			usb0_vbus: usb-otg-vbus {
+				regulator-name = "vbus_regulator";
+			};
+		};
+
+		fuel_gauge: fuel-gauge@36 {
+			compatible = "maxim,max17050";
+			status = "okay";
+			reg = <0x36>;
+
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(Y, 0) IRQ_TYPE_NONE>;
+
+			/* Actual is 5000 but driver does not account for CGAIN */
+			/* And does not take into account Rsense and CGAIN for capacity */
+			maxim,rsns-microohm = <10000>;
+			maxim,over-heat-temp = <600>;
+			maxim,dead-volt = <3000>;
+			maxim,over-volt = <4208>; /* Actual: 4258 mV */
+
+			#thermal-sensor-cells = <0>;
+		};
+
+		rt5639: audio-codec@1c {
+			status = "okay";
+			compatible = "realtek,rt5639";
+			reg = <0x1c>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(BB, 4) IRQ_TYPE_EDGE_RISING>;
+			realtek,ldo1-en-gpios = <&gpio TEGRA_GPIO(Z, 4) GPIO_ACTIVE_HIGH>;
+			realtek,over-current-threshold-microamp = <600>;
+			realtek,over-current-scale-factor = <2>;
+			realtek,jack-detect-is-jd1;
+		};
+
+		/* PD Chip */
+		bm92t: bm92t@18 {
+			compatible = "rohm,bm92t";
+			reg = <0x18>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(K, 4) IRQ_TYPE_EDGE_RISING>;
+			#extcon-cells = <1>;
+			pd_bat_chg-supply = <&battery_charger>;
+			vbus-source-supply = <&v_vdd5v3>;
+			vbus-supply = <&usb0_vbus>;
+			rohm,vconn-en-gpio = <&gpio TEGRA_GPIO(K, 5) GPIO_ACTIVE_HIGH>;
+
+			rohm,dp-lanes = <2>;
+			rohm,dp-signal-toggle-on-resume;
+
+			/* Absolute max is 2.4A, constrained by BQ24193 ILIM */
+			rohm,pd-5v-current-limit-ma = <2000>;
+			rohm,pd-9v-current-limit-ma = <2000>;
+			rohm,pd-12v-current-limit-ma = <1500>;
+			rohm,pd-15v-current-limit-ma = <1200>;
+
+			port {
+				usb_con_ep: endpoint {
+					remote-endpoint = <&usb_port_0>;
+				};
+			};
+		};
+
+		tmp451: temperature-sensor@4c {
+			compatible = "ti,tmp451";
+			status = "okay";
+			reg = <0x4c>;
+
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(X, 4) IRQ_TYPE_EDGE_FALLING>;
+			vcc-supply = <&battery_reg>;
+
+			#thermal-sensor-cells = <1>;
+		};
+    	};
+
+	/* i2c3 @ 400000hz
+	49: stm touchscreen controller
+	*/
+	i2c@7000c500 {
+		status = "okay";
+		clock-frequency = <400000>;
+
+		touchscreen@49 {
+			compatible = "stm,ftm4_fts";
+			status = "okay";
+			reg = <0x49>;
+			interrupt-parent = <&gpio>;
+			interrupts = <TEGRA_GPIO(X, 1) IRQ_TYPE_LEVEL_LOW>;
+			vdd-tp-2v9-supply = <&max77620_ldo6>;
+			stm,vio-gpio = <&gpio TEGRA_GPIO(J, 7) GPIO_ACTIVE_HIGH>;
+			stm,irq_type = <0x2000>; /* IRQF_ONESHOT */
+			stm,regulator_avdd = "vdd-tp-2v9";
+			stm,max_coords = <1280 720>;
+			stm,max-real-coords = <1264 704>;
+			stm,edge-offset = <15 15>;
+			stm,delayed-open;
+			stm,delayed-open-time = <0>;
+		};
+	};
+
+	gpu@57000000 {
+		status = "okay";
+		vdd-supply = <&gpu_max_reg>;
+	};
+
+	backlight: backlight {
+		status = "okay";
+		compatible = "pwm-backlight";
+		pwms = <&pwm 0 33898>;
+		pwm-names = "backlight";
+		brightness-levels = <
+			0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
+			17 18 19 20 21 22 23 24 25 26 27 28 29 30
+			31 32 33 34 35 36 37 38 39 40 41 42 43 44
+			45 46 47 48 49 50 51 52 53 54 55 56 57 58
+			59 60 61 62 63 64 65 66 67 68 69 70 71 72
+			73 74 75 76 77 78 79 80 81 82 83 84 85 86
+			87 88 89 90 91 92 93 94 95 96 97 98 99 100
+		>;
+		default-brightness-level = <50>;
+		enable-gpios = <&gpio TEGRA_GPIO(V, 1) GPIO_ACTIVE_HIGH>;
+		power-supply = <&max77620_sd3>;
+	};
+
+	/* Fixed regulators */
+	battery_reg: vdd-ac-bat {
+		compatible = "regulator-fixed";
+		status = "okay";
+		regulator-name = "vdd-ac-bat";
+		regulator-min-microvolt = <4800000>;
+		regulator-max-microvolt = <4800000>;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	vdd_3v3: vdd-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "vdd-3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-always-on;
+		gpio = <&pmic_b 3 0>;
+		enable-active-high;
+		regulator-enable-ramp-delay = <160>;
+		regulator-disable-ramp-delay = <10000>;
+	};
+
+	v_vdd5v3: v-vdd5v3 {
+		compatible = "regulator-fixed";
+		status = "okay"; /* Only enabled on Modin/Vali/Fric */
+		regulator-name = "v_vdd5v3";
+		regulator-min-microvolt = <5300000>;
+		regulator-max-microvolt = <5300000>;
+		gpio = <&gpio TEGRA_GPIO(X, 3) 0>;
+		enable-active-high;
+		regulator-enable-ramp-delay = <10000>;
+	};
+
+	max77620_gpio7: avdd-dsi-csi-1v2 {
+		compatible = "regulator-fixed";
+		regulator-name = "max77620-gpio7";
+		regulator-min-microvolt = <1200000>;
+		regulator-max-microvolt = <1200000>;
+		regulator-boot-on; /* Must be set for seamless display */
+		gpio = <&pmic_b 7 0>;
+		enable-active-high;
+		regulator-enable-ramp-delay = <240>;
+		regulator-disable-ramp-delay = <11340>;
+		vin-supply = <&max77620_ldo0>;
+	};
+
+	// lcd_bl_en: lcd-bl-en {
+	// 	compatible = "regulator-fixed";
+	// 	regulator-name = "lcd-bl-en";
+	// 	regulator-min-microvolt = <1800000>;
+	// 	regulator-max-microvolt = <1800000>;
+	// 	gpio = <&gpio TEGRA_GPIO(V, 1) 0>;
+	// 	regulator-boot-on; /* Must be set for seamless display */
+	// 	enable-active-high;
+	// 	regulator-always-on;
+	// 	regulator-state-mem {
+	// 		regulator-off-in-suspend;
+	// 	};
+	// };
+
+	en_vdd_sd: en-vdd-sd {
+		compatible = "regulator-fixed";
+		regulator-name = "en-vdd-sd";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio TEGRA_GPIO(E, 4) 0>;
+		enable-active-high;
+		regulator-enable-ramp-delay = <472>;
+		regulator-disable-ramp-delay = <4880>;
+		vin-supply = <&vdd_3v3>;
+	};
+
+	/* LCD Power Enable +5V. Rohm BD8316GWL. */
+	v_pavdd_5v0: v-pavdd-5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "v_pavdd_5v0";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&gpio TEGRA_GPIO(I, 0) 0>;
+		enable-active-high;
+		regulator-boot-on; /* Must be set for seamless display */
+		regulator-enable-ramp-delay = <232>;
+	};
+
+	/* LCD Power Enable -5V. Rohm BD8316GWL. */
+	v_navdd_5v0: v-navdd-5v0 {
+		compatible = "regulator-fixed";
+		regulator-name = "v_navdd_5v0";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		gpio = <&gpio TEGRA_GPIO(I, 1) 0>;
+		enable-active-high;
+		regulator-boot-on; /* Must be set for seamless display */
+		regulator-enable-ramp-delay = <232>;
+	};
+
+	soctherm@700E2000 {
+		throttle-cfgs {
+			/* PG/ACOK/USB OC pin. CLK_32K_OUT. Used for LED PWM on Vali. */
+			/*
+			throttle_oc1: oc1 { // Sticky mode but not supported.
+				nvidia,priority = <16>;
+				nvidia,polarity-active-low = <1>;
+				nvidia,count-threshold = <0>;
+				nvidia,throttle-period = <2500000>;
+				nvidia,alarm-filter = <0xFFFFFFFF>;
+				nvidia,cpu-throt-percent = <75>;
+				nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
+			};
+			*/
+
+			/* Battery OC pin. GPIO_PL1. Traced but missing resistor. */
+			/*
+			throttle_oc2: oc2 {
+				nvidia,priority = <24>;
+				nvidia,polarity-active-low = <1>;
+				nvidia,count-threshold = <0>;
+				nvidia,throttle-period = <100>;
+				nvidia,alarm-filter = <0xFFFFFFFF>;
+				nvidia,cpu-throt-percent = <75>;
+				nvidia,gpu-throt-level = <TEGRA_SOCTHERM_THROT_LEVEL_MED>;
+			};
+			*/
+
+			/* throttle_oc3: oc3: GPIO_PZ5. Floating. */
+		};
+	};
+
+	thermal-zones {
+		PLL-therm {
+			status = "okay";
+			polling-delay-passive = <500>;
+			thermal-zone-params {
+				governor-name = "step_wise";
+			};
+			trips {
+				cpu_heavy {
+					temperature = <94500>;
+					hysteresis = <0>;
+					type = "hot";
+					writable;
+				};
+				cpu_throttle {
+					temperature = <90500>;
+					hysteresis = <0>;
+					type = "passive";
+					writable;
+				};
+				cpu_critical {
+					temperature = <96000>;
+					hysteresis = <0>;
+					type = "critical";
+					writable;
+				};
+				dfll_cap_trip0: dfll-cap-trip0 {
+					temperature = <TEGRA210B01_DFLL_THERMAL_CAP_0>;
+					hysteresis = <1000>; /* millicelsius */
+					type = "active";
+				};
+				dfll_cap_trip1: dfll-cap-trip1 {
+					temperature = <TEGRA210B01_DFLL_THERMAL_CAP_1>;
+					hysteresis = <1000>; /* millicelsius */
+					type = "active";
+				};
+			};
+			// cooling-maps {
+			// 	map0 {
+			// 		trip = <&{/thermal-zones/PLL-therm/trips/cpu_heavy}>;
+			// 		cdev-type = "tegra-heavy";
+			// 		cooling-device = <&throttle_heavy 1 1>;
+			// 	};
+			// 	map1 {
+			// 		trip = <&{/thermal-zones/PLL-therm/trips/cpu_throttle}>;
+			// 		cdev-type = "cpu-balanced";
+			// 		cooling-device = <&{/bthrot_cdev/cpu_balanced}
+			// 			THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			// 	};
+			// 	dfll-cap-map0 {
+			// 		trip = <&dfll_cap_trip0>;
+			// 		cooling-device = <&dfll_cap 1 1>;
+			// 	};
+			// 	dfll-cap-map1 {
+			// 		trip = <&dfll_cap_trip1>;
+			// 		cooling-device = <&dfll_cap 2 2>;
+			// 	};
+			// };
+		};
+		Tboard_tegra {
+			status = "okay";
+			polling-delay = <0>;
+			polling-delay-passive = <5500>;
+
+			trips {
+				board_emergency {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+					writable;
+				};
+			};
+			// cooling-maps {
+			// 	map0 {
+			// 		trip = <&{/thermal-zones/Tboard_tegra/trips/board_emergency}>;
+			// 		cdev-type = "emergency-balanced";
+			// 		cooling-device = <&{/bthrot_cdev/emergency_balanced}
+			// 			THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+			// 	};
+			// };
+		};
+		Tdiode_tegra {
+			status = "okay";
+			polling-delay = <0>;
+			polling-delay-passive = <1100>;
+
+			trips {
+				gpu_shutdown {
+					temperature = <92500>;
+					hysteresis = <0>;
+					type = "critical";
+					writable;
+				};
+
+				gpu_throttle {
+					temperature = <86000>;
+					hysteresis = <0>;
+					type = "passive";
+					writable;
+				};
+				gpu_scaling_trip0: gpu-scaling-trip0 {
+					temperature = <(TEGRA210B01_GPU_DVFS_THERMAL_MIN)>;
+					hysteresis = <0>; /* millicelsius */
+					type = "active";
+				};
+				gpu_scaling_trip1: gpu-scaling-trip1 {
+					temperature = <TEGRA210B01_GPU_DVFS_THERMAL_TRIP_1>;
+					hysteresis = <1000>; /* millicelsius */
+					type = "active";
+				};
+				gpu_scaling_trip2: gpu-scaling-trip2 {
+					temperature = <TEGRA210B01_GPU_DVFS_THERMAL_TRIP_2>;
+					hysteresis = <1000>; /* millicelsius */
+					type = "active";
+				};
+				gpu_scaling_trip3: gpu-scaling-trip3 {
+					temperature = <TEGRA210B01_GPU_DVFS_THERMAL_TRIP_3>;
+					hysteresis = <1000>; /* millicelsius */
+					type = "active";
+				};
+				gpu_scaling_trip4: gpu-scaling-trip4 {
+					temperature = <TEGRA210B01_GPU_DVFS_THERMAL_TRIP_4>;
+					hysteresis = <1000>; /* millicelsius */
+					type = "active";
+				};
+				gpu_scaling_trip5: gpu-scaling-trip5 {
+					temperature = <TEGRA210B01_GPU_DVFS_THERMAL_TRIP_5>;
+					hysteresis = <1000>; /* millicelsius */
+					type = "active";
+				};
+
+				gpu_vmax_trip1: gpu-vmax-trip1 {
+					temperature = <TEGRA210B01_GPU_DVFS_THERMAL_CAP_1>;
+					hysteresis = <1000>; /* millicelsius */
+					type = "active";
+				};
+				core_dvfs_floor_trip0: core_dvfs_floor_trip0 {
+					temperature = <TEGRA210B01_SOC_THERMAL_FLOOR_0>;
+					hysteresis = <1000>;
+					type = "active";
+				};
+
+				core_dvfs_cap_trip0: core_dvfs_cap_trip0 {
+					temperature = <TEGRA210B01_SOC_THERMAL_CAP_0>;
+					hysteresis = <1000>;
+					type = "active";
+				};
+				soc_critical {
+					temperature = <96000>;
+					hysteresis = <0>;
+					type = "critical";
+					writable;
+				};
+				soc_emergency {
+					temperature = <85000>;
+					hysteresis = <2000>;
+					type = "passive";
+					writable;
+				};
+				dfll_floor_trip0: dfll-floor-trip0 {
+					temperature = <TEGRA210B01_DFLL_THERMAL_FLOOR_0>;
+					hysteresis = <1000>; /* millicelsius */
+					type = "active";
+				};
+			};
+			cooling-maps {
+				// map0 {
+				// 	trip = <&{/thermal-zones/Tdiode_tegra/trips/soc_critical}>;
+				// 	cdev-type = "tegra-shutdown";
+				// 	cooling-device = <&{/soctherm@0x700E2000/throttle@critical}
+				// 		THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				// };
+				// map1 {
+				// 	trip = <&{/thermal-zones/Tdiode_tegra/trips/soc_emergency}>;
+				// 	cdev-type = "emergency-balanced";
+				// 	cooling-device = <&{/bthrot_cdev/emergency_balanced}
+				// 		THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				// };
+				// gpu-scaling-map1 {
+				// 	trip = <&gpu_scaling_trip1>;
+				// 	cooling-device = <&gpu_scaling_cdev 1 1>;
+				// };
+				// gpu-scaling-map2 {
+				// 	trip = <&gpu_scaling_trip2>;
+				// 	cooling-device = <&gpu_scaling_cdev 2 2>;
+				// };
+				// gpu_scaling_map3 {
+				// 	trip = <&gpu_scaling_trip3>;
+				// 	cooling-device = <&gpu_scaling_cdev 3 3>;
+				// };
+				// gpu-scaling-map4 {
+				// 	trip = <&gpu_scaling_trip4>;
+				// 	cooling-device = <&gpu_scaling_cdev 4 4>;
+				// };
+				// gpu-scaling-map5 {
+				// 	trip = <&gpu_scaling_trip5>;
+				// 	cooling-device = <&gpu_scaling_cdev 5 5>;
+				// };
+
+				// gpu-vmax-map1 {
+				// 	trip = <&gpu_vmax_trip1>;
+				// 	cooling-device = <&gpu_vmax_cdev 1 1>;
+				// };
+
+				core_dvfs_floor_map0 {
+					trip = <&core_dvfs_floor_trip0>;
+					cooling-device = <&core_dvfs_floor 1 1>;
+				};
+				core_dvfs_cap_map0 {
+					trip = <&core_dvfs_cap_trip0>;
+					cooling-device = <&core_dvfs_cap 1 1>;
+				};
+
+				dfll-floor-map0 {
+					trip = <&dfll_floor_trip0>;
+					cooling-device = <&dfll_floor 1 1>;
+				};
+				// map2 {
+				// 	trip = <&{/thermal-zones/Tdiode_tegra/trips/gpu_throttle}>;
+				// 	cdev-type = "gpu-balanced";
+				// 	cooling-device = <&{/bthrot_cdev/gpu_balanced}
+				// 		THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+				// };
+			};
+		};
+		AO-therm {
+			status = "okay";
+		};
+	};
+
+	pcie@1003000 {
+		status = "okay";
+
+		avdd-pll-uerefe-supply = <&max77620_ldo1>;
+		hvddio-pex-supply = <&max77620_sd3>;
+		dvddio-pex-supply = <&max77620_ldo1>;
+		dvdd-pex-pll-supply = <&max77620_ldo1>;
+		hvdd-pex-pll-e-supply = <&max77620_sd3>;
+		vddio-pex-ctl-supply = <&max77620_sd3>;
+
+		pci@1,0 {
+			nvidia,num-lanes = <2>;
+			phys =	<&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>, /* Referred to plat config */
+				<&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
+			phy-names = "pcie-0", "pcie-1";
+			status = "disabled";
+		};
+
+		pci@2,0 {
+			status = "okay";
+			phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
+			phy-names = "pcie-0";
+
+			brcmf { /* PCIE-0 (Port 1) */
+				compatible = "brcm,bcm4356-fmac";
+			};
+		};
+	};
+
+	padctl@7009f000 {
+		status =  "okay";
+
+		pads {
+			usb2 {
+				status = "okay";
+
+				lanes {
+					usb2-0 {
+						nvidia,hs_curr_level_offset = <6>;
+						nvidia,function = "xusb";
+						status = "okay";
+					};
+				};
+			};
+
+			pcie {
+				status = "okay";
+
+				lanes {
+					/* BCM4356A3-WiFi */
+					pcie-0 {
+						nvidia,function = "pcie-x1";
+						status = "okay";
+					};
+
+					/* Unused ports */
+					pcie-1 {
+						nvidia,function = "usb3-ss";
+						status = "okay";
+					};
+
+					pcie-2 {
+						nvidia,function = "pcie-x4";
+						status = "okay";
+					};
+
+					pcie-3 {
+						nvidia,function = "pcie-x4";
+						status = "okay";
+					};
+
+					pcie-4 {
+						nvidia,function = "usb3-ss";
+						status = "okay";
+					};
+
+					/* USB3 port */
+					pcie-5 {
+						nvidia,function = "usb3-ss";
+						status = "okay";
+					};
+				};
+			};
+		};
+
+		ports {
+			usb2-0 {
+				status = "okay";
+				mode = "otg";
+
+				usb-role-switch;
+				vbus-supply = <&battery_reg>;
+
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				usb_port_0: endpoint@0 {
+					reg = <0>;
+					remote-endpoint = <&usb_con_ep>;
+				};
+			};
+
+			usb3-0 {
+				status = "okay";
+				nvidia,usb2-companion = <0>;
+			};
+		};
+	};
+
+	pinmux@700008d4 {
+		dsi_ab_pad_default: dsi_ab_pad_default {
+			dsi_ab_pad_enable {
+				nvidia,pins = "pad_dsi_ab";
+				nvidia,pad-power = <TEGRA_PIN_ENABLE>;
+			};
+		};
+		dsi_cd_pad_default: dsi_cd_pad_default {
+			dsi_cd_pad_enable {
+				nvidia,pins = "pad_dsi_cd";
+				nvidia,pad-power = <TEGRA_PIN_ENABLE>;
+			};
+		};
+		dsi_ab_pad_idle: dsi_ab_pad_idle {
+			dsi_ab_pad_disable {
+				nvidia,pins = "pad_dsi_ab";
+				nvidia,pad-power = <TEGRA_PIN_DISABLE>;
+			};
+		};
+		dsi_cd_pad_idle: dsi_cd_pad_idle {
+			dsi_cd_pad_disable {
+				nvidia,pins = "pad_dsi_cd";
+				nvidia,pad-power = <TEGRA_PIN_DISABLE>;
+			};
+		};
+
+		/* Always on for T210B01 NX */
+		sdmmc1_schmitt_disable {
+			sdmmc1 {
+				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+			};
+		};
+		sdmmc1_clk_schmitt_disable {
+			sdmmc1 {
+				nvidia,schmitt = <TEGRA_PIN_ENABLE>;
+			};
+		};
+	};
+
 	pmc@7000e400 {
 		nvidia,invert-interrupt;
 		nvidia,suspend-mode = <0>;
@@ -33,12 +748,48 @@
 		nvidia,core-power-req-active-high;
 		nvidia,sys-clock-req-active-high;
 		status = "okay";
-	};
 
-	mmc@700b0600 {
-		bus-width = <8>;
-		non-removable;
-		status = "okay";
+		// TODO
+		// bootrom-commands {
+		// 	reset-commands {
+		// 		nvidia,command-retries-count = <2>;
+		// 		nvidia,delay-between-commands-us = <10>;
+		// 		nvidia,wait-before-start-bus-clear-us = <10>;
+		// 		#address-cells = <1>;
+		// 		#size-cells = <0>;
+
+		// 		commands@4-0068 {
+		// 			nvidia,command-names = "r2p-setup";
+		// 			reg = <0x68>;
+		// 			nvidia,enable-8bit-register;
+		// 			nvidia,enable-8bit-data;
+		// 			nvidia,controller-type-i2c;
+		// 			nvidia,controller-id = <4>;
+		// 			nvidia,enable-controller-reset;
+		// 			nvidia,write-commands = <
+		// 					0x13 0x00 /* r2p enc 0 */
+		// 					0x1A 0x00 /* r2p enc 1 */
+		// 					0x11 0x00 /* r2p mgc 0 */
+		// 					0x18 0x00 /* r2p mgc 1 */
+		// 					0x04 0x01 /* Update RTC regs */
+		// 				>;
+		// 		};
+		// 		commands@4-003c {
+		// 			nvidia,command-names = "pmic-rails";
+		// 			reg = <0x3c>;
+		// 			nvidia,enable-8bit-register;
+		// 			nvidia,enable-8bit-data;
+		// 			nvidia,controller-type-i2c;
+		// 			nvidia,controller-id = <4>;
+		// 			nvidia,enable-controller-reset;
+		// 			nvidia,write-commands = <
+		// 					0x16 0x20 /* Set 1.0V and disable SD0 */
+		// 					0x42 0x99 /* Wake reasons: SFT_RST/ACOK/LID/EN0 */
+		// 					0x41 0x80 /* Reboot */
+		// 				>;
+		// 		};
+		// 	};
+		// };
 	};
 
 	clk32k_in: clock-32k {
@@ -47,6 +798,76 @@
 		#clock-cells = <0>;
 	};
 
+	host1x@50000000 {
+		vic@54340000 {
+			status = "disabled";
+		};
+		nvjpg@54380000 {
+			status = "disabled";
+		};
+		nvdec@54480000 {
+			status = "disabled";
+		};
+		nvenc@544c0000 {
+			status = "disabled";
+		};
+
+		dsia: dsi@54300000 {
+			status = "okay";
+
+			avdd-dsi-csi-supply = <&max77620_ldo0>;
+
+			panel@0 {
+				reg = <0>;
+				status = "okay";
+
+				compatible = "nintendo,panel-nx-dsi";
+				reset-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
+				backlight = <&backlight>;
+				vdd1-supply = <&v_pavdd_5v0>;
+				vdd2-supply = <&v_navdd_5v0>;
+			};
+		};
+
+		dc@54200000 {
+			status = "okay";
+
+			// pinctrl-names = "pad_ab_default", "pad_ab_idle",
+			// 	"pad_cd_default", "pad_cd_idle";
+			// pinctrl-0 = <&dsi_ab_pad_default>;
+			// pinctrl-1 = <&dsi_ab_pad_idle>;
+			// pinctrl-2 = <&dsi_cd_pad_default>;
+			// pinctrl-3 = <&dsi_cd_pad_idle>;
+
+			nvidia,outputs = <&dsia>;
+		};
+
+		/* tegradc.1: DP */
+		dc@54240000 {
+			status = "okay";
+
+			extcon-cables = <&bm92t 3>;
+			extcon-cable-names = "typec1";
+
+			//nvidia,outputs = <&sor1>;pa
+		};
+	};
+
+	tegra_clk_dfll: clock@70110000 {
+		status = "okay";
+		vdd-cpu-supply = <&cpu_max_reg>;
+		nvidia,align-step-uv = <5000>;
+		nvidia,sample-rate = <12500>;
+		nvidia,droop-ctrl = <0x00000f00>;
+		nvidia,force-mode = <1>;
+		nvidia,cf = <6>;
+		nvidia,ci = <0>;
+		nvidia,cg = <2>;
+		nvidia,i2c-fs-rate = <400000>;
+		nvidia,pmic-undershoot-gb = <0>; /* Use pmic default min */
+		/* nvidia,dfll-max-freq-khz = <1683000>; */
+	};
+
 	cpus {
 		cpu@0 {
 			enable-method = "psci";
@@ -429,4 +1250,43 @@
 			};
 		};
 	};
+
+	dfll_cap: dfll-cdev-cap {
+		compatible = "nvidia,tegra-dfll-cdev-action";
+		act-dev = <&tegra_clk_dfll>;
+		cdev-type = "DFLL-cap";
+		#cooling-cells = <2>; /* min followed by max */
+	};
+
+	dfll_floor: dfll-cdev-floor {
+		compatible = "nvidia,tegra-dfll-cdev-action";
+		act-dev = <&tegra_clk_dfll>;
+		cdev-type = "DFLL-floor";
+		#cooling-cells = <2>; /* min followed by max */
+	};
+
+	// gpu_scaling_cdev: gpu-scaling-cdev {
+	// 	cooling-min-state = <0>;
+	// 	cooling-max-state = <5>;
+	// 	#cooling-cells = <2>;
+	// 	compatible = "nvidia,tegra210-rail-scaling-cdev";
+	// 	cdev-type = "gpu_scaling";
+	// 	nvidia,constraint;
+	// 	nvidia,trips = <&gpu_scaling_trip0 800 &gpu_scaling_trip1 0
+	// 			&gpu_scaling_trip2 0 &gpu_scaling_trip3 0
+	// 			&gpu_scaling_trip4 0 &gpu_scaling_trip5 0>;
+	// };
+
+	// gpu_vmax_cdev: gpu-vmax-cdev {
+	// 	cooling-min-state = <0>;
+	// 	cooling-max-state = <1>;
+	// 	#cooling-cells = <2>;
+	// 	compatible = "nvidia,tegra210-rail-vmax-cdev";
+	// 	cdev-type = "GPU-cap";
+	// 	nvidia,constraint-ucm2;
+	// 	nvidia,trips = <&gpu_vmax_trip1 1010 1010>;
+	// 	clocks = <&tegra_car TEGRA210_CLK_CAP_VGPU_GBUS>;
+	// 	clock-names = "cap-clk";
+	// 	status = "disabled";
+	// };
 };

arch/arm64/boot/dts/nvidia/tegra210b01-vali.dts

@@ -5,7 +5,7 @@
 
 / {
 	model = "Nintendo Switch Lite";
-	compatible = "nvidia,vali", "nintendo,hoag", "nintendo,nx", "nvidia,tegra210b01";
+	compatible = "nvidia,vali", "nintendo,hoag", "nintendo,nx", "nvidia,tegra210b01", "nvidia,tegra210";
 
     /* Joycon/Fan power (usb) */
 	v_vdd50_b: v-vdd50-b {
@@ -48,6 +48,33 @@
 		};
 	};
 
+	i2c@7000c000 {
+		bm92t: bm92t@18 {
+			status = "disabled";
+			/delete-property/ rohm,dp-signal-toggle-on-resume;
+			rohm,dp-disable;
+			rohm,pd-5v-current-limit-ma = <2000>;
+			rohm,pd-9v-current-limit-ma = <1500>;
+			rohm,pd-12v-current-limit-ma = <1200>;
+			rohm,pd-15v-current-limit-ma = <900>;
+		};
+
+		bq2419x: bq24193@6b {
+			battery_charger: charger {
+				ti,charge-voltage-limit-millivolt = <4320>; /* Adjusted by cell age */
+				ti,fast-charge-current-limit-milliamp = <1664>;
+				ti,temp-range = <0 18 47 58>;
+				ti,charge-thermal-voltage-limit = <4320 4320 4320 4080>; /* Adjusted by cell age */
+				ti,charge-current-limit = <512 640 1664 1664>;
+			};
+		};
+
+		fuel_gauge: fuel-gauge@36 {
+			maxim,over-volt = <4320>; /* Actual: 4370 mV */
+			maxim,kernel-maximum-soc = <100>; /* Adjusted by cell age */
+		};
+	};
+
 	i2c@7000d000 {
 		pmic_b: pmic@3c {
 			regulators {
@@ -64,4 +91,52 @@
 		};
 	};
 
+	i2c@546c0000 {
+		bus-pullup-supply = <&battery_reg>;
+	};
+
+	host1x@50000000 {
+		/* tegradc.1: DP */
+		dc@54240000 {
+			status = "disabled";
+		};
+	};
+
+	xusb: usb@70090000 {
+		status = "okay";
+
+		phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
+			<&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>;
+		phy-names = "usb2-0", "usb3-0";
+
+		extcon = <&bm92t 0>;
+		extcon-cable-names = "vbus";
+
+		avdd-usb-supply = <&vdd_3v3>;
+		dvddio-pex-supply = <&max77620_ldo1>;
+		hvddio-pex-supply = <&max77620_sd3>;
+	};
+
+	xudc: usb@700d0000 {
+		status = "okay";
+
+		phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
+			<&{/padctl@7009f000/pads/pcie/lanes/pcie-5}>;
+		phy-names = "usb2-0", "usb3-0";
+
+		extcon = <&bm92t 1>;
+		extcon-cable-names = "id";
+
+		hvdd-usb-supply = <&vdd_3v3>;
+		avddio-usb-supply = <&max77620_ldo1>;
+	};
+
+	padctl@7009f000 {
+		status =  "okay";
+
+		avdd-pll-utmip-supply = <&max77620_sd3>;
+		avdd-pll-uerefe-supply = <&max77620_ldo1>;
+		dvdd-pex-pll-supply = <&max77620_ldo1>;
+		hvdd-pex-pll-e-supply = <&max77620_sd3>;
+	};
 };

arch/arm64/configs/defconfig

@@ -32,7 +32,6 @@ CONFIG_KALLSYMS_ALL=y
 CONFIG_PROFILING=y
 CONFIG_KEXEC=y
 CONFIG_KEXEC_FILE=y
-CONFIG_CRASH_DUMP=y
 CONFIG_ARCH_ACTIONS=y
 CONFIG_ARCH_AIROHA=y
 CONFIG_ARCH_SUNXI=y
@@ -94,7 +93,6 @@ CONFIG_CPU_FREQ_GOV_USERSPACE=y
 CONFIG_CPU_FREQ_GOV_ONDEMAND=y
 CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m
 CONFIG_CPUFREQ_DT=y
-CONFIG_ACPI_CPPC_CPUFREQ=m
 CONFIG_ARM_ALLWINNER_SUN50I_CPUFREQ_NVMEM=m
 CONFIG_ARM_ARMADA_37XX_CPUFREQ=y
 CONFIG_ARM_SCPI_CPUFREQ=y
@@ -106,6 +104,7 @@ CONFIG_ARM_RASPBERRYPI_CPUFREQ=m
 CONFIG_ARM_SCMI_CPUFREQ=y
 CONFIG_ARM_TEGRA186_CPUFREQ=y
 CONFIG_QORIQ_CPUFREQ=y
+CONFIG_ACPI_CPPC_CPUFREQ=m
 CONFIG_ACPI=y
 CONFIG_ACPI_HOTPLUG_MEMORY=y
 CONFIG_ACPI_HMAT=y
@@ -115,11 +114,9 @@ CONFIG_ACPI_APEI_PCIEAER=y
 CONFIG_ACPI_APEI_MEMORY_FAILURE=y
 CONFIG_ACPI_APEI_EINJ=y
 CONFIG_VIRTUALIZATION=y
-CONFIG_KVM=y
 CONFIG_JUMP_LABEL=y
 CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
-CONFIG_IOSCHED_BFQ=y
 # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
 # CONFIG_COMPAT_BRK is not set
 CONFIG_MEMORY_HOTPLUG=y
@@ -129,8 +126,6 @@ CONFIG_MEMORY_FAILURE=y
 CONFIG_TRANSPARENT_HUGEPAGE=y
 CONFIG_NET=y
 CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
 CONFIG_IP_MULTICAST=y
 CONFIG_IP_PNP=y
 CONFIG_IP_PNP_DHCP=y
@@ -177,6 +172,7 @@ CONFIG_NET_CLS_ACT=y
 CONFIG_NET_ACT_GACT=m
 CONFIG_NET_ACT_MIRRED=m
 CONFIG_NET_ACT_GATE=m
+CONFIG_HSR=m
 CONFIG_QRTR_SMD=m
 CONFIG_QRTR_TUN=m
 CONFIG_CAN=m
@@ -198,8 +194,8 @@ CONFIG_BT_QCOMSMD=m
 CONFIG_BT_NXPUART=m
 CONFIG_CFG80211=m
 CONFIG_MAC80211=m
-CONFIG_MAC80211_LEDS=y
 CONFIG_RFKILL=m
+CONFIG_RFKILL_GPIO=m
 CONFIG_NET_9P=y
 CONFIG_NET_9P_VIRTIO=y
 CONFIG_NFC=m
@@ -248,7 +244,6 @@ CONFIG_FW_LOADER_USER_HELPER=y
 CONFIG_HISILICON_LPC=y
 CONFIG_TEGRA_ACONNECT=m
 CONFIG_MHI_BUS_PCI_GENERIC=m
-CONFIG_ARM_SCMI_PROTOCOL=y
 CONFIG_ARM_SCPI_PROTOCOL=y
 CONFIG_RASPBERRYPI_FIRMWARE=y
 CONFIG_INTEL_STRATIX10_SERVICE=y
@@ -281,6 +276,7 @@ CONFIG_MTD_NAND_MARVELL=y
 CONFIG_MTD_NAND_BRCMNAND=m
 CONFIG_MTD_NAND_FSL_IFC=y
 CONFIG_MTD_NAND_QCOM=y
+CONFIG_MTD_SPI_NAND=m
 CONFIG_MTD_SPI_NOR=y
 CONFIG_MTD_UBI=m
 CONFIG_MTD_HYPERBUS=m
@@ -314,7 +310,6 @@ CONFIG_AHCI_XGENE=y
 CONFIG_AHCI_QORIQ=y
 CONFIG_SATA_SIL24=y
 CONFIG_SATA_RCAR=y
-CONFIG_PATA_PLATFORM=y
 CONFIG_PATA_OF_PLATFORM=y
 CONFIG_MD=y
 CONFIG_BLK_DEV_MD=m
@@ -330,6 +325,7 @@ CONFIG_VIRTIO_NET=y
 CONFIG_MHI_NET=m
 CONFIG_NET_DSA_BCM_SF2=m
 CONFIG_NET_DSA_MSCC_FELIX=m
+CONFIG_ENA_ETHERNET=m
 CONFIG_AMD_XGBE=y
 CONFIG_NET_XGENE=y
 CONFIG_ATL1C=m
@@ -358,6 +354,8 @@ CONFIG_IGBVF=y
 CONFIG_MVNETA=y
 CONFIG_MVPP2=y
 CONFIG_SKY2=y
+CONFIG_NET_VENDOR_MEDIATEK=y
+CONFIG_NET_MEDIATEK_STAR_EMAC=m
 CONFIG_MLX4_EN=m
 CONFIG_MLX5_CORE=m
 CONFIG_MLX5_CORE_EN=y
@@ -373,6 +371,7 @@ CONFIG_SMSC911X=y
 CONFIG_SNI_AVE=y
 CONFIG_SNI_NETSEC=y
 CONFIG_STMMAC_ETH=m
+CONFIG_DWMAC_MEDIATEK=m
 CONFIG_DWMAC_TEGRA=m
 CONFIG_TI_K3_AM65_CPSW_NUSS=y
 CONFIG_TI_ICSSG_PRUETH=m
@@ -516,10 +515,10 @@ CONFIG_TCG_TIS_I2C_INFINEON=y
 CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_MUX=y
 CONFIG_I2C_MUX_PCA954x=y
+CONFIG_I2C_MUX_PINCTRL=m
 CONFIG_I2C_BCM2835=m
 CONFIG_I2C_CADENCE=m
 CONFIG_I2C_DESIGNWARE_CORE=y
-CONFIG_I2C_DESIGNWARE_PLATFORM=y
 CONFIG_I2C_GPIO=m
 CONFIG_I2C_IMX=y
 CONFIG_I2C_IMX_LPI2C=y
@@ -650,14 +649,16 @@ CONFIG_GPIO_PL061=y
 CONFIG_GPIO_RCAR=y
 CONFIG_GPIO_SYSCON=y
 CONFIG_GPIO_UNIPHIER=y
+CONFIG_GPIO_VF610=y
 CONFIG_GPIO_VISCONTI=y
 CONFIG_GPIO_WCD934X=m
-CONFIG_GPIO_VF610=y
 CONFIG_GPIO_XGENE=y
 CONFIG_GPIO_XGENE_SB=y
 CONFIG_GPIO_MAX732X=y
 CONFIG_GPIO_PCA953X=y
 CONFIG_GPIO_PCA953X_IRQ=y
+CONFIG_GPIO_PCF857X=m
+CONFIG_GPIO_TPIC2810=m
 CONFIG_GPIO_ADP5585=m
 CONFIG_GPIO_BD9571MWV=m
 CONFIG_GPIO_MAX77620=y
@@ -689,6 +690,7 @@ CONFIG_SENSORS_RASPBERRYPI_HWMON=m
 CONFIG_SENSORS_SL28CPLD=m
 CONFIG_SENSORS_INA2XX=m
 CONFIG_SENSORS_INA3221=m
+CONFIG_SENSORS_TMP102=m
 CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
 CONFIG_CPU_THERMAL=y
 CONFIG_DEVFREQ_THERMAL=y
@@ -699,9 +701,6 @@ CONFIG_K3_THERMAL=m
 CONFIG_QORIQ_THERMAL=m
 CONFIG_SUN8I_THERMAL=y
 CONFIG_ROCKCHIP_THERMAL=m
-CONFIG_RCAR_THERMAL=y
-CONFIG_RCAR_GEN3_THERMAL=y
-CONFIG_RZG2L_THERMAL=y
 CONFIG_ARMADA_THERMAL=y
 CONFIG_MTK_THERMAL=m
 CONFIG_MTK_LVTS_THERMAL=m
@@ -709,6 +708,9 @@ CONFIG_BCM2711_THERMAL=m
 CONFIG_BCM2835_THERMAL=m
 CONFIG_BRCMSTB_THERMAL=m
 CONFIG_EXYNOS_THERMAL=y
+CONFIG_RCAR_THERMAL=y
+CONFIG_RCAR_GEN3_THERMAL=y
+CONFIG_RZG2L_THERMAL=y
 CONFIG_TEGRA_SOCTHERM=m
 CONFIG_TEGRA_BPMP_THERMAL=m
 CONFIG_GENERIC_ADC_THERMAL=m
@@ -736,6 +738,7 @@ CONFIG_MESON_WATCHDOG=m
 CONFIG_ARM_SMC_WATCHDOG=y
 CONFIG_RENESAS_WDT=y
 CONFIG_RENESAS_RZG2LWDT=y
+CONFIG_RENESAS_RZV2HWDT=y
 CONFIG_UNIPHIER_WATCHDOG=y
 CONFIG_PM8916_WATCHDOG=m
 CONFIG_BCM2835_WDT=y
@@ -763,6 +766,7 @@ CONFIG_MFD_TI_LP873X=m
 CONFIG_MFD_TPS65219=y
 CONFIG_MFD_TPS6594_I2C=m
 CONFIG_MFD_ROHM_BD718XX=y
+CONFIG_MFD_STM32_LPTIMER=m
 CONFIG_MFD_WCD934X=m
 CONFIG_MFD_KHADAS_MCU=m
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
@@ -777,9 +781,9 @@ CONFIG_REGULATOR_HI6421V530=y
 CONFIG_REGULATOR_HI655X=y
 CONFIG_REGULATOR_LP873X=m
 CONFIG_REGULATOR_MAX77620=y
-CONFIG_REGULATOR_MAX77812=y
 CONFIG_REGULATOR_MAX8973=y
 CONFIG_REGULATOR_MAX20411=m
+CONFIG_REGULATOR_MAX77812=y
 CONFIG_REGULATOR_MP8859=y
 CONFIG_REGULATOR_MT6315=m
 CONFIG_REGULATOR_MT6357=y
@@ -824,10 +828,11 @@ CONFIG_SDR_PLATFORM_DRIVERS=y
 CONFIG_V4L_MEM2MEM_DRIVERS=y
 CONFIG_VIDEO_AMPHION_VPU=m
 CONFIG_VIDEO_CADENCE_CSI2RX=m
-CONFIG_VIDEO_MEDIATEK_JPEG=m
-CONFIG_VIDEO_MEDIATEK_VCODEC=m
 CONFIG_VIDEO_WAVE_VPU=m
 CONFIG_VIDEO_E5010_JPEG_ENC=m
+CONFIG_VIDEO_MEDIATEK_JPEG=m
+CONFIG_VIDEO_MEDIATEK_VCODEC=m
+CONFIG_VIDEO_MEDIATEK_MDP3=m
 CONFIG_VIDEO_IMX7_CSI=m
 CONFIG_VIDEO_IMX_MIPI_CSIS=m
 CONFIG_VIDEO_IMX8_ISI=m
@@ -835,8 +840,8 @@ CONFIG_VIDEO_IMX8_ISI_M2M=y
 CONFIG_VIDEO_IMX8_JPEG=m
 CONFIG_VIDEO_QCOM_CAMSS=m
 CONFIG_VIDEO_QCOM_VENUS=m
-CONFIG_VIDEO_RCAR_ISP=m
 CONFIG_VIDEO_RCAR_CSI2=m
+CONFIG_VIDEO_RCAR_ISP=m
 CONFIG_VIDEO_RCAR_VIN=m
 CONFIG_VIDEO_RZG2L_CSI2=m
 CONFIG_VIDEO_RZG2L_CRU=m
@@ -854,7 +859,7 @@ CONFIG_VIDEO_IMX219=m
 CONFIG_VIDEO_IMX412=m
 CONFIG_VIDEO_OV5640=m
 CONFIG_VIDEO_OV5645=m
-CONFIG_DRM=m
+CONFIG_DRM=y
 CONFIG_DRM_I2C_NXP_TDA998X=m
 CONFIG_DRM_HDLCD=m
 CONFIG_DRM_MALI_DISPLAY=m
@@ -877,26 +882,26 @@ CONFIG_ROCKCHIP_INNO_HDMI=y
 CONFIG_ROCKCHIP_LVDS=y
 CONFIG_DRM_RCAR_DU=m
 CONFIG_DRM_RCAR_DW_HDMI=m
-CONFIG_DRM_RCAR_MIPI_DSI=m
-CONFIG_DRM_RZG2L_MIPI_DSI=m
 CONFIG_DRM_RZG2L_DU=m
+CONFIG_DRM_RZG2L_MIPI_DSI=m
 CONFIG_DRM_SUN4I=m
-CONFIG_DRM_SUN6I_DSI=m
-CONFIG_DRM_SUN8I_DW_HDMI=m
-CONFIG_DRM_SUN8I_MIXER=m
 CONFIG_DRM_MSM=m
-CONFIG_DRM_TEGRA=m
+CONFIG_DRM_TEGRA=y
+CONFIG_DRM_TEGRA_DEBUG=y
+CONFIG_DRM_TEGRA_STAGING=y
 CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m
 CONFIG_DRM_PANEL_LVDS=m
-CONFIG_DRM_PANEL_SIMPLE=m
-CONFIG_DRM_PANEL_EDP=m
 CONFIG_DRM_PANEL_ILITEK_ILI9882T=m
+CONFIG_DRM_PANEL_NX_DSI=y
 CONFIG_DRM_PANEL_KHADAS_TS050=m
 CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m
 CONFIG_DRM_PANEL_NOVATEK_NT36672E=m
 CONFIG_DRM_PANEL_RAYDIUM_RM67191=m
 CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m
 CONFIG_DRM_PANEL_SITRONIX_ST7703=m
+CONFIG_DRM_PANEL_STARTEK_KD070FHFID015=m
+CONFIG_DRM_PANEL_EDP=m
+CONFIG_DRM_PANEL_SIMPLE=m
 CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m
 CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m
 CONFIG_DRM_FSL_LDB=m
@@ -906,7 +911,6 @@ CONFIG_DRM_LONTIUM_LT9611UXC=m
 CONFIG_DRM_ITE_IT66121=m
 CONFIG_DRM_NWL_MIPI_DSI=m
 CONFIG_DRM_PARADE_PS8640=m
-CONFIG_DRM_SAMSUNG_DSIM=m
 CONFIG_DRM_SII902X=m
 CONFIG_DRM_SIMPLE_BRIDGE=m
 CONFIG_DRM_THINE_THC63LVD1024=m
@@ -918,6 +922,7 @@ CONFIG_DRM_TI_SN65DSI86=m
 CONFIG_DRM_ANALOGIX_ANX7625=m
 CONFIG_DRM_I2C_ADV7511=m
 CONFIG_DRM_I2C_ADV7511_AUDIO=y
+CONFIG_DRM_CDNS_DSI=m
 CONFIG_DRM_CDNS_MHDP8546=m
 CONFIG_DRM_IMX8MP_DW_HDMI_BRIDGE=m
 CONFIG_DRM_DW_HDMI_AHB_AUDIO=m
@@ -943,7 +948,8 @@ CONFIG_DRM_POWERVR=m
 CONFIG_FB=y
 CONFIG_FB_EFI=y
 CONFIG_FB_MODE_HELPERS=y
-CONFIG_BACKLIGHT_PWM=m
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_BACKLIGHT_PWM=y
 CONFIG_BACKLIGHT_LP855X=m
 CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
@@ -965,6 +971,8 @@ CONFIG_SND_SOC_IMX_AUDMIX=m
 CONFIG_SND_SOC_MT8183=m
 CONFIG_SND_SOC_MT8183_MT6358_TS3A227E_MAX98357A=m
 CONFIG_SND_SOC_MT8183_DA7219_MAX98357A=m
+CONFIG_SND_SOC_MT8188=m
+CONFIG_SND_SOC_MT8188_MT6359=m
 CONFIG_SND_SOC_MT8192=m
 CONFIG_SND_SOC_MT8192_MT6359_RT1015_RT5682=m
 CONFIG_SND_SOC_MT8195=m
@@ -993,6 +1001,7 @@ CONFIG_SND_SOC_RZ=m
 CONFIG_SND_SOC_SOF_TOPLEVEL=y
 CONFIG_SND_SOC_SOF_OF=y
 CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=y
+CONFIG_SND_SOC_SOF_MT8186=m
 CONFIG_SND_SOC_SOF_MT8195=m
 CONFIG_SND_SUN8I_CODEC=m
 CONFIG_SND_SUN8I_CODEC_ANALOG=m
@@ -1013,7 +1022,6 @@ CONFIG_SND_SOC_TEGRA210_AMX=m
 CONFIG_SND_SOC_TEGRA210_ADX=m
 CONFIG_SND_SOC_TEGRA210_MIXER=m
 CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m
-CONFIG_SND_SOC_DAVINCI_MCASP=m
 CONFIG_SND_SOC_J721E_EVM=m
 CONFIG_SND_SOC_AK4613=m
 CONFIG_SND_SOC_AK4619=m
@@ -1021,10 +1029,10 @@ CONFIG_SND_SOC_DA7213=m
 CONFIG_SND_SOC_ES7134=m
 CONFIG_SND_SOC_ES7241=m
 CONFIG_SND_SOC_ES8316=m
+CONFIG_SND_SOC_ES8328_I2C=m
 CONFIG_SND_SOC_GTM601=m
 CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
 CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
-CONFIG_SND_SOC_PCM3168A_I2C=m
 CONFIG_SND_SOC_RK3308=m
 CONFIG_SND_SOC_RK817=m
 CONFIG_SND_SOC_RT5640=m
@@ -1037,7 +1045,6 @@ CONFIG_SND_SOC_TLV320AIC32X4_I2C=m
 CONFIG_SND_SOC_TLV320AIC3X_I2C=m
 CONFIG_SND_SOC_WCD9335=m
 CONFIG_SND_SOC_WCD934X=m
-CONFIG_SND_SOC_WCD939X=m
 CONFIG_SND_SOC_WCD939X_SDW=m
 CONFIG_SND_SOC_WM8524=m
 CONFIG_SND_SOC_WM8904=m
@@ -1050,8 +1057,6 @@ CONFIG_SND_SOC_WSA884X=m
 CONFIG_SND_SOC_NAU8822=m
 CONFIG_SND_SOC_LPASS_WSA_MACRO=m
 CONFIG_SND_SOC_LPASS_VA_MACRO=m
-CONFIG_SND_SOC_LPASS_RX_MACRO=m
-CONFIG_SND_SOC_LPASS_TX_MACRO=m
 CONFIG_SND_SIMPLE_CARD=m
 CONFIG_SND_AUDIO_GRAPH_CARD=m
 CONFIG_SND_AUDIO_GRAPH_CARD2=m
@@ -1080,12 +1085,10 @@ CONFIG_USB_CDNS_SUPPORT=m
 CONFIG_USB_CDNS3=m
 CONFIG_USB_CDNS3_GADGET=y
 CONFIG_USB_CDNS3_HOST=y
-CONFIG_USB_CDNS3_IMX=m
 CONFIG_USB_MTU3=y
 CONFIG_USB_MUSB_HDRC=y
 CONFIG_USB_MUSB_SUNXI=y
 CONFIG_USB_DWC3=y
-CONFIG_OMAP_USB2=m
 CONFIG_USB_DWC2=y
 CONFIG_USB_CHIPIDEA=y
 CONFIG_USB_CHIPIDEA_UDC=y
@@ -1120,6 +1123,9 @@ CONFIG_USB_MASS_STORAGE=m
 CONFIG_TYPEC=m
 CONFIG_TYPEC_TCPM=m
 CONFIG_TYPEC_TCPCI=m
+CONFIG_TYPEC_RT1711H=m
+CONFIG_TYPEC_MT6360=m
+CONFIG_TYPEC_TCPCI_MAXIM=m
 CONFIG_TYPEC_FUSB302=m
 CONFIG_TYPEC_QCOM_PMIC=m
 CONFIG_TYPEC_UCSI=m
@@ -1129,6 +1135,7 @@ CONFIG_TYPEC_TPS6598X=m
 CONFIG_TYPEC_HD3SS3220=m
 CONFIG_TYPEC_MUX_FSA4480=m
 CONFIG_TYPEC_MUX_GPIO_SBU=m
+CONFIG_TYPEC_MUX_IT5205=m
 CONFIG_TYPEC_MUX_NB7VPQ904M=m
 CONFIG_TYPEC_MUX_WCD939X_USBSS=m
 CONFIG_TYPEC_DP_ALTMODE=m
@@ -1235,6 +1242,7 @@ CONFIG_PL330_DMA=y
 CONFIG_TEGRA186_GPC_DMA=y
 CONFIG_TEGRA20_APB_DMA=y
 CONFIG_TEGRA210_ADMA=m
+CONFIG_MTK_UART_APDMA=m
 CONFIG_QCOM_BAM_DMA=y
 CONFIG_QCOM_GPI_DMA=m
 CONFIG_QCOM_HIDMA_MGMT=y
@@ -1252,6 +1260,8 @@ CONFIG_VIRTIO_BALLOON=y
 CONFIG_VIRTIO_MMIO=y
 CONFIG_XEN_GNTDEV=y
 CONFIG_XEN_GRANT_DEV_ALLOC=y
+CONFIG_GREYBUS=m
+CONFIG_GREYBUS_BEAGLEPLAY=m
 CONFIG_STAGING=y
 CONFIG_STAGING_MEDIA=y
 CONFIG_VIDEO_MAX96712=m
@@ -1265,7 +1275,6 @@ CONFIG_CROS_EC_SPI=y
 CONFIG_CROS_KBD_LED_BACKLIGHT=m
 CONFIG_CROS_EC_CHARDEV=m
 CONFIG_COMMON_CLK_RK808=y
-CONFIG_COMMON_CLK_SCMI=y
 CONFIG_COMMON_CLK_SCPI=y
 CONFIG_COMMON_CLK_CS2000_CP=y
 CONFIG_COMMON_CLK_FSL_SAI=y
@@ -1284,31 +1293,19 @@ CONFIG_CLK_IMX8QXP=y
 CONFIG_CLK_IMX8ULP=y
 CONFIG_CLK_IMX93=y
 CONFIG_TI_SCI_CLK=y
-CONFIG_COMMON_CLK_MT8192_AUDSYS=y
-CONFIG_COMMON_CLK_MT8192_CAMSYS=y
-CONFIG_COMMON_CLK_MT8192_IMGSYS=y
-CONFIG_COMMON_CLK_MT8192_IMP_IIC_WRAP=y
-CONFIG_COMMON_CLK_MT8192_IPESYS=y
-CONFIG_COMMON_CLK_MT8192_MDPSYS=y
-CONFIG_COMMON_CLK_MT8192_MFGCFG=y
-CONFIG_COMMON_CLK_MT8192_MMSYS=y
-CONFIG_COMMON_CLK_MT8192_MSDC=y
-CONFIG_COMMON_CLK_MT8192_SCP_ADSP=y
-CONFIG_COMMON_CLK_MT8192_VDECSYS=y
-CONFIG_COMMON_CLK_MT8192_VENCSYS=y
 CONFIG_COMMON_CLK_QCOM=y
 CONFIG_CLK_X1E80100_CAMCC=m
 CONFIG_CLK_X1E80100_DISPCC=m
 CONFIG_CLK_X1E80100_GCC=y
 CONFIG_CLK_X1E80100_GPUCC=m
 CONFIG_CLK_X1E80100_TCSRCC=y
+CONFIG_CLK_QCM2290_GPUCC=m
 CONFIG_QCOM_A53PLL=y
 CONFIG_QCOM_CLK_APCS_MSM8916=y
 CONFIG_QCOM_CLK_APCC_MSM8996=y
 CONFIG_QCOM_CLK_SMD_RPM=y
 CONFIG_QCOM_CLK_RPMH=y
 CONFIG_IPQ_APSS_6018=y
-CONFIG_IPQ_APSS_5018=y
 CONFIG_IPQ_GCC_5018=y
 CONFIG_IPQ_GCC_5332=y
 CONFIG_IPQ_GCC_6018=y
@@ -1324,7 +1321,7 @@ CONFIG_MSM_MMCC_8998=m
 CONFIG_QCM_GCC_2290=y
 CONFIG_QCM_DISPCC_2290=m
 CONFIG_QCS_GCC_404=y
-CONFIG_QDU_GCC_1000=y
+CONFIG_SC_CAMCC_7280=m
 CONFIG_SC_CAMCC_8280XP=m
 CONFIG_SC_DISPCC_7280=m
 CONFIG_SC_DISPCC_8280XP=m
@@ -1337,7 +1334,10 @@ CONFIG_SC_GCC_8280XP=y
 CONFIG_SC_GPUCC_7280=m
 CONFIG_SC_GPUCC_8280XP=m
 CONFIG_SC_LPASSCC_8280XP=m
+CONFIG_SC_LPASS_CORECC_7280=m
+CONFIG_SC_VIDEOCC_7280=m
 CONFIG_SDM_CAMCC_845=m
+CONFIG_QDU_GCC_1000=y
 CONFIG_SDM_GPUCC_845=y
 CONFIG_SDM_VIDEOCC_845=y
 CONFIG_SDM_DISPCC_845=y
@@ -1348,7 +1348,6 @@ CONFIG_SM_DISPCC_6115=m
 CONFIG_SM_DISPCC_8250=y
 CONFIG_SM_DISPCC_8450=m
 CONFIG_SM_DISPCC_8550=m
-CONFIG_SM_DISPCC_8650=m
 CONFIG_SM_GCC_4450=y
 CONFIG_SM_GCC_6115=y
 CONFIG_SM_GCC_8350=y
@@ -1365,16 +1364,18 @@ CONFIG_SM_GPUCC_8650=m
 CONFIG_SM_TCSRCC_8550=y
 CONFIG_SM_TCSRCC_8650=y
 CONFIG_SM_VIDEOCC_8250=y
+CONFIG_SM_VIDEOCC_8550=m
 CONFIG_QCOM_HFPLL=y
 CONFIG_CLK_GFM_LPASS_SM8250=m
 CONFIG_CLK_RCAR_USB2_CLOCK_SEL=y
 CONFIG_HWSPINLOCK=y
+CONFIG_HWSPINLOCK_OMAP=m
 CONFIG_HWSPINLOCK_QCOM=y
 CONFIG_TEGRA186_TIMER=y
+CONFIG_CLKSRC_STM32_LP=y
 CONFIG_RENESAS_OSTM=y
 CONFIG_ARM_MHU=y
 CONFIG_IMX_MBOX=y
-CONFIG_OMAP2PLUS_MBOX=m
 CONFIG_PLATFORM_MHU=y
 CONFIG_BCM2835_MBOX=y
 CONFIG_QCOM_APCS_IPC=y
@@ -1395,6 +1396,7 @@ CONFIG_QCOM_Q6V5_PAS=m
 CONFIG_QCOM_SYSMON=m
 CONFIG_QCOM_WCNSS_PIL=m
 CONFIG_TI_K3_DSP_REMOTEPROC=m
+CONFIG_TI_K3_M4_REMOTEPROC=m
 CONFIG_TI_K3_R5_REMOTEPROC=m
 CONFIG_RPMSG_CHAR=m
 CONFIG_RPMSG_CTRL=m
@@ -1473,12 +1475,14 @@ CONFIG_ARM_MEDIATEK_CCI_DEVFREQ=m
 CONFIG_EXTCON_PTN5150=m
 CONFIG_EXTCON_USB_GPIO=y
 CONFIG_EXTCON_USBC_CROS_EC=y
+CONFIG_FSL_IFC=y
 CONFIG_RENESAS_RPCIF=m
 CONFIG_IIO=y
 CONFIG_EXYNOS_ADC=y
 CONFIG_IMX8QXP_ADC=m
 CONFIG_IMX93_ADC=m
 CONFIG_MAX9611=m
+CONFIG_MEDIATEK_MT6359_AUXADC=m
 CONFIG_MEDIATEK_MT6577_AUXADC=m
 CONFIG_QCOM_SPMI_VADC=m
 CONFIG_QCOM_SPMI_ADC5=m
@@ -1511,7 +1515,7 @@ CONFIG_PWM_RZ_MTU3=m
 CONFIG_PWM_SAMSUNG=y
 CONFIG_PWM_SL28CPLD=m
 CONFIG_PWM_SUN4I=m
-CONFIG_PWM_TEGRA=m
+CONFIG_PWM_TEGRA=y
 CONFIG_PWM_TIECAP=m
 CONFIG_PWM_TIEHRPWM=m
 CONFIG_PWM_VISCONTI=m
@@ -1528,6 +1532,7 @@ CONFIG_PHY_XGENE=y
 CONFIG_PHY_CAN_TRANSCEIVER=m
 CONFIG_PHY_SUN4I_USB=y
 CONFIG_PHY_CADENCE_TORRENT=m
+CONFIG_PHY_CADENCE_DPHY=m
 CONFIG_PHY_CADENCE_DPHY_RX=m
 CONFIG_PHY_CADENCE_SIERRA=m
 CONFIG_PHY_CADENCE_SALVO=m
@@ -1537,6 +1542,7 @@ CONFIG_PHY_HI6220_USB=y
 CONFIG_PHY_HISTB_COMBPHY=y
 CONFIG_PHY_HISI_INNO_USB2=y
 CONFIG_PHY_MVEBU_CP110_COMPHY=y
+CONFIG_PHY_MTK_PCIE=m
 CONFIG_PHY_MTK_TPHY=y
 CONFIG_PHY_QCOM_EDP=m
 CONFIG_PHY_QCOM_PCIE2=m
@@ -1570,6 +1576,7 @@ CONFIG_PHY_UNIPHIER_USB3=y
 CONFIG_PHY_TEGRA_XUSB=y
 CONFIG_PHY_AM654_SERDES=m
 CONFIG_PHY_J721E_WIZ=m
+CONFIG_OMAP_USB2=m
 CONFIG_ARM_CCI_PMU=m
 CONFIG_ARM_CCN=m
 CONFIG_ARM_CMN=m
@@ -1611,10 +1618,8 @@ CONFIG_TEE=y
 CONFIG_OPTEE=y
 CONFIG_MUX_GPIO=m
 CONFIG_MUX_MMIO=y
-CONFIG_SLIMBUS=m
 CONFIG_SLIM_QCOM_CTRL=m
 CONFIG_SLIM_QCOM_NGD_CTRL=m
-CONFIG_INTERCONNECT=y
 CONFIG_INTERCONNECT_IMX=y
 CONFIG_INTERCONNECT_IMX8MM=m
 CONFIG_INTERCONNECT_IMX8MN=m
@@ -1644,6 +1649,7 @@ CONFIG_INTERCONNECT_QCOM_SM8650=y
 CONFIG_INTERCONNECT_QCOM_X1E80100=y
 CONFIG_COUNTER=m
 CONFIG_RZ_MTU3_CNT=m
+CONFIG_TI_EQEP=m
 CONFIG_HTE=y
 CONFIG_HTE_TEGRA194=y
 CONFIG_HTE_TEGRA194_TEST=m
@@ -1662,7 +1668,6 @@ CONFIG_OVERLAY_FS=m
 CONFIG_VFAT_FS=y
 CONFIG_TMPFS_POSIX_ACL=y
 CONFIG_HUGETLBFS=y
-CONFIG_CONFIGFS_FS=y
 CONFIG_EFIVAR_FS=y
 CONFIG_UBIFS_FS=m
 CONFIG_SQUASHFS=y
@@ -1678,8 +1683,8 @@ CONFIG_NLS_ISO8859_1=y
 CONFIG_SECURITY=y
 CONFIG_CRYPTO_USER=y
 CONFIG_CRYPTO_TEST=m
+CONFIG_CRYPTO_CHACHA20=m
 CONFIG_CRYPTO_ECHAINIV=y
-CONFIG_CRYPTO_MICHAEL_MIC=m
 CONFIG_CRYPTO_ANSI_CPRNG=y
 CONFIG_CRYPTO_USER_API_RNG=m
 CONFIG_CRYPTO_CHACHA20_NEON=m
@@ -1689,7 +1694,6 @@ CONFIG_CRYPTO_SHA2_ARM64_CE=y
 CONFIG_CRYPTO_SHA512_ARM64_CE=m
 CONFIG_CRYPTO_SHA3_ARM64=m
 CONFIG_CRYPTO_SM3_ARM64_CE=m
-CONFIG_CRYPTO_AES_ARM64_CE_BLK=y
 CONFIG_CRYPTO_AES_ARM64_BS=m
 CONFIG_CRYPTO_AES_ARM64_CE_CCM=y
 CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=m
@@ -1714,7 +1718,6 @@ CONFIG_DEBUG_INFO_REDUCED=y
 CONFIG_MAGIC_SYSRQ=y
 CONFIG_DEBUG_FS=y
 # CONFIG_SCHED_DEBUG is not set
-# CONFIG_DEBUG_PREEMPT is not set
 # CONFIG_FTRACE is not set
 CONFIG_CORESIGHT=m
 CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m

drivers/clk/tegra/clk-tegra210b01.c

@@ -503,6 +503,72 @@ static unsigned long tegra210_input_freq[] = {
 #define PLLE_SS_COEFFICIENTS_VAL \
 	(PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL)
 
+bool tegra210b01_plle_hw_sequence_is_enabled(void)
+{
+	u32 value;
+
+	value = readl_relaxed(clk_base + PLLE_AUX);
+	if (value & PLLE_AUX_SEQ_ENABLE)
+		return true;
+
+	return false;
+}
+EXPORT_SYMBOL_GPL(tegra210b01_plle_hw_sequence_is_enabled);
+
+int tegra210b01_plle_hw_sequence_start(void)
+{
+	u32 value;
+
+	if (tegra210b01_plle_hw_sequence_is_enabled())
+		return 0;
+
+	/* skip if PLLE is not enabled yet */
+	value = readl_relaxed(clk_base + PLLE_MISC0);
+	if (!(value & PLLE_MISC_LOCK))
+		return -EIO;
+
+	value &= ~PLLE_MISC_IDDQ_SW_CTRL;
+	writel_relaxed(value, clk_base + PLLE_MISC0);
+
+	value = readl_relaxed(clk_base + PLLE_AUX);
+	value |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SS_SEQ_INCLUDE);
+	value &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);
+	writel_relaxed(value, clk_base + PLLE_AUX);
+
+	fence_udelay(1, clk_base);
+
+	value |= PLLE_AUX_SEQ_ENABLE;
+	writel_relaxed(value, clk_base + PLLE_AUX);
+
+	fence_udelay(1, clk_base);
+
+	return 0;
+}
+EXPORT_SYMBOL_GPL(tegra210b01_plle_hw_sequence_start);
+
+void tegra210b01_xusb_pll_hw_control_enable(void)
+{
+	u32 val;
+
+	val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
+	val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |
+		 XUSBIO_PLL_CFG0_PADPLL_RESET_SWCTL);
+	val |= XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |
+	       XUSBIO_PLL_CFG0_PADPLL_SLEEP_IDDQ;
+	writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
+}
+EXPORT_SYMBOL_GPL(tegra210b01_xusb_pll_hw_control_enable);
+
+void tegra210b01_xusb_pll_hw_sequence_start(void)
+{
+	u32 val;
+
+	val = readl_relaxed(clk_base + XUSBIO_PLL_CFG0);
+	val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;
+	writel_relaxed(val, clk_base + XUSBIO_PLL_CFG0);
+}
+EXPORT_SYMBOL_GPL(tegra210b01_xusb_pll_hw_sequence_start);
+
 static inline void _pll_misc_chk_default(void __iomem *base,
 					struct tegra_clk_pll_params *params,
 					u8 misc_num, u32 default_val, u32 mask)

drivers/memory/tegra/mc.c

@@ -526,6 +526,10 @@ int tegra30_mc_probe(struct tegra_mc *mc)
 		return err;
 	}
 
+	err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev);
+	if (err < 0)
+		return err;
+
 	return 0;
 }
 

drivers/pci/controller/pci-tegra.c

@@ -454,6 +454,7 @@ struct tegra_pcie_port {
 	unsigned int index;
 	unsigned int lanes;
 	unsigned int aspm_state;
+	bool supports_clkreq;
 
 	struct phy **phys;
 
@@ -762,6 +763,13 @@ static void tegra_pcie_enable_rp_features(struct tegra_pcie_port *port)
 			disable_aspm_l11(port);
 		if (port->aspm_state & 0x8)
 			disable_aspm_l12(port);
+
+		/* Disable L1SS capability if CLKREQ# is not present */
+		if (!port->supports_clkreq) {
+			value = readl(port->base + RP_L1_PM_SUBSTATES_CTL);
+			value |= RP_L1_PM_SUBSTATES_CTL_HIDE_CAP;
+			writel(value, port->base + RP_L1_PM_SUBSTATES_CTL);
+		}
 	}
 }
 
@@ -959,8 +967,12 @@ static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
 	value = afi_readl(port->pcie, ctrl);
 	value |= AFI_PEX_CTRL_REFCLK_EN;
 
-	if (soc->has_pex_clkreq_en)
-		value &= ~AFI_PEX_CTRL_CLKREQ_EN;
+	if (soc->has_pex_clkreq_en) {
+		if (port->supports_clkreq)
+			value &= ~AFI_PEX_CTRL_CLKREQ_EN;
+		else
+			value |= AFI_PEX_CTRL_CLKREQ_EN;
+	}
 
 	value |= AFI_PEX_CTRL_OVERRIDE_EN;
 
@@ -1394,6 +1406,14 @@ static void tegra_pcie_enable_controller(struct tegra_pcie *pcie)
 		value = afi_readl(pcie, AFI_PLLE_CONTROL);
 		value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
 		value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
+
+		list_for_each_entry(port, &pcie->ports, list) {
+			if (!port->supports_clkreq) {
+				value &= ~AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
+				break;
+			}
+		}
+
 		value &= ~AFI_PLLE_CONTROL_BYPASS_PCIE2PLLE_CONTROL;
 		value |= AFI_PLLE_CONTROL_PCIE2PLLE_CONTROL_EN;
 		afi_writel(pcie, value, AFI_PLLE_CONTROL);
@@ -2523,6 +2543,9 @@ static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
 		if (err < 0)
 			rp->aspm_state = 0;
 
+		rp->supports_clkreq = of_property_read_bool(port,
+							    "supports-clkreq");
+
 		list_add_tail(&rp->list, &pcie->ports);
 	}
 
@@ -3024,6 +3047,8 @@ static int tegra_pcie_probe(struct platform_device *pdev)
 		goto pm_runtime_put;
 	}
 
+	pci_add_flags(PCI_REASSIGN_ALL_BUS);
+
 	host->ops = &tegra_pcie_ops;
 	host->map_irq = tegra_pcie_map_irq;
 

drivers/phy/tegra/xusb-tegra210.c

@@ -230,6 +230,12 @@
 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_SLEEP_VAL GENMASK(13, 12)
 #define XUSB_PADCTL_UPHY_MISC_PAD_CTL2_RX_PWR_OVRD BIT(25)
 
+#define XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL8(x) (0x460 + (x) * (0x1c))
+#define CFG_ADDR(x) (((x) & 0xff) << 16)
+#define CFG_WDATA(x) (((x) & 0xffff) << 0)
+#define CFG_RESET (1 << 27)
+#define CFG_WS (1 << 24)
+
 #define XUSB_PADCTL_UPHY_PLL_S0_CTL1 0x860
 
 #define XUSB_PADCTL_UPHY_PLL_S0_CTL2 0x864
@@ -240,6 +246,8 @@
 
 #define XUSB_PADCTL_UPHY_PLL_S0_CTL8 0x87c
 
+#define XUSB_PADCTL_UPHY_PLL_S0_CTL10 0x384
+
 #define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL1 0x960
 #define XUSB_PADCTL_UPHY_MISC_PAD_S0_CTL2 0x964
 
@@ -407,6 +415,18 @@
 #define   UHSIC_STROBE_RPD_C			BIT(16)
 #define   UHSIC_STROBE_RPD_D			BIT(24)
 
+struct init_data {
+	u8 cfg_addr;
+	u16 cfg_wdata;
+};
+
+static struct init_data usb3_pll_g1_init_data[] = {
+	{.cfg_addr = 0x2,  .cfg_wdata = 0x0000},
+	{.cfg_addr = 0x3,  .cfg_wdata = 0x7051},
+	{.cfg_addr = 0x25, .cfg_wdata = 0x0130},
+	{.cfg_addr = 0x1E, .cfg_wdata = 0x0017},
+};
+
 struct tegra210_xusb_fuse_calibration {
 	u32 hs_curr_level[4];
 	u32 hs_term_range_adj;
@@ -444,11 +464,64 @@ static const struct tegra_xusb_lane_map tegra210_usb3_map[] = {
 	{ 0, NULL,   0 }
 };
 
+static const struct tegra_xusb_lane_map tegra210b01_usb3_map[] = {
+	{ 0, "pcie", 5 },
+	{ 1, "pcie", 4 },
+	{ 2, "pcie", 1 },
+	{ 0, NULL,   0 }
+};
+
+static int t210b01_compatible(struct tegra_xusb_padctl *padctl)
+{
+	struct device_node *np;
+	const char *compatible;
+
+	np = padctl->dev->of_node;
+	compatible = of_get_property(np, "compatible", NULL);
+
+	if (!compatible) {
+		dev_err(padctl->dev, "Failed to get compatible property\n");
+		return -ENODEV;
+	}
+
+	if (strstr(compatible, "tegra210b01") != NULL)
+		return 1;
+	return 0;
+}
+
+static bool plle_hw_sequence_is_enabled(struct tegra_xusb_padctl *padctl) {
+	if (t210b01_compatible(padctl))
+		return tegra210b01_plle_hw_sequence_is_enabled();
+	return tegra210_plle_hw_sequence_is_enabled();
+}
+
+static int plle_hw_sequence_start(struct tegra_xusb_padctl *padctl) {
+	if (t210b01_compatible(padctl))
+		return tegra210b01_plle_hw_sequence_start();
+	return tegra210_plle_hw_sequence_start();
+}
+
+static void xusb_pll_hw_control_enable(struct tegra_xusb_padctl *padctl) {
+	if (t210b01_compatible(padctl))
+		tegra210b01_xusb_pll_hw_control_enable();
+	else
+		return tegra210_xusb_pll_hw_control_enable();
+}
+
+static void xusb_pll_hw_sequence_start(struct tegra_xusb_padctl *padctl) {
+	if (t210b01_compatible(padctl))
+		tegra210b01_xusb_pll_hw_sequence_start();
+	else
+		tegra210_xusb_pll_hw_sequence_start();
+}
+
 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane)
 {
 	const struct tegra_xusb_lane_map *map;
 
-	for (map = tegra210_usb3_map; map->type; map++) {
+	for (map = t210b01_compatible(lane->pad->padctl) ?
+        tegra210b01_usb3_map : tegra210_usb3_map;
+        map->type; map++) {
 		if (map->index == lane->index &&
 		    strcmp(map->type, lane->pad->soc->name) == 0) {
 			dev_dbg(lane->pad->padctl->dev, "lane = %s map to port = usb3-%d\n",
@@ -476,13 +549,31 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
 	if (err < 0)
 		return err;
 
-	if (tegra210_plle_hw_sequence_is_enabled())
+    if (t210b01_compatible(padctl) == 1) {
+		err = clk_prepare_enable(pcie->uphy_mgmt_clk);
+		if (err < 0)
+			return err;
+	}
+
+	if (plle_hw_sequence_is_enabled(padctl))
 		goto skip_pll_init;
 
 	err = reset_control_deassert(pcie->rst);
 	if (err < 0)
 		goto disable;
 
+	if (t210b01_compatible(padctl) == 1) {
+		for (i = 0; i < ARRAY_SIZE(usb3_pll_g1_init_data); i++) {
+			value = 0;
+			value |= CFG_ADDR(usb3_pll_g1_init_data[i].cfg_addr);
+			value |= CFG_WDATA(usb3_pll_g1_init_data[i].cfg_wdata);
+			value |= CFG_RESET;
+			value |= CFG_WS;
+			padctl_writel(padctl, value,
+					XUSB_PADCTL_UPHY_PLL_S0_CTL10);
+		}
+	}
+
 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL2);
 	value &= ~(XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_MASK <<
 		   XUSB_PADCTL_UPHY_PLL_CTL2_CAL_CTRL_SHIFT);
@@ -643,7 +734,7 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
 	value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 
-	tegra210_xusb_pll_hw_control_enable();
+	xusb_pll_hw_control_enable(padctl);
 
 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 	value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
@@ -659,7 +750,7 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
 
 	usleep_range(10, 20);
 
-	tegra210_xusb_pll_hw_sequence_start();
+	xusb_pll_hw_sequence_start(padctl);
 
 skip_pll_init:
 	pcie->enable = true;
@@ -676,6 +767,8 @@ reset:
 	reset_control_assert(pcie->rst);
 disable:
 	clk_disable_unprepare(pcie->pll);
+	if (t210b01_compatible(padctl) == 1)
+		clk_disable_unprepare(pcie->uphy_mgmt_clk);
 	return err;
 }
 
@@ -697,6 +790,8 @@ static void tegra210_pex_uphy_disable(struct tegra_xusb_padctl *padctl)
 	}
 
 	clk_disable_unprepare(pcie->pll);
+    if (t210b01_compatible(padctl) == 1)
+		clk_disable_unprepare(pcie->uphy_mgmt_clk);
 }
 
 /* must be called under padctl->lock */
@@ -1008,8 +1103,8 @@ static int tegra210_uphy_init(struct tegra_xusb_padctl *padctl)
 	if (padctl->sata)
 		tegra210_sata_uphy_enable(padctl);
 
-	if (!tegra210_plle_hw_sequence_is_enabled())
-		tegra210_plle_hw_sequence_start();
+	if (!plle_hw_sequence_is_enabled(padctl))
+		plle_hw_sequence_start(padctl);
 	else
 		dev_dbg(padctl->dev, "PLLE is already in HW control\n");
 
@@ -2560,12 +2655,12 @@ static const struct tegra_xusb_lane_soc tegra210_pcie_lanes[] = {
 };
 
 static const struct tegra_xusb_lane_soc tegra210b01_pcie_lanes[] = {
-	TEGRA210_UPHY_LANE("pcie-0", 0x028, 12, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(0)),
-	TEGRA210_UPHY_LANE("pcie-1", 0x028, 14, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(1)),
-	TEGRA210_UPHY_LANE("pcie-2", 0x028, 16, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(2)),
-	TEGRA210_UPHY_LANE("pcie-3", 0x028, 18, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(3)),
-	TEGRA210_UPHY_LANE("pcie-4", 0x028, 20, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(4)),
-	TEGRA210_UPHY_LANE("pcie-5", 0x028, 22, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(5)),
+	TEGRA210_UPHY_LANE("pcie-0", 0x28, 12, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(0)),
+	TEGRA210_UPHY_LANE("pcie-1", 0x28, 14, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(0)),
+	TEGRA210_UPHY_LANE("pcie-2", 0x28, 16, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(0)),
+	TEGRA210_UPHY_LANE("pcie-3", 0x28, 18, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(0)),
+	TEGRA210_UPHY_LANE("pcie-4", 0x28, 20, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(0)),
+	TEGRA210_UPHY_LANE("pcie-5", 0x28, 22, 0x3, pcie, XUSB_PADCTL_UPHY_MISC_PAD_PX_CTL2(0)),
 };
 
 static struct tegra_xusb_usb3_port *
@@ -2816,6 +2911,15 @@ tegra210_pcie_pad_probe(struct tegra_xusb_padctl *padctl,
 		goto unregister;
 	}
 
+	if (t210b01_compatible(padctl) == 1) {
+		pcie->uphy_mgmt_clk = devm_clk_get(&pad->dev, "uphy_mgmt");
+		if (IS_ERR(pcie->uphy_mgmt_clk)) {
+			err = PTR_ERR(pcie->uphy_mgmt_clk);
+			dev_err(&pad->dev,
+				"failed to get uphy_mgmt_clk clock: %d\n", err);
+		}
+	}
+
 	pcie->rst = devm_reset_control_get(&pad->dev, "phy");
 	if (IS_ERR(pcie->rst)) {
 		err = PTR_ERR(pcie->rst);
@@ -3094,7 +3198,16 @@ static void tegra210_usb3_port_disable(struct tegra_xusb_port *port)
 static struct tegra_xusb_lane *
 tegra210_usb3_port_map(struct tegra_xusb_port *port)
 {
-	return tegra_xusb_port_find_lane(port, tegra210_usb3_map, "usb3-ss");
+	int err = t210b01_compatible(port->padctl);
+
+	if (err == 1)
+		return tegra_xusb_port_find_lane(port,
+						tegra210b01_usb3_map, "usb3-ss");
+	else if (err == 0)
+		return tegra_xusb_port_find_lane(port,
+						tegra210_usb3_map, "usb3-ss");
+	else
+		return NULL;
 }
 
 static const struct tegra_xusb_port_ops tegra210_usb3_port_ops = {

drivers/phy/tegra/xusb.h

@@ -244,6 +244,7 @@ struct tegra_xusb_pcie_pad {
 
 	struct reset_control *rst;
 	struct clk *pll;
+	struct clk *uphy_mgmt_clk;
 
 	bool enable;
 };

drivers/usb/host/xhci-tegra.c

@@ -2543,27 +2543,34 @@ static const struct tegra_xusb_soc tegra210_soc = {
 };
 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
 
+static const struct tegra_xusb_phy_type tegra210b01_phy_types[] = {
+	{ .name = "usb3", .num = 4, },
+	{ .name = "usb2", .num = 4, },
+};
+
 static const struct tegra_xusb_soc tegra210b01_soc = {
 	.firmware = "nvidia/tegra210b01/xusb.bin",
 	.supply_names = tegra210_supply_names,
 	.num_supplies = ARRAY_SIZE(tegra210_supply_names),
-	.phy_types = tegra210_phy_types,
-	.num_types = ARRAY_SIZE(tegra210_phy_types),
+	.phy_types = tegra210b01_phy_types,
+	.num_types = ARRAY_SIZE(tegra210b01_phy_types),
 	.context = &tegra124_xusb_context,
 	.ports = {
 		.usb2 = { .offset = 4, .count = 4, },
-		.hsic = { .offset = 8, .count = 1, },
 		.usb3 = { .offset = 0, .count = 4, },
 	},
 	.scale_ss_clock = false,
 	.has_ipfs = true,
 	.otg_reset_sspi = true,
+	.ops = &tegra124_ops,
 	.mbox = {
 		.cmd = 0xe4,
 		.data_in = 0xe8,
 		.data_out = 0xec,
 		.owner = 0xf0,
+		.smi_intr = XUSB_CFG_ARU_SMI_INTR,
 	},
+	.lpm_support = false,
 };
 MODULE_FIRMWARE("nvidia/tegra210b01/xusb.bin");
 

include/linux/clk/tegra.h

@@ -208,9 +208,13 @@ tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
 
 #ifdef CONFIG_ARCH_TEGRA_210_SOC
 int tegra210_plle_hw_sequence_start(void);
+int tegra210b01_plle_hw_sequence_start(void);
 bool tegra210_plle_hw_sequence_is_enabled(void);
+bool tegra210b01_plle_hw_sequence_is_enabled(void);
 void tegra210_xusb_pll_hw_control_enable(void);
+void tegra210b01_xusb_pll_hw_control_enable(void);
 void tegra210_xusb_pll_hw_sequence_start(void);
+void tegra210b01_xusb_pll_hw_sequence_start(void);
 void tegra210_sata_pll_hw_control_enable(void);
 void tegra210_sata_pll_hw_sequence_start(void);
 void tegra210_set_sata_pll_seq_sw(bool state);