clk: tegra210b01: add plle

- Add T210b01 soc data for xusb_padctl driver
- Add uphy_management clock support
- Add PLL defaults programming

Bug 200340262

Change-Id: Ie5a685a49542221142a0a8e31e5a9ebb729a3035
Signed-off-by: Rohith Seelaboyina <rseelaboyina@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1584421
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Rakesh Babu Bodla <rbodla@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

arch/arm64/boot/dts/nvidia/tegra210b01.dtsi

@@ -4,10 +4,6 @@
 / {
 	compatible = "nvidia,tegra210b01", "nvidia,tegra210";
 
-	pcie@1003000 {
-		compatible = "nvidia,tegra210b01-pcie";
-	};
-
 	host1x@50000000 {
 		/delete-node/ sor@54540000;
 		/delete-node/ dpaux@545c0000;
@@ -38,12 +34,8 @@
 	};
 
 	mc: memory-controller@70019000 {
-		#address-cells = <2>;
-		#size-cells = <2>;
-
 		emc: external-memory-controller@7001b000 {
 			compatible = "nvidia,tegra210b01-emc";
-			status = "okay";
 			reg = <0x0 0x7001b000 0x0 0x1000>,
 			      <0x0 0x7001e000 0x0 0x1000>,
 			      <0x0 0x7001f000 0x0 0x1000>;
@@ -61,7 +53,6 @@
 	/delete-node/ external-memory-controller@7001b000;
 
 	actmon@6000c800 {
-		status = "disabled";
 		clocks = <&tegra_car TEGRA210_CLK_ACTMON>,
 			 <&bpmp 0>;
 	};
@@ -128,14 +119,6 @@
 
 	padctl@7009f000 {
 		compatible = "nvidia,tegra210b01-xusb-padctl";
-
-		pads {
-			pcie {
-				clocks = <&tegra_car TEGRA210_CLK_PLL_E>,
-					 <&tegra_car TEGRA210_CLK_PLL_P_UPHY_OUT>;
-				clock-names = "pll", "uphy_mgmt";
-			};
-		};
 	};
 
 	pinmux@700008d4 {

drivers/memory/tegra/mc.c

@@ -526,10 +526,6 @@ int tegra30_mc_probe(struct tegra_mc *mc)
 		return err;
 	}
 
-	err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev);
-	if (err < 0)
-		return err;
-
 	return 0;
 }
 

drivers/pci/controller/pci-tegra.c

@@ -3003,6 +3003,7 @@ static int tegra_pcie_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct pci_host_bridge *host;
+	struct tegra_pcie_port *port;
 	struct tegra_pcie *pcie;
 	int err;
 

drivers/phy/tegra/xusb-tegra210.c

@@ -489,32 +489,6 @@ static int t210b01_compatible(struct tegra_xusb_padctl *padctl)
 	return 0;
 }
 
-static bool plle_hw_sequence_is_enabled(struct tegra_xusb_padctl *padctl) {
-	if (t210b01_compatible(padctl))
-		return tegra210b01_plle_hw_sequence_is_enabled();
-	return tegra210_plle_hw_sequence_is_enabled();
-}
-
-static int plle_hw_sequence_start(struct tegra_xusb_padctl *padctl) {
-	if (t210b01_compatible(padctl))
-		return tegra210b01_plle_hw_sequence_start();
-	return tegra210_plle_hw_sequence_start();
-}
-
-static void xusb_pll_hw_control_enable(struct tegra_xusb_padctl *padctl) {
-	if (t210b01_compatible(padctl))
-		tegra210b01_xusb_pll_hw_control_enable();
-	else
-		return tegra210_xusb_pll_hw_control_enable();
-}
-
-static void xusb_pll_hw_sequence_start(struct tegra_xusb_padctl *padctl) {
-	if (t210b01_compatible(padctl))
-		tegra210b01_xusb_pll_hw_sequence_start();
-	else
-		tegra210_xusb_pll_hw_sequence_start();
-}
-
 static int tegra210_usb3_lane_map(struct tegra_xusb_lane *lane)
 {
 	const struct tegra_xusb_lane_map *map;
@@ -555,7 +529,7 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
 			return err;
 	}
 
-	if (plle_hw_sequence_is_enabled(padctl))
+	if (tegra210_plle_hw_sequence_is_enabled())
 		goto skip_pll_init;
 
 	err = reset_control_deassert(pcie->rst);
@@ -734,7 +708,7 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
 	value &= ~XUSB_PADCTL_UPHY_PLL_CTL8_RCAL_CLK_EN;
 	padctl_writel(padctl, value, XUSB_PADCTL_UPHY_PLL_P0_CTL8);
 
-	xusb_pll_hw_control_enable(padctl);
+	tegra210_xusb_pll_hw_control_enable();
 
 	value = padctl_readl(padctl, XUSB_PADCTL_UPHY_PLL_P0_CTL1);
 	value &= ~XUSB_PADCTL_UPHY_PLL_CTL1_PWR_OVRD;
@@ -750,7 +724,7 @@ static int tegra210_pex_uphy_enable(struct tegra_xusb_padctl *padctl)
 
 	usleep_range(10, 20);
 
-	xusb_pll_hw_sequence_start(padctl);
+	tegra210_xusb_pll_hw_sequence_start();
 
 skip_pll_init:
 	pcie->enable = true;
@@ -1103,8 +1077,8 @@ static int tegra210_uphy_init(struct tegra_xusb_padctl *padctl)
 	if (padctl->sata)
 		tegra210_sata_uphy_enable(padctl);
 
-	if (!plle_hw_sequence_is_enabled(padctl))
-		plle_hw_sequence_start(padctl);
+	if (!tegra210_plle_hw_sequence_is_enabled())
+		tegra210_plle_hw_sequence_start();
 	else
 		dev_dbg(padctl->dev, "PLLE is already in HW control\n");
 
@@ -3400,6 +3374,14 @@ static const char * const tegra210_xusb_padctl_supply_names[] = {
 	"hvdd-pex-pll-e",
 };
 
+static const char * const tegra210b01_supply_names[] = {
+	"avdd_pll_uerefe",
+	"hvdd_pex_pll_e",
+	"dvdd_pex_pll",
+	"hvddio_pex",
+	"dvddio_pex",
+};
+
 const struct tegra_xusb_padctl_soc tegra210_xusb_padctl_soc = {
 	.num_pads = ARRAY_SIZE(tegra210_pads),
 	.pads = tegra210_pads,
@@ -3438,8 +3420,8 @@ const struct tegra_xusb_padctl_soc tegra210b01_xusb_padctl_soc = {
 		},
 	},
 	.ops = &tegra210_xusb_padctl_ops,
-	.supply_names = tegra210_xusb_padctl_supply_names,
-	.num_supplies = ARRAY_SIZE(tegra210_xusb_padctl_supply_names),
+	.supply_names = tegra210b01_supply_names,
+	.num_supplies = ARRAY_SIZE(tegra210b01_supply_names),
 	.need_fake_usb3_port = true,
 };
 EXPORT_SYMBOL_GPL(tegra210b01_xusb_padctl_soc);

drivers/phy/tegra/xusb.c

@@ -564,6 +564,7 @@ static int tegra_xusb_port_init(struct tegra_xusb_port *port,
 	if (err < 0)
 		goto put_device;
 
+	printk("init done!\n");
 	return 0;
 
 put_device:
@@ -799,24 +800,31 @@ static int tegra_xusb_add_usb2_port(struct tegra_xusb_padctl *padctl,
 	struct device_node *np;
 	int err = 0;
 
+	printk("adding usb2 port");
+
 	/*
 	 * USB2 ports don't require additional properties, but if the port is
 	 * marked as disabled there is no reason to register it.
 	 */
+	printk("find port node");
 	np = tegra_xusb_find_port_node(padctl, "usb2", index);
 	if (!np || !of_device_is_available(np))
 		goto out;
 
+	printk("kzalloc");
 	usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
 	if (!usb2) {
 		err = -ENOMEM;
 		goto out;
 	}
 
+	printk("init usb2 xusb port");
 	err = tegra_xusb_port_init(&usb2->base, padctl, np, "usb2", index);
 	if (err < 0)
 		goto out;
 
+	printk("set usb2 ops");
+
 	usb2->base.ops = padctl->soc->ports.usb2.ops;
 
 	usb2->base.lane = usb2->base.ops->map(&usb2->base);
@@ -880,6 +888,8 @@ static int tegra_xusb_add_ulpi_port(struct tegra_xusb_padctl *padctl,
 		goto out;
 	}
 
+	printk("init ulpi xusb port");
+
 	err = tegra_xusb_port_init(&ulpi->base, padctl, np, "ulpi", index);
 	if (err < 0)
 		goto out;
@@ -926,6 +936,7 @@ static int tegra_xusb_add_hsic_port(struct tegra_xusb_padctl *padctl,
 	struct device_node *np;
 	int err = 0;
 
+	printk("find hsic port node");
 	np = tegra_xusb_find_port_node(padctl, "hsic", index);
 	if (!np || !of_device_is_available(np))
 		goto out;
@@ -936,10 +947,13 @@ static int tegra_xusb_add_hsic_port(struct tegra_xusb_padctl *padctl,
 		goto out;
 	}
 
+	printk("init hsic xusb port");
+
 	err = tegra_xusb_port_init(&hsic->base, padctl, np, "hsic", index);
 	if (err < 0)
 		goto out;
 
+	printk("setting hsic ops");
 	hsic->base.ops = padctl->soc->ports.hsic.ops;
 
 	hsic->base.lane = hsic->base.ops->map(&hsic->base);
@@ -1028,10 +1042,14 @@ static int tegra_xusb_add_usb3_port(struct tegra_xusb_padctl *padctl,
 	if (err < 0)
 		goto out;
 
+	printk("xusb port inited. setting ops");
 	usb3->base.ops = padctl->soc->ports.usb3.ops;
 
+	printk("set lane");
+
 	usb3->base.lane = usb3->base.ops->map(&usb3->base);
 	if (IS_ERR(usb3->base.lane)) {
+		printk("usb3 lane is error!");
 		err = PTR_ERR(usb3->base.lane);
 		goto out;
 	}

drivers/phy/tegra/xusb.h

@@ -244,7 +244,6 @@ struct tegra_xusb_pcie_pad {
 
 	struct reset_control *rst;
 	struct clk *pll;
-	struct clk *uphy_mgmt_clk;
 
 	bool enable;
 };

drivers/usb/host/xhci-tegra.c

@@ -2546,34 +2546,27 @@ static const struct tegra_xusb_soc tegra210_soc = {
 };
 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
 
-static const struct tegra_xusb_phy_type tegra210b01_phy_types[] = {
-	{ .name = "usb3", .num = 4, },
-	{ .name = "usb2", .num = 4, },
-};
-
 static const struct tegra_xusb_soc tegra210b01_soc = {
 	.firmware = "nvidia/tegra210b01/xusb.bin",
 	.supply_names = tegra210_supply_names,
 	.num_supplies = ARRAY_SIZE(tegra210_supply_names),
-	.phy_types = tegra210b01_phy_types,
-	.num_types = ARRAY_SIZE(tegra210b01_phy_types),
+	.phy_types = tegra210_phy_types,
+	.num_types = ARRAY_SIZE(tegra210_phy_types),
 	.context = &tegra124_xusb_context,
 	.ports = {
 		.usb2 = { .offset = 4, .count = 4, },
+		.hsic = { .offset = 8, .count = 1, },
 		.usb3 = { .offset = 0, .count = 4, },
 	},
 	.scale_ss_clock = false,
 	.has_ipfs = true,
 	.otg_reset_sspi = true,
-	.ops = &tegra124_ops,
 	.mbox = {
 		.cmd = 0xe4,
 		.data_in = 0xe8,
 		.data_out = 0xec,
 		.owner = 0xf0,
-		.smi_intr = XUSB_CFG_ARU_SMI_INTR,
 	},
-	.lpm_support = false,
 };
 MODULE_FIRMWARE("nvidia/tegra210b01/xusb.bin");
 

gki/aarch64/abi.stg

@@ -487077,15 +487077,6 @@ elf_symbol {
   type_id: 0x578fa618
   full_name: "pci_find_next_capability"
 }
-elf_symbol {
-  id: 0xbbf8a63b
-  name: "pci_flags"
-  is_defined: true
-  symbol_type: OBJECT
-  crc: 0xf296206e
-  type_id: 0x4585663f
-  full_name: "pci_flags"
-}
 elf_symbol {
   id: 0x08190210
   name: "pci_free_irq"
@@ -504846,42 +504837,6 @@ elf_symbol {
   type_id: 0x10985193
   full_name: "tegra210_xusb_pll_hw_sequence_start"
 }
-elf_symbol {
-  id: 0xd2118b04
-  name: "tegra210b01_plle_hw_sequence_is_enabled"
-  is_defined: true
-  symbol_type: FUNCTION
-  crc: 0x5e505530
-  type_id: 0xfea45b04
-  full_name: "tegra210b01_plle_hw_sequence_is_enabled"
-}
-elf_symbol {
-  id: 0x56591275
-  name: "tegra210b01_plle_hw_sequence_start"
-  is_defined: true
-  symbol_type: FUNCTION
-  crc: 0x7851be11
-  type_id: 0x9d80e32f
-  full_name: "tegra210b01_plle_hw_sequence_start"
-}
-elf_symbol {
-  id: 0xa6a8ece8
-  name: "tegra210b01_xusb_pll_hw_control_enable"
-  is_defined: true
-  symbol_type: FUNCTION
-  crc: 0xd272d446
-  type_id: 0x10985193
-  full_name: "tegra210b01_xusb_pll_hw_control_enable"
-}
-elf_symbol {
-  id: 0xc1ac282e
-  name: "tegra210b01_xusb_pll_hw_sequence_start"
-  is_defined: true
-  symbol_type: FUNCTION
-  crc: 0xd272d446
-  type_id: 0x10985193
-  full_name: "tegra210b01_xusb_pll_hw_sequence_start"
-}
 elf_symbol {
   id: 0xe54ea1f3
   name: "tegra_bpmp_free_mrq"
@@ -522147,7 +522102,6 @@ interface {
   symbol_id: 0x780d1110
   symbol_id: 0xbbb674cc
   symbol_id: 0xdea420f5
-  symbol_id: 0xbbf8a63b
   symbol_id: 0x08190210
   symbol_id: 0x8ffabaa9
   symbol_id: 0x50bce06e
@@ -524121,10 +524075,6 @@ interface {
   symbol_id: 0xdfb56896
   symbol_id: 0x72c26996
   symbol_id: 0x7ac45534
-  symbol_id: 0xd2118b04
-  symbol_id: 0x56591275
-  symbol_id: 0xa6a8ece8
-  symbol_id: 0xc1ac282e
   symbol_id: 0xe54ea1f3
   symbol_id: 0x4a1dceb2
   symbol_id: 0xa2565005

gki/aarch64/symbols/tegra

@@ -2070,7 +2070,6 @@
   irq_set_chained_handler_and_data
   of_irq_parse_and_map_pci
   of_pci_get_devfn
-  pci_flags
   pci_generic_config_read32
   pci_generic_config_write32
   pci_host_probe
@@ -2126,10 +2125,6 @@
   phy_destroy
   regulator_get
   regulator_put
-  tegra210b01_plle_hw_sequence_is_enabled
-  tegra210b01_plle_hw_sequence_start
-  tegra210b01_xusb_pll_hw_control_enable
-  tegra210b01_xusb_pll_hw_sequence_start
   tegra210_plle_hw_sequence_is_enabled
   tegra210_plle_hw_sequence_start
   tegra210_sata_pll_hw_control_enable

include/linux/clk/tegra.h

@@ -208,13 +208,9 @@ tegra124_clk_set_emc_callbacks(tegra124_emc_prepare_timing_change_cb *prep_cb,
 
 #ifdef CONFIG_ARCH_TEGRA_210_SOC
 int tegra210_plle_hw_sequence_start(void);
-int tegra210b01_plle_hw_sequence_start(void);
 bool tegra210_plle_hw_sequence_is_enabled(void);
-bool tegra210b01_plle_hw_sequence_is_enabled(void);
 void tegra210_xusb_pll_hw_control_enable(void);
-void tegra210b01_xusb_pll_hw_control_enable(void);
 void tegra210_xusb_pll_hw_sequence_start(void);
-void tegra210b01_xusb_pll_hw_sequence_start(void);
 void tegra210_sata_pll_hw_control_enable(void);
 void tegra210_sata_pll_hw_sequence_start(void);
 void tegra210_set_sata_pll_seq_sw(bool state);