clk: tegra: dfll: fix use of tune values

There was some confusion on the use of the tune values. They were
defined in 2 different structs, but only initialzed in one of them.
Remove most of the references in struct tegra_dfll_soc_data and adjust
the code accordingly. Only tune_high_min_millivolts is left, because
this can be adjusted using debugfs. Hence copy the initial value from
the cvb table at boot.

drivers/clk/tegra/clk-dfll.c

@@ -1948,7 +1948,7 @@ static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max)
 	int i;
 	unsigned long rate, reg_volt;
 	u8 lut_bottom = MAX_DFLL_VOLTAGES;
-	int v_min = td->soc->cvb->min_millivolts * 1000;
+	int v_min = td->soc->min_millivolts * 1000;
 
 	for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {
 		reg_volt = td->lut_uv[i];
@@ -1968,7 +1968,7 @@ static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max)
 	if ((lut_bottom == MAX_DFLL_VOLTAGES) ||
 	    (lut_bottom + 1 >= td->lut_size)) {
 		dev_err(td->dev, "no voltage above DFLL minimum %d mV\n",
-			td->soc->cvb->min_millivolts);
+			td->soc->min_millivolts);
 		return -EINVAL;
 	}
 	td->lut_bottom = lut_bottom;
@@ -1977,7 +1977,7 @@ static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max)
 	rate = get_dvco_rate_below(td, td->lut_bottom);
 	if (!rate) {
 		dev_err(td->dev, "no opp below DFLL minimum voltage %d mV\n",
-			td->soc->cvb->min_millivolts);
+			td->soc->min_millivolts);
 		return -EINVAL;
 	}
 	td->dvco_rate_min = rate;
@@ -2000,17 +2000,20 @@ static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max)
  */
 static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max)
 {
-	unsigned long rate, v, v_opp;
+	unsigned long rate, v, v_opp, v_min_align;
 	int ret = -EINVAL;
 	int j, selector, lut;
 
-	v = td->soc->cvb->min_millivolts * 1000;
+	v = td->soc->min_millivolts * 1000;
 	lut = find_vdd_map_entry_exact(td, v);
 	if (lut < 0)
 		goto out;
 	td->lut[0] = lut;
 	td->lut_bottom = 0;
 
+	v_min_align = DIV_ROUND_UP(td->soc->min_millivolts * 1000,
+		td->soc->alignment.step_uv) * td->soc->alignment.step_uv;
+
 	for (j = 1, rate = 0; ; rate++) {
 		struct dev_pm_opp *opp;
 
@@ -2019,7 +2022,7 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max)
 			break;
 		v_opp = dev_pm_opp_get_voltage(opp);
 
-		if (v_opp <= td->soc->cvb->min_millivolts * 1000)
+		if (v_opp <= v_min_align)
 			td->dvco_rate_min = dev_pm_opp_get_freq(opp);
 
 		dev_pm_opp_put(opp);
@@ -2050,7 +2053,7 @@ static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max)
 
 	if (!td->dvco_rate_min)
 		dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n",
-			td->soc->cvb->min_millivolts);
+			td->soc->min_millivolts);
 	else {
 		ret = 0;
 		for (j = 0; j < td->lut_size; j++)

drivers/clk/tegra/clk-tegra124-dfll-fcpu.c

@@ -864,6 +864,9 @@ static int tegra124_dfll_fcpu_probe(struct platform_device *pdev)
 		return PTR_ERR(soc->cvb);
 	}
 
+	soc->tune_high_min_millivolts =
+			soc->cvb->cpu_dfll_data.tune_high_min_millivolts;
+
 	err = tegra_dfll_register(pdev, soc);
 	if (err < 0) {
 		tegra_cvb_remove_opp_table(soc->dev, soc->cvb, soc->max_freq);

drivers/soc/tegra/fuse/fuse-tegra.c

@@ -122,8 +122,9 @@ static void tegra_fuse_print_sku_info(struct tegra_sku_info *tegra_sku_info)
 		tegra_revision_name[tegra_sku_info->revision],
 		tegra_sku_info->sku_id, tegra_sku_info->cpu_process_id,
 		tegra_sku_info->soc_process_id);
-	pr_debug("Tegra CPU Speedo ID %d, SoC Speedo ID %d\n",
-		tegra_sku_info->cpu_speedo_id, tegra_sku_info->soc_speedo_id);
+	pr_info("Tegra CPU Speedo ID %d, SoC Speedo ID %d, GPU Speedo ID %d\n",
+		tegra_sku_info->cpu_speedo_id, tegra_sku_info->soc_speedo_id,
+		tegra_sku_info->gpu_speedo_id);
 }
 
 static int tegra_fuse_add_lookups(struct tegra_fuse *fuse)