t210b01: disable actmon and interconnects

Signed-off-by: Thomas Makin <halorocker89@gmail.com>

arch/arm64/boot/dts/nvidia/tegra210b01.dtsi

@@ -7,13 +7,19 @@
 	host1x@50000000 {
 		/delete-node/ sor@54540000;
 		/delete-node/ dpaux@545c0000;
+		/delete-node/ vi@54080000;
+		/delete-node/ i2c@546c0000;
 
 		dc@54200000 {
 			nvidia,outputs = <&dsia &dsib &sor1>;
+			/delete-property/ interconnects;
+			/delete-property/ interconnect-names;
 		};
 
 		dc@54240000 {
 			nvidia,outputs = <&dsia &dsib &sor1>;
+			/delete-property/ interconnects;
+			/delete-property/ interconnect-names;
 		};
 	};
 
@@ -27,12 +33,80 @@
 		/delete-property/ pinctrl-names;
 	};
 
+	emc: external-memory-controller@7001b000 {
+		compatible = "nvidia,tegra210b01-emc";
+
+		clocks = <&bpmp 0>;
+		clock-names = "emc";
+
+		nvidia,bpmp = <&bpmp>;
+		/delete-property/ operating-points-v2;
+	};
+
+	actmon@6000c800 {
+		// clocks = <&tegra_car TEGRA210_CLK_ACTMON>,
+		// 	 <&bpmp 0>;
+		status = "disabled";
+	};
+
+	mmc@700b0600 {
+		nvidia,default-tap = <9>;
+		nvidia,default-trim = <13>;
+
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+
+		assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+			 <&tegra_car TEGRA210_CLK_PLL_C4_OUT2>;
+		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT2>;
+	};
+
+	mmc@700b0400 {
+		nvidia,default-tap = <11>;
+		nvidia,default-trim = <18>;
+
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
+			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+	};
+
+	mmc@700b0200 {
+		nvidia,default-tap = <8>;
+		nvidia,default-trim = <13>;
+
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
+			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+	};
+
+	mmc@700b0000 {
+		nvidia,default-tap = <11>;
+		nvidia,default-trim = <14>;
+
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
+			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+
+		assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+				  <&tegra_car TEGRA210_CLK_PLL_C4_OUT2>,
+				  <&tegra_car TEGRA210_CLK_PLL_C4>;
+		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT2>;
+	};
+
+	pcie@1003000 {
+		compatible = "nvidia,tegra210b01-pcie";
+	};
+
+	/* Tegra210B01 has MBIST patched and is missing VI unit */
 	pmc@7000e400 {
 		compatible = "nvidia,tegra210b01-pmc";
+
+		powergates {
+			/delete-node/ venc;
+		};
 	};
 
 	bpmp@70016000 {
 		status = "okay";
+
+		#clock-cells = <1>;
 	};
 
 	usb@70090000 {
@@ -43,6 +117,41 @@
 		compatible = "nvidia,tegra210b01-xusb-padctl";
 	};
 
+	pinmux@700008d4 {
+		status = "okay";
+		sdmmc1_drv_code_1_8V: sdmmc1_drv_code {
+			sdmmc1 {
+				nvidia,pins = "drive_sdmmc1";
+				nvidia,pull-down-strength = <8>;
+				nvidia,pull-up-strength = <8>;
+			};
+		};
+
+		sdmmc1_default_drv_code_3_3V: sdmmc1_default_drv_code {
+			sdmmc1 {
+				nvidia,pins = "drive_sdmmc1";
+				nvidia,pull-down-strength = <8>;
+				nvidia,pull-up-strength = <8>;
+			};
+		};
+
+		sdmmc3_drv_code_1_8V: sdmmc3_drv_code {
+			sdmmc3 {
+				nvidia,pins = "drive_sdmmc3";
+				nvidia,pull-down-strength = <8>;
+				nvidia,pull-up-strength = <8>;
+			};
+		};
+
+		sdmmc3_default_drv_code_3_3V: sdmmc3_default_drv_code {
+			sdmmc3 {
+				nvidia,pins = "drive_sdmmc3";
+				nvidia,pull-down-strength = <8>;
+				nvidia,pull-up-strength = <8>;
+			};
+		};
+	};
+
 	usb@700d0000 {
 		compatible = "nvidia,tegra210b01-xudc";
 	};

drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h

@@ -134,5 +134,6 @@ int gf100_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct
 int gk104_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
 int gk20a_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
 int gm20b_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
+int gm20b_b01_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
 int gp10b_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
 #endif

drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h

@@ -42,4 +42,5 @@ int gf117_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct
 int gk104_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
 int gk20a_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
 int gm20b_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
+int gm20b_b01_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
 #endif

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

@@ -2072,6 +2072,31 @@ nv12b_chipset = {
 	.sw       = { 0x00000001, gf100_sw_new },
 };
 
+static const struct nvkm_device_chip
+nv12e_chipset = {
+	.name = "GM20B",
+	.acr      = { 0x00000001, gm20b_acr_new },
+	.bar      = { 0x00000001, gm20b_bar_new },
+	.bus      = { 0x00000001, gf100_bus_new },
+	.clk      = { 0x00000001, gm20b_b01_clk_new },
+	.fb       = { 0x00000001, gm20b_fb_new },
+	.fuse     = { 0x00000001, gm107_fuse_new },
+	.imem     = { 0x00000001, gk20a_instmem_new },
+	.ltc      = { 0x00000001, gm200_ltc_new },
+	.mc       = { 0x00000001, gk20a_mc_new },
+	.mmu      = { 0x00000001, gm20b_mmu_new },
+	.pmu      = { 0x00000001, gm20b_pmu_new },
+	.privring = { 0x00000001, gk20a_privring_new },
+	.timer    = { 0x00000001, gk20a_timer_new },
+	.top      = { 0x00000001, gk104_top_new },
+	.volt     = { 0x00000001, gm20b_b01_volt_new },
+	.ce       = { 0x00000004, gm200_ce_new },
+	.dma      = { 0x00000001, gf119_dma_new },
+	.fifo     = { 0x00000001, gm200_fifo_new },
+	.gr       = { 0x00000001, gm20b_gr_new },
+	.sw       = { 0x00000001, gf100_sw_new },
+};
+
 static const struct nvkm_device_chip
 nv130_chipset = {
 	.name = "GP100",
@@ -3225,6 +3250,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
 	case 0x124: device->chip = &nv124_chipset; break;
 	case 0x126: device->chip = &nv126_chipset; break;
 	case 0x12b: device->chip = &nv12b_chipset; break;
+	case 0x12e: device->chip = &nv12e_chipset; break;
 	case 0x130: device->chip = &nv130_chipset; break;
 	case 0x132: device->chip = &nv132_chipset; break;
 	case 0x134: device->chip = &nv134_chipset; break;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c

@@ -717,6 +717,112 @@ gm20b_pstates[] = {
 	},
 };
 
+static struct nvkm_pstate
+gm20b_b01_pstates[] = {
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 76800,
+			.voltage = 0,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 153600,
+			.voltage = 1,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 230400,
+			.voltage = 2,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 307200,
+			.voltage = 3,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 384000,
+			.voltage = 4,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 460800,
+			.voltage = 5,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 537600,
+			.voltage = 6,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 614400,
+			.voltage = 7,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 691200,
+			.voltage = 8,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 768000,
+			.voltage = 9,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 844800,
+			.voltage = 10,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 921600,
+			.voltage = 11,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 998400,
+			.voltage = 12,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 1075200,
+			.voltage = 13,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 1152000,
+			.voltage = 14,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 1228800,
+			.voltage = 15,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 1267200,
+			.voltage = 16,
+		},
+	},
+};
+
 static void
 gm20b_clk_fini(struct nvkm_clk *base)
 {
@@ -912,6 +1018,41 @@ gm20b_clk = {
 	},
 };
 
+static const struct nvkm_clk_func
+gm20b_b01_clk = {
+	.init = gm20b_clk_init,
+	.fini = gk20a_clk_fini,
+	.read = gk20a_clk_read,
+	.calc = gk20a_clk_calc,
+	.prog = gk20a_clk_prog,
+	.tidy = gk20a_clk_tidy,
+	.pstates = gm20b_b01_pstates,
+	.nr_pstates = ARRAY_SIZE(gm20b_b01_pstates),
+	.domains = {
+		{ nv_clk_src_crystal, 0xff },
+		{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
+		{ nv_clk_src_max },
+	},
+};
+
+static const struct nvkm_clk_func
+gm20b_b01_hiopt_clk_speedo = {
+	.init = gm20b_clk_init,
+	.fini = gk20a_clk_fini,
+	.read = gk20a_clk_read,
+	.calc = gk20a_clk_calc,
+	.prog = gk20a_clk_prog,
+	.tidy = gk20a_clk_tidy,
+	.pstates = gm20b_pstates,
+	/* HIOPT speedo only supports 16 voltages */
+	.nr_pstates = ARRAY_SIZE(gm20b_pstates) - 1,
+	.domains = {
+		{ nv_clk_src_crystal, 0xff },
+		{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
+		{ nv_clk_src_max },
+	},
+};
+
 static int
 gm20b_clk_new_speedo0(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
 		      struct nvkm_clk **pclk)
@@ -930,6 +1071,24 @@ gm20b_clk_new_speedo0(struct nvkm_device *device, enum nvkm_subdev_type type, in
 	return ret;
 }
 
+static int
+gm20b_b01_clk_new_hiopt(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+		      struct nvkm_clk **pclk)
+{
+	struct gk20a_clk *clk;
+	int ret;
+
+	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+	if (!clk)
+		return -ENOMEM;
+	*pclk = &clk->base;
+
+	ret = gk20a_clk_ctor(device, type, inst, &gm20b_b01_hiopt_clk_speedo, &gm20b_pllg_params, clk);
+	clk->pl_to_div = pl_to_div;
+	clk->div_to_pl = div_to_pl;
+	return ret;
+}
+
 /* FUSE register */
 #define FUSE_RESERVED_CALIB0	0x204
 #define FUSE_RESERVED_CALIB0_INTERCEPT_FRAC_SHIFT	0
@@ -1074,3 +1233,63 @@ gm20b_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
 
 	return 0;
 }
+
+int
+gm20b_b01_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	      struct nvkm_clk **pclk)
+{
+	struct nvkm_device_tegra *tdev = device->func->tegra(device);
+	struct gm20b_clk *clk;
+	struct nvkm_subdev *subdev;
+	struct gk20a_clk_pllg_params *clk_params;
+	int ret;
+
+	/* Speedo 0 GPUs cannot use noise-aware PLL */
+	if (tdev->gpu_speedo_id == 0)
+		return gm20b_b01_clk_new_hiopt(device, type, inst, pclk);
+
+	/* Speedo >= 1, use NAPLL */
+	clk = kzalloc(sizeof(*clk) + sizeof(*clk_params), GFP_KERNEL);
+	if (!clk)
+		return -ENOMEM;
+	*pclk = &clk->base.base;
+	subdev = &clk->base.base.subdev;
+
+	/* duplicate the clock parameters since we will patch them below */
+	clk_params = (void *) (clk + 1);
+	*clk_params = gm20b_pllg_params;
+	ret = gk20a_clk_ctor(device, type, inst, &gm20b_b01_clk, clk_params, &clk->base);
+	if (ret)
+		return ret;
+
+	/*
+	 * NAPLL can only work with max_u, clamp the m range so
+	 * gk20a_pllg_calc_mnp always uses it
+	 */
+	clk_params->max_m = clk_params->min_m = DIV_ROUND_UP(clk_params->max_u,
+						(clk->base.parent_rate / KHZ));
+	if (clk_params->max_m == 0) {
+		nvkm_warn(subdev, "cannot use NAPLL, using legacy clock...\n");
+		kfree(clk);
+		return gm20b_b01_clk_new_hiopt(device, type, inst, pclk);
+	}
+
+	clk->base.pl_to_div = pl_to_div;
+	clk->base.div_to_pl = div_to_pl;
+
+	clk->dvfs_params = &gm20b_dvfs_params;
+
+	ret = gm20b_clk_init_fused_params(clk);
+	/*
+	 * we will calibrate during init - should never happen on
+	 * prod parts
+	 */
+	if (ret)
+		nvkm_warn(subdev, "no fused calibration parameters\n");
+
+	ret = gm20b_clk_init_safe_fmax(clk);
+	if (ret)
+		return ret;
+
+	return 0;
+}

drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c

@@ -91,3 +91,99 @@ gm20b_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
 		return gk20a_volt_ctor(device, type, inst, gm20b_cvb_coef,
 				       ARRAY_SIZE(gm20b_cvb_coef), vmin, volt);
 }
+
+static const struct cvb_coef gm20b_b01_na_cvb_slt_coef[] = {
+	/* KHz,         c0,     c1,   c2,    c3,     c4,   c5 */
+	/* 76800 */   { 590000,        0,        0,        0,        0,        0 },
+	/* 153600 */  { 590000,        0,        0,        0,        0,        0 },
+	/* 230400 */  { 590000,        0,        0,        0,        0,        0 },
+	/* 307200 */  { 590000,        0,        0,        0,        0,        0 },
+	/* 384000 */  { 590000,        0,        0,        0,        0,        0 },
+	/* 460800 */  { 795089,   -11096,     -163,      298,   -10421,      162},
+	/* 537600 */  { 795089,   -11096,     -163,      298,   -10421,      162 },
+	/* 614400 */  { 820606,    -6285,     -452,      238,    -6182,       81 },
+	/* 691200 */  { 846289,    -4565,     -552,      119,    -3958,       -2 },
+	/* 768000 */  { 888720,    -5110,     -584,        0,    -2849,       39 },
+	/* 844800 */  { 936634,    -6089,     -602,      -60,      -99,      -93 },
+	/* 921600 */  { 982562,    -7373,     -614,     -179,     1797,      -13 },
+	/* 998400 */  { 1090179,   -14125,     -497,     -179,     3518,        9 },
+	/* 1075200 */ { 1155798,   -13465,     -648,        0,     1077,       40 },
+	/* 1152000 */ { 1198568,   -10904,     -830,        0,     1469,      110 },
+	/* 1228800 */ { 1269988,   -12707,     -859,        0,     3722,      313 },
+	/* 1267200 */ { 1308155,   -13694,     -867,        0,     3681,      559 },
+};
+
+static const struct cvb_coef gm20b_b01_na_cvb_coef[] = {
+	/* KHz,         c0,     c1,   c2,    c3,     c4,   c5 */
+	/* 76800 */   { 610000,        0,        0,        0,        0,        0 },
+	/* 153600 */  { 610000,        0,        0,        0,        0,        0 },
+	/* 230400 */  { 610000,        0,        0,        0,        0,        0 },
+	/* 307200 */  { 610000,        0,        0,        0,        0,        0 },
+	/* 384000 */  { 610000,        0,        0,        0,        0,        0 },
+	/* 460800 */  { 610000,        0,        0,        0,        0,        0 },
+	/* 537600 */  { 801688,   -10900,     -163,      298,   -10599,      162 },
+	/* 614400 */  { 824214,    -5743,     -452,      238,    -6325,       81 },
+	/* 691200 */  { 848830,    -3903,     -552,      119,    -4030,       -2 },
+	/* 768000 */  { 891575,    -4409,     -584,        0,    -2849,       39 },
+	/* 844800 */  { 940071,    -5367,     -602,      -60,      -63,      -93 },
+	/* 921600 */  { 986765,    -6637,     -614,     -179,     1905,      -13 },
+	/* 998400 */  { 1098475,   -13529,     -497,     -179,     3626,        9 },
+	/* 1075200 */ { 1163644,   -12688,     -648,        0,     1077,       40 },
+	/* 1152000 */ { 1204812,    -9908,     -830,        0,     1469,      110 },
+	/* 1228800 */ { 1277303,   -11675,     -859,        0,     3722,      313 },
+	/* 1267200 */ { 1335531,   -12567,     -867,        0,     3681,      559 },
+};
+
+static const struct cvb_coef gm20b_b01_na_cvb_hiopt_coef[] = {
+	/* KHz,         c0,     c1,   c2,    c3,     c4,   c5 */
+	/* 76800 */   {   590000,        0,        0,        0,        0,        0 },
+	/* 153600 */  {   590000,        0,        0,        0,        0,        0 },
+	/* 230400 */  {   590000,        0,        0,        0,        0,        0 },
+	/* 307200 */  {   590000,        0,        0,        0,        0,        0 },
+	/* 384000 */  {   590000,        0,        0,        0,        0,        0 },
+	/* 460800 */  {   590000,        0,        0,        0,        0,        0 },
+	/* 537600 */  {   590000,        0,        0,        0,        0,        0 },
+	/* 614400 */  {   590000,        0,        0,        0,        0,        0 },
+	/* 691200 */  {   838712,    -7304,     -552,     1785,   -56250,     -450 },
+	/* 768000 */  {   880210,    -7955,     -584,        0,   -42735,     8775 },
+	/* 844800 */  {   926398,    -8892,     -602,     -900,    -5760,   -20925 },
+	/* 921600 */  {   970060,   -10108,     -614,    -2685,    22620,    -2925 },
+	/* 998400 */  {  1065665,   -16075,     -497,    -2685,    48195,     2025 },
+	/* 1075200 */ {  1132576,   -16093,     -648,        0,    16155,     9000 },
+	/* 1152000 */ {  1180029,   -14534,     -830,        0,    22035,    24750 },
+	/* 1228800 */ {  1248293,   -16383,     -859,        0,    55830,    70425 },
+};
+
+int
+gm20b_b01_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	       struct nvkm_volt **pvolt)
+{
+	struct nvkm_device_tegra *tdev = device->func->tegra(device);
+	struct gk20a_volt *volt;
+	u32 vmin;
+
+	if (tdev->gpu_speedo_id >= ARRAY_SIZE(speedo_to_vmin)) {
+		nvdev_error(device, "unsupported speedo %d\n",
+			    tdev->gpu_speedo_id);
+		return -EINVAL;
+	}
+
+	volt = kzalloc(sizeof(*volt), GFP_KERNEL);
+	if (!volt)
+		return -ENOMEM;
+	*pvolt = &volt->base;
+
+	vmin = speedo_to_vmin[tdev->gpu_speedo_id];
+
+	switch (tdev->gpu_speedo_id) {
+		case 3: /* HIOPT table */
+			return gk20a_volt_ctor(device, type, inst, gm20b_b01_na_cvb_hiopt_coef,
+						ARRAY_SIZE(gm20b_b01_na_cvb_hiopt_coef), vmin, volt);
+		case 2: /* SLT table */
+			return gk20a_volt_ctor(device, type, inst, gm20b_b01_na_cvb_slt_coef,
+						ARRAY_SIZE(gm20b_b01_na_cvb_slt_coef), vmin, volt);
+		default:
+			return gk20a_volt_ctor(device, type, inst, gm20b_b01_na_cvb_coef,
+						ARRAY_SIZE(gm20b_b01_na_cvb_coef), vmin, volt);
+	}
+}

drivers/memory/tegra/tegra186-emc.c

@@ -516,6 +516,9 @@ static const struct of_device_id tegra186_emc_of_match[] = {
 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
 	{ .compatible = "nvidia,tegra186-emc" },
 #endif
+#if defined(CONFIG_ARCH_TEGRA_210_SOC)
+	{ .compatible = "nvidia,tegra210b01-emc" },
+#endif
 #if defined(CONFIG_ARCH_TEGRA_194_SOC)
 	{ .compatible = "nvidia,tegra194-emc" },
 #endif

drivers/pci/controller/pci-tegra.c

@@ -1846,6 +1846,15 @@ static void tegra_pcie_disable_interrupts(struct tegra_pcie *pcie)
 	afi_writel(pcie, value, AFI_INTR_MASK);
 }
 
+static void update_rp_lanes(struct tegra_pcie *pcie, u32 lanes)
+{
+	struct tegra_pcie_port *port = NULL;
+
+	list_for_each_entry(port, &pcie->ports, list)
+		port->lanes = (lanes >> (port->index << 3)) & 0xFF;
+
+}
+
 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
 				      u32 *xbar)
 {
@@ -1874,6 +1883,21 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
 				 "switching to default 2x1, 1x1, 1x1 "
 				 "configuration\n");
 			*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_211;
+			update_rp_lanes(pcie, 0x010102);
+			return 0;
+		}
+	} else if (of_device_is_compatible(np, "nvidia,tegra210b01-pcie")) {
+		switch (lanes) {
+		case 0x0104:
+			dev_info(pcie->dev, "4x1, 1x1 configuration\n");
+			*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
+			return 0;
+
+		default:
+			dev_info(pcie->dev, "wrong configuration updated in DT, "
+				"switching to default 4x1, 1x1 configuration\n");
+			*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
+			update_rp_lanes(pcie, 0x0104);
 			return 0;
 		}
 	} else if (of_device_is_compatible(np, "nvidia,tegra124-pcie") ||
@@ -1888,6 +1912,13 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
 			dev_info(dev, "2x1, 1x1 configuration\n");
 			*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
 			return 0;
+
+		default:
+			dev_info(pcie->dev, "wrong configuration updated in DT, "
+				"switching to default 4x1, 1x1 configuration\n");
+			*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
+			update_rp_lanes(pcie, 0x0104);
+			return 0;
 		}
 	} else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
 		switch (lanes) {
@@ -1905,6 +1936,14 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
 			dev_info(dev, "4x1, 1x2 configuration\n");
 			*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
 			return 0;
+
+		default:
+			dev_info(dev, "wrong configuration updated in DT, "
+				 "switching to default 4x1, 1x2 "
+				 "configuration\n");
+			*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
+			update_rp_lanes(pcie, 0x010104);
+			return 0;
 		}
 	} else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
 		switch (lanes) {
@@ -1917,6 +1956,14 @@ static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
 			dev_info(dev, "dual-mode configuration\n");
 			*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
 			return 0;
+
+		default:
+			dev_info(dev, "wrong configuration updated in DT, "
+				 "switching to default dual-mode "
+				 "configuration\n");
+			*xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
+			update_rp_lanes(pcie, 0x000202);
+			return 0;
 		}
 	}
 
@@ -2010,7 +2057,8 @@ static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
 		pcie->supplies[i++].supply = "hvdd-pex-pll";
 		pcie->supplies[i++].supply = "hvdd-pex";
 		pcie->supplies[i++].supply = "vddio-pexctl-aud";
-	} else if (of_device_is_compatible(np, "nvidia,tegra210-pcie")) {
+	} else if (of_device_is_compatible(np, "nvidia,tegra210-pcie") ||
+				of_device_is_compatible(np, "nvidia,tegra210b01-pcie")) {
 		pcie->num_supplies = 3;
 
 		pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
@@ -2490,6 +2538,40 @@ static const struct tegra_pcie_soc tegra210_pcie = {
 	},
 };
 
+static const struct tegra_pcie_soc tegra210b01_pcie = {
+	.num_ports = 2,
+	.ports = tegra20_pcie_ports,
+	.msi_base_shift = 8,
+	.pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
+	.tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
+	.pads_refclk_cfg0 = 0x90b890b8,
+	/* FC threshold is bit[25:18] */
+	.update_fc_threshold = 0x01800000,
+	.has_pex_clkreq_en = true,
+	.has_pex_bias_ctrl = true,
+	.has_intr_prsnt_sense = true,
+	.has_cml_clk = true,
+	.has_gen2 = true,
+	.force_pca_enable = true,
+	.program_uphy = true,
+	.program_deskew_time = true,
+	.update_fc_timer = true,
+	.has_cache_bars = false,
+	.ectl = {
+		.regs = {
+			.rp_ectl_2_r1 = 0x0000000f,
+			.rp_ectl_4_r1 = 0x00000067,
+			.rp_ectl_5_r1 = 0x55010000,
+			.rp_ectl_6_r1 = 0x00000001,
+			.rp_ectl_2_r2 = 0x0000008f,
+			.rp_ectl_4_r2 = 0x000000c7,
+			.rp_ectl_5_r2 = 0x55010000,
+			.rp_ectl_6_r2 = 0x00000001,
+		},
+		.enable = true,
+	},
+};
+
 static const struct tegra_pcie_port_soc tegra186_pcie_ports[] = {
 	{ .pme.turnoff_bit =  0, .pme.ack_bit =  5 },
 	{ .pme.turnoff_bit =  8, .pme.ack_bit = 10 },
@@ -2522,6 +2604,7 @@ static const struct tegra_pcie_soc tegra186_pcie = {
 static const struct of_device_id tegra_pcie_of_match[] = {
 	{ .compatible = "nvidia,tegra186-pcie", .data = &tegra186_pcie },
 	{ .compatible = "nvidia,tegra210-pcie", .data = &tegra210_pcie },
+	{ .compatible = "nvidia,tegra210b01-pcie", .data = &tegra210b01_pcie },
 	{ .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie },
 	{ .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie },
 	{ .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie },

drivers/phy/tegra/xusb.c

@@ -525,6 +525,8 @@ static void tegra_xusb_port_release(struct device *dev)
 {
 	struct tegra_xusb_port *port = to_tegra_xusb_port(dev);
 
+	printk("release\n");
+
 	if (port->ops->release)
 		port->ops->release(port);
 }
@@ -541,19 +543,23 @@ static int tegra_xusb_port_init(struct tegra_xusb_port *port,
 {
 	int err;
 
+	printk("init list\n");
 	INIT_LIST_HEAD(&port->list);
 	port->padctl = padctl;
 	port->index = index;
 
+	printk("init device\n");
 	device_initialize(&port->dev);
 	port->dev.type = &tegra_xusb_port_type;
 	port->dev.of_node = of_node_get(np);
 	port->dev.parent = padctl->dev;
 
+	printk("set name\n");
 	err = dev_set_name(&port->dev, "%s-%u", name, index);
 	if (err < 0)
 		goto put_device;
 
+	printk("device add\n");
 	err = device_add(&port->dev);
 	if (err < 0)
 		goto put_device;
@@ -561,6 +567,7 @@ static int tegra_xusb_port_init(struct tegra_xusb_port *port,
 	return 0;
 
 put_device:
+	printk("put device\n");
 	put_device(&port->dev);
 	return err;
 }
@@ -969,6 +976,7 @@ static int tegra_xusb_usb3_port_parse_dt(struct tegra_xusb_usb3_port *usb3)
 	u32 value;
 	int err;
 
+	printk("check usb2-companion\n");
 	err = of_property_read_u32(np, "nvidia,usb2-companion", &value);
 	if (err < 0) {
 		dev_err(&port->dev, "failed to read port: %d\n", err);
@@ -1004,6 +1012,7 @@ static int tegra_xusb_add_usb3_port(struct tegra_xusb_padctl *padctl,
 	 * port is unusable. But it is valid to configure only a single port,
 	 * hence return 0 instead of an error to allow ports to be optional.
 	 */
+	printk("find port node usb3\n");
 	np = tegra_xusb_find_port_node(padctl, "usb3", index);
 	if (!np || !of_device_is_available(np))
 		goto out;
@@ -1014,6 +1023,7 @@ static int tegra_xusb_add_usb3_port(struct tegra_xusb_padctl *padctl,
 		goto out;
 	}
 
+	printk("xusb port init\n");
 	err = tegra_xusb_port_init(&usb3->base, padctl, np, "usb3", index);
 	if (err < 0)
 		goto out;
@@ -1026,6 +1036,7 @@ static int tegra_xusb_add_usb3_port(struct tegra_xusb_padctl *padctl,
 		goto out;
 	}
 
+	printk("xusb usb3 port parse dt\n");
 	err = tegra_xusb_usb3_port_parse_dt(usb3);
 	if (err < 0) {
 		tegra_xusb_port_unregister(&usb3->base);
@@ -1118,24 +1129,28 @@ static int tegra_xusb_setup_ports(struct tegra_xusb_padctl *padctl)
 	mutex_lock(&padctl->lock);
 
 	for (i = 0; i < padctl->soc->ports.usb2.count; i++) {
+		printk("add usb2 port %d\n", i);
 		err = tegra_xusb_add_usb2_port(padctl, i);
 		if (err < 0)
 			goto remove_ports;
 	}
 
 	for (i = 0; i < padctl->soc->ports.ulpi.count; i++) {
+		printk("add ulpi port %d\n", i);
 		err = tegra_xusb_add_ulpi_port(padctl, i);
 		if (err < 0)
 			goto remove_ports;
 	}
 
 	for (i = 0; i < padctl->soc->ports.hsic.count; i++) {
+		printk("add hsic port %d\n", i);
 		err = tegra_xusb_add_hsic_port(padctl, i);
 		if (err < 0)
 			goto remove_ports;
 	}
 
 	for (i = 0; i < padctl->soc->ports.usb3.count; i++) {
+		printk("add usb3 port %d\n", i);
 		err = tegra_xusb_add_usb3_port(padctl, i);
 		if (err < 0)
 			goto remove_ports;
@@ -1143,10 +1158,12 @@ static int tegra_xusb_setup_ports(struct tegra_xusb_padctl *padctl)
 
 	if (padctl->soc->need_fake_usb3_port) {
 		for (i = 0; i < padctl->soc->ports.usb2.count; i++) {
+			printk("checking usb2 port %d\n", i);
 			usb2 = tegra_xusb_find_usb2_port(padctl, i);
 			if (!usb2)
 				continue;
 
+			printk("update usb3 fake port %d\n", i);
 			err = tegra_xusb_update_usb3_fake_port(usb2);
 			if (err < 0)
 				goto remove_ports;
@@ -1154,12 +1171,14 @@ static int tegra_xusb_setup_ports(struct tegra_xusb_padctl *padctl)
 	}
 
 	list_for_each_entry(port, &padctl->ports, list) {
+		printk("enable port\n");
 		err = port->ops->enable(port);
 		if (err < 0)
 			dev_err(padctl->dev, "failed to enable port %s: %d\n",
 				dev_name(&port->dev), err);
 	}
 
+	printk("unlock\n");
 	goto unlock;
 
 remove_ports:

drivers/soc/tegra/pmc.c

@@ -3593,6 +3593,32 @@ static const char * const tegra210_powergates[] = {
 	[TEGRA_POWERGATE_VE2] = "ve2",
 };
 
+static const char * const tegra210b01_powergates[] = {
+	[TEGRA_POWERGATE_CPU] = "crail",
+	[TEGRA_POWERGATE_3D] = "3d",
+	[TEGRA_POWERGATE_PCIE] = "pcie",
+	[TEGRA_POWERGATE_MPE] = "mpe",
+	[TEGRA_POWERGATE_SATA] = "sata",
+	[TEGRA_POWERGATE_CPU1] = "cpu1",
+	[TEGRA_POWERGATE_CPU2] = "cpu2",
+	[TEGRA_POWERGATE_CPU3] = "cpu3",
+	[TEGRA_POWERGATE_CPU0] = "cpu0",
+	[TEGRA_POWERGATE_C0NC] = "c0nc",
+	[TEGRA_POWERGATE_SOR] = "sor",
+	[TEGRA_POWERGATE_DIS] = "dis",
+	[TEGRA_POWERGATE_DISB] = "disb",
+	[TEGRA_POWERGATE_XUSBA] = "xusba",
+	[TEGRA_POWERGATE_XUSBB] = "xusbb",
+	[TEGRA_POWERGATE_XUSBC] = "xusbc",
+	[TEGRA_POWERGATE_VIC] = "vic",
+	[TEGRA_POWERGATE_IRAM] = "iram",
+	[TEGRA_POWERGATE_NVDEC] = "nvdec",
+	[TEGRA_POWERGATE_NVJPG] = "nvjpg",
+	[TEGRA_POWERGATE_AUD] = "aud",
+	[TEGRA_POWERGATE_DFD] = "dfd",
+};
+
+
 static const u8 tegra210_cpu_powergates[] = {
 	TEGRA_POWERGATE_CPU0,
 	TEGRA_POWERGATE_CPU1,
@@ -3814,13 +3840,13 @@ static const struct pinctrl_pin_desc tegra210b01_pin_descs[] = {
 
 static const struct tegra_pmc_soc tegra210b01_pmc_soc = {
 	.supports_core_domain = false,
-	.num_powergates = ARRAY_SIZE(tegra210_powergates),
-	.powergates = tegra210_powergates,
+	.num_powergates = ARRAY_SIZE(tegra210b01_powergates),
+	.powergates = tegra210b01_powergates,
 	.num_cpu_powergates = ARRAY_SIZE(tegra210_cpu_powergates),
 	.cpu_powergates = tegra210_cpu_powergates,
 	.has_tsense_reset = true,
 	.has_gpu_clamps = true,
-	.needs_mbist_war = true,
+	.needs_mbist_war = false,
 	.has_impl_33v_pwr = false,
 	.maybe_tz_only = true,
 	.num_io_pads = ARRAY_SIZE(tegra210b01_io_pads),

drivers/usb/typec/Kconfig

@@ -110,6 +110,15 @@ config TYPEC_WUSB3801
 	  If you choose to build this driver as a dynamically linked module, the
 	  module will be called wusb3801.ko.
 
+config TYPEC_BM92TXX
+	tristate "Rohm Semiconductor BM92TXX USB Type-C Support"
+	depends on I2C
+	depends on USB_ROLE_SWITCH
+	help
+	  Say yes here to support for Rohm Semiconductor BM92TXX. This is a USB
+	  Type-C connection IC. This driver provies common support for power
+	  negotiation, USB ID detection and Hot-plug-detection on Display Port.
+
 source "drivers/usb/typec/mux/Kconfig"
 
 source "drivers/usb/typec/altmodes/Kconfig"

drivers/usb/typec/Makefile

@@ -11,4 +11,5 @@ obj-$(CONFIG_TYPEC_HD3SS3220)	+= hd3ss3220.o
 obj-$(CONFIG_TYPEC_STUSB160X) 	+= stusb160x.o
 obj-$(CONFIG_TYPEC_RT1719)	+= rt1719.o
 obj-$(CONFIG_TYPEC_WUSB3801)	+= wusb3801.o
+obj-$(CONFIG_TYPEC_BM92TXX)		+= bm92txx.o
 obj-$(CONFIG_TYPEC)		+= mux/

gki/aarch64/abi.stg

@@ -125397,23 +125397,29 @@ member {
   offset: 2880
 }
 member {
-  id: 0x8998723d
-  name: "gpu_process_id"
+  id: 0x716f03bc
+  name: "gpu_iddq_value"
   type_id: 0x6720d32f
-  offset: 256
+  offset: 384
 }
 member {
-  id: 0xc59015c8
-  name: "gpu_speedo_id"
+  id: 0x8998764f
+  name: "gpu_process_id"
   type_id: 0x6720d32f
   offset: 288
 }
 member {
-  id: 0x1839ab9c
-  name: "gpu_speedo_value"
+  id: 0xc59016d6
+  name: "gpu_speedo_id"
   type_id: 0x6720d32f
   offset: 320
 }
+member {
+  id: 0x1839a802
+  name: "gpu_speedo_value"
+  type_id: 0x6720d32f
+  offset: 352
+}
 member {
   id: 0x220ee7b2
   name: "gpuva"
@@ -189897,10 +189903,10 @@ member {
   bitsize: 1
 }
 member {
-  id: 0x2bdf1e4c
+  id: 0x2bdf18a9
   name: "platform"
   type_id: 0x4bb568ad
-  offset: 384
+  offset: 448
 }
 member {
   id: 0x38c654ae
@@ -210651,10 +210657,10 @@ member {
   offset: 12480
 }
 member {
-  id: 0x94eb2e6e
+  id: 0x94eb2857
   name: "revision"
   type_id: 0x43f6ac22
-  offset: 352
+  offset: 416
 }
 member {
   id: 0xbcd2bfaa
@@ -227338,6 +227344,12 @@ member {
   type_id: 0x3e10b518
   offset: 256
 }
+member {
+  id: 0x97cc708c
+  name: "soc_iddq_value"
+  type_id: 0x6720d32f
+  offset: 256
+}
 member {
   id: 0x8d753502
   name: "soc_process_id"
@@ -228117,6 +228129,12 @@ member {
   type_id: 0xc9082b19
   offset: 704
 }
+member {
+  id: 0x9b8091d9
+  name: "speedo_rev"
+  type_id: 0x6720d32f
+  offset: 512
+}
 member {
   id: 0xd0391586
   name: "spi"
@@ -248697,6 +248715,12 @@ member {
   type_id: 0x790929c4
   offset: 8512
 }
+member {
+  id: 0xe7a15159
+  name: "ucm"
+  type_id: 0x7c124706
+  offset: 480
+}
 member {
   id: 0x14b7816e
   name: "ucontext"
@@ -340766,7 +340790,7 @@ struct_union {
   kind: STRUCT
   name: "tegra_sku_info"
   definition {
-    bytesize: 52
+    bytesize: 68
     member_id: 0x159f315d
     member_id: 0x7be41b46
     member_id: 0x9bd81e85
@@ -340775,11 +340799,15 @@ struct_union {
     member_id: 0x8d753502
     member_id: 0x509bfc34
     member_id: 0x0ef921fa
-    member_id: 0x8998723d
-    member_id: 0xc59015c8
-    member_id: 0x1839ab9c
-    member_id: 0x94eb2e6e
-    member_id: 0x2bdf1e4c
+    member_id: 0x97cc708c
+    member_id: 0x8998764f
+    member_id: 0xc59016d6
+    member_id: 0x1839a802
+    member_id: 0x716f03bc
+    member_id: 0x94eb2857
+    member_id: 0x2bdf18a9
+    member_id: 0xe7a15159
+    member_id: 0x9b8091d9
   }
 }
 struct_union {
@@ -370359,9 +370387,27 @@ enumeration {
       value: 5
     }
     enumerator {
-      name: "TEGRA_REVISION_MAX"
+      name: "TEGRA_REVISION_B01"
       value: 6
     }
+    enumerator {
+      name: "TEGRA_REVISION_MAX"
+      value: 7
+    }
+  }
+}
+enumeration {
+  id: 0x7c124706
+  name: "tegra_ucm"
+  definition {
+    underlying_type_id: 0x4585663f
+    enumerator {
+      name: "TEGRA_UCM1"
+    }
+    enumerator {
+      name: "TEGRA_UCM2"
+      value: 1
+    }
   }
 }
 enumeration {
@@ -505039,7 +505085,7 @@ elf_symbol {
   name: "tegra_sku_info"
   is_defined: true
   symbol_type: OBJECT
-  crc: 0xbbcfcffc
+  crc: 0xe4a4fdfb
   type_id: 0x539be05c
   full_name: "tegra_sku_info"
 }

gki/aarch64/symbols/tegra

@@ -720,11 +720,14 @@
   memstart_addr
   mipi_dsi_attach
   mipi_dsi_create_packet
+  mipi_dsi_dcs_read
+  mipi_dsi_dcs_set_pixel_format
   mipi_dsi_detach
   mipi_dsi_driver_register_full
   mipi_dsi_driver_unregister
   mipi_dsi_host_register
   mipi_dsi_host_unregister
+  mipi_dsi_set_maximum_return_packet_size
   misc_deregister
   misc_register
   __mmap_lock_do_trace_acquire_returned
@@ -1184,6 +1187,7 @@
   up_read
   up_write
   usb_control_msg
+  usb_role_switch_get_role
   usb_role_switch_put
   usb_role_switch_set_role
   __usecs_to_jiffies
@@ -1244,6 +1248,14 @@
   report_iommu_fault
   tegra_mc_probe_device
 
+# required by bm92txx.ko
+  devm_gpio_request
+  extcon_get_state
+  extcon_set_state
+  fwnode_graph_get_endpoint_by_id
+  fwnode_graph_get_remote_endpoint
+  regulator_set_current_limit
+
 # required by bq24190_charger.ko
   kstrtou8
   power_supply_get_property_from_supplier
@@ -2019,11 +2031,15 @@
   devm_of_find_backlight
   mipi_dsi_dcs_enter_sleep_mode
   mipi_dsi_dcs_exit_sleep_mode
-  mipi_dsi_dcs_read
   mipi_dsi_dcs_set_display_off
   mipi_dsi_dcs_set_display_on
-  mipi_dsi_dcs_set_pixel_format
-  mipi_dsi_set_maximum_return_packet_size
+
+# required by panel-nx-dsi.ko
+  mipi_dsi_dcs_set_column_address
+  mipi_dsi_dcs_set_page_address
+  mipi_dsi_dcs_set_tear_on
+  mipi_dsi_dcs_write
+  of_find_backlight_by_node
 
 # required by panel-simple.ko
   drm_bus_flags_from_videomode
@@ -2122,7 +2138,6 @@
   usb_phy_set_event
   usb_remove_phy
   usb_role_switch_get_drvdata
-  usb_role_switch_get_role
   usb_role_switch_register
   usb_role_switch_set_drvdata
   usb_role_switch_unregister