memory: tegra186-emc: support t210b01

Tegra210b01 uses Tegra186 style emc management, as in it is
offloaded to BPMP. This driver already implements this, so no
reason to shoehorn in elsewhere.

arch/arm64/boot/dts/nvidia/tegra210b01-fric.dts

@@ -5,5 +5,5 @@
 
 / {
 	model = "Nintendo Switch (OLED model)";
-	compatible = "nvidia,fric", "nintendo,aula", "nintendo,nx", "nvidia,tegra210b01";
+	compatible = "nvidia,fric", "nintendo,aula", "nintendo,nx", "nvidia,tegra210b01", "nvidia,tegra210";
 };

arch/arm64/boot/dts/nvidia/tegra210b01-nx.dtsi

@@ -30,6 +30,66 @@
 		status = "okay";
 	};
 
+	/* SDMMC4 for EMMC */
+	mmc@700b0600 {
+		status = "disabled";
+		bus-width = <8>;
+		max-frequency = <200000000>;
+
+		cd-gpios = <&gpio TEGRA_GPIO(Z, 1) GPIO_ACTIVE_HIGH>;
+
+		cap-mmc-highspeed;
+		mmc-ddr-1_8v;
+		mmc-hs200-1_8v;
+		mmc-hs400-1_8v;
+		non-removable;
+
+		vqmmc-supply = <&max77620_sd3>;
+		vmmc-supply = <&vdd_3v3>;
+	};
+
+	/* SDMMC3 Not Used */
+	mmc@700b0400 {
+		status = "disabled";
+	};
+
+	/* SDMMC2 for Gamecard */
+	mmc@700b0200 {
+		status = "disabled";
+		bus-width = <8>;
+		max-frequency = <200000000>;
+
+		mmc-ddr-1_8v;
+		mmc-hs400-1_8v;
+		mmc-hs200-1_8v;
+		cap-mmc-highspeed;
+		cap-sd-highspeed;
+		non-removable;
+
+		vqmmc-supply = <&max77620_sd3>;
+		vmmc-supply = <&vdd_3v3>;
+	};
+
+	/* SDMMC1 for SD Card */
+	mmc@700b0000 {
+		status = "okay";
+		bus-width = <4>;
+		max-frequency = <200000000>;
+
+		cap-sd-highspeed;
+		sd-uhs-sdr12;
+		sd-uhs-sdr50;
+		sd-uhs-sdr104;
+
+		vmmc-supply = <&en_vdd_sd>;
+		vqmmc-supply = <&max77620_ldo2>;
+	};
+
+	gpu@57000000 {
+		status = "okay";
+		vdd-supply = <&gpu_max_reg>;
+	};
+
 	backlight: backlight {
 		status = "okay";
 		compatible = "pwm-backlight";

arch/arm64/boot/dts/nvidia/tegra210b01-odin.dts

@@ -6,5 +6,5 @@
 / {
 
 	model = "Nintendo Switch (2019)";
-	compatible = "nvidia,modin", "nvidia,odin", "nintendo,iowa", "nintendo,nx", "nvidia,tegra210b01";
+	compatible = "nvidia,modin", "nvidia,odin", "nintendo,iowa", "nintendo,nx", "nvidia,tegra210b01", "nvidia,tegra210";
 };

arch/arm64/boot/dts/nvidia/tegra210b01-vali.dts

@@ -5,7 +5,7 @@
 
 / {
 	model = "Nintendo Switch Lite";
-	compatible = "nvidia,vali", "nintendo,hoag", "nintendo,nx", "nvidia,tegra210b01";
+	compatible = "nvidia,vali", "nintendo,hoag", "nintendo,nx", "nvidia,tegra210b01", "nvidia,tegra210";
 
     /* Joycon/Fan power (usb) */
 	v_vdd50_b: v-vdd50-b {

arch/arm64/boot/dts/nvidia/tegra210b01.dtsi

@@ -33,6 +33,51 @@
 		/delete-property/ pinctrl-names;
 	};
 
+	mmc@700b0600 {
+		nvidia,default-tap = <9>;
+		nvidia,default-trim = <13>;
+
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+		clock-names = "sdmmc4", "sdmmc_legacy";
+
+		assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+			 <&tegra_car TEGRA210_CLK_PLL_C4_OUT2>;
+		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT2>;
+	};
+
+	mmc@700b0400 {
+		nvidia,default-tap = <11>;
+		nvidia,default-trim = <18>;
+
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC3>,
+			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+		clock-names = "sdmmc3", "sdmmc_legacy";
+	};
+
+	mmc@700b0200 {
+		nvidia,default-tap = <8>;
+		nvidia,default-trim = <13>;
+
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC2>,
+			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+		clock-names = "sdmmc2", "sdmmc_legacy";
+	};
+
+	mmc@700b0000 {
+		nvidia,default-tap = <11>;
+		nvidia,default-trim = <14>;
+
+		clocks = <&tegra_car TEGRA210_CLK_SDMMC1>,
+			 <&tegra_car TEGRA210_CLK_SDMMC_LEGACY>;
+		clock-names = "sdmmc1", "sdmmc_legacy";
+
+		assigned-clocks = <&tegra_car TEGRA210_CLK_SDMMC4>,
+				  <&tegra_car TEGRA210_CLK_PLL_C4_OUT2>,
+				  <&tegra_car TEGRA210_CLK_PLL_C4>;
+		assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_C4_OUT2>;
+	};
+
 	/* Tegra210B01 has MBIST patched and is missing VI unit */
 	pmc@7000e400 {
 		compatible = "nvidia,tegra210b01-pmc";
@@ -54,6 +99,41 @@
 		compatible = "nvidia,tegra210b01-xusb-padctl";
 	};
 
+	pinmux@700008d4 {
+		status = "okay";
+		sdmmc1_drv_code_1_8V: sdmmc1_drv_code {
+			sdmmc1 {
+				nvidia,pins = "drive_sdmmc1";
+				nvidia,pull-down-strength = <8>;
+				nvidia,pull-up-strength = <8>;
+			};
+		};
+
+		sdmmc1_default_drv_code_3_3V: sdmmc1_default_drv_code {
+			sdmmc1 {
+				nvidia,pins = "drive_sdmmc1";
+				nvidia,pull-down-strength = <8>;
+				nvidia,pull-up-strength = <8>;
+			};
+		};
+
+		sdmmc3_drv_code_1_8V: sdmmc3_drv_code {
+			sdmmc3 {
+				nvidia,pins = "drive_sdmmc3";
+				nvidia,pull-down-strength = <8>;
+				nvidia,pull-up-strength = <8>;
+			};
+		};
+
+		sdmmc3_default_drv_code_3_3V: sdmmc3_default_drv_code {
+			sdmmc3 {
+				nvidia,pins = "drive_sdmmc3";
+				nvidia,pull-down-strength = <8>;
+				nvidia,pull-up-strength = <8>;
+			};
+		};
+	};
+
 	usb@700d0000 {
 		compatible = "nvidia,tegra210b01-xudc";
 	};

drivers/clk/tegra/clk-dfll.c

@@ -4124,7 +4124,8 @@ int tegra_dfll_register(struct platform_device *pdev,
 	}
 
 	/* Initialize tuning timer */
-	hrtimer_setup(&td->tune_timer, &dfll_tune_timer_cb, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+	hrtimer_init(&td->tune_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+	td->tune_timer.function = dfll_tune_timer_cb;
 	td->tune_delay = ktime_set(0, DFLL_TUNE_HIGH_DELAY * 1000);
 	td->tune_ramp_delay = ktime_set(0, td->one_shot_settle_time * 1000);
 

drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h

@@ -134,5 +134,6 @@ int gf100_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct
 int gk104_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
 int gk20a_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
 int gm20b_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
+int gm20b_b01_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
 int gp10b_clk_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_clk **);
 #endif

drivers/gpu/drm/nouveau/include/nvkm/subdev/volt.h

@@ -42,4 +42,5 @@ int gf117_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct
 int gk104_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
 int gk20a_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
 int gm20b_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
+int gm20b_b01_volt_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_volt **);
 #endif

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

@@ -2072,6 +2072,31 @@ nv12b_chipset = {
 	.sw       = { 0x00000001, gf100_sw_new },
 };
 
+static const struct nvkm_device_chip
+nv12e_chipset = {
+	.name = "GM20B",
+	.acr      = { 0x00000001, gm20b_acr_new },
+	.bar      = { 0x00000001, gm20b_bar_new },
+	.bus      = { 0x00000001, gf100_bus_new },
+	.clk      = { 0x00000001, gm20b_b01_clk_new },
+	.fb       = { 0x00000001, gm20b_fb_new },
+	.fuse     = { 0x00000001, gm107_fuse_new },
+	.imem     = { 0x00000001, gk20a_instmem_new },
+	.ltc      = { 0x00000001, gm200_ltc_new },
+	.mc       = { 0x00000001, gk20a_mc_new },
+	.mmu      = { 0x00000001, gm20b_mmu_new },
+	.pmu      = { 0x00000001, gm20b_pmu_new },
+	.privring = { 0x00000001, gk20a_privring_new },
+	.timer    = { 0x00000001, gk20a_timer_new },
+	.top      = { 0x00000001, gk104_top_new },
+	.volt     = { 0x00000001, gm20b_b01_volt_new },
+	.ce       = { 0x00000004, gm200_ce_new },
+	.dma      = { 0x00000001, gf119_dma_new },
+	.fifo     = { 0x00000001, gm200_fifo_new },
+	.gr       = { 0x00000001, gm20b_gr_new },
+	.sw       = { 0x00000001, gf100_sw_new },
+};
+
 static const struct nvkm_device_chip
 nv130_chipset = {
 	.name = "GP100",
@@ -3225,6 +3250,7 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
 	case 0x124: device->chip = &nv124_chipset; break;
 	case 0x126: device->chip = &nv126_chipset; break;
 	case 0x12b: device->chip = &nv12b_chipset; break;
+	case 0x12e: device->chip = &nv12e_chipset; break;
 	case 0x130: device->chip = &nv130_chipset; break;
 	case 0x132: device->chip = &nv132_chipset; break;
 	case 0x134: device->chip = &nv134_chipset; break;

drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.c

@@ -717,6 +717,112 @@ gm20b_pstates[] = {
 	},
 };
 
+static struct nvkm_pstate
+gm20b_b01_pstates[] = {
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 76800,
+			.voltage = 0,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 153600,
+			.voltage = 1,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 230400,
+			.voltage = 2,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 307200,
+			.voltage = 3,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 384000,
+			.voltage = 4,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 460800,
+			.voltage = 5,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 537600,
+			.voltage = 6,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 614400,
+			.voltage = 7,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 691200,
+			.voltage = 8,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 768000,
+			.voltage = 9,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 844800,
+			.voltage = 10,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 921600,
+			.voltage = 11,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 998400,
+			.voltage = 12,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 1075200,
+			.voltage = 13,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 1152000,
+			.voltage = 14,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 1228800,
+			.voltage = 15,
+		},
+	},
+	{
+		.base = {
+			.domain[nv_clk_src_gpc] = 1267200,
+			.voltage = 16,
+		},
+	},
+};
+
 static void
 gm20b_clk_fini(struct nvkm_clk *base)
 {
@@ -912,6 +1018,41 @@ gm20b_clk = {
 	},
 };
 
+static const struct nvkm_clk_func
+gm20b_b01_clk = {
+	.init = gm20b_clk_init,
+	.fini = gk20a_clk_fini,
+	.read = gk20a_clk_read,
+	.calc = gk20a_clk_calc,
+	.prog = gk20a_clk_prog,
+	.tidy = gk20a_clk_tidy,
+	.pstates = gm20b_b01_pstates,
+	.nr_pstates = ARRAY_SIZE(gm20b_b01_pstates),
+	.domains = {
+		{ nv_clk_src_crystal, 0xff },
+		{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
+		{ nv_clk_src_max },
+	},
+};
+
+static const struct nvkm_clk_func
+gm20b_b01_hiopt_clk_speedo = {
+	.init = gm20b_clk_init,
+	.fini = gk20a_clk_fini,
+	.read = gk20a_clk_read,
+	.calc = gk20a_clk_calc,
+	.prog = gk20a_clk_prog,
+	.tidy = gk20a_clk_tidy,
+	.pstates = gm20b_pstates,
+	/* HIOPT speedo only supports 16 voltages */
+	.nr_pstates = ARRAY_SIZE(gm20b_pstates) - 1,
+	.domains = {
+		{ nv_clk_src_crystal, 0xff },
+		{ nv_clk_src_gpc, 0xff, 0, "core", GK20A_CLK_GPC_MDIV },
+		{ nv_clk_src_max },
+	},
+};
+
 static int
 gm20b_clk_new_speedo0(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
 		      struct nvkm_clk **pclk)
@@ -930,6 +1071,24 @@ gm20b_clk_new_speedo0(struct nvkm_device *device, enum nvkm_subdev_type type, in
 	return ret;
 }
 
+static int
+gm20b_b01_clk_new_hiopt(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+		      struct nvkm_clk **pclk)
+{
+	struct gk20a_clk *clk;
+	int ret;
+
+	clk = kzalloc(sizeof(*clk), GFP_KERNEL);
+	if (!clk)
+		return -ENOMEM;
+	*pclk = &clk->base;
+
+	ret = gk20a_clk_ctor(device, type, inst, &gm20b_b01_hiopt_clk_speedo, &gm20b_pllg_params, clk);
+	clk->pl_to_div = pl_to_div;
+	clk->div_to_pl = div_to_pl;
+	return ret;
+}
+
 /* FUSE register */
 #define FUSE_RESERVED_CALIB0	0x204
 #define FUSE_RESERVED_CALIB0_INTERCEPT_FRAC_SHIFT	0
@@ -1074,3 +1233,63 @@ gm20b_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
 
 	return 0;
 }
+
+int
+gm20b_b01_clk_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	      struct nvkm_clk **pclk)
+{
+	struct nvkm_device_tegra *tdev = device->func->tegra(device);
+	struct gm20b_clk *clk;
+	struct nvkm_subdev *subdev;
+	struct gk20a_clk_pllg_params *clk_params;
+	int ret;
+
+	/* Speedo 0 GPUs cannot use noise-aware PLL */
+	if (tdev->gpu_speedo_id == 0)
+		return gm20b_b01_clk_new_hiopt(device, type, inst, pclk);
+
+	/* Speedo >= 1, use NAPLL */
+	clk = kzalloc(sizeof(*clk) + sizeof(*clk_params), GFP_KERNEL);
+	if (!clk)
+		return -ENOMEM;
+	*pclk = &clk->base.base;
+	subdev = &clk->base.base.subdev;
+
+	/* duplicate the clock parameters since we will patch them below */
+	clk_params = (void *) (clk + 1);
+	*clk_params = gm20b_pllg_params;
+	ret = gk20a_clk_ctor(device, type, inst, &gm20b_b01_clk, clk_params, &clk->base);
+	if (ret)
+		return ret;
+
+	/*
+	 * NAPLL can only work with max_u, clamp the m range so
+	 * gk20a_pllg_calc_mnp always uses it
+	 */
+	clk_params->max_m = clk_params->min_m = DIV_ROUND_UP(clk_params->max_u,
+						(clk->base.parent_rate / KHZ));
+	if (clk_params->max_m == 0) {
+		nvkm_warn(subdev, "cannot use NAPLL, using legacy clock...\n");
+		kfree(clk);
+		return gm20b_b01_clk_new_hiopt(device, type, inst, pclk);
+	}
+
+	clk->base.pl_to_div = pl_to_div;
+	clk->base.div_to_pl = div_to_pl;
+
+	clk->dvfs_params = &gm20b_dvfs_params;
+
+	ret = gm20b_clk_init_fused_params(clk);
+	/*
+	 * we will calibrate during init - should never happen on
+	 * prod parts
+	 */
+	if (ret)
+		nvkm_warn(subdev, "no fused calibration parameters\n");
+
+	ret = gm20b_clk_init_safe_fmax(clk);
+	if (ret)
+		return ret;
+
+	return 0;
+}

drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.c

@@ -91,3 +91,99 @@ gm20b_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
 		return gk20a_volt_ctor(device, type, inst, gm20b_cvb_coef,
 				       ARRAY_SIZE(gm20b_cvb_coef), vmin, volt);
 }
+
+static const struct cvb_coef gm20b_b01_na_cvb_slt_coef[] = {
+	/* KHz,         c0,     c1,   c2,    c3,     c4,   c5 */
+	/* 76800 */   { 590000,        0,        0,        0,        0,        0 },
+	/* 153600 */  { 590000,        0,        0,        0,        0,        0 },
+	/* 230400 */  { 590000,        0,        0,        0,        0,        0 },
+	/* 307200 */  { 590000,        0,        0,        0,        0,        0 },
+	/* 384000 */  { 590000,        0,        0,        0,        0,        0 },
+	/* 460800 */  { 795089,   -11096,     -163,      298,   -10421,      162},
+	/* 537600 */  { 795089,   -11096,     -163,      298,   -10421,      162 },
+	/* 614400 */  { 820606,    -6285,     -452,      238,    -6182,       81 },
+	/* 691200 */  { 846289,    -4565,     -552,      119,    -3958,       -2 },
+	/* 768000 */  { 888720,    -5110,     -584,        0,    -2849,       39 },
+	/* 844800 */  { 936634,    -6089,     -602,      -60,      -99,      -93 },
+	/* 921600 */  { 982562,    -7373,     -614,     -179,     1797,      -13 },
+	/* 998400 */  { 1090179,   -14125,     -497,     -179,     3518,        9 },
+	/* 1075200 */ { 1155798,   -13465,     -648,        0,     1077,       40 },
+	/* 1152000 */ { 1198568,   -10904,     -830,        0,     1469,      110 },
+	/* 1228800 */ { 1269988,   -12707,     -859,        0,     3722,      313 },
+	/* 1267200 */ { 1308155,   -13694,     -867,        0,     3681,      559 },
+};
+
+static const struct cvb_coef gm20b_b01_na_cvb_coef[] = {
+	/* KHz,         c0,     c1,   c2,    c3,     c4,   c5 */
+	/* 76800 */   { 610000,        0,        0,        0,        0,        0 },
+	/* 153600 */  { 610000,        0,        0,        0,        0,        0 },
+	/* 230400 */  { 610000,        0,        0,        0,        0,        0 },
+	/* 307200 */  { 610000,        0,        0,        0,        0,        0 },
+	/* 384000 */  { 610000,        0,        0,        0,        0,        0 },
+	/* 460800 */  { 610000,        0,        0,        0,        0,        0 },
+	/* 537600 */  { 801688,   -10900,     -163,      298,   -10599,      162 },
+	/* 614400 */  { 824214,    -5743,     -452,      238,    -6325,       81 },
+	/* 691200 */  { 848830,    -3903,     -552,      119,    -4030,       -2 },
+	/* 768000 */  { 891575,    -4409,     -584,        0,    -2849,       39 },
+	/* 844800 */  { 940071,    -5367,     -602,      -60,      -63,      -93 },
+	/* 921600 */  { 986765,    -6637,     -614,     -179,     1905,      -13 },
+	/* 998400 */  { 1098475,   -13529,     -497,     -179,     3626,        9 },
+	/* 1075200 */ { 1163644,   -12688,     -648,        0,     1077,       40 },
+	/* 1152000 */ { 1204812,    -9908,     -830,        0,     1469,      110 },
+	/* 1228800 */ { 1277303,   -11675,     -859,        0,     3722,      313 },
+	/* 1267200 */ { 1335531,   -12567,     -867,        0,     3681,      559 },
+};
+
+static const struct cvb_coef gm20b_b01_na_cvb_hiopt_coef[] = {
+	/* KHz,         c0,     c1,   c2,    c3,     c4,   c5 */
+	/* 76800 */   {   590000,        0,        0,        0,        0,        0 },
+	/* 153600 */  {   590000,        0,        0,        0,        0,        0 },
+	/* 230400 */  {   590000,        0,        0,        0,        0,        0 },
+	/* 307200 */  {   590000,        0,        0,        0,        0,        0 },
+	/* 384000 */  {   590000,        0,        0,        0,        0,        0 },
+	/* 460800 */  {   590000,        0,        0,        0,        0,        0 },
+	/* 537600 */  {   590000,        0,        0,        0,        0,        0 },
+	/* 614400 */  {   590000,        0,        0,        0,        0,        0 },
+	/* 691200 */  {   838712,    -7304,     -552,     1785,   -56250,     -450 },
+	/* 768000 */  {   880210,    -7955,     -584,        0,   -42735,     8775 },
+	/* 844800 */  {   926398,    -8892,     -602,     -900,    -5760,   -20925 },
+	/* 921600 */  {   970060,   -10108,     -614,    -2685,    22620,    -2925 },
+	/* 998400 */  {  1065665,   -16075,     -497,    -2685,    48195,     2025 },
+	/* 1075200 */ {  1132576,   -16093,     -648,        0,    16155,     9000 },
+	/* 1152000 */ {  1180029,   -14534,     -830,        0,    22035,    24750 },
+	/* 1228800 */ {  1248293,   -16383,     -859,        0,    55830,    70425 },
+};
+
+int
+gm20b_b01_volt_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
+	       struct nvkm_volt **pvolt)
+{
+	struct nvkm_device_tegra *tdev = device->func->tegra(device);
+	struct gk20a_volt *volt;
+	u32 vmin;
+
+	if (tdev->gpu_speedo_id >= ARRAY_SIZE(speedo_to_vmin)) {
+		nvdev_error(device, "unsupported speedo %d\n",
+			    tdev->gpu_speedo_id);
+		return -EINVAL;
+	}
+
+	volt = kzalloc(sizeof(*volt), GFP_KERNEL);
+	if (!volt)
+		return -ENOMEM;
+	*pvolt = &volt->base;
+
+	vmin = speedo_to_vmin[tdev->gpu_speedo_id];
+
+	switch (tdev->gpu_speedo_id) {
+		case 3: /* HIOPT table */
+			return gk20a_volt_ctor(device, type, inst, gm20b_b01_na_cvb_hiopt_coef,
+						ARRAY_SIZE(gm20b_b01_na_cvb_hiopt_coef), vmin, volt);
+		case 2: /* SLT table */
+			return gk20a_volt_ctor(device, type, inst, gm20b_b01_na_cvb_slt_coef,
+						ARRAY_SIZE(gm20b_b01_na_cvb_slt_coef), vmin, volt);
+		default:
+			return gk20a_volt_ctor(device, type, inst, gm20b_b01_na_cvb_coef,
+						ARRAY_SIZE(gm20b_b01_na_cvb_coef), vmin, volt);
+	}
+}

drivers/gpu/drm/panel/panel-nx-dsi.c

@@ -32,39 +32,38 @@
 #include <drm/drm_modes.h>
 
 /*! MIPI DCS Panel Private CMDs. */
-#define MIPI_DCS_PRIV_SM_SET_COLOR_MODE 0xA0
-#define MIPI_DCS_PRIV_SM_SET_REG_OFFSET 0xB0
-#define MIPI_DCS_PRIV_SM_SET_ELVSS \
-	0xB1 // OLED backlight tuning. Byte7: PWM transition time in frames.
-#define MIPI_DCS_PRIV_SET_POWER_CONTROL 0xB1
-#define MIPI_DCS_PRIV_SET_EXTC 0xB9 // Enable extended commands.
-#define MIPI_DCS_PRIV_UNK_BD 0xBD
-#define MIPI_DCS_PRIV_UNK_D5 0xD5
-#define MIPI_DCS_PRIV_UNK_D6 0xD6
-#define MIPI_DCS_PRIV_UNK_D8 0xD8
-#define MIPI_DCS_PRIV_UNK_D9 0xD9
+#define MIPI_DCS_PRIV_SM_SET_COLOR_MODE      ((u8)0xA0)
+#define MIPI_DCS_PRIV_SM_SET_REG_OFFSET      ((u8)0xB0)
+#define MIPI_DCS_PRIV_SM_SET_ELVSS           ((u8)0xB1) /* OLED backlight tuning. Byte7: PWM transition time in frames. */
+#define MIPI_DCS_PRIV_SET_POWER_CONTROL      ((u8)0xB1)
+#define MIPI_DCS_PRIV_SET_EXTC               ((u8)0xB9) /* Enable extended commands. */
+#define MIPI_DCS_PRIV_UNK_BD                 ((u8)0xBD)
+#define MIPI_DCS_PRIV_UNK_D5                 ((u8)0xD5)
+#define MIPI_DCS_PRIV_UNK_D6                 ((u8)0xD6)
+#define MIPI_DCS_PRIV_UNK_D8                 ((u8)0xD8)
+#define MIPI_DCS_PRIV_UNK_D9                 ((u8)0xD9)
 
-#define MIPI_DCS_PRIV_SM_SET_REGS_LOCK 0xE2
+#define MIPI_DCS_PRIV_SM_SET_REGS_LOCK       ((u8)0xE2)
 
-// BL Control
-#define DCS_CONTROL_DISPLAY_SM_FLASHLIGHT   BIT(2)
-#define DCS_CONTROL_DISPLAY_BACKLIGHT_CTRL  BIT(2)
-#define DCS_CONTROL_DISPLAY_DIMMING_CTRL    BIT(3)
-#define DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL BIT(5)
+/* BL Control */
+#define DCS_CONTROL_DISPLAY_SM_FLASHLIGHT    ((u8)BIT(2))
+#define DCS_CONTROL_DISPLAY_BACKLIGHT_CTRL   ((u8)BIT(2))
+#define DCS_CONTROL_DISPLAY_DIMMING_CTRL     ((u8)BIT(3))
+#define DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL  ((u8)BIT(5))
 
-// OLED Panels color mode
-#define DCS_SM_COLOR_MODE_SATURATED 0x00 // Disabled. Similar to vivid but over-saturated. Wide gamut?
-#define DCS_SM_COLOR_MODE_WASHED    0x45
-#define DCS_SM_COLOR_MODE_BASIC     0x03
-#define DCS_SM_COLOR_MODE_POR_RESET 0x20 // Reset value on power on.
-#define DCS_SM_COLOR_MODE_NATURAL   0x23 // Not actually natural..
-#define DCS_SM_COLOR_MODE_VIVID     0x65
-#define DCS_SM_COLOR_MODE_NIGHT0    0x43 // Based on washed out.
-#define DCS_SM_COLOR_MODE_NIGHT1    0x15 // Based on basic.
-#define DCS_SM_COLOR_MODE_NIGHT2    0x35 // Based on natural.
-#define DCS_SM_COLOR_MODE_NIGHT3    0x75 // Based on vivid.
+/* OLED Panels color mode */
+#define DCS_SM_COLOR_MODE_SATURATED          ((u8)0x00) /* Disabled. Similar to vivid but over-saturated. Wide gamut? */
+#define DCS_SM_COLOR_MODE_WASHED             ((u8)0x45)
+#define DCS_SM_COLOR_MODE_BASIC              ((u8)0x03)
+#define DCS_SM_COLOR_MODE_POR_RESET          ((u8)0x20) /* Reset value on power on. */
+#define DCS_SM_COLOR_MODE_NATURAL            ((u8)0x23) /* Not actually natural.. */
+#define DCS_SM_COLOR_MODE_VIVID              ((u8)0x65)
+#define DCS_SM_COLOR_MODE_NIGHT0             ((u8)0x43) /* Based on washed out. */
+#define DCS_SM_COLOR_MODE_NIGHT1             ((u8)0x15) /* Based on basic. */
+#define DCS_SM_COLOR_MODE_NIGHT2             ((u8)0x35) /* Based on natural. */
+#define DCS_SM_COLOR_MODE_NIGHT3             ((u8)0x75) /* Based on vivid. */
 
-#define DCS_SM_COLOR_MODE_ENABLE    BIT(0)
+#define DCS_SM_COLOR_MODE_ENABLE             ((u8)BIT(0))
 
 enum
 {
@@ -115,7 +114,7 @@ struct nx_panel {
 	struct init_cmd *init_cmds;
 	struct init_cmd *suspend_cmds;
 
-	u8 display_id[3];
+	u16 display_id;
 };
 
 struct init_cmd init_cmds_default[] = {
@@ -124,6 +123,11 @@ struct init_cmd init_cmds_default[] = {
 		0xFF,
 		120,
 	},
+	{ MIPI_DCS_SET_DISPLAY_ON, 2, { 0x00, 0x0 } },
+	{
+		0xFF,
+		20,
+	},
 };
 
 struct init_cmd init_cmds_PANEL_JDI_XXX062M[] = {
@@ -193,23 +197,23 @@ struct init_cmd init_cmds_PANEL_SAM_AMS699VC01[] = {
 	},
 
 	// Set color mode to basic (natural). Stock is Saturated (0x00). (Reset value is 0x20).
-	{ MIPI_DCS_PRIV_SM_SET_COLOR_MODE | (DCS_SM_COLOR_MODE_BASIC << 8), 2, { 0x00, 0x0 } },
+	{ MIPI_DCS_PRIV_SM_SET_COLOR_MODE, 2, { 0x23, 0x0 } },
 
 	// Enable backlight and smooth PWM.
-	{ MIPI_DCS_WRITE_CONTROL_DISPLAY | ((DCS_CONTROL_DISPLAY_BRIGHTNESS_CTRL | DCS_CONTROL_DISPLAY_DIMMING_CTRL) << 8), 2, { 0x00, 0x0 } },
+	{ MIPI_DCS_WRITE_CONTROL_DISPLAY, 2, { 0x28, 0x0 } },
 
 	// Unlock Level 2 registers.
-	{ MIPI_DCS_PRIV_SM_SET_REGS_LOCK, 4, { 0x5A, 0x5A, 0x5A, 0x5A, 0x0 } },
+	{ 0x05, 9, { 0x0, 0x0, 0xE2, 0x5A, 0x5A, 0x5A, 0x5A, 0x0, 0x0 } },
 
 	// Set registers offset and set PWM transition to 6 frames (100ms).
-	{ MIPI_DCS_PRIV_SM_SET_REG_OFFSET | (7 << 8), 2, { 0x00, 0x0 } },
-	{ MIPI_DCS_PRIV_SM_SET_ELVSS      | (6 << 8), 2, { 0x00, 0x0 } },
+	{ MIPI_DCS_PRIV_SM_SET_REG_OFFSET, 2, { 0x07, 0x0 } },
+	{ MIPI_DCS_PRIV_SM_SET_ELVSS, 2, { 0x06, 0x0 } },
 
 	// Relock Level 2 registers.
-	{ MIPI_DCS_PRIV_SM_SET_REGS_LOCK, 4, { 0x5A, 0x5A, 0xA5, 0xA5, 0x0 } },
+	{ 0x05, 9, { 0x0, 0x0, 0xE2, 0x5A, 0x5A, 0xA5, 0xA5, 0x0, 0x0 } },
 
 	// MIPI_DCS_SET_BRIGHTNESS 0000: 0%. FF07: 100%.
-	{ MIPI_DCS_SET_DISPLAY_BRIGHTNESS, 3, { 0x00, 0x00, 0x0 } },
+	{ 0x03, 7, { 0x00, 0x00, 0x51, 0x0, 0x0, 0x0, 0x0 } },
 
 	{
 		0xFF,
@@ -353,22 +357,21 @@ static void nx_panel_detect(struct nx_panel *nx)
 
 	printk("nx_panel_detect");
 
-	memset(nx->display_id, 0, sizeof(nx->display_id));
+	memset(&(nx->display_id), 0, sizeof(nx->display_id));
 
 	ret = mipi_dsi_dcs_read(nx->dsi, MIPI_DCS_GET_DISPLAY_ID,
-				nx->display_id, sizeof(nx->display_id));
+				&(nx->display_id), sizeof(nx->display_id));
 	if (ret < 0) {
 		dev_err(&nx->dsi->dev, "failed to read panel ID: %d\n", ret);
 	} else {
-		dev_info(&nx->dsi->dev, "display ID[%d]: %02x %02x %02x\n",
-			 ret, nx->display_id[0], nx->display_id[1],
-			 nx->display_id[2]);
+		dev_info(&nx->dsi->dev, "display ID[%d]: %04x\n",
+			 ret, nx->display_id);
 	}
 
 	dev_info(&nx->dsi->dev,
-		 "setting init sequence for ID %02x\n", nx->display_id[0]);
+		 "setting init sequence for ID %04x\n", nx->display_id);
 
-	switch (nx->display_id[0]) {
+	switch (nx->display_id) {
 	case PANEL_JDI_XXX062M:
 		nx->init_cmds = init_cmds_PANEL_JDI_XXX062M;
 		break;
@@ -391,9 +394,9 @@ static void nx_panel_detect(struct nx_panel *nx)
 	}
 
 	dev_info(&nx->dsi->dev,
-		"setting suspend sequence for ID %02x\n", nx->display_id[0]);
+		"setting suspend sequence for ID %04x\n", nx->display_id);
 
-	switch (nx->display_id[0]) {
+	switch (nx->display_id) {
 	case PANEL_JDI_XXX062M:
 		nx->suspend_cmds = suspend_cmds_PANEL_JDI_XXX062M;
 		break;

drivers/memory/tegra/tegra186-emc.c

@@ -516,6 +516,9 @@ static const struct of_device_id tegra186_emc_of_match[] = {
 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
 	{ .compatible = "nvidia,tegra186-emc" },
 #endif
+#if defined(CONFIG_ARCH_TEGRA_210_SOC)
+	{ .compatible = "nvidia,tegra210b01-emc" },
+#endif
 #if defined(CONFIG_ARCH_TEGRA_194_SOC)
 	{ .compatible = "nvidia,tegra194-emc" },
 #endif

gki/aarch64/abi.stg

@@ -125397,23 +125397,29 @@ member {
   offset: 2880
 }
 member {
-  id: 0x8998723d
-  name: "gpu_process_id"
+  id: 0x716f03bc
+  name: "gpu_iddq_value"
   type_id: 0x6720d32f
-  offset: 256
+  offset: 384
 }
 member {
-  id: 0xc59015c8
-  name: "gpu_speedo_id"
+  id: 0x8998764f
+  name: "gpu_process_id"
   type_id: 0x6720d32f
   offset: 288
 }
 member {
-  id: 0x1839ab9c
-  name: "gpu_speedo_value"
+  id: 0xc59016d6
+  name: "gpu_speedo_id"
   type_id: 0x6720d32f
   offset: 320
 }
+member {
+  id: 0x1839a802
+  name: "gpu_speedo_value"
+  type_id: 0x6720d32f
+  offset: 352
+}
 member {
   id: 0x220ee7b2
   name: "gpuva"
@@ -189897,10 +189903,10 @@ member {
   bitsize: 1
 }
 member {
-  id: 0x2bdf1e4c
+  id: 0x2bdf18a9
   name: "platform"
   type_id: 0x4bb568ad
-  offset: 384
+  offset: 448
 }
 member {
   id: 0x38c654ae
@@ -210651,10 +210657,10 @@ member {
   offset: 12480
 }
 member {
-  id: 0x94eb2e6e
+  id: 0x94eb2857
   name: "revision"
   type_id: 0x43f6ac22
-  offset: 352
+  offset: 416
 }
 member {
   id: 0xbcd2bfaa
@@ -227338,6 +227344,12 @@ member {
   type_id: 0x3e10b518
   offset: 256
 }
+member {
+  id: 0x97cc708c
+  name: "soc_iddq_value"
+  type_id: 0x6720d32f
+  offset: 256
+}
 member {
   id: 0x8d753502
   name: "soc_process_id"
@@ -228117,6 +228129,12 @@ member {
   type_id: 0xc9082b19
   offset: 704
 }
+member {
+  id: 0x9b8091d9
+  name: "speedo_rev"
+  type_id: 0x6720d32f
+  offset: 512
+}
 member {
   id: 0xd0391586
   name: "spi"
@@ -248697,6 +248715,12 @@ member {
   type_id: 0x790929c4
   offset: 8512
 }
+member {
+  id: 0xe7a15159
+  name: "ucm"
+  type_id: 0x7c124706
+  offset: 480
+}
 member {
   id: 0x14b7816e
   name: "ucontext"
@@ -340766,7 +340790,7 @@ struct_union {
   kind: STRUCT
   name: "tegra_sku_info"
   definition {
-    bytesize: 52
+    bytesize: 68
     member_id: 0x159f315d
     member_id: 0x7be41b46
     member_id: 0x9bd81e85
@@ -340775,11 +340799,15 @@ struct_union {
     member_id: 0x8d753502
     member_id: 0x509bfc34
     member_id: 0x0ef921fa
-    member_id: 0x8998723d
-    member_id: 0xc59015c8
-    member_id: 0x1839ab9c
-    member_id: 0x94eb2e6e
-    member_id: 0x2bdf1e4c
+    member_id: 0x97cc708c
+    member_id: 0x8998764f
+    member_id: 0xc59016d6
+    member_id: 0x1839a802
+    member_id: 0x716f03bc
+    member_id: 0x94eb2857
+    member_id: 0x2bdf18a9
+    member_id: 0xe7a15159
+    member_id: 0x9b8091d9
   }
 }
 struct_union {
@@ -370359,9 +370387,27 @@ enumeration {
       value: 5
     }
     enumerator {
-      name: "TEGRA_REVISION_MAX"
+      name: "TEGRA_REVISION_B01"
       value: 6
     }
+    enumerator {
+      name: "TEGRA_REVISION_MAX"
+      value: 7
+    }
+  }
+}
+enumeration {
+  id: 0x7c124706
+  name: "tegra_ucm"
+  definition {
+    underlying_type_id: 0x4585663f
+    enumerator {
+      name: "TEGRA_UCM1"
+    }
+    enumerator {
+      name: "TEGRA_UCM2"
+      value: 1
+    }
   }
 }
 enumeration {
@@ -505039,7 +505085,7 @@ elf_symbol {
   name: "tegra_sku_info"
   is_defined: true
   symbol_type: OBJECT
-  crc: 0xbbcfcffc
+  crc: 0xe4a4fdfb
   type_id: 0x539be05c
   full_name: "tegra_sku_info"
 }

gki/aarch64/symbols/tegra

@@ -720,11 +720,14 @@
   memstart_addr
   mipi_dsi_attach
   mipi_dsi_create_packet
+  mipi_dsi_dcs_read
+  mipi_dsi_dcs_set_pixel_format
   mipi_dsi_detach
   mipi_dsi_driver_register_full
   mipi_dsi_driver_unregister
   mipi_dsi_host_register
   mipi_dsi_host_unregister
+  mipi_dsi_set_maximum_return_packet_size
   misc_deregister
   misc_register
   __mmap_lock_do_trace_acquire_returned
@@ -2019,11 +2022,15 @@
   devm_of_find_backlight
   mipi_dsi_dcs_enter_sleep_mode
   mipi_dsi_dcs_exit_sleep_mode
-  mipi_dsi_dcs_read
   mipi_dsi_dcs_set_display_off
   mipi_dsi_dcs_set_display_on
-  mipi_dsi_dcs_set_pixel_format
-  mipi_dsi_set_maximum_return_packet_size
+
+# required by panel-nx-dsi.ko
+  mipi_dsi_dcs_set_column_address
+  mipi_dsi_dcs_set_page_address
+  mipi_dsi_dcs_set_tear_on
+  mipi_dsi_dcs_write
+  of_find_backlight_by_node
 
 # required by panel-simple.ko
   drm_bus_flags_from_videomode