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pinctrl: samsung: add dedicated SoC eint suspend/resume callbacks

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[ Upstream commit 77ac6b742eba063a5b6600cda67834a7a212281a ]

Refactor the existing platform specific suspend/resume callback
so that each SoC variant has it's own callback containing the
SoC specific logic.

This allows exynosautov920 to have a dedicated function for using
eint_con_offset and eint_mask_offset. Also it is easily extendable
for gs101 which will need dedicated logic for handling the varying
register offset of fltcon0 via eint_fltcon_offset.

Reviewed-by: André Draszik <andre.draszik@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20250402-pinctrl-fltcon-suspend-v6-2-78ce0d4eb30c@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Stable-dep-of: bdbe0a0f7100 ("pinctrl: samsung: add gs101 specific eint suspend/resume callbacks")
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Peter Griffin
2025-04-02 16:17:31 +01:00
committed by Greg Kroah-Hartman
parent d5d5193dde
commit f33266ec35
3 changed files with 105 additions and 93 deletions
Download Patch File Download Diff File Expand all files Collapse all files

28
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
View File

@@ -809,8 +809,8 @@ static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = {
.pin_banks = exynosautov920_pin_banks0,
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks0),
.eint_wkup_init = exynos_eint_wkup_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.suspend = exynosautov920_pinctrl_suspend,
.resume = exynosautov920_pinctrl_resume,
.retention_data = &exynosautov920_retention_data,
}, {
/* pin-controller instance 1 AUD data */
@@ -821,43 +821,43 @@ static const struct samsung_pin_ctrl exynosautov920_pin_ctrl[] = {
.pin_banks = exynosautov920_pin_banks2,
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks2),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.suspend = exynosautov920_pinctrl_suspend,
.resume = exynosautov920_pinctrl_resume,
}, {
/* pin-controller instance 3 HSI1 data */
.pin_banks = exynosautov920_pin_banks3,
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks3),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.suspend = exynosautov920_pinctrl_suspend,
.resume = exynosautov920_pinctrl_resume,
}, {
/* pin-controller instance 4 HSI2 data */
.pin_banks = exynosautov920_pin_banks4,
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks4),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.suspend = exynosautov920_pinctrl_suspend,
.resume = exynosautov920_pinctrl_resume,
}, {
/* pin-controller instance 5 HSI2UFS data */
.pin_banks = exynosautov920_pin_banks5,
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks5),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.suspend = exynosautov920_pinctrl_suspend,
.resume = exynosautov920_pinctrl_resume,
}, {
/* pin-controller instance 6 PERIC0 data */
.pin_banks = exynosautov920_pin_banks6,
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks6),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.suspend = exynosautov920_pinctrl_suspend,
.resume = exynosautov920_pinctrl_resume,
}, {
/* pin-controller instance 7 PERIC1 data */
.pin_banks = exynosautov920_pin_banks7,
.nr_banks = ARRAY_SIZE(exynosautov920_pin_banks7),
.eint_gpio_init = exynos_eint_gpio_init,
.suspend = exynos_pinctrl_suspend,
.resume = exynos_pinctrl_resume,
.suspend = exynosautov920_pinctrl_suspend,
.resume = exynosautov920_pinctrl_resume,
},
};

168
drivers/pinctrl/samsung/pinctrl-exynos.c
View File

@@ -761,105 +761,115 @@ __init int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
return 0;
}
static void exynos_pinctrl_suspend_bank(struct samsung_pin_bank *bank)
static void exynos_set_wakeup(struct samsung_pin_bank *bank)
{
struct exynos_eint_gpio_save *save = bank->soc_priv;
const void __iomem *regs = bank->eint_base;
struct exynos_irq_chip *irq_chip;
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
+ bank->eint_offset);
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+ 2 * bank->eint_offset);
save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+ 2 * bank->eint_offset + 4);
save->eint_mask = readl(regs + bank->irq_chip->eint_mask
+ bank->eint_offset);
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
}
static void exynosauto_pinctrl_suspend_bank(struct samsung_pin_bank *bank)
{
struct exynos_eint_gpio_save *save = bank->soc_priv;
const void __iomem *regs = bank->eint_base;
save->eint_con = readl(regs + bank->pctl_offset + bank->eint_con_offset);
save->eint_mask = readl(regs + bank->pctl_offset + bank->eint_mask_offset);
pr_debug("%s: save con %#010x\n", bank->name, save->eint_con);
pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask);
if (bank->irq_chip) {
irq_chip = bank->irq_chip;
irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip);
}
}
void exynos_pinctrl_suspend(struct samsung_pin_bank *bank)
{
struct exynos_irq_chip *irq_chip = NULL;
struct exynos_eint_gpio_save *save = bank->soc_priv;
const void __iomem *regs = bank->eint_base;
if (bank->eint_type == EINT_TYPE_GPIO) {
if (bank->eint_con_offset)
exynosauto_pinctrl_suspend_bank(bank);
else
exynos_pinctrl_suspend_bank(bank);
save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
+ bank->eint_offset);
save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+ 2 * bank->eint_offset);
save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+ 2 * bank->eint_offset + 4);
save->eint_mask = readl(regs + bank->irq_chip->eint_mask
+ bank->eint_offset);
pr_debug("%s: save con %#010x\n",
bank->name, save->eint_con);
pr_debug("%s: save fltcon0 %#010x\n",
bank->name, save->eint_fltcon0);
pr_debug("%s: save fltcon1 %#010x\n",
bank->name, save->eint_fltcon1);
pr_debug("%s: save mask %#010x\n",
bank->name, save->eint_mask);
} else if (bank->eint_type == EINT_TYPE_WKUP) {
if (!irq_chip) {
irq_chip = bank->irq_chip;
irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip);
}
exynos_set_wakeup(bank);
}
}
static void exynos_pinctrl_resume_bank(struct samsung_pin_bank *bank)
void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank)
{
struct exynos_eint_gpio_save *save = bank->soc_priv;
void __iomem *regs = bank->eint_base;
pr_debug("%s: con %#010x => %#010x\n", bank->name,
readl(regs + EXYNOS_GPIO_ECON_OFFSET
+ bank->eint_offset), save->eint_con);
pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+ 2 * bank->eint_offset), save->eint_fltcon0);
pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+ 2 * bank->eint_offset + 4), save->eint_fltcon1);
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
readl(regs + bank->irq_chip->eint_mask
+ bank->eint_offset), save->eint_mask);
writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
+ bank->eint_offset);
writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+ 2 * bank->eint_offset);
writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+ 2 * bank->eint_offset + 4);
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
+ bank->eint_offset);
}
static void exynosauto_pinctrl_resume_bank(struct samsung_pin_bank *bank)
{
struct exynos_eint_gpio_save *save = bank->soc_priv;
void __iomem *regs = bank->eint_base;
pr_debug("%s: con %#010x => %#010x\n", bank->name,
readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con);
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_mask);
writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset);
writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset);
const void __iomem *regs = bank->eint_base;
if (bank->eint_type == EINT_TYPE_GPIO) {
save->eint_con = readl(regs + bank->pctl_offset +
bank->eint_con_offset);
save->eint_mask = readl(regs + bank->pctl_offset +
bank->eint_mask_offset);
pr_debug("%s: save con %#010x\n",
bank->name, save->eint_con);
pr_debug("%s: save mask %#010x\n",
bank->name, save->eint_mask);
} else if (bank->eint_type == EINT_TYPE_WKUP) {
exynos_set_wakeup(bank);
}
}
void exynos_pinctrl_resume(struct samsung_pin_bank *bank)
{
struct exynos_eint_gpio_save *save = bank->soc_priv;
void __iomem *regs = bank->eint_base;
if (bank->eint_type == EINT_TYPE_GPIO) {
if (bank->eint_con_offset)
exynosauto_pinctrl_resume_bank(bank);
else
exynos_pinctrl_resume_bank(bank);
pr_debug("%s: con %#010x => %#010x\n", bank->name,
readl(regs + EXYNOS_GPIO_ECON_OFFSET
+ bank->eint_offset), save->eint_con);
pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+ 2 * bank->eint_offset), save->eint_fltcon0);
pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+ 2 * bank->eint_offset + 4),
save->eint_fltcon1);
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
readl(regs + bank->irq_chip->eint_mask
+ bank->eint_offset), save->eint_mask);
writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
+ bank->eint_offset);
writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+ 2 * bank->eint_offset);
writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+ 2 * bank->eint_offset + 4);
writel(save->eint_mask, regs + bank->irq_chip->eint_mask
+ bank->eint_offset);
}
}
void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank)
{
struct exynos_eint_gpio_save *save = bank->soc_priv;
void __iomem *regs = bank->eint_base;
if (bank->eint_type == EINT_TYPE_GPIO) {
/* exynosautov920 has eint_con_offset for all but one bank */
if (!bank->eint_con_offset)
exynos_pinctrl_resume(bank);
pr_debug("%s: con %#010x => %#010x\n", bank->name,
readl(regs + bank->pctl_offset + bank->eint_con_offset),
save->eint_con);
pr_debug("%s: mask %#010x => %#010x\n", bank->name,
readl(regs + bank->pctl_offset +
bank->eint_mask_offset), save->eint_mask);
writel(save->eint_con,
regs + bank->pctl_offset + bank->eint_con_offset);
writel(save->eint_mask,
regs + bank->pctl_offset + bank->eint_mask_offset);
}
}

2
drivers/pinctrl/samsung/pinctrl-exynos.h
View File

@@ -211,6 +211,8 @@ struct exynos_muxed_weint_data {
int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d);
int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d);
void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank);
void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank);
void exynos_pinctrl_suspend(struct samsung_pin_bank *bank);
void exynos_pinctrl_resume(struct samsung_pin_bank *bank);
struct samsung_retention_ctrl *