tmakin/ack-tegra
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch/tile: catch up on various minor cleanups.

Browse Source 
None of these changes fix any actual bugs, but are just various cleanups
that fell out along the way.  In particular, some unused #defines and
includes are removed, PREFETCH_STRIDE is added (the default is right for
our shipping chips, but wrong for our next generation), our tile-specific
prefetching code is removed so the (identical) generic prefetching code
can be used instead, a comment is fixed to be proper GPL and not just a
"paste GPL here" token, a "//" comment is converted to "/* */", etc.

Signed-off-by: Chris Metcalf <cmetcalf@tilera.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Chris Metcalf
2010-07-02 14:19:35 -04:00
parent bcd97c3f9a
commit ef06f55a5c
7 changed files with 16 additions and 41 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/tile/include/asm/cache.h
-5
View File
@@ -21,11 +21,6 @@
#define L1_CACHE_SHIFT CHIP_L1D_LOG_LINE_SIZE()
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
/* bytes per L1 instruction cache line */
#define L1I_CACHE_SHIFT CHIP_L1I_LOG_LINE_SIZE()
#define L1I_CACHE_BYTES (1 << L1I_CACHE_SHIFT)
#define L1I_CACHE_ALIGN(x) (((x)+(L1I_CACHE_BYTES-1)) & -L1I_CACHE_BYTES)
/* bytes per L2 cache line */
#define L2_CACHE_SHIFT CHIP_L2_LOG_LINE_SIZE()
#define L2_CACHE_BYTES (1 << L2_CACHE_SHIFT)