ARC: Fix typos
Fix typos, most reported by "codespell arch/arc". Only touches comments, no code changes. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Vineet Gupta <vgupta@kernel.org>
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Bjorn Helgaas
committed by
Vineet Gupta
Vineet Gupta
parent
d5272aaa82
commit
ebfc2fd887
@@ -12,7 +12,7 @@
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/*
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* DSP-related saved registers - need to be saved only when you are
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* scheduled out.
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* structure fields name must correspond to aux register defenitions for
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* structure fields name must correspond to aux register definitions for
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* automatic offset calculation in DSP_AUX_SAVE_RESTORE macros
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*/
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struct dsp_callee_regs {
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@@ -7,7 +7,7 @@
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* Stack switching code can no longer reliably rely on the fact that
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* if we are NOT in user mode, stack is switched to kernel mode.
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* e.g. L2 IRQ interrupted a L1 ISR which had not yet completed
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* it's prologue including stack switching from user mode
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* its prologue including stack switching from user mode
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*
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* Vineetg: Aug 28th 2008: Bug #94984
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* -Zero Overhead Loop Context shd be cleared when entering IRQ/EXcp/Trap
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@@ -143,7 +143,7 @@
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* 2. L1 IRQ taken, ISR starts (CPU auto-switched to KERNEL mode)
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* 3. But before it could switch SP from USER to KERNEL stack
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* a L2 IRQ "Interrupts" L1
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* Thay way although L2 IRQ happened in Kernel mode, stack is still
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* That way although L2 IRQ happened in Kernel mode, stack is still
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* not switched.
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* To handle this, we may need to switch stack even if in kernel mode
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* provided SP has values in range of USER mode stack ( < 0x7000_0000 )
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@@ -173,7 +173,7 @@
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GET_CURR_TASK_ON_CPU r9
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/* With current tsk in r9, get it's kernel mode stack base */
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/* With current tsk in r9, get its kernel mode stack base */
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GET_TSK_STACK_BASE r9, r9
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/* save U mode SP @ pt_regs->sp */
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@@ -282,7 +282,7 @@
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* NOTE:
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*
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* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
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* for memory load operations. If used in that way interrupts are deffered
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* for memory load operations. If used in that way interrupts are deferred
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* by hardware and that is not good.
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*-------------------------------------------------------------*/
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.macro EXCEPTION_EPILOGUE
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@@ -350,7 +350,7 @@
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* NOTE:
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*
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* It is recommended that lp_count/ilink1/ilink2 not be used as a dest reg
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* for memory load operations. If used in that way interrupts are deffered
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* for memory load operations. If used in that way interrupts are deferred
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* by hardware and that is not good.
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*-------------------------------------------------------------*/
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.macro INTERRUPT_EPILOGUE LVL
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@@ -7,7 +7,7 @@
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#ifndef __ASM_ARC_ENTRY_H
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#define __ASM_ARC_ENTRY_H
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#include <asm/unistd.h> /* For NR_syscalls defination */
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#include <asm/unistd.h> /* For NR_syscalls definition */
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#include <asm/arcregs.h>
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#include <asm/ptrace.h>
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#include <asm/processor.h> /* For VMALLOC_START */
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@@ -56,7 +56,7 @@
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.endm
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/*-------------------------------------------------------------
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* given a tsk struct, get to the base of it's kernel mode stack
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* given a tsk struct, get to the base of its kernel mode stack
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* tsk->thread_info is really a PAGE, whose bottom hoists stack
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* which grows upwards towards thread_info
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*------------------------------------------------------------*/
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@@ -10,7 +10,7 @@
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* ARCv2 can support 240 interrupts in the core interrupts controllers and
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* 128 interrupts in IDU. Thus 512 virtual IRQs must be enough for most
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* configurations of boards.
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* This doesnt affect ARCompact, but we change it to same value
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* This doesn't affect ARCompact, but we change it to same value
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*/
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#define NR_IRQS 512
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@@ -46,7 +46,7 @@
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* IRQ Control Macros
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*
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* All of them have "memory" clobber (compiler barrier) which is needed to
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* ensure that LD/ST requiring irq safetly (R-M-W when LLSC is not available)
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* ensure that LD/ST requiring irq safety (R-M-W when LLSC is not available)
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* are redone after IRQs are re-enabled (and gcc doesn't reuse stale register)
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*
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* Noted at the time of Abilis Timer List corruption
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@@ -165,7 +165,7 @@ static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
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* for retiring-mm. However destroy_context( ) still needs to do that because
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* between mm_release( ) = >deactive_mm( ) and
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* mmput => .. => __mmdrop( ) => destroy_context( )
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* there is a good chance that task gets sched-out/in, making it's ASID valid
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* there is a good chance that task gets sched-out/in, making its ASID valid
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* again (this teased me for a whole day).
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*/
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@@ -66,7 +66,7 @@
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* Other rules which cause the divergence from 1:1 mapping
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*
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* 1. Although ARC700 can do exclusive execute/write protection (meaning R
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* can be tracked independet of X/W unlike some other CPUs), still to
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* can be tracked independently of X/W unlike some other CPUs), still to
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* keep things consistent with other archs:
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* -Write implies Read: W => R
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* -Execute implies Read: X => R
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@@ -6,7 +6,7 @@
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#ifndef __ARC_ASM_SHMPARAM_H
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#define __ARC_ASM_SHMPARAM_H
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/* Handle upto 2 cache bins */
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/* Handle up to 2 cache bins */
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#define SHMLBA (2 * PAGE_SIZE)
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/* Enforce SHMLBA in shmat */
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@@ -77,7 +77,7 @@ static inline const char *arc_platform_smp_cpuinfo(void)
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/*
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* ARC700 doesn't support atomic Read-Modify-Write ops.
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* Originally Interrupts had to be disabled around code to gaurantee atomicity.
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* Originally Interrupts had to be disabled around code to guarantee atomicity.
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* The LLOCK/SCOND insns allow writing interrupt-hassle-free based atomic ops
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* based on retry-if-irq-in-atomic (with hardware assist).
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* However despite these, we provide the IRQ disabling variant
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@@ -86,7 +86,7 @@ static inline const char *arc_platform_smp_cpuinfo(void)
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* support needed.
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*
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* (2) In a SMP setup, the LLOCK/SCOND atomicity across CPUs needs to be
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* gaurantted by the platform (not something which core handles).
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* guaranteed by the platform (not something which core handles).
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* Assuming a platform won't, SMP Linux needs to use spinlocks + local IRQ
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* disabling for atomicity.
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*
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@@ -38,7 +38,7 @@
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struct thread_info {
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unsigned long flags; /* low level flags */
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unsigned long ksp; /* kernel mode stack top in __switch_to */
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int preempt_count; /* 0 => preemptable, <0 => BUG */
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int preempt_count; /* 0 => preemptible, <0 => BUG */
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int cpu; /* current CPU */
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unsigned long thr_ptr; /* TLS ptr */
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struct task_struct *task; /* main task structure */
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@@ -62,7 +62,7 @@
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* 8051fdc4: st r2,[r1,20] ; Mem op : save result back to mem
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*
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* Joern suggested a better "C" algorithm which is great since
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* (1) It is portable to any architecure
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* (1) It is portable to any architecture
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* (2) At the same time it takes advantage of ARC ISA (rotate intrns)
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*/
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