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Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

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* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (76 commits)
  [ARM] 4002/1: S3C24XX: leave parent IRQs unmasked
  [ARM] 4001/1: S3C24XX: shorten reboot time
  [ARM] 3983/2: remove unused argument to __bug()
  [ARM] 4000/1: Osiris: add third serial port in
  [ARM] 3999/1: RX3715: suspend to RAM support
  [ARM] 3998/1: VR1000: LED platform devices
  [ARM] 3995/1: iop13xx: add iop13xx support
  [ARM] 3968/1: iop13xx: add iop13xx_defconfig
  [ARM] Update mach-types
  [ARM] Allow gcc to optimise arm_add_memory a little more
  [ARM] 3991/1: i.MX/MX1 high resolution time source
  [ARM] 3990/1: i.MX/MX1 more precise PLL decode
  [ARM] 3986/1: H1940: suspend to RAM support
  [ARM] 3985/1: ixp4xx clocksource cleanup
  [ARM] 3984/1: ixp4xx/nslu2: Fix disk LED numbering (take 2)
  [ARM] 3994/1: ixp23xx: fix handling of pci master aborts
  [ARM] 3981/1: sched_clock for PXA2xx
  [ARM] 3980/1: extend the ARM Versatile sched_clock implementation from 32 to 63 bit
  [ARM] 3979/1: extend the SA11x0 sched_clock implementation from 32 to 63 bit period
  [ARM] 3978/1: macro to provide a 63-bit value from a 32-bit hardware counter
  ...
This commit is contained in:
Linus Torvalds
2006-12-07 15:40:39 -08:00
parent 6ee7e78e7c 6705cda24f
commit ea14fad0d4
290 changed files with 13141 additions and 1986 deletions
Download Patch File Download Diff File Expand all files Collapse all files
include/asm-arm/arch-aaec2000/memory.h
+1 -39
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@@ -17,8 +17,6 @@
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#ifdef CONFIG_DISCONTIGMEM
/*
* The nodes are the followings:
*
@@ -27,42 +25,6 @@
* node 2: 0xf800.0000 - 0xfbff.ffff
* node 3: 0xfc00.0000 - 0xffff.ffff
*/
/*
* Given a kernel address, find the home node of the underlying memory.
*/
#define KVADDR_TO_NID(addr) \
(((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
/*
* Given a page frame number, convert it to a node id.
*/
#define PFN_TO_NID(pfn) \
(((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
/*
* Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
* and return the mem_map of that node.
*/
#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
/*
* Given a page frame number, find the owning node of the memory
* and return the mem_map of that node.
*/
#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
/*
* Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
* and returns the index corresponding to the appropriate page in the
* node's mem_map.
*/
#define LOCAL_MAP_NR(addr) \
(((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
#define NODE_MAX_MEM_SHIFT 26
#define NODE_MAX_MEM_SIZE (1 << NODE_MAX_MEM_SHIFT)
#endif /* CONFIG_DISCONTIGMEM */
#define NODE_MEM_SIZE_BITS 26
#endif /* __ASM_ARCH_MEMORY_H */
include/asm-arm/arch-at91rm9200/at91_aic.h
+53
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@@ -0,0 +1,53 @@
/*
* include/asm-arm/arch-at91rm9200/at91_aic.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Advanced Interrupt Controller (AIC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_AIC_H
#define AT91_AIC_H
#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
#define AT91_AIC_SRCTYPE_LOW (0 << 5)
#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
#define AT91_AIC_SRCTYPE_RISING (3 << 5)
#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
#endif
include/asm-arm/arch-at91rm9200/at91_dbgu.h
+45
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@@ -0,0 +1,45 @@
/*
* include/asm-arm/arch-at91rm9200/at91_dbgu.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Debug Unit (DBGU) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_DBGU_H
#define AT91_DBGU_H
#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
#define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */
#define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */
#endif
include/asm-arm/arch-at91rm9200/at91_ecc.h
+38
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@@ -0,0 +1,38 @@
/*
* include/asm-arm/arch-at91rm9200/at91_ecc.h
*
* Error Corrected Code Controller (ECC) - System peripherals regsters.
* Based on AT91SAM9260 datasheet revision B.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef AT91_ECC_H
#define AT91_ECC_H
#define AT91_ECC_CR (AT91_ECC + 0x00) /* Control register */
#define AT91_ECC_RST (1 << 0) /* Reset parity */
#define AT91_ECC_MR (AT91_ECC + 0x04) /* Mode register */
#define AT91_ECC_PAGESIZE (3 << 0) /* Page Size */
#define AT91_ECC_PAGESIZE_528 (0)
#define AT91_ECC_PAGESIZE_1056 (1)
#define AT91_ECC_PAGESIZE_2112 (2)
#define AT91_ECC_PAGESIZE_4224 (3)
#define AT91_ECC_SR (AT91_ECC + 0x08) /* Status register */
#define AT91_ECC_RECERR (1 << 0) /* Recoverable Error */
#define AT91_ECC_ECCERR (1 << 1) /* ECC Single Bit Error */
#define AT91_ECC_MULERR (1 << 2) /* Multiple Errors */
#define AT91_ECC_PR (AT91_ECC + 0x0c) /* Parity register */
#define AT91_ECC_BITADDR (0xf << 0) /* Bit Error Address */
#define AT91_ECC_WORDADDR (0xfff << 4) /* Word Error Address */
#define AT91_ECC_NPR (AT91_ECC + 0x10) /* NParity register */
#define AT91_ECC_NPARITY (0xffff << 0) /* NParity */
#endif
include/asm-arm/arch-at91rm9200/at91_lcdc.h
+148
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@@ -0,0 +1,148 @@
/*
* include/asm-arm/arch-at91rm9200/at91_lcdc.h
*
* LCD Controller (LCDC).
* Based on AT91SAM9261 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_LCDC_H
#define AT91_LCDC_H
#define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */
#define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */
#define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */
#define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */
#define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */
#define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */
#define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */
#define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */
#define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */
#define AT91_LCDC_DMACON 0x1c /* DMA Control Register */
#define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */
#define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */
#define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */
#define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */
#define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */
#define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */
#define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */
#define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */
#define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */
#define AT91_LCDC_DISTYPE_STNMONO (0 << 0)
#define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0)
#define AT91_LCDC_DISTYPE_TFT (2 << 0)
#define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */
#define AT91_LCDC_SCANMOD_SINGLE (0 << 2)
#define AT91_LCDC_SCANMOD_DUAL (1 << 2)
#define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */
#define AT91_LCDC_IFWIDTH_4 (0 << 3)
#define AT91_LCDC_IFWIDTH_8 (1 << 3)
#define AT91_LCDC_IFWIDTH_16 (2 << 3)
#define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */
#define AT91_LCDC_PIXELSIZE_1 (0 << 5)
#define AT91_LCDC_PIXELSIZE_2 (1 << 5)
#define AT91_LCDC_PIXELSIZE_4 (2 << 5)
#define AT91_LCDC_PIXELSIZE_8 (3 << 5)
#define AT91_LCDC_PIXELSIZE_16 (4 << 5)
#define AT91_LCDC_PIXELSIZE_24 (5 << 5)
#define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */
#define AT91_LCDC_INVVD_NORMAL (0 << 8)
#define AT91_LCDC_INVVD_INVERTED (1 << 8)
#define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */
#define AT91_LCDC_INVFRAME_NORMAL (0 << 9)
#define AT91_LCDC_INVFRAME_INVERTED (1 << 9)
#define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */
#define AT91_LCDC_INVLINE_NORMAL (0 << 10)
#define AT91_LCDC_INVLINE_INVERTED (1 << 10)
#define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */
#define AT91_LCDC_INVCLK_NORMAL (0 << 11)
#define AT91_LCDC_INVCLK_INVERTED (1 << 11)
#define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */
#define AT91_LCDC_INVDVAL_NORMAL (0 << 12)
#define AT91_LCDC_INVDVAL_INVERTED (1 << 12)
#define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */
#define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
#define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
#define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */
#define AT91_LCDC_MEMOR_BIG (0 << 31)
#define AT91_LCDC_MEMOR_LITTLE (1 << 31)
#define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */
#define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */
#define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */
#define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */
#define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */
#define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */
#define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */
#define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */
#define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */
#define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */
#define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */
#define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */
#define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */
#define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */
#define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */
#define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */
#define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */
#define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */
#define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */
#define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */
#define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */
#define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */
#define AT91_LCDC_DP1_2_VAL (0xff)
#define AT91_LCDC_DP4_7_VAL (0xfffffff)
#define AT91_LCDC_DP3_5_VAL (0xfffff)
#define AT91_LCDC_DP2_3_VAL (0xfff)
#define AT91_LCDC_DP5_7_VAL (0xfffffff)
#define AT91_LCDC_DP3_4_VAL (0xffff)
#define AT91_LCDC_DP4_5_VAL (0xfffff)
#define AT91_LCDC_DP6_7_VAL (0xfffffff)
#define AT91_LCDC_PWRCON 0x083c /* Power Control Register */
#define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */
#define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */
#define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */
#define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */
#define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */
#define AT91_LCDC_PS_DIV1 (0 << 0)
#define AT91_LCDC_PS_DIV2 (1 << 0)
#define AT91_LCDC_PS_DIV4 (2 << 0)
#define AT91_LCDC_PS_DIV8 (3 << 0)
#define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */
#define AT91_LCDC_POL_NEGATIVE (0 << 2)
#define AT91_LCDC_POL_POSITIVE (1 << 2)
#define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */
#define AT91_LCDC_ENA_PWMDISABLE (0 << 3)
#define AT91_LCDC_ENA_PWMENABLE (1 << 3)
#define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */
#define AT91_LCDC_CVAL (0xff) /* PWM compare value */
#define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */
#define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */
#define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */
#define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */
#define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */
#define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */
#define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */
#define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */
#define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */
#define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */
#define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */
#define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */
#endif
include/asm-arm/arch-at91rm9200/at91rm9200_mci.h → include/asm-arm/arch-at91rm9200/at91_mci.h
+13 -11
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@@ -1,11 +1,11 @@
/*
* include/asm-arm/arch-at91rm9200/at91rm9200_mci.h
* include/asm-arm/arch-at91rm9200/at91_mci.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* MultiMedia Card Interface (MCI) registers.
* Based on AT91RM9200 datasheet revision E.
* Based on AT91RM9200 datasheet revision F.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -13,8 +13,8 @@
* (at your option) any later version.
*/
#ifndef AT91RM9200_MCI_H
#define AT91RM9200_MCI_H
#ifndef AT91_MCI_H
#define AT91_MCI_H
#define AT91_MCI_CR 0x00 /* Control Register */
#define AT91_MCI_MCIEN (1 << 0) /* Multi-Media Interface Enable */
@@ -25,10 +25,10 @@
#define AT91_MCI_MR 0x04 /* Mode Register */
#define AT91_MCI_CLKDIV (0xff << 0) /* Clock Divider */
#define AT91_MCI_PWSDIV (3 << 8) /* Power Saving Divider */
#define AT91_MCI_PWSDIV (7 << 8) /* Power Saving Divider */
#define AT91_MCI_PDCPADV (1 << 14) /* PDC Padding Value */
#define AT91_MCI_PDCMODE (1 << 15) /* PDC-orientated Mode */
#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
#define AT91_MCI_BLKLEN (0xfff << 18) /* Data Block Length */
#define AT91_MCI_DTOR 0x08 /* Data Timeout Register */
#define AT91_MCI_DTOCYC (0xf << 0) /* Data Timeout Cycle Number */
@@ -43,8 +43,8 @@
#define AT91_MCI_DTOMUL_1M (7 << 4)
#define AT91_MCI_SDCR 0x0c /* SD Card Register */
#define AT91_MCI_SDCSEL (0xf << 0) /* SD Card Selector */
#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
#define AT91_MCI_SDCSEL (3 << 0) /* SD Card Selector */
#define AT91_MCI_SDCBUS (1 << 7) /* 1-bit or 4-bit bus */
#define AT91_MCI_ARGR 0x10 /* Argument Register */
@@ -78,18 +78,20 @@
#define AT91_MCI_SR 0x40 /* Status Register */
#define AT91_MCI_CMDRDY (1 << 0) /* Command Ready */
#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */
#define AT91_MCI_RXRDY (1 << 1) /* Receiver Ready */
#define AT91_MCI_TXRDY (1 << 2) /* Transmit Ready */
#define AT91_MCI_BLKE (1 << 3) /* Data Block Ended */
#define AT91_MCI_DTIP (1 << 4) /* Data Transfer in Progress */
#define AT91_MCI_NOTBUSY (1 << 5) /* Data Not Busy */
#define AT91_MCI_ENDRX (1 << 6) /* End of RX Buffer */
#define AT91_MCI_ENDTX (1 << 7) /* End fo TX Buffer */
#define AT91_MCI_SDIOIRQA (1 << 8) /* SDIO Interrupt for Slot A */
#define At91_MCI_SDIOIRQB (1 << 9) /* SDIO Interrupt for Slot B [AT91RM9200 only] */
#define AT91_MCI_RXBUFF (1 << 14) /* RX Buffer Full */
#define AT91_MCI_TXBUFE (1 << 15) /* TX Buffer Empty */
#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
#define AT91_MCI_RINDE (1 << 16) /* Response Index Error */
#define AT91_MCI_RDIRE (1 << 17) /* Response Direction Error */
#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */
#define AT91_MCI_RCRCE (1 << 18) /* Response CRC Error */
#define AT91_MCI_RENDE (1 << 19) /* Response End Bit Error */
#define AT91_MCI_RTOE (1 << 20) /* Reponse Time-out Error */
#define AT91_MCI_DCRCE (1 << 21) /* Data CRC Error */
include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h → include/asm-arm/arch-at91rm9200/at91_pdc.h
+3 -3
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@@ -1,5 +1,5 @@
/*
* include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
* include/asm-arm/arch-at91rm9200/at91_pdc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
@@ -13,8 +13,8 @@
* (at your option) any later version.
*/
#ifndef AT91RM9200_PDC_H
#define AT91RM9200_PDC_H
#ifndef AT91_PDC_H
#define AT91_PDC_H
#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
#define AT91_PDC_RCR 0x104 /* Receive Counter Register */
include/asm-arm/arch-at91rm9200/at91_pio.h
+49
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@@ -0,0 +1,49 @@
/*
* include/asm-arm/arch-at91rm9200/at91_pio.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Parallel I/O Controller (PIO) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PIO_H
#define AT91_PIO_H
#define PIO_PER 0x00 /* Enable Register */
#define PIO_PDR 0x04 /* Disable Register */
#define PIO_PSR 0x08 /* Status Register */
#define PIO_OER 0x10 /* Output Enable Register */
#define PIO_ODR 0x14 /* Output Disable Register */
#define PIO_OSR 0x18 /* Output Status Register */
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
#define PIO_SODR 0x30 /* Set Output Data Register */
#define PIO_CODR 0x34 /* Clear Output Data Register */
#define PIO_ODSR 0x38 /* Output Data Status Register */
#define PIO_PDSR 0x3c /* Pin Data Status Register */
#define PIO_IER 0x40 /* Interrupt Enable Register */
#define PIO_IDR 0x44 /* Interrupt Disable Register */
#define PIO_IMR 0x48 /* Interrupt Mask Register */
#define PIO_ISR 0x4c /* Interrupt Status Register */
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
#define PIO_PUER 0x64 /* Pull-up Enable Register */
#define PIO_PUSR 0x68 /* Pull-up Status Register */
#define PIO_ASR 0x70 /* Peripheral A Select Register */
#define PIO_BSR 0x74 /* Peripheral B Select Register */
#define PIO_ABSR 0x78 /* AB Status Register */
#define PIO_OWER 0xa0 /* Output Write Enable Register */
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
#define PIO_OWSR 0xa8 /* Output Write Status Register */
#endif
include/asm-arm/arch-at91rm9200/at91_pit.h
+29
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@@ -0,0 +1,29 @@
/*
* include/asm-arm/arch-at91rm9200/at91_pit.h
*
* Periodic Interval Timer (PIT) - System peripherals regsters.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PIT_H
#define AT91_PIT_H
#define AT91_PIT_MR (AT91_PIT + 0x00) /* Mode Register */
#define AT91_PIT_PITIEN (1 << 25) /* Timer Interrupt Enable */
#define AT91_PIT_PITEN (1 << 24) /* Timer Enabled */
#define AT91_PIT_PIV (0xfffff) /* Periodic Interval Value */
#define AT91_PIT_SR (AT91_PIT + 0x04) /* Status Register */
#define AT91_PIT_PITS (1 << 0) /* Timer Status */
#define AT91_PIT_PIVR (AT91_PIT + 0x08) /* Periodic Interval Value Register */
#define AT91_PIT_PIIR (AT91_PIT + 0x0c) /* Periodic Interval Image Register */
#define AT91_PIT_PICNT (0xfff << 20) /* Interval Counter */
#define AT91_PIT_CPIV (0xfffff) /* Inverval Value */
#endif
include/asm-arm/arch-at91rm9200/at91_pmc.h
+92
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@@ -0,0 +1,92 @@
/*
* include/asm-arm/arch-at91rm9200/at91_pmc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Power Management Controller (PMC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_PMC_H
#define AT91_PMC_H
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
#define AT91_PMC_DIV (0xff << 0) /* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
#define AT91_PMC_CSS_PLLA (2 << 0)
#define AT91_PMC_CSS_PLLB (3 << 0)
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
#define AT91_PMC_PRES_1 (0 << 2)
#define AT91_PMC_PRES_2 (1 << 2)
#define AT91_PMC_PRES_4 (2 << 2)
#define AT91_PMC_PRES_8 (3 << 2)
#define AT91_PMC_PRES_16 (4 << 2)
#define AT91_PMC_PRES_32 (5 << 2)
#define AT91_PMC_PRES_64 (6 << 2)
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
#define AT91_PMC_MDIV_1 (0 << 8)
#define AT91_PMC_MDIV_2 (1 << 8)
#define AT91_PMC_MDIV_3 (2 << 8)
#define AT91_PMC_MDIV_4 (3 << 8)
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
#endif
include/asm-arm/arch-at91rm9200/at91_rstc.h
+39
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@@ -0,0 +1,39 @@
/*
* include/asm-arm/arch-at91rm9200/at91_rstc.h
*
* Reset Controller (RSTC) - System peripherals regsters.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_RSTC_H
#define AT91_RSTC_H
#define AT91_RSTC_CR (AT91_RSTC + 0x00) /* Reset Controller Control Register */
#define AT91_RSTC_PROCRST (1 << 0) /* Processor Reset */
#define AT91_RSTC_PERRST (1 << 2) /* Peripheral Reset */
#define AT91_RSTC_EXTRST (1 << 3) /* External Reset */
#define AT01_RSTC_KEY (0xff << 24) /* KEY Password */
#define AT91_RSTC_SR (AT91_RSTC + 0x04) /* Reset Controller Status Register */
#define AT91_RSTC_URSTS (1 << 0) /* User Reset Status */
#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */
#define AT91_RSTC_RSTTYP_GENERAL (0 << 8)
#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8)
#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8)
#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8)
#define AT91_RSTC_RSTTYP_USER (4 << 8)
#define AT91_RSTC_NRSTL (1 << 16) /* NRST Pin Level */
#define AT91_RSTC_SRCMP (1 << 17) /* Software Reset Command in Progress */
#define AT91_RSTC_MR (AT91_RSTC + 0x08) /* Reset Controller Mode Register */
#define AT91_RSTC_URSTEN (1 << 0) /* User Reset Enable */
#define AT91_RSTC_URSTIEN (1 << 4) /* User Reset Interrupt Enable */
#define AT91_RSTC_ERSTL (0xf << 8) /* External Reset Length */
#define AT91_RSTC_KEY (0xff << 24) /* KEY Password */
#endif
include/asm-arm/arch-at91rm9200/at91_rtc.h
+75
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@@ -0,0 +1,75 @@
/*
* include/asm-arm/arch-at91rm9200/at91_rtc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Real Time Clock (RTC) - System peripheral registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_RTC_H
#define AT91_RTC_H
#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */
#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
#define AT91_RTC_DAY (7 << 21) /* Current Day */
#define AT91_RTC_DATE (0x3f << 24) /* Current Date */
#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */
#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */
#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */
#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
#define AT91_RTC_SECEV (1 << 2) /* Second Event */
#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */
#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */
#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */
#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */
#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */
#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */
#endif
include/asm-arm/arch-at91rm9200/at91_rtt.h
+32
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@@ -0,0 +1,32 @@
/*
* include/asm-arm/arch-at91rm9200/at91_rtt.h
*
* Real-time Timer (RTT) - System peripherals regsters.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_RTT_H
#define AT91_RTT_H
#define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */
#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
#define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */
#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
#define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */
#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
#define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */
#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
#endif
include/asm-arm/arch-at91rm9200/at91_shdwc.h
+33
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@@ -0,0 +1,33 @@
/*
* include/asm-arm/arch-at91rm9200/at91_shdwc.h
*
* Shutdown Controller (SHDWC) - System peripherals regsters.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_SHDWC_H
#define AT91_SHDWC_H
#define AT91_SHDW_CR (AT91_SHDWC + 0x00) /* Shut Down Control Register */
#define AT91_SHDW_SHDW (1 << 0) /* Processor Reset */
#define AT91_SHDW_KEY (0xff << 24) /* KEY Password */
#define AT91_SHDW_MR (AT91_SHDWC + 0x04) /* Shut Down Mode Register */
#define AT91_SHDW_WKMODE0 (3 << 0) /* Wake-up 0 Mode Selection */
#define AT91_SHDW_WKMODE0_NONE 0
#define AT91_SHDW_WKMODE0_HIGH 1
#define AT91_SHDW_WKMODE0_LOW 2
#define AT91_SHDW_WKMODE0_ANYLEVEL 3
#define AT91_SHDW_CPTWK0 (0xf << 4) /* Counter On Wake Up 0 */
#define AT91_SHDW_RTTWKEN (1 << 16) /* Real Time Timer Wake-up Enable */
#define AT91_SHDW_SR (AT91_SHDWC + 0x08) /* Shut Down Status Register */
#define AT91_SHDW_WAKEUP0 (1 << 0) /* Wake-up 0 Status */
#define AT91_SHDW_RTTWK (1 << 16) /* Real-time Timer Wake-up */
#endif
include/asm-arm/arch-at91rm9200/at91rm9200_spi.h → include/asm-arm/arch-at91rm9200/at91_spi.h
+4 -4
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@@ -1,5 +1,5 @@
/*
* include/asm-arm/arch-at91rm9200/at91rm9200_spi.h
* include/asm-arm/arch-at91rm9200/at91_spi.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
@@ -13,8 +13,8 @@
* (at your option) any later version.
*/
#ifndef AT91RM9200_SPI_H
#define AT91RM9200_SPI_H
#ifndef AT91_SPI_H
#define AT91_SPI_H
#define AT91_SPI_CR 0x00 /* Control Register */
#define AT91_SPI_SPIEN (1 << 0) /* SPI Enable */
@@ -28,7 +28,7 @@
#define AT91_SPI_PS_FIXED (0 << 1)
#define AT91_SPI_PS_VARIABLE (1 << 1)
#define AT91_SPI_PCSDEC (1 << 2) /* Chip Select Decode */
#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection */
#define AT91_SPI_DIV32 (1 << 3) /* Clock Selection [AT91RM9200 only] */
#define AT91_SPI_MODFDIS (1 << 4) /* Mode Fault Detection */
#define AT91_SPI_LLB (1 << 7) /* Local Loopback Enable */
#define AT91_SPI_PCS (0xf << 16) /* Peripheral Chip Select */
include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h → include/asm-arm/arch-at91rm9200/at91_ssc.h
+13 -3
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@@ -1,5 +1,5 @@
/*
* include/asm-arm/arch-at91rm9200/at91rm9200_ssc.h
* include/asm-arm/arch-at91rm9200/at91_ssc.h
*
* Copyright (C) SAN People
*
@@ -12,8 +12,8 @@
* (at your option) any later version.
*/
#ifndef AT91RM9200_SSC_H
#define AT91RM9200_SSC_H
#ifndef AT91_SSC_H
#define AT91_SSC_H
#define AT91_SSC_CR 0x00 /* Control Register */
#define AT91_SSC_RXEN (1 << 0) /* Receive Enable */
@@ -36,6 +36,10 @@
#define AT91_SSC_CKI (1 << 5) /* Clock Inversion */
#define AT91_SSC_CKI_FALLING (0 << 5)
#define AT91_SSC_CK_RISING (1 << 5)
#define AT91_SSC_CKG (1 << 6) /* Receive Clock Gating Selection [AT91SAM9261 only] */
#define AT91_SSC_CKG_NONE (0 << 6)
#define AT91_SSC_CKG_RFLOW (1 << 6)
#define AT91_SSC_CKG_RFHIGH (2 << 6)
#define AT91_SSC_START (0xf << 8) /* Start Selection */
#define AT91_SSC_START_CONTINUOUS (0 << 8)
#define AT91_SSC_START_TX_RX (1 << 8)
@@ -45,6 +49,7 @@
#define AT91_SSC_START_RISING_RF (5 << 8)
#define AT91_SSC_START_LEVEL_RF (6 << 8)
#define AT91_SSC_START_EDGE_RF (7 << 8)
#define AT91_SSC_STOP (1 << 12) /* Receive Stop Selection [AT91SAM9261 only] */
#define AT91_SSC_STTDLY (0xff << 16) /* Start Delay */
#define AT91_SSC_PERIOD (0xff << 24) /* Period Divider Selection */
@@ -75,6 +80,9 @@
#define AT91_SSC_RSHR 0x30 /* Receive Sync Holding Register */
#define AT91_SSC_TSHR 0x34 /* Transmit Sync Holding Register */
#define AT91_SSC_RC0R 0x38 /* Receive Compare 0 Register [AT91SAM9261 only] */
#define AT91_SSC_RC1R 0x3c /* Receive Compare 1 Register [AT91SAM9261 only] */
#define AT91_SSC_SR 0x40 /* Status Register */
#define AT91_SSC_TXRDY (1 << 0) /* Transmit Ready */
#define AT91_SSC_TXEMPTY (1 << 1) /* Transmit Empty */
@@ -84,6 +92,8 @@
#define AT91_SSC_OVRUN (1 << 5) /* Receive Overrun */
#define AT91_SSC_ENDRX (1 << 6) /* End of Reception */
#define AT91_SSC_RXBUFF (1 << 7) /* Receive Buffer Full */
#define AT91_SSC_CP0 (1 << 8) /* Compare 0 [AT91SAM9261 only] */
#define AT91_SSC_CP1 (1 << 9) /* Compare 1 [AT91SAM9261 only] */
#define AT91_SSC_TXSYN (1 << 10) /* Transmit Sync */
#define AT91_SSC_RXSYN (1 << 11) /* Receive Sync */
#define AT91_SSC_TXENA (1 << 16) /* Transmit Enable */
include/asm-arm/arch-at91rm9200/at91_st.h
+49
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@@ -0,0 +1,49 @@
/*
* include/asm-arm/arch-at91rm9200/at91_st.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* System Timer (ST) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_ST_H
#define AT91_ST_H
#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
#endif
include/asm-arm/arch-at91rm9200/at91rm9200_tc.h → include/asm-arm/arch-at91rm9200/at91_tc.h
+3 -3
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@@ -1,5 +1,5 @@
/*
* include/asm-arm/arch-at91rm9200/at91rm9200_tc.h
* include/asm-arm/arch-at91rm9200/at91_tc.h
*
* Copyright (C) SAN People
*
@@ -12,8 +12,8 @@
* (at your option) any later version.
*/
#ifndef AT91RM9200_TC_H
#define AT91RM9200_TC_H
#ifndef AT91_TC_H
#define AT91_TC_H
#define AT91_TC_BCR 0xc0 /* TC Block Control Register */
#define AT91_TC_SYNC (1 << 0) /* Synchro Command */
include/asm-arm/arch-at91rm9200/at91rm9200_twi.h → include/asm-arm/arch-at91rm9200/at91_twi.h
+5 -5
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@@ -1,5 +1,5 @@
/*
* include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
* include/asm-arm/arch-at91rm9200/at91_twi.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
@@ -13,8 +13,8 @@
* (at your option) any later version.
*/
#ifndef AT91RM9200_TWI_H
#define AT91RM9200_TWI_H
#ifndef AT91_TWI_H
#define AT91_TWI_H
#define AT91_TWI_CR 0x00 /* Control Register */
#define AT91_TWI_START (1 << 0) /* Send a Start Condition */
@@ -43,8 +43,8 @@
#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
#define AT91_TWI_OVRE (1 << 6) /* Overrun Error */
#define AT91_TWI_UNRE (1 << 7) /* Underrun Error */
#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */
#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */
#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
include/asm-arm/arch-at91rm9200/at91_wdt.h
+34
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@@ -0,0 +1,34 @@
/*
* include/asm-arm/arch-at91rm9200/at91_wdt.h
*
* Watchdog Timer (WDT) - System peripherals regsters.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91_WDT_H
#define AT91_WDT_H
#define AT91_WDT_CR (AT91_WDT + 0x00) /* Watchdog Control Register */
#define AT91_WDT_WDRSTT (1 << 0) /* Restart */
#define AT91_WDT_KEY (0xff << 24) /* KEY Password */
#define AT91_WDT_MR (AT91_WDT + 0x04) /* Watchdog Mode Register */
#define AT91_WDT_WDV (0xfff << 0) /* Counter Value */
#define AT91_WDT_WDFIEN (1 << 12) /* Fault Interrupt Enable */
#define AT91_WDT_WDRSTEN (1 << 13) /* Reset Processor */
#define AT91_WDT_WDRPROC (1 << 14) /* Timer Restart */
#define AT91_WDT_WDDIS (1 << 15) /* Watchdog Disable */
#define AT91_WDT_WDD (0xfff << 16) /* Delta Value */
#define AT91_WDT_WDDBGHLT (1 << 28) /* Debug Halt */
#define AT91_WDT_WDIDLEHLT (1 << 29) /* Idle Halt */
#define AT91_WDT_SR (AT91_WDT + 0x08) /* Watchdog Status Register */
#define AT91_WDT_WDUNF (1 << 0) /* Watchdog Underflow */
#define AT91_WDT_WDERR (1 << 1) /* Watchdog Error */
#endif
include/asm-arm/arch-at91rm9200/at91rm9200.h
+16
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@@ -79,6 +79,22 @@
#define AT91_BASE_SYS 0xfffff000
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS) /* Advanced Interrupt Controller */
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS) /* Debug Unit */
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS) /* PIO Controller A */
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS) /* PIO Controller B */
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS) /* PIO Controller C */
#define AT91_PIOD (0xfffffa00 - AT91_BASE_SYS) /* PIO Controller D */
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS) /* Power Management Controller */
#define AT91_ST (0xfffffd00 - AT91_BASE_SYS) /* System Timer */
#define AT91_RTC (0xfffffe00 - AT91_BASE_SYS) /* Real-Time Clock */
#define AT91_MC (0xffffff00 - AT91_BASE_SYS) /* Memory Controllers */
#define AT91_MATRIX 0 /* not supported */
/*
* Internal Memory.
*/
include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
+160
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@@ -0,0 +1,160 @@
/*
* include/asm-arm/arch-at91rm9200/at91rm9200_mc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_MC_H
#define AT91RM9200_MC_H
/* Memory Controller */
#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
#define AT91_MC_ABTSZ_BYTE (0 << 8)
#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
#define AT91_MC_ABTSZ_WORD (2 << 8)
#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
#define AT91_MC_ABTTYP_FETCH (2 << 10)
#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
/* External Bus Interface (EBI) registers */
#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
#define AT91_EBI_CS0A_SMC (0 << 0)
#define AT91_EBI_CS0A_BFC (1 << 0)
#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_EBI_CS1A_SMC (0 << 1)
#define AT91_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
#define AT91_EBI_CS3A_SMC (0 << 3)
#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
#define AT91_EBI_CS4A_SMC (0 << 4)
#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
/* Static Memory Controller (SMC) registers */
#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
#define AT91_SMC_NWS_(x) ((x) << 0)
#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
#define AT91_SMC_TDF_(x) ((x) << 8)
#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
#define AT91_SMC_DBW_16 (1 << 13)
#define AT91_SMC_DBW_8 (2 << 13)
#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
#define AT91_SMC_ACSS_STD (0 << 16)
#define AT91_SMC_ACSS_1 (1 << 16)
#define AT91_SMC_ACSS_2 (2 << 16)
#define AT91_SMC_ACSS_3 (3 << 16)
#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
#define AT91_SMC_RWSETUP_(x) ((x) << 24)
#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
#define AT91_SMC_RWHOLD_(x) ((x) << 28)
/* SDRAM Controller registers */
#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
#define AT91_SDRAMC_MODE_NOP (1 << 0)
#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
#define AT91_SDRAMC_MODE_LMR (3 << 0)
#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
#define AT91_SDRAMC_DBW_32 (0 << 4)
#define AT91_SDRAMC_DBW_16 (1 << 4)
#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
#define AT91_SDRAMC_NC_8 (0 << 0)
#define AT91_SDRAMC_NC_9 (1 << 0)
#define AT91_SDRAMC_NC_10 (2 << 0)
#define AT91_SDRAMC_NC_11 (3 << 0)
#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
#define AT91_SDRAMC_NR_11 (0 << 2)
#define AT91_SDRAMC_NR_12 (1 << 2)
#define AT91_SDRAMC_NR_13 (2 << 2)
#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
#define AT91_SDRAMC_NB_2 (0 << 4)
#define AT91_SDRAMC_NB_4 (1 << 4)
#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
#define AT91_SDRAMC_CAS_2 (2 << 5)
#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
/* Burst Flash Controller register */
#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
#define AT91_BFC_BFCOM_DISABLED (0 << 0)
#define AT91_BFC_BFCOM_ASYNC (1 << 0)
#define AT91_BFC_BFCOM_BURST (2 << 0)
#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
#define AT91_BFC_BFCC_MCK (1 << 2)
#define AT91_BFC_BFCC_DIV2 (2 << 2)
#define AT91_BFC_BFCC_DIV4 (3 << 2)
#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
#define AT91_BFC_PAGES (7 << 8) /* Page Size */
#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
#define AT91_BFC_PAGES_16 (1 << 8)
#define AT91_BFC_PAGES_32 (2 << 8)
#define AT91_BFC_PAGES_64 (3 << 8)
#define AT91_BFC_PAGES_128 (4 << 8)
#define AT91_BFC_PAGES_256 (5 << 8)
#define AT91_BFC_PAGES_512 (6 << 8)
#define AT91_BFC_PAGES_1024 (7 << 8)
#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
#endif
include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
-438
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@@ -1,438 +0,0 @@
/*
* include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* System peripherals registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_SYS_H
#define AT91RM9200_SYS_H
/*
* Advanced Interrupt Controller.
*/
#define AT91_AIC 0x000
#define AT91_AIC_SMR(n) (AT91_AIC + ((n) * 4)) /* Source Mode Registers 0-31 */
#define AT91_AIC_PRIOR (7 << 0) /* Priority Level */
#define AT91_AIC_SRCTYPE (3 << 5) /* Interrupt Source Type */
#define AT91_AIC_SRCTYPE_LOW (0 << 5)
#define AT91_AIC_SRCTYPE_FALLING (1 << 5)
#define AT91_AIC_SRCTYPE_HIGH (2 << 5)
#define AT91_AIC_SRCTYPE_RISING (3 << 5)
#define AT91_AIC_SVR(n) (AT91_AIC + 0x80 + ((n) * 4)) /* Source Vector Registers 0-31 */
#define AT91_AIC_IVR (AT91_AIC + 0x100) /* Interrupt Vector Register */
#define AT91_AIC_FVR (AT91_AIC + 0x104) /* Fast Interrupt Vector Register */
#define AT91_AIC_ISR (AT91_AIC + 0x108) /* Interrupt Status Register */
#define AT91_AIC_IRQID (0x1f << 0) /* Current Interrupt Identifier */
#define AT91_AIC_IPR (AT91_AIC + 0x10c) /* Interrupt Pending Register */
#define AT91_AIC_IMR (AT91_AIC + 0x110) /* Interrupt Mask Register */
#define AT91_AIC_CISR (AT91_AIC + 0x114) /* Core Interrupt Status Register */
#define AT91_AIC_NFIQ (1 << 0) /* nFIQ Status */
#define AT91_AIC_NIRQ (1 << 1) /* nIRQ Status */
#define AT91_AIC_IECR (AT91_AIC + 0x120) /* Interrupt Enable Command Register */
#define AT91_AIC_IDCR (AT91_AIC + 0x124) /* Interrupt Disable Command Register */
#define AT91_AIC_ICCR (AT91_AIC + 0x128) /* Interrupt Clear Command Register */
#define AT91_AIC_ISCR (AT91_AIC + 0x12c) /* Interrupt Set Command Register */
#define AT91_AIC_EOICR (AT91_AIC + 0x130) /* End of Interrupt Command Register */
#define AT91_AIC_SPU (AT91_AIC + 0x134) /* Spurious Interrupt Vector Register */
#define AT91_AIC_DCR (AT91_AIC + 0x138) /* Debug Control Register */
#define AT91_AIC_DCR_PROT (1 << 0) /* Protection Mode */
#define AT91_AIC_DCR_GMSK (1 << 1) /* General Mask */
/*
* Debug Unit.
*/
#define AT91_DBGU 0x200
#define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */
#define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */
#define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */
#define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */
#define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */
#define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */
#define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */
#define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */
#define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */
#define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */
#define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */
#define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */
#define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */
#define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */
#define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */
#define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */
#define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */
#define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */
#define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */
#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
/*
* PIO Controllers.
*/
#define AT91_PIOA 0x400
#define AT91_PIOB 0x600
#define AT91_PIOC 0x800
#define AT91_PIOD 0xa00
#define PIO_PER 0x00 /* Enable Register */
#define PIO_PDR 0x04 /* Disable Register */
#define PIO_PSR 0x08 /* Status Register */
#define PIO_OER 0x10 /* Output Enable Register */
#define PIO_ODR 0x14 /* Output Disable Register */
#define PIO_OSR 0x18 /* Output Status Register */
#define PIO_IFER 0x20 /* Glitch Input Filter Enable */
#define PIO_IFDR 0x24 /* Glitch Input Filter Disable */
#define PIO_IFSR 0x28 /* Glitch Input Filter Status */
#define PIO_SODR 0x30 /* Set Output Data Register */
#define PIO_CODR 0x34 /* Clear Output Data Register */
#define PIO_ODSR 0x38 /* Output Data Status Register */
#define PIO_PDSR 0x3c /* Pin Data Status Register */
#define PIO_IER 0x40 /* Interrupt Enable Register */
#define PIO_IDR 0x44 /* Interrupt Disable Register */
#define PIO_IMR 0x48 /* Interrupt Mask Register */
#define PIO_ISR 0x4c /* Interrupt Status Register */
#define PIO_MDER 0x50 /* Multi-driver Enable Register */
#define PIO_MDDR 0x54 /* Multi-driver Disable Register */
#define PIO_MDSR 0x58 /* Multi-driver Status Register */
#define PIO_PUDR 0x60 /* Pull-up Disable Register */
#define PIO_PUER 0x64 /* Pull-up Enable Register */
#define PIO_PUSR 0x68 /* Pull-up Status Register */
#define PIO_ASR 0x70 /* Peripheral A Select Register */
#define PIO_BSR 0x74 /* Peripheral B Select Register */
#define PIO_ABSR 0x78 /* AB Status Register */
#define PIO_OWER 0xa0 /* Output Write Enable Register */
#define PIO_OWDR 0xa4 /* Output Write Disable Register */
#define PIO_OWSR 0xa8 /* Output Write Status Register */
#define AT91_PIO_P(n) (1 << (n))
/*
* Power Management Controller.
*/
#define AT91_PMC 0xc00
#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
#define AT91_PMC_UDP (1 << 1) /* USB Devcice Port Clock */
#define AT91_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend */
#define AT91_PMC_UHP (1 << 4) /* USB Host Port Clock */
#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */
#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
#define AT91_PMC_DIV (0xff << 0) /* Divider */
#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
#define AT91_PMC_CSS_SLOW (0 << 0)
#define AT91_PMC_CSS_MAIN (1 << 0)
#define AT91_PMC_CSS_PLLA (2 << 0)
#define AT91_PMC_CSS_PLLB (3 << 0)
#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
#define AT91_PMC_PRES_1 (0 << 2)
#define AT91_PMC_PRES_2 (1 << 2)
#define AT91_PMC_PRES_4 (2 << 2)
#define AT91_PMC_PRES_8 (3 << 2)
#define AT91_PMC_PRES_16 (4 << 2)
#define AT91_PMC_PRES_32 (5 << 2)
#define AT91_PMC_PRES_64 (6 << 2)
#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
#define AT91_PMC_MDIV_1 (0 << 8)
#define AT91_PMC_MDIV_2 (1 << 8)
#define AT91_PMC_MDIV_3 (2 << 8)
#define AT91_PMC_MDIV_4 (3 << 8)
#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
/*
* System Timer.
*/
#define AT91_ST 0xd00
#define AT91_ST_CR (AT91_ST + 0x00) /* Control Register */
#define AT91_ST_WDRST (1 << 0) /* Watchdog Timer Restart */
#define AT91_ST_PIMR (AT91_ST + 0x04) /* Period Interval Mode Register */
#define AT91_ST_PIV (0xffff << 0) /* Period Interval Value */
#define AT91_ST_WDMR (AT91_ST + 0x08) /* Watchdog Mode Register */
#define AT91_ST_WDV (0xffff << 0) /* Watchdog Counter Value */
#define AT91_ST_RSTEN (1 << 16) /* Reset Enable */
#define AT91_ST_EXTEN (1 << 17) /* External Signal Assertion Enable */
#define AT91_ST_RTMR (AT91_ST + 0x0c) /* Real-time Mode Register */
#define AT91_ST_RTPRES (0xffff << 0) /* Real-time Prescalar Value */
#define AT91_ST_SR (AT91_ST + 0x10) /* Status Register */
#define AT91_ST_PITS (1 << 0) /* Period Interval Timer Status */
#define AT91_ST_WDOVF (1 << 1) /* Watchdog Overflow */
#define AT91_ST_RTTINC (1 << 2) /* Real-time Timer Increment */
#define AT91_ST_ALMS (1 << 3) /* Alarm Status */
#define AT91_ST_IER (AT91_ST + 0x14) /* Interrupt Enable Register */
#define AT91_ST_IDR (AT91_ST + 0x18) /* Interrupt Disable Register */
#define AT91_ST_IMR (AT91_ST + 0x1c) /* Interrupt Mask Register */
#define AT91_ST_RTAR (AT91_ST + 0x20) /* Real-time Alarm Register */
#define AT91_ST_ALMV (0xfffff << 0) /* Alarm Value */
#define AT91_ST_CRTR (AT91_ST + 0x24) /* Current Real-time Register */
#define AT91_ST_CRTV (0xfffff << 0) /* Current Real-Time Value */
/*
* Real-time Clock.
*/
#define AT91_RTC 0xe00
#define AT91_RTC_CR (AT91_RTC + 0x00) /* Control Register */
#define AT91_RTC_UPDTIM (1 << 0) /* Update Request Time Register */
#define AT91_RTC_UPDCAL (1 << 1) /* Update Request Calendar Register */
#define AT91_RTC_TIMEVSEL (3 << 8) /* Time Event Selection */
#define AT91_RTC_TIMEVSEL_MINUTE (0 << 8)
#define AT91_RTC_TIMEVSEL_HOUR (1 << 8)
#define AT91_RTC_TIMEVSEL_DAY24 (2 << 8)
#define AT91_RTC_TIMEVSEL_DAY12 (3 << 8)
#define AT91_RTC_CALEVSEL (3 << 16) /* Calendar Event Selection */
#define AT91_RTC_CALEVSEL_WEEK (0 << 16)
#define AT91_RTC_CALEVSEL_MONTH (1 << 16)
#define AT91_RTC_CALEVSEL_YEAR (2 << 16)
#define AT91_RTC_MR (AT91_RTC + 0x04) /* Mode Register */
#define AT91_RTC_HRMOD (1 << 0) /* 12/24 Hour Mode */
#define AT91_RTC_TIMR (AT91_RTC + 0x08) /* Time Register */
#define AT91_RTC_SEC (0x7f << 0) /* Current Second */
#define AT91_RTC_MIN (0x7f << 8) /* Current Minute */
#define AT91_RTC_HOUR (0x3f << 16) /* Current Hour */
#define AT91_RTC_AMPM (1 << 22) /* Ante Meridiem Post Meridiem Indicator */
#define AT91_RTC_CALR (AT91_RTC + 0x0c) /* Calendar Register */
#define AT91_RTC_CENT (0x7f << 0) /* Current Century */
#define AT91_RTC_YEAR (0xff << 8) /* Current Year */
#define AT91_RTC_MONTH (0x1f << 16) /* Current Month */
#define AT91_RTC_DAY (7 << 21) /* Current Day */
#define AT91_RTC_DATE (0x3f << 24) /* Current Date */
#define AT91_RTC_TIMALR (AT91_RTC + 0x10) /* Time Alarm Register */
#define AT91_RTC_SECEN (1 << 7) /* Second Alarm Enable */
#define AT91_RTC_MINEN (1 << 15) /* Minute Alarm Enable */
#define AT91_RTC_HOUREN (1 << 23) /* Hour Alarm Enable */
#define AT91_RTC_CALALR (AT91_RTC + 0x14) /* Calendar Alarm Register */
#define AT91_RTC_MTHEN (1 << 23) /* Month Alarm Enable */
#define AT91_RTC_DATEEN (1 << 31) /* Date Alarm Enable */
#define AT91_RTC_SR (AT91_RTC + 0x18) /* Status Register */
#define AT91_RTC_ACKUPD (1 << 0) /* Acknowledge for Update */
#define AT91_RTC_ALARM (1 << 1) /* Alarm Flag */
#define AT91_RTC_SECEV (1 << 2) /* Second Event */
#define AT91_RTC_TIMEV (1 << 3) /* Time Event */
#define AT91_RTC_CALEV (1 << 4) /* Calendar Event */
#define AT91_RTC_SCCR (AT91_RTC + 0x1c) /* Status Clear Command Register */
#define AT91_RTC_IER (AT91_RTC + 0x20) /* Interrupt Enable Register */
#define AT91_RTC_IDR (AT91_RTC + 0x24) /* Interrupt Disable Register */
#define AT91_RTC_IMR (AT91_RTC + 0x28) /* Interrupt Mask Register */
#define AT91_RTC_VER (AT91_RTC + 0x2c) /* Valid Entry Register */
#define AT91_RTC_NVTIM (1 << 0) /* Non valid Time */
#define AT91_RTC_NVCAL (1 << 1) /* Non valid Calendar */
#define AT91_RTC_NVTIMALR (1 << 2) /* Non valid Time Alarm */
#define AT91_RTC_NVCALALR (1 << 3) /* Non valid Calendar Alarm */
/*
* Memory Controller.
*/
#define AT91_MC 0xf00
#define AT91_MC_RCR (AT91_MC + 0x00) /* MC Remap Control Register */
#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
#define AT91_MC_ABTSZ_BYTE (0 << 8)
#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
#define AT91_MC_ABTSZ_WORD (2 << 8)
#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
#define AT91_MC_ABTTYP_FETCH (2 << 10)
#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
/* External Bus Interface (EBI) registers */
#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
#define AT91_EBI_CS0A (1 << 0) /* Chip Select 0 Assignment */
#define AT91_EBI_CS0A_SMC (0 << 0)
#define AT91_EBI_CS0A_BFC (1 << 0)
#define AT91_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_EBI_CS1A_SMC (0 << 1)
#define AT91_EBI_CS1A_SDRAMC (1 << 1)
#define AT91_EBI_CS3A (1 << 3) /* Chip Select 2 Assignment */
#define AT91_EBI_CS3A_SMC (0 << 3)
#define AT91_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_EBI_CS4A (1 << 4) /* Chip Select 3 Assignment */
#define AT91_EBI_CS4A_SMC (0 << 4)
#define AT91_EBI_CS4A_SMC_COMPACTFLASH (1 << 4)
#define AT91_EBI_CFGR (AT91_MC + 0x64) /* Configuration Register */
#define AT91_EBI_DBPUC (1 << 0) /* Data Bus Pull-Up Configuration */
/* Static Memory Controller (SMC) registers */
#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
#define AT91_SMC_NWS_(x) ((x) << 0)
#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
#define AT91_SMC_TDF_(x) ((x) << 8)
#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
#define AT91_SMC_DBW_16 (1 << 13)
#define AT91_SMC_DBW_8 (2 << 13)
#define AT91_SMC_DPR (1 << 15) /* Data Read Protocol */
#define AT91_SMC_ACSS (3 << 16) /* Address to Chip Select Setup */
#define AT91_SMC_ACSS_STD (0 << 16)
#define AT91_SMC_ACSS_1 (1 << 16)
#define AT91_SMC_ACSS_2 (2 << 16)
#define AT91_SMC_ACSS_3 (3 << 16)
#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
#define AT91_SMC_RWSETUP_(x) ((x) << 24)
#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
#define AT91_SMC_RWHOLD_(x) ((x) << 28)
/* SDRAM Controller registers */
#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
#define AT91_SDRAMC_MODE_NOP (1 << 0)
#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
#define AT91_SDRAMC_MODE_LMR (3 << 0)
#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
#define AT91_SDRAMC_DBW_32 (0 << 4)
#define AT91_SDRAMC_DBW_16 (1 << 4)
#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
#define AT91_SDRAMC_NC_8 (0 << 0)
#define AT91_SDRAMC_NC_9 (1 << 0)
#define AT91_SDRAMC_NC_10 (2 << 0)
#define AT91_SDRAMC_NC_11 (3 << 0)
#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
#define AT91_SDRAMC_NR_11 (0 << 2)
#define AT91_SDRAMC_NR_12 (1 << 2)
#define AT91_SDRAMC_NR_13 (2 << 2)
#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
#define AT91_SDRAMC_NB_2 (0 << 4)
#define AT91_SDRAMC_NB_4 (1 << 4)
#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
#define AT91_SDRAMC_CAS_2 (2 << 5)
#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
/* Burst Flash Controller register */
#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
#define AT91_BFC_BFCOM_DISABLED (0 << 0)
#define AT91_BFC_BFCOM_ASYNC (1 << 0)
#define AT91_BFC_BFCOM_BURST (2 << 0)
#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
#define AT91_BFC_BFCC_MCK (1 << 2)
#define AT91_BFC_BFCC_DIV2 (2 << 2)
#define AT91_BFC_BFCC_DIV4 (3 << 2)
#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
#define AT91_BFC_PAGES (7 << 8) /* Page Size */
#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
#define AT91_BFC_PAGES_16 (1 << 8)
#define AT91_BFC_PAGES_32 (2 << 8)
#define AT91_BFC_PAGES_64 (3 << 8)
#define AT91_BFC_PAGES_128 (4 << 8)
#define AT91_BFC_PAGES_256 (5 << 8)
#define AT91_BFC_PAGES_512 (6 << 8)
#define AT91_BFC_PAGES_1024 (7 << 8)
#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
#endif
include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
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/*
* include/asm-arm/arch-at91rm9200/at91rm9200_udp.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
*
* USB Device Port (UDP) registers.
* Based on AT91RM9200 datasheet revision E.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91RM9200_UDP_H
#define AT91RM9200_UDP_H
#define AT91_UDP_FRM_NUM 0x00 /* Frame Number Register */
#define AT91_UDP_NUM (0x7ff << 0) /* Frame Number */
#define AT91_UDP_FRM_ERR (1 << 16) /* Frame Error */
#define AT91_UDP_FRM_OK (1 << 17) /* Frame OK */
#define AT91_UDP_GLB_STAT 0x04 /* Global State Register */
#define AT91_UDP_FADDEN (1 << 0) /* Function Address Enable */
#define AT91_UDP_CONFG (1 << 1) /* Configured */
#define AT91_UDP_ESR (1 << 2) /* Enable Send Resume */
#define AT91_UDP_RSMINPR (1 << 3) /* Resume has been sent */
#define AT91_UDP_RMWUPE (1 << 4) /* Remote Wake Up Enable */
#define AT91_UDP_FADDR 0x08 /* Function Address Register */
#define AT91_UDP_FADD (0x7f << 0) /* Function Address Value */
#define AT91_UDP_FEN (1 << 8) /* Function Enable */
#define AT91_UDP_IER 0x10 /* Interrupt Enable Register */
#define AT91_UDP_IDR 0x14 /* Interrupt Disable Register */
#define AT91_UDP_IMR 0x18 /* Interrupt Mask Register */
#define AT91_UDP_ISR 0x1c /* Interrupt Status Register */
#define AT91_UDP_EP(n) (1 << (n)) /* Endpoint Interrupt Status */
#define AT91_UDP_RXSUSP (1 << 8) /* USB Suspend Interrupt Status */
#define AT91_UDP_RXRSM (1 << 9) /* USB Resume Interrupt Status */
#define AT91_UDP_EXTRSM (1 << 10) /* External Resume Interrupt Status */
#define AT91_UDP_SOFINT (1 << 11) /* Start of Frame Interrupt Status */
#define AT91_UDP_ENDBUSRES (1 << 12) /* End of Bus Reset Interrpt Status */
#define AT91_UDP_WAKEUP (1 << 13) /* USB Wakeup Interrupt Status */
#define AT91_UDP_ICR 0x20 /* Interrupt Clear Register */
#define AT91_UDP_RST_EP 0x28 /* Reset Endpoint Register */
#define AT91_UDP_CSR(n) (0x30 + ((n) * 4)) /* Endpoint Control/Status Registers 0-7 */
#define AT91_UDP_TXCOMP (1 << 0) /* Generates IN packet with data previously written in DPR */
#define AT91_UDP_RX_DATA_BK0 (1 << 1) /* Receive Data Bank 0 */
#define AT91_UDP_RXSETUP (1 << 2) /* Send STALL to the host */
#define AT91_UDP_STALLSENT (1 << 3) /* Stall Sent / Isochronous error (Isochronous endpoints) */
#define AT91_UDP_TXPKTRDY (1 << 4) /* Transmit Packet Ready */
#define AT91_UDP_FORCESTALL (1 << 5) /* Force Stall */
#define AT91_UDP_RX_DATA_BK1 (1 << 6) /* Receive Data Bank 1 */
#define AT91_UDP_DIR (1 << 7) /* Transfer Direction */
#define AT91_UDP_EPTYPE (7 << 8) /* Endpoint Type */
#define AT91_UDP_EPTYPE_CTRL (0 << 8)
#define AT91_UDP_EPTYPE_ISO_OUT (1 << 8)
#define AT91_UDP_EPTYPE_BULK_OUT (2 << 8)
#define AT91_UDP_EPTYPE_INT_OUT (3 << 8)
#define AT91_UDP_EPTYPE_ISO_IN (5 << 8)
#define AT91_UDP_EPTYPE_BULK_IN (6 << 8)
#define AT91_UDP_EPTYPE_INT_IN (7 << 8)
#define AT91_UDP_DTGLE (1 << 11) /* Data Toggle */
#define AT91_UDP_EPEDS (1 << 15) /* Endpoint Enable/Disable */
#define AT91_UDP_RXBYTECNT (0x7ff << 16) /* Number of bytes in FIFO */
#define AT91_UDP_FDR(n) (0x50 + ((n) * 4)) /* Endpoint FIFO Data Registers 0-7 */
#define AT91_UDP_TXVC 0x74 /* Transceiver Control Register */
#define AT91_UDP_TXVC_TXVDIS (1 << 8) /* Transceiver Disable */
#endif
include/asm-arm/arch-at91rm9200/at91sam9260.h
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/*
* include/asm-arm/arch-at91rm9200/at91sam9260.h
*
* (C) 2006 Andrew Victor
*
* Common definitions.
* Based on AT91SAM9260 datasheet revision A (Preliminary).
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9260_H
#define AT91SAM9260_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9260_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9260_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9260_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91SAM9260_ID_ADC 5 /* Analog-to-Digital Converter */
#define AT91SAM9260_ID_US0 6 /* USART 0 */
#define AT91SAM9260_ID_US1 7 /* USART 1 */
#define AT91SAM9260_ID_US2 8 /* USART 2 */
#define AT91SAM9260_ID_MCI 9 /* Multimedia Card Interface */
#define AT91SAM9260_ID_UDP 10 /* USB Device Port */
#define AT91SAM9260_ID_TWI 11 /* Two-Wire Interface */
#define AT91SAM9260_ID_SPI0 12 /* Serial Peripheral Interface 0 */
#define AT91SAM9260_ID_SPI1 13 /* Serial Peripheral Interface 1 */
#define AT91SAM9260_ID_SSC 14 /* Serial Synchronous Controller */
#define AT91SAM9260_ID_TC0 17 /* Timer Counter 0 */
#define AT91SAM9260_ID_TC1 18 /* Timer Counter 1 */
#define AT91SAM9260_ID_TC2 19 /* Timer Counter 2 */
#define AT91SAM9260_ID_UHP 20 /* USB Host port */
#define AT91SAM9260_ID_EMAC 21 /* Ethernet */
#define AT91SAM9260_ID_ISI 22 /* Image Sensor Interface */
#define AT91SAM9260_ID_US3 23 /* USART 3 */
#define AT91SAM9260_ID_US4 24 /* USART 4 */
#define AT91SAM9260_ID_US5 25 /* USART 5 */
#define AT91SAM9260_ID_TC3 26 /* Timer Counter 3 */
#define AT91SAM9260_ID_TC4 27 /* Timer Counter 4 */
#define AT91SAM9260_ID_TC5 28 /* Timer Counter 5 */
#define AT91SAM9260_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9260_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
#define AT91SAM9260_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9260_BASE_TCB0 0xfffa0000
#define AT91SAM9260_BASE_TC0 0xfffa0000
#define AT91SAM9260_BASE_TC1 0xfffa0040
#define AT91SAM9260_BASE_TC2 0xfffa0080
#define AT91SAM9260_BASE_UDP 0xfffa4000
#define AT91SAM9260_BASE_MCI 0xfffa8000
#define AT91SAM9260_BASE_TWI 0xfffac000
#define AT91SAM9260_BASE_US0 0xfffb0000
#define AT91SAM9260_BASE_US1 0xfffb4000
#define AT91SAM9260_BASE_US2 0xfffb8000
#define AT91SAM9260_BASE_SSC 0xfffbc000
#define AT91SAM9260_BASE_ISI 0xfffc0000
#define AT91SAM9260_BASE_EMAC 0xfffc4000
#define AT91SAM9260_BASE_SPI0 0xfffc8000
#define AT91SAM9260_BASE_SPI1 0xfffcc000
#define AT91SAM9260_BASE_US3 0xfffd0000
#define AT91SAM9260_BASE_US4 0xfffd4000
#define AT91SAM9260_BASE_US5 0xfffd8000
#define AT91SAM9260_BASE_TCB1 0xfffdc000
#define AT91SAM9260_BASE_TC3 0xfffdc000
#define AT91SAM9260_BASE_TC4 0xfffdc040
#define AT91SAM9260_BASE_TC5 0xfffdc080
#define AT91SAM9260_BASE_ADC 0xfffe0000
#define AT91_BASE_SYS 0xffffe800
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_ECC (0xffffe800 - AT91_BASE_SYS)
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_CCFG (0xffffef10 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
/*
* Internal Memory.
*/
#define AT91SAM9260_ROM_BASE 0x00100000 /* Internal ROM base address */
#define AT91SAM9260_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
#define AT91SAM9260_SRAM0_BASE 0x00200000 /* Internal SRAM 0 base address */
#define AT91SAM9260_SRAM0_SIZE SZ_4K /* Internal SRAM 0 size (4Kb) */
#define AT91SAM9260_SRAM1_BASE 0x00300000 /* Internal SRAM 1 base address */
#define AT91SAM9260_SRAM1_SIZE SZ_4K /* Internal SRAM 1 size (4Kb) */
#define AT91SAM9260_UHP_BASE 0x00500000 /* USB Host controller */
#if 0
/*
* PIO pin definitions (peripheral A/B multiplexing).
*/
// TODO: Add
#endif
#endif
include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
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/*
* include/asm-arm/arch-at91rm9200/at91sam9260_matrix.h
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9260 datasheet revision B.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9260_MATRIX_H
#define AT91SAM9260_MATRIX_H
#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x04) /* Master Configuration Register 5 */
#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
#define AT91_MATRIX_ULBT_FOUR (2 << 0)
#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x11C) /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_CS1A_SMC (0 << 1)
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_CS3A_SMC (0 << 3)
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_CS4A_SMC (0 << 4)
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */
#define AT91_MATRIX_CS5A_SMC (0 << 5)
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_VDDIOMSEL (1 << 16) /* Memory voltage selection */
#define AT91_MATRIX_VDDIOMSEL_1_8V (0 << 16)
#define AT91_MATRIX_VDDIOMSEL_3_3V (1 << 16)
#endif
include/asm-arm/arch-at91rm9200/at91sam9261.h
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/*
* include/asm-arm/arch-at91rm9200/at91sam9261.h
*
* Copyright (C) SAN People
*
* Common definitions.
* Based on AT91SAM9261 datasheet revision E. (Preliminary)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9261_H
#define AT91SAM9261_H
/*
* Peripheral identifiers/interrupts.
*/
#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
#define AT91_ID_SYS 1 /* System Peripherals */
#define AT91SAM9261_ID_PIOA 2 /* Parallel IO Controller A */
#define AT91SAM9261_ID_PIOB 3 /* Parallel IO Controller B */
#define AT91SAM9261_ID_PIOC 4 /* Parallel IO Controller C */
#define AT91SAM9261_ID_US0 6 /* USART 0 */
#define AT91SAM9261_ID_US1 7 /* USART 1 */
#define AT91SAM9261_ID_US2 8 /* USART 2 */
#define AT91SAM9261_ID_MCI 9 /* Multimedia Card Interface */
#define AT91SAM9261_ID_UDP 10 /* USB Device Port */
#define AT91SAM9261_ID_TWI 11 /* Two-Wire Interface */
#define AT91SAM9261_ID_SPI0 12 /* Serial Peripheral Interface 0 */
#define AT91SAM9261_ID_SPI1 13 /* Serial Peripheral Interface 1 */
#define AT91SAM9261_ID_SSC0 14 /* Serial Synchronous Controller 0 */
#define AT91SAM9261_ID_SSC1 15 /* Serial Synchronous Controller 1 */
#define AT91SAM9261_ID_SSC2 16 /* Serial Synchronous Controller 2 */
#define AT91SAM9261_ID_TC0 17 /* Timer Counter 0 */
#define AT91SAM9261_ID_TC1 18 /* Timer Counter 1 */
#define AT91SAM9261_ID_TC2 19 /* Timer Counter 2 */
#define AT91SAM9261_ID_UHP 20 /* USB Host port */
#define AT91SAM9261_ID_LCDC 21 /* LDC Controller */
#define AT91SAM9261_ID_IRQ0 29 /* Advanced Interrupt Controller (IRQ0) */
#define AT91SAM9261_ID_IRQ1 30 /* Advanced Interrupt Controller (IRQ1) */
#define AT91SAM9261_ID_IRQ2 31 /* Advanced Interrupt Controller (IRQ2) */
/*
* User Peripheral physical base addresses.
*/
#define AT91SAM9261_BASE_TCB0 0xfffa0000
#define AT91SAM9261_BASE_TC0 0xfffa0000
#define AT91SAM9261_BASE_TC1 0xfffa0040
#define AT91SAM9261_BASE_TC2 0xfffa0080
#define AT91SAM9261_BASE_UDP 0xfffa4000
#define AT91SAM9261_BASE_MCI 0xfffa8000
#define AT91SAM9261_BASE_TWI 0xfffac000
#define AT91SAM9261_BASE_US0 0xfffb0000
#define AT91SAM9261_BASE_US1 0xfffb4000
#define AT91SAM9261_BASE_US2 0xfffb8000
#define AT91SAM9261_BASE_SSC0 0xfffbc000
#define AT91SAM9261_BASE_SSC1 0xfffc0000
#define AT91SAM9261_BASE_SSC2 0xfffc4000
#define AT91SAM9261_BASE_SPI0 0xfffc8000
#define AT91SAM9261_BASE_SPI1 0xfffcc000
#define AT91_BASE_SYS 0xffffea00
/*
* System Peripherals (offset from AT91_BASE_SYS)
*/
#define AT91_SDRAMC (0xffffea00 - AT91_BASE_SYS)
#define AT91_SMC (0xffffec00 - AT91_BASE_SYS)
#define AT91_MATRIX (0xffffee00 - AT91_BASE_SYS)
#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
#define AT91_DBGU (0xfffff200 - AT91_BASE_SYS)
#define AT91_PIOA (0xfffff400 - AT91_BASE_SYS)
#define AT91_PIOB (0xfffff600 - AT91_BASE_SYS)
#define AT91_PIOC (0xfffff800 - AT91_BASE_SYS)
#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
#define AT91_SHDWC (0xfffffd10 - AT91_BASE_SYS)
#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
/*
* Internal Memory.
*/
#define AT91SAM9261_SRAM_BASE 0x00300000 /* Internal SRAM base address */
#define AT91SAM9261_SRAM_SIZE 0x00028000 /* Internal SRAM size (160Kb) */
#define AT91SAM9261_ROM_BASE 0x00400000 /* Internal ROM base address */
#define AT91SAM9261_ROM_SIZE SZ_32K /* Internal ROM size (32Kb) */
#define AT91SAM9261_UHP_BASE 0x00500000 /* USB Host controller */
#define AT91SAM9261_LCDC_BASE 0x00600000 /* LDC controller */
#if 0
/*
* PIO pin definitions (peripheral A/B multiplexing).
*/
#define AT91_PA0_SPI0_MISO (1 << 0) /* A: SPI0 Master In Slave */
#define AT91_PA0_MCDA0 (1 << 0) /* B: Multimedia Card A Data 0 */
#define AT91_PA1_SPI0_MOSI (1 << 1) /* A: SPI0 Master Out Slave */
#define AT91_PA1_MCCDA (1 << 1) /* B: Multimedia Card A Command */
#define AT91_PA2_SPI0_SPCK (1 << 2) /* A: SPI0 Serial Clock */
#define AT91_PA2_MCCK (1 << 2) /* B: Multimedia Card Clock */
#define AT91_PA3_SPI0_NPCS0 (1 << 3) /* A: SPI0 Peripheral Chip Select 0 */
#define AT91_PA4_SPI0_NPCS1 (1 << 4) /* A: SPI0 Peripheral Chip Select 1 */
#define AT91_PA4_MCDA1 (1 << 4) /* B: Multimedia Card A Data 1 */
#define AT91_PA5_SPI0_NPCS2 (1 << 5) /* A: SPI0 Peripheral Chip Select 2 */
#define AT91_PA5_MCDA2 (1 << 5) /* B: Multimedia Card A Data 2 */
#define AT91_PA6_SPI0_NPCS3 (1 << 6) /* A: SPI0 Peripheral Chip Select 3 */
#define AT91_PA6_MCDA3 (1 << 6) /* B: Multimedia Card A Data 3 */
#define AT91_PA7_TWD (1 << 7) /* A: TWI Two-wire Serial Data */
#define AT91_PA7_PCK0 (1 << 7) /* B: PMC Programmable clock Output 0 */
#define AT91_PA8_TWCK (1 << 8) /* A: TWI Two-wire Serial Clock */
#define AT91_PA8_PCK1 (1 << 8) /* B: PMC Programmable clock Output 1 */
#define AT91_PA9_DRXD (1 << 9) /* A: DBGU Debug Receive Data */
#define AT91_PA9_PCK2 (1 << 9) /* B: PMC Programmable clock Output 2 */
#define AT91_PA10_DTXD (1 << 10) /* A: DBGU Debug Transmit Data */
#define AT91_PA10_PCK3 (1 << 10) /* B: PMC Programmable clock Output 3 */
#define AT91_PA11_TSYNC (1 << 11) /* A: Trace Synchronization Signal */
#define AT91_PA11_SCK1 (1 << 11) /* B: USART1 Serial Clock */
#define AT91_PA12_TCLK (1 << 12) /* A: Trace Clock */
#define AT91_PA12_RTS1 (1 << 12) /* B: USART1 Ready To Send */
#define AT91_PA13_TPS0 (1 << 13) /* A: Trace ARM Pipeline Status 0 */
#define AT91_PA13_CTS1 (1 << 13) /* B: USART1 Clear To Send */
#define AT91_PA14_TPS1 (1 << 14) /* A: Trace ARM Pipeline Status 1 */
#define AT91_PA14_SCK2 (1 << 14) /* B: USART2 Serial Clock */
#define AT91_PA15_TPS2 (1 << 15) /* A: Trace ARM Pipeline Status 2 */
#define AT91_PA15_RTS2 (1 << 15) /* B: USART2 Ready To Send */
#define AT91_PA16_TPK0 (1 << 16) /* A: Trace Packet Port 0 */
#define AT91_PA16_CTS2 (1 << 16) /* B: USART2 Clear To Send */
#define AT91_PA17_TPK1 (1 << 17) /* A: Trace Packet Port 1 */
#define AT91_PA17_TF1 (1 << 17) /* B: SSC1 Transmit Frame Sync */
#define AT91_PA18_TPK2 (1 << 18) /* A: Trace Packet Port 2 */
#define AT91_PA18_TK1 (1 << 18) /* B: SSC1 Transmit Clock */
#define AT91_PA19_TPK3 (1 << 19) /* A: Trace Packet Port 3 */
#define AT91_PA19_TD1 (1 << 19) /* B: SSC1 Transmit Data */
#define AT91_PA20_TPK4 (1 << 20) /* A: Trace Packet Port 4 */
#define AT91_PA20_RD1 (1 << 20) /* B: SSC1 Receive Data */
#define AT91_PA21_TPK5 (1 << 21) /* A: Trace Packet Port 5 */
#define AT91_PA21_RK1 (1 << 21) /* B: SSC1 Receive Clock */
#define AT91_PA22_TPK6 (1 << 22) /* A: Trace Packet Port 6 */
#define AT91_PA22_RF1 (1 << 22) /* B: SSC1 Receive Frame Sync */
#define AT91_PA23_TPK7 (1 << 23) /* A: Trace Packet Port 7 */
#define AT91_PA23_RTS0 (1 << 23) /* B: USART0 Ready To Send */
#define AT91_PA24_TPK8 (1 << 24) /* A: Trace Packet Port 8 */
#define AT91_PA24_SPI1_NPCS1 (1 << 24) /* B: SPI1 Peripheral Chip Select 1 */
#define AT91_PA25_TPK9 (1 << 25) /* A: Trace Packet Port 9 */
#define AT91_PA25_SPI1_NPCS2 (1 << 25) /* B: SPI1 Peripheral Chip Select 2 */
#define AT91_PA26_TPK10 (1 << 26) /* A: Trace Packet Port 10 */
#define AT91_PA26_SPI1_NPCS3 (1 << 26) /* B: SPI1 Peripheral Chip Select 3 */
#define AT91_PA27_TPK11 (1 << 27) /* A: Trace Packet Port 11 */
#define AT91_PA27_SPI0_NPCS1 (1 << 27) /* B: SPI0 Peripheral Chip Select 1 */
#define AT91_PA28_TPK12 (1 << 28) /* A: Trace Packet Port 12 */
#define AT91_PA28_SPI0_NPCS2 (1 << 28) /* B: SPI0 Peripheral Chip Select 2 */
#define AT91_PA29_TPK13 (1 << 29) /* A: Trace Packet Port 13 */
#define AT91_PA29_SPI0_NPCS3 (1 << 29) /* B: SPI0 Peripheral Chip Select 3 */
#define AT91_PA30_TPK14 (1 << 30) /* A: Trace Packet Port 14 */
#define AT91_PA30_A23 (1 << 30) /* B: Address Bus bit 23 */
#define AT91_PA31_TPK15 (1 << 31) /* A: Trace Packet Port 15 */
#define AT91_PA31_A24 (1 << 31) /* B: Address Bus bit 24 */
#define AT91_PB0_LCDVSYNC (1 << 0) /* A: LCD Vertical Synchronization */
#define AT91_PB1_LCDHSYNC (1 << 1) /* A: LCD Horizontal Synchronization */
#define AT91_PB2_LCDDOTCK (1 << 2) /* A: LCD Dot Clock */
#define AT91_PB2_PCK0 (1 << 2) /* B: PMC Programmable clock Output 0 */
#define AT91_PB3_LCDDEN (1 << 3) /* A: LCD Data Enable */
#define AT91_PB4_LCDCC (1 << 4) /* A: LCD Contrast Control */
#define AT91_PB4_LCDD2 (1 << 4) /* B: LCD Data Bus Bit 2 */
#define AT91_PB5_LCDD0 (1 << 5) /* A: LCD Data Bus Bit 0 */
#define AT91_PB5_LCDD3 (1 << 5) /* B: LCD Data Bus Bit 3 */
#define AT91_PB6_LCDD1 (1 << 6) /* A: LCD Data Bus Bit 1 */
#define AT91_PB6_LCDD4 (1 << 6) /* B: LCD Data Bus Bit 4 */
#define AT91_PB7_LCDD2 (1 << 7) /* A: LCD Data Bus Bit 2 */
#define AT91_PB7_LCDD5 (1 << 7) /* B: LCD Data Bus Bit 5 */
#define AT91_PB8_LCDD3 (1 << 8) /* A: LCD Data Bus Bit 3 */
#define AT91_PB8_LCDD6 (1 << 8) /* B: LCD Data Bus Bit 6 */
#define AT91_PB9_LCDD4 (1 << 9) /* A: LCD Data Bus Bit 4 */
#define AT91_PB9_LCDD7 (1 << 9) /* B: LCD Data Bus Bit 7 */
#define AT91_PB10_LCDD5 (1 << 10) /* A: LCD Data Bus Bit 5 */
#define AT91_PB10_LCDD10 (1 << 10) /* B: LCD Data Bus Bit 10 */
#define AT91_PB11_LCDD6 (1 << 11) /* A: LCD Data Bus Bit 6 */
#define AT91_PB11_LCDD11 (1 << 11) /* B: LCD Data Bus Bit 11 */
#define AT91_PB12_LCDD7 (1 << 12) /* A: LCD Data Bus Bit 7 */
#define AT91_PB12_LCDD12 (1 << 12) /* B: LCD Data Bus Bit 12 */
#define AT91_PB13_LCDD8 (1 << 13) /* A: LCD Data Bus Bit 8 */
#define AT91_PB13_LCDD13 (1 << 13) /* B: LCD Data Bus Bit 13 */
#define AT91_PB14_LCDD9 (1 << 14) /* A: LCD Data Bus Bit 9 */
#define AT91_PB14_LCDD14 (1 << 14) /* B: LCD Data Bus Bit 14 */
#define AT91_PB15_LCDD10 (1 << 15) /* A: LCD Data Bus Bit 10 */
#define AT91_PB15_LCDD15 (1 << 15) /* B: LCD Data Bus Bit 15 */
#define AT91_PB16_LCDD11 (1 << 16) /* A: LCD Data Bus Bit 11 */
#define AT91_PB16_LCDD19 (1 << 16) /* B: LCD Data Bus Bit 19 */
#define AT91_PB17_LCDD12 (1 << 17) /* A: LCD Data Bus Bit 12 */
#define AT91_PB17_LCDD20 (1 << 17) /* B: LCD Data Bus Bit 20 */
#define AT91_PB18_LCDD13 (1 << 18) /* A: LCD Data Bus Bit 13 */
#define AT91_PB18_LCDD21 (1 << 18) /* B: LCD Data Bus Bit 21 */
#define AT91_PB19_LCDD14 (1 << 19) /* A: LCD Data Bus Bit 14 */
#define AT91_PB19_LCDD22 (1 << 19) /* B: LCD Data Bus Bit 22 */
#define AT91_PB20_LCDD15 (1 << 20) /* A: LCD Data Bus Bit 15 */
#define AT91_PB20_LCDD23 (1 << 20) /* B: LCD Data Bus Bit 23 */
#define AT91_PB21_TF0 (1 << 21) /* A: SSC0 Transmit Frame Sync */
#define AT91_PB21_LCDD16 (1 << 21) /* B: LCD Data Bus Bit 16 */
#define AT91_PB22_TK0 (1 << 22) /* A: SSC0 Transmit Clock */
#define AT91_PB22_LCDD17 (1 << 22) /* B: LCD Data Bus Bit 17 */
#define AT91_PB23_TD0 (1 << 23) /* A: SSC0 Transmit Data */
#define AT91_PB23_LCDD18 (1 << 23) /* B: LCD Data Bus Bit 18 */
#define AT91_PB24_RD0 (1 << 24) /* A: SSC0 Receive Data */
#define AT91_PB24_LCDD19 (1 << 24) /* B: LCD Data Bus Bit 19 */
#define AT91_PB25_RK0 (1 << 25) /* A: SSC0 Receive Clock */
#define AT91_PB25_LCDD20 (1 << 25) /* B: LCD Data Bus Bit 20 */
#define AT91_PB26_RF0 (1 << 26) /* A: SSC0 Receive Frame Sync */
#define AT91_PB26_LCDD21 (1 << 26) /* B: LCD Data Bus Bit 21 */
#define AT91_PB27_SPI1_NPCS1 (1 << 27) /* A: SPI1 Peripheral Chip Select 1 */
#define AT91_PB27_LCDD22 (1 << 27) /* B: LCD Data Bus Bit 22 */
#define AT91_PB28_SPI1_NPCS0 (1 << 28) /* A: SPI1 Peripheral Chip Select 0 */
#define AT91_PB28_LCDD23 (1 << 28) /* B: LCD Data Bus Bit 23 */
#define AT91_PB29_SPI1_SPCK (1 << 29) /* A: SPI1 Serial Clock */
#define AT91_PB29_IRQ2 (1 << 29) /* B: Interrupt input 2 */
#define AT91_PB30_SPI1_MISO (1 << 30) /* A: SPI1 Master In Slave */
#define AT91_PB30_IRQ1 (1 << 30) /* B: Interrupt input 1 */
#define AT91_PB31_SPI1_MOSI (1 << 31) /* A: SPI1 Master Out Slave */
#define AT91_PB31_PCK2 (1 << 31) /* B: PMC Programmable clock Output 2 */
#define AT91_PC0_SMOE (1 << 0) /* A: SmartMedia Output Enable */
#define AT91_PC0_NCS6 (1 << 0) /* B: Chip Select 6 */
#define AT91_PC1_SMWE (1 << 1) /* A: SmartMedia Write Enable */
#define AT91_PC1_NCS7 (1 << 1) /* B: Chip Select 7 */
#define AT91_PC2_NWAIT (1 << 2) /* A: NWAIT */
#define AT91_PC2_IRQ0 (1 << 2) /* B: Interrupt input 0 */
#define AT91_PC3_A25_CFRNW (1 << 3) /* A: Address Bus[25] / Compact Flash Read Not Write */
#define AT91_PC4_NCS4_CFCS0 (1 << 4) /* A: Chip Select 4 / CompactFlash Chip Select 0 */
#define AT91_PC5_NCS5_CFCS1 (1 << 5) /* A: Chip Select 5 / CompactFlash Chip Select 1 */
#define AT91_PC6_CFCE1 (1 << 6) /* A: CompactFlash Chip Enable 1 */
#define AT91_PC7_CFCE2 (1 << 7) /* A: CompactFlash Chip Enable 2 */
#define AT91_PC8_TXD0 (1 << 8) /* A: USART0 Transmit Data */
#define AT91_PC8_PCK2 (1 << 8) /* B: PMC Programmable clock Output 2 */
#define AT91_PC9_RXD0 (1 << 9) /* A: USART0 Receive Data */
#define AT91_PC9_PCK3 (1 << 9) /* B: PMC Programmable clock Output 3 */
#define AT91_PC10_RTS0 (1 << 10) /* A: USART0 Ready To Send */
#define AT91_PC10_SCK0 (1 << 10) /* B: USART0 Serial Clock */
#define AT91_PC11_CTS0 (1 << 11) /* A: USART0 Clear To Send */
#define AT91_PC11_FIQ (1 << 11) /* B: AIC Fast Interrupt Input */
#define AT91_PC12_TXD1 (1 << 12) /* A: USART1 Transmit Data */
#define AT91_PC12_NCS6 (1 << 12) /* B: Chip Select 6 */
#define AT91_PC13_RXD1 (1 << 13) /* A: USART1 Receive Data */
#define AT91_PC13_NCS7 (1 << 13) /* B: Chip Select 7 */
#define AT91_PC14_TXD2 (1 << 14) /* A: USART2 Transmit Data */
#define AT91_PC14_SPI1_NPCS2 (1 << 14) /* B: SPI1 Peripheral Chip Select 2 */
#define AT91_PC15_RXD2 (1 << 15) /* A: USART2 Receive Data */
#define AT91_PC15_SPI1_NPCS3 (1 << 15) /* B: SPI1 Peripheral Chip Select 3 */
#define AT91_PC16_D16 (1 << 16) /* A: Data Bus [16] */
#define AT91_PC16_TCLK0 (1 << 16) /* B: Timer Counter 0 external clock input */
#define AT91_PC17_D17 (1 << 17) /* A: Data Bus [17] */
#define AT91_PC17_TCLK1 (1 << 17) /* B: Timer Counter 1 external clock input */
#define AT91_PC18_D18 (1 << 18) /* A: Data Bus [18] */
#define AT91_PC18_TCLK2 (1 << 18) /* B: Timer Counter 2 external clock input */
#define AT91_PC19_D19 (1 << 19) /* A: Data Bus [19] */
#define AT91_PC19_TIOA0 (1 << 19) /* B: Timer Counter 0 Multipurpose Timer I/O Pin A */
#define AT91_PC20_D20 (1 << 20) /* A: Data Bus [20] */
#define AT91_PC20_TIOB0 (1 << 20) /* B: Timer Counter 0 Multipurpose Timer I/O Pin B */
#define AT91_PC21_D21 (1 << 21) /* A: Data Bus [21] */
#define AT91_PC21_TIOA1 (1 << 21) /* B: Timer Counter 1 Multipurpose Timer I/O Pin A */
#define AT91_PC22_D22 (1 << 22) /* A: Data Bus [22] */
#define AT91_PC22_TIOB1 (1 << 22) /* B: Timer Counter 1 Multipurpose Timer I/O Pin B */
#define AT91_PC23_D23 (1 << 23) /* A: Data Bus [23] */
#define AT91_PC23_TIOA2 (1 << 23) /* B: Timer Counter 2 Multipurpose Timer I/O Pin A */
#define AT91_PC24_D24 (1 << 24) /* A: Data Bus [24] */
#define AT91_PC24_TIOB2 (1 << 24) /* B: Timer Counter 2 Multipurpose Timer I/O Pin B */
#define AT91_PC25_D25 (1 << 25) /* A: Data Bus [25] */
#define AT91_PC25_TF2 (1 << 25) /* B: SSC2 Transmit Frame Sync */
#define AT91_PC26_D26 (1 << 26) /* A: Data Bus [26] */
#define AT91_PC26_TK2 (1 << 26) /* B: SSC2 Transmit Clock */
#define AT91_PC27_D27 (1 << 27) /* A: Data Bus [27] */
#define AT91_PC27_TD2 (1 << 27) /* B: SSC2 Transmit Data */
#define AT91_PC28_D28 (1 << 28) /* A: Data Bus [28] */
#define AT91_PC28_RD2 (1 << 28) /* B: SSC2 Receive Data */
#define AT91_PC29_D29 (1 << 29) /* A: Data Bus [29] */
#define AT91_PC29_RK2 (1 << 29) /* B: SSC2 Receive Clock */
#define AT91_PC30_D30 (1 << 30) /* A: Data Bus [30] */
#define AT91_PC30_RF2 (1 << 30) /* B: SSC2 Receive Frame Sync */
#define AT91_PC31_D31 (1 << 31) /* A: Data Bus [31] */
#define AT91_PC31_PCK1 (1 << 31) /* B: PMC Programmable clock Output 1 */
#endif
#endif
include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
+62
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@@ -0,0 +1,62 @@
/*
* include/asm-arm/arch-at91rm9200/at91sam9261_matrix.h
*
* Memory Controllers (MATRIX, EBI) - System peripherals registers.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM9261_MATRIX_H
#define AT91SAM9261_MATRIX_H
#define AT91_MATRIX_MCFG (AT91_MATRIX + 0x00) /* Master Configuration Register */
#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
#define AT01_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x04) /* Slave Configuration Register 0 */
#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x08) /* Slave Configuration Register 1 */
#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x0C) /* Slave Configuration Register 2 */
#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x10) /* Slave Configuration Register 3 */
#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x14) /* Slave Configuration Register 4 */
#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */
#define AT91_MATRIX_TCR (AT91_MATRIX + 0x24) /* TCM Configuration Register */
#define AT91_MATRIX_ITCM_SIZE (0xf << 0) /* Size of ITCM enabled memory block */
#define AT91_MATRIX_ITCM_0 (0 << 0)
#define AT91_MATRIX_ITCM_16 (5 << 0)
#define AT91_MATRIX_ITCM_32 (6 << 0)
#define AT91_MATRIX_ITCM_64 (7 << 0)
#define AT91_MATRIX_DTCM_SIZE (0xf << 4) /* Size of DTCM enabled memory block */
#define AT91_MATRIX_DTCM_0 (0 << 4)
#define AT91_MATRIX_DTCM_16 (5 << 4)
#define AT91_MATRIX_DTCM_32 (6 << 4)
#define AT91_MATRIX_DTCM_64 (7 << 4)
#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x30) /* EBI Chip Select Assignment Register */
#define AT91_MATRIX_CS1A (1 << 1) /* Chip Select 1 Assignment */
#define AT91_MATRIX_CS1A_SMC (0 << 1)
#define AT91_MATRIX_CS1A_SDRAMC (1 << 1)
#define AT91_MATRIX_CS3A (1 << 3) /* Chip Select 3 Assignment */
#define AT91_MATRIX_CS3A_SMC (0 << 3)
#define AT91_MATRIX_CS3A_SMC_SMARTMEDIA (1 << 3)
#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
#define AT91_MATRIX_CS4A_SMC (0 << 4)
#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
#define AT91_MATRIX_CS5A_SMC (0 << 5)
#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
#define AT91_MATRIX_USBPUCR (AT91_MATRIX + 0x34) /* USB Pad Pull-Up Control Register */
#define AT91_MATRIX_USBPUCR_PUON (1 << 30) /* USB Device PAD Pull-up Enable */
#endif
include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
+134
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@@ -0,0 +1,134 @@
/*
* include/asm-arm/arch-at91rm9200/at91sam926x_mc.h
*
* Memory Controllers (SMC, SDRAMC) - System peripherals registers.
* Based on AT91SAM9261 datasheet revision D.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#ifndef AT91SAM926x_MC_H
#define AT91SAM926x_MC_H
/* SDRAM Controller (SDRAMC) registers */
#define AT91_SDRAMC_MR (AT91_SDRAMC + 0x00) /* SDRAM Controller Mode Register */
#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
#define AT91_SDRAMC_MODE_NORMAL 0
#define AT91_SDRAMC_MODE_NOP 1
#define AT91_SDRAMC_MODE_PRECHARGE 2
#define AT91_SDRAMC_MODE_LMR 3
#define AT91_SDRAMC_MODE_REFRESH 4
#define AT91_SDRAMC_MODE_EXT_LMR 5
#define AT91_SDRAMC_MODE_DEEP 6
#define AT91_SDRAMC_TR (AT91_SDRAMC + 0x04) /* SDRAM Controller Refresh Timer Register */
#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
#define AT91_SDRAMC_CR (AT91_SDRAMC + 0x08) /* SDRAM Controller Configuration Register */
#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
#define AT91_SDRAMC_NC_8 (0 << 0)
#define AT91_SDRAMC_NC_9 (1 << 0)
#define AT91_SDRAMC_NC_10 (2 << 0)
#define AT91_SDRAMC_NC_11 (3 << 0)
#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
#define AT91_SDRAMC_NR_11 (0 << 2)
#define AT91_SDRAMC_NR_12 (1 << 2)
#define AT91_SDRAMC_NR_13 (2 << 2)
#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
#define AT91_SDRAMC_NB_2 (0 << 4)
#define AT91_SDRAMC_NB_4 (1 << 4)
#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
#define AT91_SDRAMC_CAS_1 (1 << 5)
#define AT91_SDRAMC_CAS_2 (2 << 5)
#define AT91_SDRAMC_CAS_3 (3 << 5)
#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
#define AT91_SDRAMC_DBW_32 (0 << 7)
#define AT91_SDRAMC_DBW_16 (1 << 7)
#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
#define AT91_SDRAMC_LPR (AT91_SDRAMC + 0x10) /* SDRAM Controller Low Power Register */
#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
#define AT91_SDRAMC_LPCB_DISABLE 0
#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
#define AT91_SDRAMC_LPCB_POWER_DOWN 2
#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
#define AT91_SDRAMC_DS (3 << 10) /* Drive Strenght */
#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
#define AT91_SDRAMC_IER (AT91_SDRAMC + 0x14) /* SDRAM Controller Interrupt Enable Register */
#define AT91_SDRAMC_IDR (AT91_SDRAMC + 0x18) /* SDRAM Controller Interrupt Disable Register */
#define AT91_SDRAMC_IMR (AT91_SDRAMC + 0x1C) /* SDRAM Controller Interrupt Mask Register */
#define AT91_SDRAMC_ISR (AT91_SDRAMC + 0x20) /* SDRAM Controller Interrupt Status Register */
#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
#define AT91_SDRAMC_MDR (AT91_SDRAMC + 0x24) /* SDRAM Memory Device Register */
#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
#define AT91_SDRAMC_MD_SDRAM 0
#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
/* Static Memory Controller (SMC) registers */
#define AT91_SMC_SETUP(n) (AT91_SMC + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
#define AT91_SMC_NWESETUP (0x3f << 0) /* NWE Setup Length */
#define AT91_SMC_NWESETUP_(x) ((x) << 0)
#define AT91_SMC_NCS_WRSETUP (0x3f << 8) /* NCS Setup Length in Write Access */
#define AT91_SMC_NCS_WRSETUP_(x) ((x) << 8)
#define AT91_SMC_NRDSETUP (0x3f << 16) /* NRD Setup Length */
#define AT91_SMC_NRDSETUP_(x) ((x) << 16)
#define AT91_SMC_NCS_RDSETUP (0x3f << 24) /* NCS Setup Length in Read Access */
#define AT91_SMC_NCS_RDSETUP_(x) ((x) << 24)
#define AT91_SMC_PULSE(n) (AT91_SMC + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
#define AT91_SMC_NWEPULSE (0x7f << 0) /* NWE Pulse Length */
#define AT91_SMC_NWEPULSE_(x) ((x) << 0)
#define AT91_SMC_NCS_WRPULSE (0x7f << 8) /* NCS Pulse Length in Write Access */
#define AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
#define AT91_SMC_NRDPULSE (0x7f << 16) /* NRD Pulse Length */
#define AT91_SMC_NRDPULSE_(x) ((x) << 16)
#define AT91_SMC_NCS_RDPULSE (0x7f << 24) /* NCS Pulse Length in Read Access */
#define AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
#define AT91_SMC_CYCLE(n) (AT91_SMC + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
#define AT91_SMC_NWECYCLE (0x1ff << 0 ) /* Total Write Cycle Length */
#define AT91_SMC_NWECYCLE_(x) ((x) << 0)
#define AT91_SMC_NRDCYCLE (0x1ff << 16) /* Total Read Cycle Length */
#define AT91_SMC_NRDCYCLE_(x) ((x) << 16)
#define AT91_SMC_MODE(n) (AT91_SMC + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
#define AT91_SMC_READMODE (1 << 0) /* Read Mode */
#define AT91_SMC_WRITEMODE (1 << 1) /* Write Mode */
#define AT91_SMC_EXNWMODE (3 << 5) /* NWAIT Mode */
#define AT91_SMC_EXNWMODE_DISABLE (0 << 5)
#define AT91_SMC_EXNWMODE_FROZEN (2 << 5)
#define AT91_SMC_EXNWMODE_READY (3 << 5)
#define AT91_SMC_BAT (1 << 8) /* Byte Access Type */
#define AT91_SMC_BAT_SELECT (0 << 8)
#define AT91_SMC_BAT_WRITE (1 << 8)
#define AT91_SMC_DBW (3 << 12) /* Data Bus Width */
#define AT91_SMC_DBW_8 (0 << 12)
#define AT91_SMC_DBW_16 (1 << 12)
#define AT91_SMC_DBW_32 (2 << 12)
#define AT91_SMC_TDF (0xf << 16) /* Data Float Time. */
#define AT91_SMC_TDF_(x) ((x) << 16)
#define AT91_SMC_TDFMODE (1 << 20) /* TDF Optimization - Enabled */
#define AT91_SMC_PMEN (1 << 24) /* Page Mode Enabled */
#define AT91_SMC_PS (3 << 28) /* Page Size */
#define AT91_SMC_PS_4 (0 << 28)
#define AT91_SMC_PS_8 (1 << 28)
#define AT91_SMC_PS_16 (2 << 28)
#define AT91_SMC_PS_32 (3 << 28)
#endif
include/asm-arm/arch-at91rm9200/board.h
+4 -2
View File
@@ -48,13 +48,14 @@ struct at91_cf_data {
u8 det_pin; /* Card detect */
u8 vcc_pin; /* power switching */
u8 rst_pin; /* card reset */
u8 chipselect; /* EBI Chip Select number */
};
extern void __init at91_add_device_cf(struct at91_cf_data *data);
/* MMC / SD */
struct at91_mmc_data {
u8 det_pin; /* card detect IRQ */
unsigned is_b:1; /* uses B side (vs A) */
unsigned slot_b:1; /* uses Slot B */
unsigned wire4:1; /* (SD) supports DAT0..DAT3 */
u8 wp_pin; /* (SD) writeprotect detect */
u8 vcc_pin; /* power switching (high == on) */
@@ -81,7 +82,8 @@ struct at91_nand_data {
u8 rdy_pin; /* ready/busy */
u8 ale; /* address line number connected to ALE */
u8 cle; /* address line number connected to CLE */
struct mtd_partition* (*partition_info)(int, int*);
u8 bus_width_16; /* buswidth is 16 bit */
struct mtd_partition* (*partition_info)(int, int*);
};
extern void __init at91_add_device_nand(struct at91_nand_data *data);
include/asm-arm/arch-at91rm9200/cpu.h
+49
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@@ -0,0 +1,49 @@
/*
* include/asm-arm/arch-at91rm9200/cpu.h
*
* Copyright (C) 2006 SAN People
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
*/
#ifndef __ASM_ARCH_CPU_H
#define __ASM_ARCH_CPU_H
#include <asm/hardware.h>
#include <asm/arch/at91_dbgu.h>
#define ARCH_ID_AT91RM9200 0x09290780
#define ARCH_ID_AT91SAM9260 0x019803a0
#define ARCH_ID_AT91SAM9261 0x019703a0
static inline unsigned long at91_cpu_identify(void)
{
return (at91_sys_read(AT91_DBGU_CIDR) & ~AT91_CIDR_VERSION);
}
#ifdef CONFIG_ARCH_AT91RM9200
#define cpu_is_at91rm9200() (at91_cpu_identify() == ARCH_ID_AT91RM9200)
#else
#define cpu_is_at91rm9200() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9260
#define cpu_is_at91sam9260() (at91_cpu_identify() == ARCH_ID_AT91SAM9260)
#else
#define cpu_is_at91sam9260() (0)
#endif
#ifdef CONFIG_ARCH_AT91SAM9261
#define cpu_is_at91sam9261() (at91_cpu_identify() == ARCH_ID_AT91SAM9261)
#else
#define cpu_is_at91sam9261() (0)
#endif
#endif
include/asm-arm/arch-at91rm9200/debug-macro.S
+1
View File
@@ -12,6 +12,7 @@
*/
#include <asm/hardware.h>
#include <asm/arch/at91_dbgu.h>
.macro addruart,rx
mrc p15, 0, \rx, c1, c0
include/asm-arm/arch-at91rm9200/entry-macro.S
+1
View File
@@ -11,6 +11,7 @@
*/
#include <asm/hardware.h>
#include <asm/arch/at91_aic.h>
.macro disable_fiq
.endm
include/asm-arm/arch-at91rm9200/hardware.h
+22 -16
View File
@@ -16,8 +16,16 @@
#include <asm/sizes.h>
#if defined(CONFIG_ARCH_AT91RM9200)
#include <asm/arch/at91rm9200.h>
#include <asm/arch/at91rm9200_sys.h>
#elif defined(CONFIG_ARCH_AT91SAM9260)
#include <asm/arch/at91sam9260.h>
#elif defined(CONFIG_ARCH_AT91SAM9261)
#include <asm/arch/at91sam9261.h>
#else
#error "Unsupported AT91 processor"
#endif
/*
* Remap the peripherals from address 0xFFFA0000 .. 0xFFFFFFFF
@@ -34,29 +42,27 @@
* Virtual to Physical Address mapping for IO devices.
*/
#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91RM9200_BASE_SPI)
#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC)
#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91RM9200_BASE_TWI)
#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91RM9200_BASE_MCI)
#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91RM9200_BASE_UDP)
/* Internal SRAM is mapped below the IO devices */
#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE)
#define AT91_SRAM_MAX SZ_1M
#define AT91_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_MAX)
/* Serial ports */
#define ATMEL_MAX_UART 5 /* 4 USART3's and one DBGU port */
#define ATMEL_MAX_UART 7 /* 6 USART3's and one DBGU port (SAM9260) */
/* FLASH */
#define AT91_FLASH_BASE 0x10000000 /* NCS0: Flash physical base address */
/* External Memory Map */
#define AT91_CHIPSELECT_0 0x10000000
#define AT91_CHIPSELECT_1 0x20000000
#define AT91_CHIPSELECT_2 0x30000000
#define AT91_CHIPSELECT_3 0x40000000
#define AT91_CHIPSELECT_4 0x50000000
#define AT91_CHIPSELECT_5 0x60000000
#define AT91_CHIPSELECT_6 0x70000000
#define AT91_CHIPSELECT_7 0x80000000
/* SDRAM */
#define AT91_SDRAM_BASE 0x20000000 /* NCS1: SDRAM physical base address */
/* SmartMedia */
#define AT91_SMARTMEDIA_BASE 0x40000000 /* NCS3: Smartmedia physical base address */
/* Compact Flash */
#define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */
#define AT91_SDRAM_BASE AT91_CHIPSELECT_1
/* Clocks */
#define AT91_SLOW_CLOCK 32768 /* slow clock */
include/asm-arm/arch-at91rm9200/irqs.h
+2
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@@ -21,6 +21,8 @@
#ifndef __ASM_ARCH_IRQS_H
#define __ASM_ARCH_IRQS_H
#include <asm/arch/at91_aic.h>
#define NR_AIC_IRQS 32
include/asm-arm/arch-at91rm9200/system.h
+7 -13
View File
@@ -22,6 +22,8 @@
#define __ASM_ARCH_SYSTEM_H
#include <asm/hardware.h>
#include <asm/arch/at91_st.h>
#include <asm/arch/at91_dbgu.h>
static inline void arch_idle(void)
{
@@ -39,21 +41,13 @@ static inline void arch_idle(void)
cpu_do_idle();
}
void (*at91_arch_reset)(void);
static inline void arch_reset(char mode)
{
/*
* Perform a hardware reset with the use of the Watchdog timer.
*/
at91_sys_write(AT91_ST_WDMR, AT91_ST_RSTEN | AT91_ST_EXTEN | 1);
at91_sys_write(AT91_ST_CR, AT91_ST_WDRST);
}
#define ARCH_ID_AT91RM9200 0x09200080
#define ARCH_ID_AT91SAM9261 0x019000a0
static inline unsigned long arch_identify(void)
{
return at91_sys_read(AT91_DBGU_CIDR) & (AT91_CIDR_EPROC | AT91_CIDR_ARCH);
/* call the CPU-specific reset function */
if (at91_arch_reset)
(at91_arch_reset)();
}
#endif
include/asm-arm/arch-at91rm9200/timex.h
+9
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@@ -23,6 +23,15 @@
#include <asm/hardware.h>
#if defined(CONFIG_ARCH_AT91RM9200)
#define CLOCK_TICK_RATE (AT91_SLOW_CLOCK)
#elif defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9261)
#define AT91SAM9_MASTER_CLOCK 99300000
#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
#endif
#endif
include/asm-arm/arch-at91rm9200/uncompress.h
+2 -2
View File
@@ -22,11 +22,11 @@
#define __ASM_ARCH_UNCOMPRESS_H
#include <asm/hardware.h>
#include <asm/arch/at91_dbgu.h>
/*
* The following code assumes the serial port has already been
* initialized by the bootloader. We search for the first enabled
* port in the most probable order. If you didn't setup a port in
* initialized by the bootloader. If you didn't setup a port in
* your bootloader then nothing will appear (which might be desired).
*
* This does not append a newline
include/asm-arm/arch-at91rm9200/vmalloc.h
+1 -1
View File
@@ -21,6 +21,6 @@
#ifndef __ASM_ARCH_VMALLOC_H
#define __ASM_ARCH_VMALLOC_H
#define VMALLOC_END (AT91_SRAM_VIRT_BASE & PGDIR_MASK)
#define VMALLOC_END (AT91_VIRT_BASE & PGDIR_MASK)
#endif
include/asm-arm/arch-clps711x/memory.h
+10 -43
View File
@@ -62,7 +62,15 @@
* memory bank. For those systems, simply undefine CONFIG_DISCONTIGMEM.
*/
#ifdef CONFIG_DISCONTIGMEM
/*
* The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
* uses only one of the two banks (bank #1). However, even within
* bank #1, memory is discontiguous.
*
* The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
* them, so we use 24 for the node max shift to get 16MB node sizes.
*/
/*
* Because of the wide memory address space between physical RAM banks on the
* SA1100, it's much more convenient to use Linux's NUMA support to implement
@@ -80,48 +88,7 @@
* node 2: 0xd0000000 - 0xd7ffffff
* node 3: 0xd8000000 - 0xdfffffff
*/
/*
* Given a kernel address, find the home node of the underlying memory.
*/
#define KVADDR_TO_NID(addr) \
(((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MAX_MEM_SHIFT)
/*
* Given a page frame number, convert it to a node id.
*/
#define PFN_TO_NID(pfn) \
(((pfn) - PHYS_PFN_OFFSET) >> (NODE_MAX_MEM_SHIFT - PAGE_SHIFT))
/*
* Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
* and returns the mem_map of that node.
*/
#define ADDR_TO_MAPBASE(kaddr) \
NODE_MEM_MAP(KVADDR_TO_NID((unsigned long)(kaddr)))
#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
/*
* Given a kaddr, LOCAL_MAR_NR finds the owning node of the memory
* and returns the index corresponding to the appropriate page in the
* node's mem_map.
*/
#define LOCAL_MAP_NR(addr) \
(((unsigned long)(addr) & (NODE_MAX_MEM_SIZE - 1)) >> PAGE_SHIFT)
/*
* The PS7211 allows up to 256MB max per DRAM bank, but the EDB7211
* uses only one of the two banks (bank #1). However, even within
* bank #1, memory is discontiguous.
*
* The EDB7211 has two 8MB DRAM areas with 8MB of empty space between
* them, so we use 24 for the node max shift to get 16MB node sizes.
*/
#define NODE_MAX_MEM_SHIFT 24
#define NODE_MAX_MEM_SIZE (1<<NODE_MAX_MEM_SHIFT)
#endif /* CONFIG_DISCONTIGMEM */
#define NODE_MEM_SIZE_BITS 24
#endif
include/asm-arm/arch-imx/timex.h
+1 -2
View File
@@ -21,7 +21,6 @@
#ifndef __ASM_ARCH_TIMEX_H
#define __ASM_ARCH_TIMEX_H
#include <asm/hardware.h>
#define CLOCK_TICK_RATE (CLK32)
#define CLOCK_TICK_RATE (16000000)
#endif
include/asm-arm/arch-iop13xx/debug-macro.S
+26
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@@ -0,0 +1,26 @@
/*
* include/asm-arm/arch-iop13xx/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 1994-1999 Russell King
* Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
.macro addruart, rx
mrc p15, 0, \rx, c1, c0
tst \rx, #1 @ mmu enabled?
moveq \rx, #0xff000000 @ physical
orreq \rx, \rx, #0x00d80000
movne \rx, #0xfe000000 @ virtual
orrne \rx, \rx, #0x00e80000
orr \rx, \rx, #0x00002300
orr \rx, \rx, #0x00000040
.endm
#define UART_SHIFT 2
#include <asm/hardware/debug-8250.S>
include/asm-arm/arch-iop13xx/dma.h
+3
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@@ -0,0 +1,3 @@
#ifndef _IOP13XX_DMA_H
#define _IOP13XX_DMA_H_
#endif
include/asm-arm/arch-iop13xx/entry-macro.S
+39
View File
@@ -0,0 +1,39 @@
/*
* iop13xx low level irq macros
* Copyright (c) 2005-2006, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
*/
.macro disable_fiq
.endm
/*
* Note: a 1-cycle window exists where iintvec will return the value
* of iintbase, so we explicitly check for "bad zeros"
*/
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mrc p15, 0, \tmp, c15, c1, 0
orr \tmp, \tmp, #(1 << 6)
mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC
cmp \irqnr, #0
mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero
adds \irqstat, \irqnr, #1 @ Check for 0xffffffff
movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr
biceq \tmp, \tmp, #(1 << 6)
mcreq p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access if no more interrupts
.endm
include/asm-arm/arch-iop13xx/hardware.h
+28
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@@ -0,0 +1,28 @@
#ifndef __ASM_ARCH_HARDWARE_H
#define __ASM_ARCH_HARDWARE_H
#include <asm/types.h>
#define pcibios_assign_all_busses() 1
#ifndef __ASSEMBLY__
extern unsigned long iop13xx_pcibios_min_io;
extern unsigned long iop13xx_pcibios_min_mem;
extern u16 iop13xx_dev_id(void);
extern void iop13xx_set_atu_mmr_bases(void);
#endif
#define PCIBIOS_MIN_IO (iop13xx_pcibios_min_io)
#define PCIBIOS_MIN_MEM (iop13xx_pcibios_min_mem)
/*
* Generic chipset bits
*
*/
#include "iop13xx.h"
/*
* Board specific bits
*/
#include "iq81340.h"
#endif /* _ASM_ARCH_HARDWARE_H */
include/asm-arm/arch-iop13xx/io.h
+41
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@@ -0,0 +1,41 @@
/*
* iop13xx custom ioremap implementation
* Copyright (c) 2005-2006, Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License along with
* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
* Place - Suite 330, Boston, MA 02111-1307 USA.
*
*/
#ifndef __ASM_ARM_ARCH_IO_H
#define __ASM_ARM_ARCH_IO_H
#define IO_SPACE_LIMIT 0xffffffff
#define __io(a) (a)
#define __mem_pci(a) (a)
#define __mem_isa(a) (a)
extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
unsigned long flags);
extern void __iop13xx_iounmap(void __iomem *addr);
extern u32 iop13xx_atue_mem_base;
extern u32 iop13xx_atux_mem_base;
extern size_t iop13xx_atue_mem_size;
extern size_t iop13xx_atux_mem_size;
#define __arch_ioremap(a, s, f) __iop13xx_ioremap(a, s, f)
#define __arch_iounmap(a) __iop13xx_iounmap(a)
#endif
include/asm-arm/arch-iop13xx/iop13xx.h
+492
View File
@@ -0,0 +1,492 @@
#ifndef _IOP13XX_HW_H_
#define _IOP13XX_HW_H_
#ifndef __ASSEMBLY__
/* The ATU offsets can change based on the strapping */
extern u32 iop13xx_atux_pmmr_offset;
extern u32 iop13xx_atue_pmmr_offset;
void iop13xx_init_irq(void);
void iop13xx_map_io(void);
void iop13xx_platform_init(void);
void iop13xx_init_irq(void);
void iop13xx_init_time(unsigned long tickrate);
unsigned long iop13xx_gettimeoffset(void);
/* handle cp6 access
* to do: handle access in entry-armv5.S and unify with
* the iop3xx implementation
* note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
* when interrupts are enabled
*/
static inline unsigned long iop13xx_cp6_save(void)
{
u32 temp, cp_flags;
asm volatile (
"mrc p15, 0, %1, c15, c1, 0\n\t"
"orr %0, %1, #(1 << 6)\n\t"
"mcr p15, 0, %0, c15, c1, 0\n\t"
: "=r" (temp), "=r"(cp_flags));
return cp_flags;
}
static inline void iop13xx_cp6_restore(unsigned long cp_flags)
{
asm volatile (
"mcr p15, 0, %0, c15, c1, 0\n\t"
: : "r" (cp_flags) );
}
/* CPUID CP6 R0 Page 0 */
static inline int iop13xx_cpu_id(void)
{
int id;
asm volatile("mrc p6, 0, %0, c0, c0, 0":"=r" (id));
return id;
}
#endif
/*
* IOP13XX I/O and Mem space regions for PCI autoconfiguration
*/
#define IOP13XX_MAX_RAM_SIZE 0x80000000UL /* 2GB */
#define IOP13XX_PCI_OFFSET IOP13XX_MAX_RAM_SIZE
/* PCI MAP
* 0x0000.0000 - 0x8000.0000 1:1 mapping with Physical RAM
* 0x8000.0000 - 0x8800.0000 PCIX/PCIE memory window (128MB)
*/
#define IOP13XX_PCIX_IO_WINDOW_SIZE 0x10000UL
#define IOP13XX_PCIX_LOWER_IO_PA 0xfffb0000UL
#define IOP13XX_PCIX_LOWER_IO_VA 0xfec60000UL
#define IOP13XX_PCIX_LOWER_IO_BA 0x0fff0000UL
#define IOP13XX_PCIX_UPPER_IO_PA (IOP13XX_PCIX_LOWER_IO_PA +\
IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
#define IOP13XX_PCIX_UPPER_IO_VA (IOP13XX_PCIX_LOWER_IO_VA +\
IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
#define IOP13XX_PCIX_IO_OFFSET (IOP13XX_PCIX_LOWER_IO_VA -\
IOP13XX_PCIX_LOWER_IO_BA)
#define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
(IOP13XX_PCIX_LOWER_IO_PA\
- IOP13XX_PCIX_LOWER_IO_VA))
#define IOP13XX_PCIX_MEM_PHYS_OFFSET 0x100000000ULL
#define IOP13XX_PCIX_MEM_WINDOW_SIZE 0x3a000000UL
#define IOP13XX_PCIX_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
#define IOP13XX_PCIX_LOWER_MEM_PA (IOP13XX_PCIX_MEM_PHYS_OFFSET +\
IOP13XX_PCIX_LOWER_MEM_BA)
#define IOP13XX_PCIX_UPPER_MEM_PA (IOP13XX_PCIX_LOWER_MEM_PA +\
IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIX_UPPER_MEM_BA (IOP13XX_PCIX_LOWER_MEM_BA +\
IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIX_MEM_COOKIE 0x80000000UL
#define IOP13XX_PCIX_LOWER_MEM_RA IOP13XX_PCIX_MEM_COOKIE
#define IOP13XX_PCIX_UPPER_MEM_RA (IOP13XX_PCIX_LOWER_MEM_RA +\
IOP13XX_PCIX_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIX_MEM_OFFSET (IOP13XX_PCIX_MEM_COOKIE -\
IOP13XX_PCIX_LOWER_MEM_BA)
/* PCI-E ranges */
#define IOP13XX_PCIE_IO_WINDOW_SIZE 0x10000UL
#define IOP13XX_PCIE_LOWER_IO_PA 0xfffd0000UL
#define IOP13XX_PCIE_LOWER_IO_VA 0xfed70000UL
#define IOP13XX_PCIE_LOWER_IO_BA 0x0fff0000UL
#define IOP13XX_PCIE_UPPER_IO_PA (IOP13XX_PCIE_LOWER_IO_PA +\
IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
#define IOP13XX_PCIE_UPPER_IO_VA (IOP13XX_PCIE_LOWER_IO_VA +\
IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
#define IOP13XX_PCIE_UPPER_IO_BA (IOP13XX_PCIE_LOWER_IO_BA +\
IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
#define IOP13XX_PCIE_IO_OFFSET (IOP13XX_PCIE_LOWER_IO_VA -\
IOP13XX_PCIE_LOWER_IO_BA)
#define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
(IOP13XX_PCIE_LOWER_IO_PA\
- IOP13XX_PCIE_LOWER_IO_VA))
#define IOP13XX_PCIE_MEM_PHYS_OFFSET 0x200000000ULL
#define IOP13XX_PCIE_MEM_WINDOW_SIZE 0x3a000000UL
#define IOP13XX_PCIE_LOWER_MEM_BA (PHYS_OFFSET + IOP13XX_PCI_OFFSET)
#define IOP13XX_PCIE_LOWER_MEM_PA (IOP13XX_PCIE_MEM_PHYS_OFFSET +\
IOP13XX_PCIE_LOWER_MEM_BA)
#define IOP13XX_PCIE_UPPER_MEM_PA (IOP13XX_PCIE_LOWER_MEM_PA +\
IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIE_UPPER_MEM_BA (IOP13XX_PCIE_LOWER_MEM_BA +\
IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
/* All 0xc000.0000 - 0xfdff.ffff addresses belong to PCIe */
#define IOP13XX_PCIE_MEM_COOKIE 0xc0000000UL
#define IOP13XX_PCIE_LOWER_MEM_RA IOP13XX_PCIE_MEM_COOKIE
#define IOP13XX_PCIE_UPPER_MEM_RA (IOP13XX_PCIE_LOWER_MEM_RA +\
IOP13XX_PCIE_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PCIE_MEM_OFFSET (IOP13XX_PCIE_MEM_COOKIE -\
IOP13XX_PCIE_LOWER_MEM_BA)
/* PBI Ranges */
#define IOP13XX_PBI_LOWER_MEM_PA 0xf0000000UL
#define IOP13XX_PBI_MEM_WINDOW_SIZE 0x04000000UL
#define IOP13XX_PBI_MEM_COOKIE 0xfa000000UL
#define IOP13XX_PBI_LOWER_MEM_RA IOP13XX_PBI_MEM_COOKIE
#define IOP13XX_PBI_UPPER_MEM_RA (IOP13XX_PBI_LOWER_MEM_RA +\
IOP13XX_PBI_MEM_WINDOW_SIZE - 1)
/*
* IOP13XX chipset registers
*/
#define IOP13XX_PMMR_PHYS_MEM_BASE 0xffd80000UL /* PMMR phys. address */
#define IOP13XX_PMMR_VIRT_MEM_BASE 0xfee80000UL /* PMMR phys. address */
#define IOP13XX_PMMR_MEM_WINDOW_SIZE 0x80000
#define IOP13XX_PMMR_UPPER_MEM_VA (IOP13XX_PMMR_VIRT_MEM_BASE +\
IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PMMR_UPPER_MEM_PA (IOP13XX_PMMR_PHYS_MEM_BASE +\
IOP13XX_PMMR_MEM_WINDOW_SIZE - 1)
#define IOP13XX_PMMR_VIRT_TO_PHYS(addr) (u32) ((u32) addr +\
(IOP13XX_PMMR_PHYS_MEM_BASE\
- IOP13XX_PMMR_VIRT_MEM_BASE))
#define IOP13XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
(IOP13XX_PMMR_PHYS_MEM_BASE\
- IOP13XX_PMMR_VIRT_MEM_BASE))
#define IOP13XX_REG_ADDR32(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR16(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR8(reg) (IOP13XX_PMMR_VIRT_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR32_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR16_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
#define IOP13XX_REG_ADDR8_PHYS(reg) (IOP13XX_PMMR_PHYS_MEM_BASE + (reg))
#define IOP13XX_PMMR_SIZE 0x00080000
/*=================== Defines for Platform Devices =====================*/
#define IOP13XX_UART0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002300)
#define IOP13XX_UART1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002340)
#define IOP13XX_UART0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002300)
#define IOP13XX_UART1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002340)
#define IOP13XX_I2C0_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002500)
#define IOP13XX_I2C1_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002520)
#define IOP13XX_I2C2_PHYS (IOP13XX_PMMR_PHYS_MEM_BASE | 0x00002540)
#define IOP13XX_I2C0_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002500)
#define IOP13XX_I2C1_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002520)
#define IOP13XX_I2C2_VIRT (IOP13XX_PMMR_VIRT_MEM_BASE | 0x00002540)
/* ATU selection flags */
/* IOP13XX_INIT_ATU_DEFAULT = Rely on CONFIG_IOP13XX_ATU* */
#define IOP13XX_INIT_ATU_DEFAULT (0)
#define IOP13XX_INIT_ATU_ATUX (1 << 0)
#define IOP13XX_INIT_ATU_ATUE (1 << 1)
#define IOP13XX_INIT_ATU_NONE (1 << 2)
/* UART selection flags */
/* IOP13XX_INIT_UART_DEFAULT = Rely on CONFIG_IOP13XX_UART* */
#define IOP13XX_INIT_UART_DEFAULT (0)
#define IOP13XX_INIT_UART_0 (1 << 0)
#define IOP13XX_INIT_UART_1 (1 << 1)
/* I2C selection flags */
/* IOP13XX_INIT_I2C_DEFAULT = Rely on CONFIG_IOP13XX_I2C* */
#define IOP13XX_INIT_I2C_DEFAULT (0)
#define IOP13XX_INIT_I2C_0 (1 << 0)
#define IOP13XX_INIT_I2C_1 (1 << 1)
#define IOP13XX_INIT_I2C_2 (1 << 2)
#define IQ81340_NUM_UART 2
#define IQ81340_NUM_I2C 3
#define IQ81340_NUM_PHYS_MAP_FLASH 1
#define IQ81340_MAX_PLAT_DEVICES (IQ81340_NUM_UART +\
IQ81340_NUM_I2C +\
IQ81340_NUM_PHYS_MAP_FLASH)
/*========================== PMMR offsets for key registers ============*/
#define IOP13XX_ATU0_PMMR_OFFSET 0x00048000
#define IOP13XX_ATU1_PMMR_OFFSET 0x0004c000
#define IOP13XX_ATU2_PMMR_OFFSET 0x0004d000
#define IOP13XX_ADMA0_PMMR_OFFSET 0x00000000
#define IOP13XX_ADMA1_PMMR_OFFSET 0x00000200
#define IOP13XX_ADMA2_PMMR_OFFSET 0x00000400
#define IOP13XX_PBI_PMMR_OFFSET 0x00001580
#define IOP13XX_ESSR0_PMMR_OFFSET 0x00002188
#define IOP13XX_ESSR0 IOP13XX_REG_ADDR32(0x00002188)
#define IOP13XX_ESSR0_IFACE_MASK 0x00004000 /* Interface PCI-X / PCI-E */
#define IOP13XX_CONTROLLER_ONLY (1 << 14)
#define IOP13XX_INTERFACE_SEL_PCIX (1 << 15)
#define IOP13XX_PMON_PMMR_OFFSET 0x0001A000
#define IOP13XX_PMON_BASE (IOP13XX_PMMR_VIRT_MEM_BASE +\
IOP13XX_PMON_PMMR_OFFSET)
#define IOP13XX_PMON_PHYSBASE (IOP13XX_PMMR_PHYS_MEM_BASE +\
IOP13XX_PMON_PMMR_OFFSET)
#define IOP13XX_PMON_CMD0 (IOP13XX_PMON_BASE + 0x0)
#define IOP13XX_PMON_EVR0 (IOP13XX_PMON_BASE + 0x4)
#define IOP13XX_PMON_STS0 (IOP13XX_PMON_BASE + 0x8)
#define IOP13XX_PMON_DATA0 (IOP13XX_PMON_BASE + 0xC)
#define IOP13XX_PMON_CMD3 (IOP13XX_PMON_BASE + 0x30)
#define IOP13XX_PMON_EVR3 (IOP13XX_PMON_BASE + 0x34)
#define IOP13XX_PMON_STS3 (IOP13XX_PMON_BASE + 0x38)
#define IOP13XX_PMON_DATA3 (IOP13XX_PMON_BASE + 0x3C)
#define IOP13XX_PMON_CMD7 (IOP13XX_PMON_BASE + 0x70)
#define IOP13XX_PMON_EVR7 (IOP13XX_PMON_BASE + 0x74)
#define IOP13XX_PMON_STS7 (IOP13XX_PMON_BASE + 0x78)
#define IOP13XX_PMON_DATA7 (IOP13XX_PMON_BASE + 0x7C)
#define IOP13XX_PMONEN (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E040)
#define IOP13XX_PMONSTAT (IOP13XX_PMMR_VIRT_MEM_BASE + 0x4E044)
/*================================ATU===================================*/
#define IOP13XX_ATUX_OFFSET(ofs) IOP13XX_REG_ADDR32(\
iop13xx_atux_pmmr_offset + (ofs))
#define IOP13XX_ATUX_DID IOP13XX_REG_ADDR16(\
iop13xx_atux_pmmr_offset + 0x2)
#define IOP13XX_ATUX_ATUCMD IOP13XX_REG_ADDR16(\
iop13xx_atux_pmmr_offset + 0x4)
#define IOP13XX_ATUX_ATUSR IOP13XX_REG_ADDR16(\
iop13xx_atux_pmmr_offset + 0x6)
#define IOP13XX_ATUX_IABAR0 IOP13XX_ATUX_OFFSET(0x10)
#define IOP13XX_ATUX_IAUBAR0 IOP13XX_ATUX_OFFSET(0x14)
#define IOP13XX_ATUX_IABAR1 IOP13XX_ATUX_OFFSET(0x18)
#define IOP13XX_ATUX_IAUBAR1 IOP13XX_ATUX_OFFSET(0x1c)
#define IOP13XX_ATUX_IABAR2 IOP13XX_ATUX_OFFSET(0x20)
#define IOP13XX_ATUX_IAUBAR2 IOP13XX_ATUX_OFFSET(0x24)
#define IOP13XX_ATUX_IALR0 IOP13XX_ATUX_OFFSET(0x40)
#define IOP13XX_ATUX_IATVR0 IOP13XX_ATUX_OFFSET(0x44)
#define IOP13XX_ATUX_IAUTVR0 IOP13XX_ATUX_OFFSET(0x48)
#define IOP13XX_ATUX_IALR1 IOP13XX_ATUX_OFFSET(0x4c)
#define IOP13XX_ATUX_IATVR1 IOP13XX_ATUX_OFFSET(0x50)
#define IOP13XX_ATUX_IAUTVR1 IOP13XX_ATUX_OFFSET(0x54)
#define IOP13XX_ATUX_IALR2 IOP13XX_ATUX_OFFSET(0x58)
#define IOP13XX_ATUX_IATVR2 IOP13XX_ATUX_OFFSET(0x5c)
#define IOP13XX_ATUX_IAUTVR2 IOP13XX_ATUX_OFFSET(0x60)
#define IOP13XX_ATUX_ATUCR IOP13XX_ATUX_OFFSET(0x70)
#define IOP13XX_ATUX_PCSR IOP13XX_ATUX_OFFSET(0x74)
#define IOP13XX_ATUX_ATUISR IOP13XX_ATUX_OFFSET(0x78)
#define IOP13XX_ATUX_PCIXSR IOP13XX_ATUX_OFFSET(0xD4)
#define IOP13XX_ATUX_IABAR3 IOP13XX_ATUX_OFFSET(0x200)
#define IOP13XX_ATUX_IAUBAR3 IOP13XX_ATUX_OFFSET(0x204)
#define IOP13XX_ATUX_IALR3 IOP13XX_ATUX_OFFSET(0x208)
#define IOP13XX_ATUX_IATVR3 IOP13XX_ATUX_OFFSET(0x20c)
#define IOP13XX_ATUX_IAUTVR3 IOP13XX_ATUX_OFFSET(0x210)
#define IOP13XX_ATUX_OIOBAR IOP13XX_ATUX_OFFSET(0x300)
#define IOP13XX_ATUX_OIOWTVR IOP13XX_ATUX_OFFSET(0x304)
#define IOP13XX_ATUX_OUMBAR0 IOP13XX_ATUX_OFFSET(0x308)
#define IOP13XX_ATUX_OUMWTVR0 IOP13XX_ATUX_OFFSET(0x30c)
#define IOP13XX_ATUX_OUMBAR1 IOP13XX_ATUX_OFFSET(0x310)
#define IOP13XX_ATUX_OUMWTVR1 IOP13XX_ATUX_OFFSET(0x314)
#define IOP13XX_ATUX_OUMBAR2 IOP13XX_ATUX_OFFSET(0x318)
#define IOP13XX_ATUX_OUMWTVR2 IOP13XX_ATUX_OFFSET(0x31c)
#define IOP13XX_ATUX_OUMBAR3 IOP13XX_ATUX_OFFSET(0x320)
#define IOP13XX_ATUX_OUMWTVR3 IOP13XX_ATUX_OFFSET(0x324)
#define IOP13XX_ATUX_OUDMABAR IOP13XX_ATUX_OFFSET(0x328)
#define IOP13XX_ATUX_OUMSIBAR IOP13XX_ATUX_OFFSET(0x32c)
#define IOP13XX_ATUX_OCCAR IOP13XX_ATUX_OFFSET(0x330)
#define IOP13XX_ATUX_OCCDR IOP13XX_ATUX_OFFSET(0x334)
#define IOP13XX_ATUX_ATUCR_OUT_EN (1 << 1)
#define IOP13XX_ATUX_PCSR_CENTRAL_RES (1 << 25)
#define IOP13XX_ATUX_PCSR_P_RSTOUT (1 << 21)
#define IOP13XX_ATUX_PCSR_OUT_Q_BUSY (1 << 15)
#define IOP13XX_ATUX_PCSR_IN_Q_BUSY (1 << 14)
#define IOP13XX_ATUX_PCSR_FREQ_OFFSET (16)
#define IOP13XX_ATUX_STAT_PCI_IFACE_ERR (1 << 18)
#define IOP13XX_ATUX_STAT_VPD_ADDR (1 << 17)
#define IOP13XX_ATUX_STAT_INT_PAR_ERR (1 << 16)
#define IOP13XX_ATUX_STAT_CFG_WRITE (1 << 15)
#define IOP13XX_ATUX_STAT_ERR_COR (1 << 14)
#define IOP13XX_ATUX_STAT_TX_SCEM (1 << 13)
#define IOP13XX_ATUX_STAT_REC_SCEM (1 << 12)
#define IOP13XX_ATUX_STAT_POWER_TRAN (1 << 11)
#define IOP13XX_ATUX_STAT_TX_SERR (1 << 10)
#define IOP13XX_ATUX_STAT_DET_PAR_ERR (1 << 9 )
#define IOP13XX_ATUX_STAT_BIST (1 << 8 )
#define IOP13XX_ATUX_STAT_INT_REC_MABORT (1 << 7 )
#define IOP13XX_ATUX_STAT_REC_SERR (1 << 4 )
#define IOP13XX_ATUX_STAT_EXT_REC_MABORT (1 << 3 )
#define IOP13XX_ATUX_STAT_EXT_REC_TABORT (1 << 2 )
#define IOP13XX_ATUX_STAT_EXT_SIG_TABORT (1 << 1 )
#define IOP13XX_ATUX_STAT_MASTER_DATA_PAR (1 << 0 )
#define IOP13XX_ATUX_PCIXSR_BUS_NUM (8)
#define IOP13XX_ATUX_PCIXSR_DEV_NUM (3)
#define IOP13XX_ATUX_PCIXSR_FUNC_NUM (0)
#define IOP13XX_ATUX_IALR_DISABLE 0x00000001
#define IOP13XX_ATUX_OUMBAR_ENABLE 0x80000000
#define IOP13XX_ATUE_OFFSET(ofs) IOP13XX_REG_ADDR32(\
iop13xx_atue_pmmr_offset + (ofs))
#define IOP13XX_ATUE_DID IOP13XX_REG_ADDR16(\
iop13xx_atue_pmmr_offset + 0x2)
#define IOP13XX_ATUE_ATUCMD IOP13XX_REG_ADDR16(\
iop13xx_atue_pmmr_offset + 0x4)
#define IOP13XX_ATUE_ATUSR IOP13XX_REG_ADDR16(\
iop13xx_atue_pmmr_offset + 0x6)
#define IOP13XX_ATUE_IABAR0 IOP13XX_ATUE_OFFSET(0x10)
#define IOP13XX_ATUE_IAUBAR0 IOP13XX_ATUE_OFFSET(0x14)
#define IOP13XX_ATUE_IABAR1 IOP13XX_ATUE_OFFSET(0x18)
#define IOP13XX_ATUE_IAUBAR1 IOP13XX_ATUE_OFFSET(0x1c)
#define IOP13XX_ATUE_IABAR2 IOP13XX_ATUE_OFFSET(0x20)
#define IOP13XX_ATUE_IAUBAR2 IOP13XX_ATUE_OFFSET(0x24)
#define IOP13XX_ATUE_IALR0 IOP13XX_ATUE_OFFSET(0x40)
#define IOP13XX_ATUE_IATVR0 IOP13XX_ATUE_OFFSET(0x44)
#define IOP13XX_ATUE_IAUTVR0 IOP13XX_ATUE_OFFSET(0x48)
#define IOP13XX_ATUE_IALR1 IOP13XX_ATUE_OFFSET(0x4c)
#define IOP13XX_ATUE_IATVR1 IOP13XX_ATUE_OFFSET(0x50)
#define IOP13XX_ATUE_IAUTVR1 IOP13XX_ATUE_OFFSET(0x54)
#define IOP13XX_ATUE_IALR2 IOP13XX_ATUE_OFFSET(0x58)
#define IOP13XX_ATUE_IATVR2 IOP13XX_ATUE_OFFSET(0x5c)
#define IOP13XX_ATUE_IAUTVR2 IOP13XX_ATUE_OFFSET(0x60)
#define IOP13XX_ATUE_PE_LSTS IOP13XX_REG_ADDR16(\
iop13xx_atue_pmmr_offset + 0xe2)
#define IOP13XX_ATUE_OIOWTVR IOP13XX_ATUE_OFFSET(0x304)
#define IOP13XX_ATUE_OUMBAR0 IOP13XX_ATUE_OFFSET(0x308)
#define IOP13XX_ATUE_OUMWTVR0 IOP13XX_ATUE_OFFSET(0x30c)
#define IOP13XX_ATUE_OUMBAR1 IOP13XX_ATUE_OFFSET(0x310)
#define IOP13XX_ATUE_OUMWTVR1 IOP13XX_ATUE_OFFSET(0x314)
#define IOP13XX_ATUE_OUMBAR2 IOP13XX_ATUE_OFFSET(0x318)
#define IOP13XX_ATUE_OUMWTVR2 IOP13XX_ATUE_OFFSET(0x31c)
#define IOP13XX_ATUE_OUMBAR3 IOP13XX_ATUE_OFFSET(0x320)
#define IOP13XX_ATUE_OUMWTVR3 IOP13XX_ATUE_OFFSET(0x324)
#define IOP13XX_ATUE_ATUCR IOP13XX_ATUE_OFFSET(0x70)
#define IOP13XX_ATUE_PCSR IOP13XX_ATUE_OFFSET(0x74)
#define IOP13XX_ATUE_ATUISR IOP13XX_ATUE_OFFSET(0x78)
#define IOP13XX_ATUE_OIOBAR IOP13XX_ATUE_OFFSET(0x300)
#define IOP13XX_ATUE_OCCAR IOP13XX_ATUE_OFFSET(0x32c)
#define IOP13XX_ATUE_OCCDR IOP13XX_ATUE_OFFSET(0x330)
#define IOP13XX_ATUE_PIE_STS IOP13XX_ATUE_OFFSET(0x384)
#define IOP13XX_ATUE_PIE_MSK IOP13XX_ATUE_OFFSET(0x388)
#define IOP13XX_ATUE_ATUCR_IVM (1 << 6)
#define IOP13XX_ATUE_ATUCR_OUT_EN (1 << 1)
#define IOP13XX_ATUE_OCCAR_BUS_NUM (24)
#define IOP13XX_ATUE_OCCAR_DEV_NUM (19)
#define IOP13XX_ATUE_OCCAR_FUNC_NUM (16)
#define IOP13XX_ATUE_OCCAR_EXT_REG (8)
#define IOP13XX_ATUE_OCCAR_REG (2)
#define IOP13XX_ATUE_PCSR_BUS_NUM (24)
#define IOP13XX_ATUE_PCSR_DEV_NUM (19)
#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
#define IOP13XX_ATUE_PCSR_OUT_Q_BUSY (1 << 15)
#define IOP13XX_ATUE_PCSR_IN_Q_BUSY (1 << 14)
#define IOP13XX_ATUE_PCSR_END_POINT (1 << 13)
#define IOP13XX_ATUE_PCSR_LLRB_BUSY (1 << 12)
#define IOP13XX_ATUE_PCSR_BUS_NUM_MASK (0xff)
#define IOP13XX_ATUE_PCSR_DEV_NUM_MASK (0x1f)
#define IOP13XX_ATUE_PCSR_FUNC_NUM_MASK (0x7)
#define IOP13XX_ATUE_PCSR_CORE_RESET (8)
#define IOP13XX_ATUE_PCSR_FUNC_NUM (16)
#define IOP13XX_ATUE_LSTS_TRAINING (1 << 11)
#define IOP13XX_ATUE_STAT_SLOT_PWR_MSG (1 << 28)
#define IOP13XX_ATUE_STAT_PME (1 << 27)
#define IOP13XX_ATUE_STAT_HOT_PLUG_MSG (1 << 26)
#define IOP13XX_ATUE_STAT_IVM (1 << 25)
#define IOP13XX_ATUE_STAT_BIST (1 << 24)
#define IOP13XX_ATUE_STAT_CFG_WRITE (1 << 18)
#define IOP13XX_ATUE_STAT_VPD_ADDR (1 << 17)
#define IOP13XX_ATUE_STAT_POWER_TRAN (1 << 16)
#define IOP13XX_ATUE_STAT_HALT_ON_ERROR (1 << 13)
#define IOP13XX_ATUE_STAT_ROOT_SYS_ERR (1 << 12)
#define IOP13XX_ATUE_STAT_ROOT_ERR_MSG (1 << 11)
#define IOP13XX_ATUE_STAT_PCI_IFACE_ERR (1 << 10)
#define IOP13XX_ATUE_STAT_ERR_COR (1 << 9 )
#define IOP13XX_ATUE_STAT_ERR_UNCOR (1 << 8 )
#define IOP13XX_ATUE_STAT_CRS (1 << 7 )
#define IOP13XX_ATUE_STAT_LNK_DWN (1 << 6 )
#define IOP13XX_ATUE_STAT_INT_REC_MABORT (1 << 5 )
#define IOP13XX_ATUE_STAT_DET_PAR_ERR (1 << 4 )
#define IOP13XX_ATUE_STAT_EXT_REC_MABORT (1 << 3 )
#define IOP13XX_ATUE_STAT_SIG_TABORT (1 << 2 )
#define IOP13XX_ATUE_STAT_EXT_REC_TABORT (1 << 1 )
#define IOP13XX_ATUE_STAT_MASTER_DATA_PAR (1 << 0 )
#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_COMP_REQ (1 << 31)
#define IOP13XX_ATUE_ESTAT_REC_COMPLETER_ABORT (1 << 30)
#define IOP13XX_ATUE_ESTAT_TX_POISONED_TLP (1 << 29)
#define IOP13XX_ATUE_ESTAT_TX_PAR_ERR (1 << 28)
#define IOP13XX_ATUE_ESTAT_REC_UNSUPPORTED_REQ (1 << 20)
#define IOP13XX_ATUE_ESTAT_REC_ECRC_ERR (1 << 19)
#define IOP13XX_ATUE_ESTAT_REC_MALFORMED_TLP (1 << 18)
#define IOP13XX_ATUE_ESTAT_TX_RECEIVER_OVERFLOW (1 << 17)
#define IOP13XX_ATUE_ESTAT_REC_UNEXPECTED_COMP (1 << 16)
#define IOP13XX_ATUE_ESTAT_INT_COMP_ABORT (1 << 15)
#define IOP13XX_ATUE_ESTAT_COMP_TIMEOUT (1 << 14)
#define IOP13XX_ATUE_ESTAT_FLOW_CONTROL_ERR (1 << 13)
#define IOP13XX_ATUE_ESTAT_REC_POISONED_TLP (1 << 12)
#define IOP13XX_ATUE_ESTAT_DATA_LNK_ERR (1 << 4 )
#define IOP13XX_ATUE_ESTAT_TRAINING_ERR (1 << 0 )
#define IOP13XX_ATUE_IALR_DISABLE (0x00000001)
#define IOP13XX_ATUE_OUMBAR_ENABLE (0x80000000)
#define IOP13XX_ATU_OUMBAR_FUNC_NUM (28)
#define IOP13XX_ATU_OUMBAR_FUNC_NUM_MASK (0x7)
/*=======================================================================*/
/*==============================ADMA UNITS===============================*/
#define IOP13XX_ADMA_PHYS_BASE(chan) IOP13XX_REG_ADDR32_PHYS((chan << 9))
#define IOP13XX_ADMA_UPPER_PA(chan) (IOP13XX_ADMA_PHYS_BASE(chan) + 0xc0)
#define IOP13XX_ADMA_OFFSET(chan, ofs) IOP13XX_REG_ADDR32((chan << 9) + (ofs))
#define IOP13XX_ADMA_ACCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x0)
#define IOP13XX_ADMA_ACSR(chan) IOP13XX_ADMA_OFFSET(chan, 0x4)
#define IOP13XX_ADMA_ADAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x8)
#define IOP13XX_ADMA_IIPCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x18)
#define IOP13XX_ADMA_IIPAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x1c)
#define IOP13XX_ADMA_IIPUAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x20)
#define IOP13XX_ADMA_ANDAR(chan) IOP13XX_ADMA_OFFSET(chan, 0x24)
#define IOP13XX_ADMA_ADCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x28)
#define IOP13XX_ADMA_CARMD(chan) IOP13XX_ADMA_OFFSET(chan, 0x2c)
#define IOP13XX_ADMA_ABCR(chan) IOP13XX_ADMA_OFFSET(chan, 0x30)
#define IOP13XX_ADMA_DLADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x34)
#define IOP13XX_ADMA_DUADR(chan) IOP13XX_ADMA_OFFSET(chan, 0x38)
#define IOP13XX_ADMA_SLAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x3c + (src <<3))
#define IOP13XX_ADMA_SUAR(src, chan) IOP13XX_ADMA_OFFSET(chan, 0x40 + (src <<3))
/*==============================XSI BRIDGE===============================*/
#define IOP13XX_XBG_BECSR IOP13XX_REG_ADDR32(0x178c)
#define IOP13XX_XBG_BERAR IOP13XX_REG_ADDR32(0x1790)
#define IOP13XX_XBG_BERUAR IOP13XX_REG_ADDR32(0x1794)
#define is_atue_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
IOP13XX_PMMR_VIRT_TO_PHYS(\
IOP13XX_ATUE_OCCDR))\
&& (__raw_readl(IOP13XX_XBG_BECSR) & 1))
#define is_atux_occdr_error(x) ((__raw_readl(IOP13XX_XBG_BERAR) == \
IOP13XX_PMMR_VIRT_TO_PHYS(\
IOP13XX_ATUX_OCCDR))\
&& (__raw_readl(IOP13XX_XBG_BECSR) & 1))
/*=======================================================================*/
#define IOP13XX_PBI_OFFSET(ofs) IOP13XX_REG_ADDR32(IOP13XX_PBI_PMMR_OFFSET +\
(ofs))
#define IOP13XX_PBI_CR IOP13XX_PBI_OFFSET(0x0)
#define IOP13XX_PBI_SR IOP13XX_PBI_OFFSET(0x4)
#define IOP13XX_PBI_BAR0 IOP13XX_PBI_OFFSET(0x8)
#define IOP13XX_PBI_LR0 IOP13XX_PBI_OFFSET(0xc)
#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
#define IOP13XX_TMR_TC 0x01
#define IOP13XX_TMR_EN 0x02
#define IOP13XX_TMR_RELOAD 0x04
#define IOP13XX_TMR_PRIVILEGED 0x08
#define IOP13XX_TMR_RATIO_1_1 0x00
#define IOP13XX_TMR_RATIO_4_1 0x10
#define IOP13XX_TMR_RATIO_8_1 0x20
#define IOP13XX_TMR_RATIO_16_1 0x30
#endif /* _IOP13XX_HW_H_ */
include/asm-arm/arch-iop13xx/iq81340.h
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#ifndef _IQ81340_H_
#define _IQ81340_H_
#define IQ81340_PCE_BAR0 IOP13XX_PBI_LOWER_MEM_RA
#define IQ81340_PCE_BAR1 (IQ81340_PCE_BAR0 + 0x02000000)
#define IQ81340_FLASHBASE IQ81340_PCE_BAR0 /* Flash */
#define IQ81340_PCE_BAR1_OFFSET(a) (IQ81340_PCE_BAR1 + (a))
#define IQ81340_PRD_CODE IQ81340_PCE_BAR1_OFFSET(0)
#define IQ81340_BRD_STEP IQ81340_PCE_BAR1_OFFSET(0x10000)
#define IQ81340_CPLD_REV IQ81340_PCE_BAR1_OFFSET(0x20000)
#define IQ81340_LED IQ81340_PCE_BAR1_OFFSET(0x30000)
#define IQ81340_LHEX IQ81340_PCE_BAR1_OFFSET(0x40000)
#define IQ81340_RHEX IQ81340_PCE_BAR1_OFFSET(0x50000)
#define IQ81340_BUZZER IQ81340_PCE_BAR1_OFFSET(0x60000)
#define IQ81340_32K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x70000)
#define IQ81340_256K_NVRAM IQ81340_PCE_BAR1_OFFSET(0x80000)
#define IQ81340_ROTARY_SW IQ81340_PCE_BAR1_OFFSET(0xd0000)
#define IQ81340_BATT_STAT IQ81340_PCE_BAR1_OFFSET(0xf0000)
#define IQ81340_CMP_FLSH IQ81340_PCE_BAR1_OFFSET(0x1000000) /* 16MB */
#define PBI_CF_IDE_BASE (IQ81340_CMP_FLSH)
#define PBI_CF_BAR_ADDR (IOP13XX_PBI_BAR1)
/* These are the values used in the Machine description */
#define PHYS_IO 0xfeffff00
#define IO_PG_OFFSET 0xffffff00
#define BOOT_PARAM_OFFSET 0x00000100
#endif /* _IQ81340_H_ */
include/asm-arm/arch-iop13xx/irqs.h
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#ifndef _IOP13XX_IRQS_H_
#define _IOP13XX_IRQS_H_
#ifndef __ASSEMBLER__
#include <linux/types.h>
#include <asm/system.h> /* local_irq_save */
#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */
/* INTPND0 CP6 R0 Page 3
*/
static inline u32 read_intpnd_0(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c0, c3, 0":"=r" (val));
return val;
}
/* INTPND1 CP6 R1 Page 3
*/
static inline u32 read_intpnd_1(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c1, c3, 0":"=r" (val));
return val;
}
/* INTPND2 CP6 R2 Page 3
*/
static inline u32 read_intpnd_2(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c2, c3, 0":"=r" (val));
return val;
}
/* INTPND3 CP6 R3 Page 3
*/
static inline u32 read_intpnd_3(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
return val;
}
static inline void
iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags)
{
local_irq_save(*irq_flags);
*cp_flags = iop13xx_cp6_save();
}
static inline void
iop13xx_cp6_irq_restore(unsigned long *cp_flags,
unsigned long *irq_flags)
{
iop13xx_cp6_restore(*cp_flags);
local_irq_restore(*irq_flags);
}
#endif
#define INTBASE 0
#define INTSIZE_4 1
/*
* iop34x chipset interrupts
*/
#define IOP13XX_IRQ(x) (IOP13XX_IRQ_OFS + (x))
/*
* On IRQ or FIQ register
*/
#define IRQ_IOP13XX_ADMA0_EOT (0)
#define IRQ_IOP13XX_ADMA0_EOC (1)
#define IRQ_IOP13XX_ADMA1_EOT (2)
#define IRQ_IOP13XX_ADMA1_EOC (3)
#define IRQ_IOP13XX_ADMA2_EOT (4)
#define IRQ_IOP13XX_ADMA2_EOC (5)
#define IRQ_IOP134_WATCHDOG (6)
#define IRQ_IOP13XX_RSVD_7 (7)
#define IRQ_IOP13XX_TIMER0 (8)
#define IRQ_IOP13XX_TIMER1 (9)
#define IRQ_IOP13XX_I2C_0 (10)
#define IRQ_IOP13XX_I2C_1 (11)
#define IRQ_IOP13XX_MSG (12)
#define IRQ_IOP13XX_MSGIBQ (13)
#define IRQ_IOP13XX_ATU_IM (14)
#define IRQ_IOP13XX_ATU_BIST (15)
#define IRQ_IOP13XX_PPMU (16)
#define IRQ_IOP13XX_COREPMU (17)
#define IRQ_IOP13XX_CORECACHE (18)
#define IRQ_IOP13XX_RSVD_19 (19)
#define IRQ_IOP13XX_RSVD_20 (20)
#define IRQ_IOP13XX_RSVD_21 (21)
#define IRQ_IOP13XX_RSVD_22 (22)
#define IRQ_IOP13XX_RSVD_23 (23)
#define IRQ_IOP13XX_XINT0 (24)
#define IRQ_IOP13XX_XINT1 (25)
#define IRQ_IOP13XX_XINT2 (26)
#define IRQ_IOP13XX_XINT3 (27)
#define IRQ_IOP13XX_XINT4 (28)
#define IRQ_IOP13XX_XINT5 (29)
#define IRQ_IOP13XX_XINT6 (30)
#define IRQ_IOP13XX_XINT7 (31)
/* IINTSRC1 bit */
#define IRQ_IOP13XX_XINT8 (32) /* 0 */
#define IRQ_IOP13XX_XINT9 (33) /* 1 */
#define IRQ_IOP13XX_XINT10 (34) /* 2 */
#define IRQ_IOP13XX_XINT11 (35) /* 3 */
#define IRQ_IOP13XX_XINT12 (36) /* 4 */
#define IRQ_IOP13XX_XINT13 (37) /* 5 */
#define IRQ_IOP13XX_XINT14 (38) /* 6 */
#define IRQ_IOP13XX_XINT15 (39) /* 7 */
#define IRQ_IOP13XX_RSVD_40 (40) /* 8 */
#define IRQ_IOP13XX_RSVD_41 (41) /* 9 */
#define IRQ_IOP13XX_RSVD_42 (42) /* 10 */
#define IRQ_IOP13XX_RSVD_43 (43) /* 11 */
#define IRQ_IOP13XX_RSVD_44 (44) /* 12 */
#define IRQ_IOP13XX_RSVD_45 (45) /* 13 */
#define IRQ_IOP13XX_RSVD_46 (46) /* 14 */
#define IRQ_IOP13XX_RSVD_47 (47) /* 15 */
#define IRQ_IOP13XX_RSVD_48 (48) /* 16 */
#define IRQ_IOP13XX_RSVD_49 (49) /* 17 */
#define IRQ_IOP13XX_RSVD_50 (50) /* 18 */
#define IRQ_IOP13XX_UART0 (51) /* 19 */
#define IRQ_IOP13XX_UART1 (52) /* 20 */
#define IRQ_IOP13XX_PBIE (53) /* 21 */
#define IRQ_IOP13XX_ATU_CRW (54) /* 22 */
#define IRQ_IOP13XX_ATU_ERR (55) /* 23 */
#define IRQ_IOP13XX_MCU_ERR (56) /* 24 */
#define IRQ_IOP13XX_ADMA0_ERR (57) /* 25 */
#define IRQ_IOP13XX_ADMA1_ERR (58) /* 26 */
#define IRQ_IOP13XX_ADMA2_ERR (59) /* 27 */
#define IRQ_IOP13XX_RSVD_60 (60) /* 28 */
#define IRQ_IOP13XX_RSVD_61 (61) /* 29 */
#define IRQ_IOP13XX_MSG_ERR (62) /* 30 */
#define IRQ_IOP13XX_RSVD_63 (63) /* 31 */
/* IINTSRC2 bit */
#define IRQ_IOP13XX_INTERPROC (64) /* 0 */
#define IRQ_IOP13XX_RSVD_65 (65) /* 1 */
#define IRQ_IOP13XX_RSVD_66 (66) /* 2 */
#define IRQ_IOP13XX_RSVD_67 (67) /* 3 */
#define IRQ_IOP13XX_RSVD_68 (68) /* 4 */
#define IRQ_IOP13XX_RSVD_69 (69) /* 5 */
#define IRQ_IOP13XX_RSVD_70 (70) /* 6 */
#define IRQ_IOP13XX_RSVD_71 (71) /* 7 */
#define IRQ_IOP13XX_RSVD_72 (72) /* 8 */
#define IRQ_IOP13XX_RSVD_73 (73) /* 9 */
#define IRQ_IOP13XX_RSVD_74 (74) /* 10 */
#define IRQ_IOP13XX_RSVD_75 (75) /* 11 */
#define IRQ_IOP13XX_RSVD_76 (76) /* 12 */
#define IRQ_IOP13XX_RSVD_77 (77) /* 13 */
#define IRQ_IOP13XX_RSVD_78 (78) /* 14 */
#define IRQ_IOP13XX_RSVD_79 (79) /* 15 */
#define IRQ_IOP13XX_RSVD_80 (80) /* 16 */
#define IRQ_IOP13XX_RSVD_81 (81) /* 17 */
#define IRQ_IOP13XX_RSVD_82 (82) /* 18 */
#define IRQ_IOP13XX_RSVD_83 (83) /* 19 */
#define IRQ_IOP13XX_RSVD_84 (84) /* 20 */
#define IRQ_IOP13XX_RSVD_85 (85) /* 21 */
#define IRQ_IOP13XX_RSVD_86 (86) /* 22 */
#define IRQ_IOP13XX_RSVD_87 (87) /* 23 */
#define IRQ_IOP13XX_RSVD_88 (88) /* 24 */
#define IRQ_IOP13XX_RSVD_89 (89) /* 25 */
#define IRQ_IOP13XX_RSVD_90 (90) /* 26 */
#define IRQ_IOP13XX_RSVD_91 (91) /* 27 */
#define IRQ_IOP13XX_RSVD_92 (92) /* 28 */
#define IRQ_IOP13XX_RSVD_93 (93) /* 29 */
#define IRQ_IOP13XX_SIB_ERR (94) /* 30 */
#define IRQ_IOP13XX_SRAM_ERR (95) /* 31 */
/* IINTSRC3 bit */
#define IRQ_IOP13XX_I2C_2 (96) /* 0 */
#define IRQ_IOP13XX_ATUE_BIST (97) /* 1 */
#define IRQ_IOP13XX_ATUE_CRW (98) /* 2 */
#define IRQ_IOP13XX_ATUE_ERR (99) /* 3 */
#define IRQ_IOP13XX_IMU (100) /* 4 */
#define IRQ_IOP13XX_RSVD_101 (101) /* 5 */
#define IRQ_IOP13XX_RSVD_102 (102) /* 6 */
#define IRQ_IOP13XX_TPMI0_OUT (103) /* 7 */
#define IRQ_IOP13XX_TPMI1_OUT (104) /* 8 */
#define IRQ_IOP13XX_TPMI2_OUT (105) /* 9 */
#define IRQ_IOP13XX_TPMI3_OUT (106) /* 10 */
#define IRQ_IOP13XX_ATUE_IMA (107) /* 11 */
#define IRQ_IOP13XX_ATUE_IMB (108) /* 12 */
#define IRQ_IOP13XX_ATUE_IMC (109) /* 13 */
#define IRQ_IOP13XX_ATUE_IMD (110) /* 14 */
#define IRQ_IOP13XX_MU_MSI_TB (111) /* 15 */
#define IRQ_IOP13XX_RSVD_112 (112) /* 16 */
#define IRQ_IOP13XX_RSVD_113 (113) /* 17 */
#define IRQ_IOP13XX_RSVD_114 (114) /* 18 */
#define IRQ_IOP13XX_RSVD_115 (115) /* 19 */
#define IRQ_IOP13XX_RSVD_116 (116) /* 20 */
#define IRQ_IOP13XX_RSVD_117 (117) /* 21 */
#define IRQ_IOP13XX_RSVD_118 (118) /* 22 */
#define IRQ_IOP13XX_RSVD_119 (119) /* 23 */
#define IRQ_IOP13XX_RSVD_120 (120) /* 24 */
#define IRQ_IOP13XX_RSVD_121 (121) /* 25 */
#define IRQ_IOP13XX_RSVD_122 (122) /* 26 */
#define IRQ_IOP13XX_RSVD_123 (123) /* 27 */
#define IRQ_IOP13XX_RSVD_124 (124) /* 28 */
#define IRQ_IOP13XX_RSVD_125 (125) /* 29 */
#define IRQ_IOP13XX_RSVD_126 (126) /* 30 */
#define IRQ_IOP13XX_HPI (127) /* 31 */
#define NR_IOP13XX_IRQS (IRQ_IOP13XX_HPI + 1)
#define NR_IRQS NR_IOP13XX_IRQS
#endif /* _IOP13XX_IRQ_H_ */
include/asm-arm/arch-iop13xx/memory.h
+64
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@@ -0,0 +1,64 @@
#ifndef __ASM_ARCH_MEMORY_H
#define __ASM_ARCH_MEMORY_H
#include <asm/arch/hardware.h>
/*
* Physical DRAM offset.
*/
#define PHYS_OFFSET UL(0x00000000)
#define TASK_SIZE UL(0x3f000000)
#define PAGE_OFFSET UL(0x40000000)
#define TASK_UNMAPPED_BASE ((TASK_SIZE + 0x01000000) / 3)
#ifndef __ASSEMBLY__
#if defined(CONFIG_ARCH_IOP13XX)
#define IOP13XX_PMMR_V_START (IOP13XX_PMMR_VIRT_MEM_BASE)
#define IOP13XX_PMMR_V_END (IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_SIZE)
#define IOP13XX_PMMR_P_START (IOP13XX_PMMR_PHYS_MEM_BASE)
#define IOP13XX_PMMR_P_END (IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_SIZE)
/*
* Virtual view <-> PCI DMA view memory address translations
* virt_to_bus: Used to translate the virtual address to an
* address suitable to be passed to set_dma_addr
* bus_to_virt: Used to convert an address for DMA operations
* to an address that the kernel can use.
*/
/* RAM has 1:1 mapping on the PCIe/x Busses */
#define __virt_to_bus(x) (__virt_to_phys(x))
#define __bus_to_virt(x) (__phys_to_virt(x))
#define virt_to_lbus(x) \
(( ((void*)(x) >= (void*)IOP13XX_PMMR_V_START) && \
((void*)(x) < (void*)IOP13XX_PMMR_V_END) ) ? \
((x) - IOP13XX_PMMR_VIRT_MEM_BASE + IOP13XX_PMMR_PHYS_MEM_BASE) : \
((x) - PAGE_OFFSET + PHYS_OFFSET))
#define lbus_to_virt(x) \
(( ((x) >= IOP13XX_PMMR_P_START) && ((x) < IOP13XX_PMMR_P_END) ) ? \
((x) - IOP13XX_PMMR_PHYS_MEM_BASE + IOP13XX_PMMR_VIRT_MEM_BASE ) : \
((x) - PHYS_OFFSET + PAGE_OFFSET))
/* Device is an lbus device if it is on the platform bus of the IOP13XX */
#define is_lbus_device(dev) (dev &&\
(strncmp(dev->bus->name, "platform", 8) == 0))
#define __arch_page_to_dma(dev, page) \
({is_lbus_device(dev) ? (dma_addr_t)virt_to_lbus(page_address(page)) : \
(dma_addr_t)__virt_to_bus(page_address(page));})
#define __arch_dma_to_virt(dev, addr) \
({is_lbus_device(dev) ? lbus_to_virt(addr) : __bus_to_virt(addr);})
#define __arch_virt_to_dma(dev, addr) \
({is_lbus_device(dev) ? virt_to_lbus(addr) : __virt_to_bus(addr);})
#endif /* CONFIG_ARCH_IOP13XX */
#endif /* !ASSEMBLY */
#define PFN_TO_NID(addr) (0)
#endif
include/asm-arm/arch-iop13xx/pci.h
+57
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@@ -0,0 +1,57 @@
#ifndef _IOP13XX_PCI_H_
#define _IOP13XX_PCI_H_
#include <asm/arch/irqs.h>
#include <asm/io.h>
struct pci_sys_data;
struct hw_pci;
int iop13xx_pci_setup(int nr, struct pci_sys_data *sys);
struct pci_bus *iop13xx_scan_bus(int nr, struct pci_sys_data *);
void iop13xx_atu_select(struct hw_pci *plat_pci);
void iop13xx_pci_init(void);
void iop13xx_map_pci_memory(void);
#define IOP_PCI_STATUS_ERROR (PCI_STATUS_PARITY | \
PCI_STATUS_SIG_TARGET_ABORT | \
PCI_STATUS_REC_TARGET_ABORT | \
PCI_STATUS_REC_TARGET_ABORT | \
PCI_STATUS_REC_MASTER_ABORT | \
PCI_STATUS_SIG_SYSTEM_ERROR | \
PCI_STATUS_DETECTED_PARITY)
#define IOP13XX_ATUE_ATUISR_ERROR (IOP13XX_ATUE_STAT_HALT_ON_ERROR | \
IOP13XX_ATUE_STAT_ROOT_SYS_ERR | \
IOP13XX_ATUE_STAT_PCI_IFACE_ERR | \
IOP13XX_ATUE_STAT_ERR_COR | \
IOP13XX_ATUE_STAT_ERR_UNCOR | \
IOP13XX_ATUE_STAT_CRS | \
IOP13XX_ATUE_STAT_DET_PAR_ERR | \
IOP13XX_ATUE_STAT_EXT_REC_MABORT | \
IOP13XX_ATUE_STAT_SIG_TABORT | \
IOP13XX_ATUE_STAT_EXT_REC_TABORT | \
IOP13XX_ATUE_STAT_MASTER_DATA_PAR)
#define IOP13XX_ATUX_ATUISR_ERROR (IOP13XX_ATUX_STAT_TX_SCEM | \
IOP13XX_ATUX_STAT_REC_SCEM | \
IOP13XX_ATUX_STAT_TX_SERR | \
IOP13XX_ATUX_STAT_DET_PAR_ERR | \
IOP13XX_ATUX_STAT_INT_REC_MABORT | \
IOP13XX_ATUX_STAT_REC_SERR | \
IOP13XX_ATUX_STAT_EXT_REC_MABORT | \
IOP13XX_ATUX_STAT_EXT_REC_TABORT | \
IOP13XX_ATUX_STAT_EXT_SIG_TABORT | \
IOP13XX_ATUX_STAT_MASTER_DATA_PAR)
/* PCI interrupts
*/
#define ATUX_INTA IRQ_IOP13XX_XINT0
#define ATUX_INTB IRQ_IOP13XX_XINT1
#define ATUX_INTC IRQ_IOP13XX_XINT2
#define ATUX_INTD IRQ_IOP13XX_XINT3
#define ATUE_INTA IRQ_IOP13XX_ATUE_IMA
#define ATUE_INTB IRQ_IOP13XX_ATUE_IMB
#define ATUE_INTC IRQ_IOP13XX_ATUE_IMC
#define ATUE_INTD IRQ_IOP13XX_ATUE_IMD
#endif /* _IOP13XX_PCI_H_ */
include/asm-arm/arch-iop13xx/system.h
+59
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@@ -0,0 +1,59 @@
/*
* linux/include/asm-arm/arch-iop13xx/system.h
*
* Copyright (C) 2004 Intel Corp.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <asm/arch/iop13xx.h>
static inline void arch_idle(void)
{
cpu_do_idle();
}
/* WDTCR CP6 R7 Page 9 */
static inline u32 read_wdtcr(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
return val;
}
static inline void write_wdtcr(u32 val)
{
asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
}
/* WDTSR CP6 R8 Page 9 */
static inline u32 read_wdtsr(void)
{
u32 val;
asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
return val;
}
static inline void write_wdtsr(u32 val)
{
asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
}
#define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e
#define IOP13XX_WDTCR_EN 0xe1e1e1e1
#define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f
#define IOP13XX_WDTCR_DIS 0xf1f1f1f1
#define IOP13XX_WDTSR_WRITE_EN (1 << 31)
#define IOP13XX_WDTCR_IB_RESET (1 << 0)
static inline void arch_reset(char mode)
{
/*
* Reset the internal bus (warning both cores are reset)
*/
u32 cp_flags = iop13xx_cp6_save();
write_wdtcr(IOP13XX_WDTCR_EN_ARM);
write_wdtcr(IOP13XX_WDTCR_EN);
write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
write_wdtcr(0x1000);
iop13xx_cp6_restore(cp_flags);
for(;;);
}
include/asm-arm/arch-iop13xx/timex.h
+3
View File
@@ -0,0 +1,3 @@
#include <asm/hardware.h>
#define CLOCK_TICK_RATE (100 * HZ)
include/asm-arm/arch-iop13xx/uncompress.h
+24
View File
@@ -0,0 +1,24 @@
#include <asm/types.h>
#include <linux/serial_reg.h>
#include <asm/hardware.h>
#include <asm/processor.h>
#define UART_BASE ((volatile u32 *)IOP13XX_UART1_PHYS)
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
static inline void putc(char c)
{
while ((UART_BASE[UART_LSR] & TX_DONE) != TX_DONE)
cpu_relax();
UART_BASE[UART_TX] = c;
}
static inline void flush(void)
{
}
/*
* nothing to do
*/
#define arch_decomp_setup()
#define arch_decomp_wdog()
include/asm-arm/arch-iop13xx/vmalloc.h
+4
View File
@@ -0,0 +1,4 @@
#ifndef _VMALLOC_H_
#define _VMALLOC_H_
#define VMALLOC_END 0xfa000000UL
#endif
include/asm-arm/arch-ixp4xx/nslu2.h
+3 -2
View File
@@ -76,6 +76,7 @@
#define NSLU2_GPIO_BUZZ 4
#define NSLU2_BZ_BM (1L << NSLU2_GPIO_BUZZ)
/* LEDs */
#define NSLU2_LED_RED NSLU2_GPIO0
@@ -84,8 +85,8 @@
#define NSLU2_LED_RED_BM (1L << NSLU2_LED_RED)
#define NSLU2_LED_GRN_BM (1L << NSLU2_LED_GRN)
#define NSLU2_LED_DISK1 NSLU2_GPIO2
#define NSLU2_LED_DISK2 NSLU2_GPIO3
#define NSLU2_LED_DISK1 NSLU2_GPIO3
#define NSLU2_LED_DISK2 NSLU2_GPIO2
#define NSLU2_LED_DISK1_BM (1L << NSLU2_GPIO2)
#define NSLU2_LED_DISK2_BM (1L << NSLU2_GPIO3)
include/asm-arm/arch-ixp4xx/udc.h
+8
View File
@@ -0,0 +1,8 @@
/*
* linux/include/asm-arm/arch-ixp4xx/udc.h
*
*/
#include <asm/mach/udc_pxa2xx.h>
extern void ixp4xx_set_udc_info(struct pxa2xx_udc_mach_info *info);
include/asm-arm/arch-l7200/io.h
+5 -53
View File
@@ -17,59 +17,11 @@
/*
* There are not real ISA nor PCI buses, so we fake it.
*/
#define __io_pci(a) ((void __iomem *)(PCIO_BASE + (a)))
static inline void __iomem *__io(unsigned long addr)
{
return (void __iomem *)addr;
}
#define __io(a) __io(a)
#define __mem_pci(a) (a)
#define __ioaddr(p) __io_pci(p)
/*
* Generic virtual read/write
*/
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getl(a) (*(volatile unsigned int *)(a))
static inline unsigned int __arch_getw(unsigned long a)
{
unsigned int value;
__asm__ __volatile__("ldrh %0, [%1, #0] @ getw"
: "=&r" (value)
: "r" (a) : "cc");
return value;
}
#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
static inline void __arch_putw(unsigned int value, unsigned long a)
{
__asm__ __volatile__("strh %0, [%1, #0] @ putw"
: : "r" (value), "r" (a) : "cc");
}
/*
* Translated address IO functions
*
* IO address has already been translated to a virtual address
*/
#define outb_t(v,p) (*(volatile unsigned char *)(p) = (v))
#define inb_t(p) (*(volatile unsigned char *)(p))
#define outw_t(v,p) (*(volatile unsigned int *)(p) = (v))
#define inw_t(p) (*(volatile unsigned int *)(p))
#define outl_t(v,p) (*(volatile unsigned long *)(p) = (v))
#define inl_t(p) (*(volatile unsigned long *)(p))
/*
* FIXME - These are to allow for linking. On all the other
* ARM platforms, the entire IO space is contiguous.
* The 7200 has three separate IO spaces. The below
* macros will eventually become more involved. Use
* with caution and don't be surprised by kernel oopses!!!
*/
#define inb(p) inb_t(p)
#define inw(p) inw_t(p)
#define inl(p) inl_t(p)
#define outb(v,p) outb_t(v,p)
#define outw(v,p) outw_t(v,p)
#define outl(v,p) outl_t(v,p)
#endif
include/asm-arm/arch-lh7a40x/memory.h
-12
View File
@@ -57,18 +57,6 @@
(((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
#endif
/*
* Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
* and return the mem_map of that node.
*/
# define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
/*
* Given a page frame number, find the owning node of the memory
* and return the mem_map of that node.
*/
# define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
/*
* Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
* and returns the index corresponding to the appropriate page in the
include/asm-arm/arch-pxa/memory.h
+3 -33
View File
@@ -27,7 +27,6 @@
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#ifdef CONFIG_DISCONTIGMEM
/*
* The nodes are matched with the physical SDRAM banks as follows:
*
@@ -35,38 +34,9 @@
* node 1: 0xa4000000-0xa7ffffff --> 0xc4000000-0xc7ffffff
* node 2: 0xa8000000-0xabffffff --> 0xc8000000-0xcbffffff
* node 3: 0xac000000-0xafffffff --> 0xcc000000-0xcfffffff
*
* This needs a node mem size of 26 bits.
*/
/*
* Given a kernel address, find the home node of the underlying memory.
*/
#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 26)
/*
* Given a page frame number, convert it to a node id.
*/
#define PFN_TO_NID(pfn) (((pfn) - PHYS_PFN_OFFSET) >> (26 - PAGE_SHIFT))
/*
* Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
* and returns the mem_map of that node.
*/
#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
/*
* Given a page frame number, find the owning node of the memory
* and returns the mem_map of that node.
*/
#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
/*
* Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
* and returns the index corresponding to the appropriate page in the
* node's mem_map.
*/
#define LOCAL_MAP_NR(addr) \
(((unsigned long)(addr) & 0x03ffffff) >> PAGE_SHIFT)
#endif
#define NODE_MEM_SIZE_BITS 26
#endif
include/asm-arm/arch-pxa/pxa-regs.h
+6 -7
View File
@@ -99,7 +99,7 @@
#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
#define DCSR_ENRINTR (1 << 9) /* The end of Receive */
#define DCSR_EORINTR (1 << 9) /* The end of Receive */
#endif
#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
@@ -803,12 +803,11 @@
#define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
#define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
#define UDCISR_INT(n,intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
#define UDCISR1_IECC (1 << 31) /* IntEn - Configuration Change */
#define UDCISR1_IESOF (1 << 30) /* IntEn - Start of Frame */
#define UDCISR1_IERU (1 << 29) /* IntEn - Resume */
#define UDCISR1_IESU (1 << 28) /* IntEn - Suspend */
#define UDCISR1_IERS (1 << 27) /* IntEn - Reset */
#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
#define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
#define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
include/asm-arm/arch-s3c2410/h1940.h
+21
View File
@@ -0,0 +1,21 @@
/* linux/include/asm-arm/arch-s3c2410/h1940.h
*
* Copyright 2006 Ben Dooks <ben-linux@fluff.org>
*
* H1940 definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_H1940_H
#define __ASM_ARCH_H1940_H
#define H1940_SUSPEND_CHECKSUM (0x30003ff8)
#define H1940_SUSPEND_RESUMEAT (0x30081000)
#define H1940_SUSPEND_CHECK (0x30080000)
extern void h1940_pm_return(void);
#endif /* __ASM_ARCH_H1940_H */
include/asm-arm/arch-s3c2410/system.h
+1 -1
View File
@@ -71,7 +71,7 @@ arch_reset(char mode)
/* set the watchdog to go and reset... */
__raw_writel(S3C2410_WTCON_ENABLE|S3C2410_WTCON_DIV16|S3C2410_WTCON_RSTEN |
S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
S3C2410_WTCON_PRESCALE(0x20), S3C2410_WTCON);
/* wait for reset to assert... */
mdelay(5000);
include/asm-arm/arch-sa1100/jornada720.h
-42
View File
@@ -1,42 +0,0 @@
/*
* linux/include/asm-arm/arch-sa1100/jornada720.h
*
* Created 2000/11/29 by John Ankcorn <jca@lcs.mit.edu>
*
* This file contains the hardware specific definitions for HP Jornada 720
*
*/
#ifndef __ASM_ARCH_HARDWARE_H
#error "include <asm/hardware.h> instead"
#endif
#define SA1111_BASE (0x40000000)
#define GPIO_JORNADA720_KEYBOARD GPIO_GPIO(0)
#define GPIO_JORNADA720_MOUSE GPIO_GPIO(9)
#define GPIO_JORNADA720_KEYBOARD_IRQ IRQ_GPIO0
#define GPIO_JORNADA720_MOUSE_IRQ IRQ_GPIO9
/* MCU COMMANDS */
#define MCU_GetBatteryData 0xc0
#define MCU_GetScanKeyCode 0x90
#define MCU_GetTouchSamples 0xa0
#define MCU_GetContrast 0xD0
#define MCU_SetContrast 0xD1
#define MCU_GetBrightness 0xD2
#define MCU_SetBrightness 0xD3
#define MCU_ContrastOff 0xD8
#define MCU_BrightnessOff 0xD9
#define MCU_PWMOFF 0xDF
#define MCU_TxDummy 0x11
#define MCU_ErrorCode 0x00
#ifndef __ASSEMBLY__
void jornada720_mcu_init(void);
void jornada_contrast(int arg_contrast);
void jornada720_battery(void);
int jornada720_getkey(unsigned char *data, int size);
#endif
include/asm-arm/arch-sa1100/memory.h
+1 -33
View File
@@ -39,7 +39,6 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
#define __virt_to_bus(x) __virt_to_phys(x)
#define __bus_to_virt(x) __phys_to_virt(x)
#ifdef CONFIG_DISCONTIGMEM
/*
* Because of the wide memory address space between physical RAM banks on the
* SA1100, it's much convenient to use Linux's NUMA support to implement our
@@ -57,38 +56,7 @@ void sa1111_adjust_zones(int node, unsigned long *size, unsigned long *holes);
* node 2: 0xd0000000 - 0xd7ffffff
* node 3: 0xd8000000 - 0xdfffffff
*/
/*
* Given a kernel address, find the home node of the underlying memory.
*/
#define KVADDR_TO_NID(addr) (((unsigned long)(addr) - PAGE_OFFSET) >> 27)
/*
* Given a page frame number, convert it to a node id.
*/
#define PFN_TO_NID(pfn) (((pfn) - PHYS_PFN_OFFSET) >> (27 - PAGE_SHIFT))
/*
* Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
* and return the mem_map of that node.
*/
#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
/*
* Given a page frame number, find the owning node of the memory
* and return the mem_map of that node.
*/
#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
/*
* Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
* and returns the index corresponding to the appropriate page in the
* node's mem_map.
*/
#define LOCAL_MAP_NR(addr) \
(((unsigned long)(addr) & 0x07ffffff) >> PAGE_SHIFT)
#endif
#define NODE_MEM_SIZE_BITS 27
/*
* Cache flushing area - SA1100 zero bank
include/asm-arm/bug.h
+2 -2
View File
@@ -4,10 +4,10 @@
#ifdef CONFIG_BUG
#ifdef CONFIG_DEBUG_BUGVERBOSE
extern void __bug(const char *file, int line, void *data) __attribute__((noreturn));
extern void __bug(const char *file, int line) __attribute__((noreturn));
/* give file/line information */
#define BUG() __bug(__FILE__, __LINE__, NULL)
#define BUG() __bug(__FILE__, __LINE__)
#else
include/asm-arm/cnt32_to_63.h
+78
View File
@@ -0,0 +1,78 @@
/*
* include/asm/cnt32_to_63.h -- extend a 32-bit counter to 63 bits
*
* Author: Nicolas Pitre
* Created: December 3, 2006
* Copyright: MontaVista Software, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2
* as published by the Free Software Foundation.
*/
#ifndef __INCLUDE_CNT32_TO_63_H__
#define __INCLUDE_CNT32_TO_63_H__
#include <linux/compiler.h>
#include <asm/types.h>
#include <asm/byteorder.h>
/*
* Prototype: u64 cnt32_to_63(u32 cnt)
* Many hardware clock counters are only 32 bits wide and therefore have
* a relatively short period making wrap-arounds rather frequent. This
* is a problem when implementing sched_clock() for example, where a 64-bit
* non-wrapping monotonic value is expected to be returned.
*
* To overcome that limitation, let's extend a 32-bit counter to 63 bits
* in a completely lock free fashion. Bits 0 to 31 of the clock are provided
* by the hardware while bits 32 to 62 are stored in memory. The top bit in
* memory is used to synchronize with the hardware clock half-period. When
* the top bit of both counters (hardware and in memory) differ then the
* memory is updated with a new value, incrementing it when the hardware
* counter wraps around.
*
* Because a word store in memory is atomic then the incremented value will
* always be in synch with the top bit indicating to any potential concurrent
* reader if the value in memory is up to date or not with regards to the
* needed increment. And any race in updating the value in memory is harmless
* as the same value would simply be stored more than once.
*
* The only restriction for the algorithm to work properly is that this
* code must be executed at least once per each half period of the 32-bit
* counter to properly update the state bit in memory. This is usually not a
* problem in practice, but if it is then a kernel timer could be scheduled
* to manage for this code to be executed often enough.
*
* Note that the top bit (bit 63) in the returned value should be considered
* as garbage. It is not cleared here because callers are likely to use a
* multiplier on the returned value which can get rid of the top bit
* implicitly by making the multiplier even, therefore saving on a runtime
* clear-bit instruction. Otherwise caller must remember to clear the top
* bit explicitly.
*/
/* this is used only to give gcc a clue about good code generation */
typedef union {
struct {
#if defined(__LITTLE_ENDIAN)
u32 lo, hi;
#elif defined(__BIG_ENDIAN)
u32 hi, lo;
#endif
};
u64 val;
} cnt32_to_63_t;
#define cnt32_to_63(cnt_lo) \
({ \
static volatile u32 __m_cnt_hi = 0; \
cnt32_to_63_t __x; \
__x.hi = __m_cnt_hi; \
__x.lo = (cnt_lo); \
if (unlikely((s32)(__x.hi ^ __x.lo) < 0)) \
__m_cnt_hi = __x.hi = (__x.hi ^ 0x80000000) + (__x.hi >> 31); \
__x.val; \
})
#endif
include/asm-arm/div64.h
+179 -1
View File
@@ -27,7 +27,7 @@
#define __xh "r1"
#endif
#define do_div(n,base) \
#define __do_div_asm(n, base) \
({ \
register unsigned int __base asm("r4") = base; \
register unsigned long long __n asm("r0") = n; \
@@ -45,4 +45,182 @@
__rem; \
})
#if __GNUC__ < 4
/*
* gcc versions earlier than 4.0 are simply too problematic for the
* optimized implementation below. First there is gcc PR 15089 that
* tend to trig on more complex constructs, spurious .global __udivsi3
* are inserted even if none of those symbols are referenced in the
* generated code, and those gcc versions are not able to do constant
* propagation on long long values anyway.
*/
#define do_div(n, base) __do_div_asm(n, base)
#elif __GNUC__ >= 4
#include <asm/bug.h>
/*
* If the divisor happens to be constant, we determine the appropriate
* inverse at compile time to turn the division into a few inline
* multiplications instead which is much faster. And yet only if compiling
* for ARMv4 or higher (we need umull/umlal) and if the gcc version is
* sufficiently recent to perform proper long long constant propagation.
* (It is unfortunate that gcc doesn't perform all this internally.)
*/
#define do_div(n, base) \
({ \
unsigned int __r, __b = (base); \
if (!__builtin_constant_p(__b) || __b == 0 || \
(__LINUX_ARM_ARCH__ < 4 && (__b & (__b - 1)) != 0)) { \
/* non-constant divisor (or zero): slow path */ \
__r = __do_div_asm(n, __b); \
} else if ((__b & (__b - 1)) == 0) { \
/* Trivial: __b is constant and a power of 2 */ \
/* gcc does the right thing with this code. */ \
__r = n; \
__r &= (__b - 1); \
n /= __b; \
} else { \
/* Multiply by inverse of __b: n/b = n*(p/b)/p */ \
/* We rely on the fact that most of this code gets */ \
/* optimized away at compile time due to constant */ \
/* propagation and only a couple inline assembly */ \
/* instructions should remain. Better avoid any */ \
/* code construct that might prevent that. */ \
unsigned long long __res, __x, __t, __m, __n = n; \
unsigned int __c, __p, __z = 0; \
/* preserve low part of n for reminder computation */ \
__r = __n; \
/* determine number of bits to represent __b */ \
__p = 1 << __div64_fls(__b); \
/* compute __m = ((__p << 64) + __b - 1) / __b */ \
__m = (~0ULL / __b) * __p; \
__m += (((~0ULL % __b + 1) * __p) + __b - 1) / __b; \
/* compute __res = __m*(~0ULL/__b*__b-1)/(__p << 64) */ \
__x = ~0ULL / __b * __b - 1; \
__res = (__m & 0xffffffff) * (__x & 0xffffffff); \
__res >>= 32; \
__res += (__m & 0xffffffff) * (__x >> 32); \
__t = __res; \
__res += (__x & 0xffffffff) * (__m >> 32); \
__t = (__res < __t) ? (1ULL << 32) : 0; \
__res = (__res >> 32) + __t; \
__res += (__m >> 32) * (__x >> 32); \
__res /= __p; \
/* Now sanitize and optimize what we've got. */ \
if (~0ULL % (__b / (__b & -__b)) == 0) { \
/* those cases can be simplified with: */ \
__n /= (__b & -__b); \
__m = ~0ULL / (__b / (__b & -__b)); \
__p = 1; \
__c = 1; \
} else if (__res != __x / __b) { \
/* We can't get away without a correction */ \
/* to compensate for bit truncation errors. */ \
/* To avoid it we'd need an additional bit */ \
/* to represent __m which would overflow it. */ \
/* Instead we do m=p/b and n/b=(n*m+m)/p. */ \
__c = 1; \
/* Compute __m = (__p << 64) / __b */ \
__m = (~0ULL / __b) * __p; \
__m += ((~0ULL % __b + 1) * __p) / __b; \
} else { \
/* Reduce __m/__p, and try to clear bit 31 */ \
/* of __m when possible otherwise that'll */ \
/* need extra overflow handling later. */ \
unsigned int __bits = -(__m & -__m); \
__bits |= __m >> 32; \
__bits = (~__bits) << 1; \
/* If __bits == 0 then setting bit 31 is */ \
/* unavoidable. Simply apply the maximum */ \
/* possible reduction in that case. */ \
/* Otherwise the MSB of __bits indicates the */ \
/* best reduction we should apply. */ \
if (!__bits) { \
__p /= (__m & -__m); \
__m /= (__m & -__m); \
} else { \
__p >>= __div64_fls(__bits); \
__m >>= __div64_fls(__bits); \
} \
/* No correction needed. */ \
__c = 0; \
} \
/* Now we have a combination of 2 conditions: */ \
/* 1) whether or not we need a correction (__c), and */ \
/* 2) whether or not there might be an overflow in */ \
/* the cross product (__m & ((1<<63) | (1<<31))) */ \
/* Select the best insn combination to perform the */ \
/* actual __m * __n / (__p << 64) operation. */ \
if (!__c) { \
asm ( "umull %Q0, %R0, %1, %Q2\n\t" \
"mov %Q0, #0" \
: "=&r" (__res) \
: "r" (__m), "r" (__n) \
: "cc" ); \
} else if (!(__m & ((1ULL << 63) | (1ULL << 31)))) { \
__res = __m; \
asm ( "umlal %Q0, %R0, %Q1, %Q2\n\t" \
"mov %Q0, #0" \
: "+r" (__res) \
: "r" (__m), "r" (__n) \
: "cc" ); \
} else { \
asm ( "umull %Q0, %R0, %Q1, %Q2\n\t" \
"cmn %Q0, %Q1\n\t" \
"adcs %R0, %R0, %R1\n\t" \
"adc %Q0, %3, #0" \
: "=&r" (__res) \
: "r" (__m), "r" (__n), "r" (__z) \
: "cc" ); \
} \
if (!(__m & ((1ULL << 63) | (1ULL << 31)))) { \
asm ( "umlal %R0, %Q0, %R1, %Q2\n\t" \
"umlal %R0, %Q0, %Q1, %R2\n\t" \
"mov %R0, #0\n\t" \
"umlal %Q0, %R0, %R1, %R2" \
: "+r" (__res) \
: "r" (__m), "r" (__n) \
: "cc" ); \
} else { \
asm ( "umlal %R0, %Q0, %R2, %Q3\n\t" \
"umlal %R0, %1, %Q2, %R3\n\t" \
"mov %R0, #0\n\t" \
"adds %Q0, %1, %Q0\n\t" \
"adc %R0, %R0, #0\n\t" \
"umlal %Q0, %R0, %R2, %R3" \
: "+r" (__res), "+r" (__z) \
: "r" (__m), "r" (__n) \
: "cc" ); \
} \
__res /= __p; \
/* The reminder can be computed with 32-bit regs */ \
/* only, and gcc is good at that. */ \
{ \
unsigned int __res0 = __res; \
unsigned int __b0 = __b; \
__r -= __res0 * __b0; \
} \
/* BUG_ON(__r >= __b || __res * __b + __r != n); */ \
n = __res; \
} \
__r; \
})
/* our own fls implementation to make sure constant propagation is fine */
#define __div64_fls(bits) \
({ \
unsigned int __left = (bits), __nr = 0; \
if (__left & 0xffff0000) __nr += 16, __left >>= 16; \
if (__left & 0x0000ff00) __nr += 8, __left >>= 8; \
if (__left & 0x000000f0) __nr += 4, __left >>= 4; \
if (__left & 0x0000000c) __nr += 2, __left >>= 2; \
if (__left & 0x00000002) __nr += 1; \
__nr; \
})
#endif
#endif
include/asm-arm/elf.h
+77 -75
View File
@@ -1,17 +1,22 @@
#ifndef __ASMARM_ELF_H
#define __ASMARM_ELF_H
#ifndef __ASSEMBLY__
/*
* ELF register definitions..
*/
#include <asm/ptrace.h>
#include <asm/user.h>
typedef unsigned long elf_greg_t;
typedef unsigned long elf_freg_t[3];
#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef struct user_fp elf_fpregset_t;
#endif
#define EM_ARM 40
#define EF_ARM_APCS26 0x08
#define EF_ARM_SOFT_FLOAT 0x200
@@ -23,11 +28,6 @@ typedef unsigned long elf_freg_t[3];
#define R_ARM_CALL 28
#define R_ARM_JUMP24 29
#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
typedef elf_greg_t elf_gregset_t[ELF_NGREG];
typedef struct user_fp elf_fpregset_t;
/*
* These are used to set parameters in the core dumps.
*/
@@ -39,13 +39,65 @@ typedef struct user_fp elf_fpregset_t;
#endif
#define ELF_ARCH EM_ARM
/*
* HWCAP flags - for elf_hwcap (in kernel) and AT_HWCAP
*/
#define HWCAP_SWP 1
#define HWCAP_HALF 2
#define HWCAP_THUMB 4
#define HWCAP_26BIT 8 /* Play it safe */
#define HWCAP_FAST_MULT 16
#define HWCAP_FPA 32
#define HWCAP_VFP 64
#define HWCAP_EDSP 128
#define HWCAP_JAVA 256
#define HWCAP_IWMMXT 512
#ifdef __KERNEL__
#include <asm/procinfo.h>
#ifndef __ASSEMBLY__
/*
* This yields a mask that user programs can use to figure out what
* instruction set this cpu supports.
*/
#define ELF_HWCAP (elf_hwcap)
extern unsigned int elf_hwcap;
/*
* This yields a string that ld.so will use to load implementation
* specific libraries for optimization. This is more specific in
* intent than poking at uname or /proc/cpuinfo.
*
* For now we just provide a fairly general string that describes the
* processor family. This could be made more specific later if someone
* implemented optimisations that require it. 26-bit CPUs give you
* "v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't
* supported). 32-bit CPUs give you "v3[lb]" for anything based on an
* ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1
* core.
*/
#define ELF_PLATFORM_SIZE 8
#define ELF_PLATFORM (elf_platform)
extern char elf_platform[];
#endif
/*
* This is used to ensure we don't load something for the wrong architecture.
*/
#define elf_check_arch(x) ( ((x)->e_machine == EM_ARM) && (ELF_PROC_OK((x))) )
#define elf_check_arch(x) ((x)->e_machine == EM_ARM && ELF_PROC_OK(x))
/*
* 32-bit code is always OK. Some cpus can do 26-bit, some can't.
*/
#define ELF_PROC_OK(x) (ELF_THUMB_OK(x) && ELF_26BIT_OK(x))
#define ELF_THUMB_OK(x) \
((elf_hwcap & HWCAP_THUMB && ((x)->e_entry & 1) == 1) || \
((x)->e_entry & 3) == 0)
#define ELF_26BIT_OK(x) \
((elf_hwcap & HWCAP_26BIT && (x)->e_flags & EF_ARM_APCS26) || \
((x)->e_flags & EF_ARM_APCS26) == 0)
#define USE_ELF_CORE_DUMP
#define ELF_EXEC_PAGESIZE 4096
@@ -62,74 +114,24 @@ typedef struct user_fp elf_fpregset_t;
have no such handler. */
#define ELF_PLAT_INIT(_r, load_addr) (_r)->ARM_r0 = 0
/* This yields a mask that user programs can use to figure out what
instruction set this cpu supports. */
#define ELF_HWCAP (elf_hwcap)
/* This yields a string that ld.so will use to load implementation
specific libraries for optimization. This is more specific in
intent than poking at uname or /proc/cpuinfo. */
/* For now we just provide a fairly general string that describes the
processor family. This could be made more specific later if someone
implemented optimisations that require it. 26-bit CPUs give you
"v1l" for ARM2 (no SWP) and "v2l" for anything else (ARM1 isn't
supported). 32-bit CPUs give you "v3[lb]" for anything based on an
ARM6 or ARM7 core and "armv4[lb]" for anything based on a StrongARM-1
core. */
#define ELF_PLATFORM_SIZE 8
extern char elf_platform[];
#define ELF_PLATFORM (elf_platform)
/*
* 32-bit code is always OK. Some cpus can do 26-bit, some can't.
* Since the FPA coprocessor uses CP1 and CP2, and iWMMXt uses CP0
* and CP1, we only enable access to the iWMMXt coprocessor if the
* binary is EABI or softfloat (and thus, guaranteed not to use
* FPA instructions.)
*/
#define ELF_PROC_OK(x) (ELF_THUMB_OK(x) && ELF_26BIT_OK(x))
#define ELF_THUMB_OK(x) \
(( (elf_hwcap & HWCAP_THUMB) && ((x)->e_entry & 1) == 1) || \
((x)->e_entry & 3) == 0)
#define ELF_26BIT_OK(x) \
(( (elf_hwcap & HWCAP_26BIT) && (x)->e_flags & EF_ARM_APCS26) || \
((x)->e_flags & EF_ARM_APCS26) == 0)
#ifndef CONFIG_IWMMXT
/* Old NetWinder binaries were compiled in such a way that the iBCS
heuristic always trips on them. Until these binaries become uncommon
enough not to care, don't trust the `ibcs' flag here. In any case
there is no other ELF system currently supported by iBCS.
@@ Could print a warning message to encourage users to upgrade. */
#define SET_PERSONALITY(ex,ibcs2) \
set_personality(((ex).e_flags&EF_ARM_APCS26 ?PER_LINUX :PER_LINUX_32BIT))
#else
/*
* All iWMMXt capable CPUs don't support 26-bit mode. Yet they can run
* legacy binaries which used to contain FPA11 floating point instructions
* that have always been emulated by the kernel. PFA11 and iWMMXt overlap
* on coprocessor 1 space though. We therefore must decide if given task
* is allowed to use CP 0 and 1 for iWMMXt, or if they should be blocked
* at all times for the prefetch exception handler to catch FPA11 opcodes
* and emulate them. The best indication to discriminate those two cases
* is the SOFT_FLOAT flag in the ELF header.
*/
#define SET_PERSONALITY(ex,ibcs2) \
do { \
set_personality(PER_LINUX_32BIT); \
if (((ex).e_flags & EF_ARM_EABI_MASK) || \
((ex).e_flags & EF_ARM_SOFT_FLOAT)) \
set_thread_flag(TIF_USING_IWMMXT); \
else \
clear_thread_flag(TIF_USING_IWMMXT); \
} while (0)
#endif
#define SET_PERSONALITY(ex, ibcs2) \
do { \
if ((ex).e_flags & EF_ARM_APCS26) { \
set_personality(PER_LINUX); \
} else { \
set_personality(PER_LINUX_32BIT); \
if (elf_hwcap & HWCAP_IWMMXT && (ex).e_flags & (EF_ARM_EABI_MASK | EF_ARM_SOFT_FLOAT)) \
set_thread_flag(TIF_USING_IWMMXT); \
else \
clear_thread_flag(TIF_USING_IWMMXT); \
} \
} while (0)
#endif
include/asm-arm/io.h
-8
View File
@@ -75,14 +75,6 @@ extern void __readwrite_bug(const char *fn);
*/
#include <asm/arch/io.h>
#ifdef __io_pci
#warning machine class uses buggy __io_pci
#endif
#if defined(__arch_putb) || defined(__arch_putw) || defined(__arch_putl) || \
defined(__arch_getb) || defined(__arch_getw) || defined(__arch_getl)
#warning machine class uses old __arch_putw or __arch_getw
#endif
/*
* IO port access primitives
* -------------------------
include/asm-arm/mach/irq.h
-12
View File
@@ -21,12 +21,6 @@ extern void (*init_arch_irq)(void);
extern void init_FIQ(void);
extern int show_fiq_list(struct seq_file *, void *);
/*
* Function wrappers
*/
#define set_irq_chipdata(irq, d) set_irq_chip_data(irq, d)
#define get_irq_chipdata(irq) get_irq_chip_data(irq)
/*
* Obsolete inline function for calling irq descriptor handlers.
*/
@@ -44,12 +38,6 @@ void set_irq_flags(unsigned int irq, unsigned int flags);
/*
* This is for easy migration, but should be changed in the source
*/
#define do_level_IRQ handle_level_irq
#define do_edge_IRQ handle_edge_irq
#define do_simple_IRQ handle_simple_irq
#define irqdesc irq_desc
#define irqchip irq_chip
#define do_bad_IRQ(irq,desc) \
do { \
spin_lock(&desc->lock); \
include/asm-arm/memory.h
+39
View File
@@ -215,6 +215,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
* virt_addr_valid(k) indicates whether a virtual address is valid
*/
#ifndef CONFIG_DISCONTIGMEM
#define ARCH_PFN_OFFSET PHYS_PFN_OFFSET
#define pfn_valid(pfn) ((pfn) >= PHYS_PFN_OFFSET && (pfn) < (PHYS_PFN_OFFSET + max_mapnr))
@@ -230,6 +231,7 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
* around in memory.
*/
#include <linux/numa.h>
#define arch_pfn_to_nid(pfn) PFN_TO_NID(pfn)
#define arch_local_page_offset(pfn, nid) LOCAL_MAP_NR((pfn) << PAGE_SHIFT)
@@ -256,6 +258,43 @@ static inline __deprecated void *bus_to_virt(unsigned long x)
*/
#define PHYS_TO_NID(addr) PFN_TO_NID((addr) >> PAGE_SHIFT)
/*
* Given a kaddr, ADDR_TO_MAPBASE finds the owning node of the memory
* and returns the mem_map of that node.
*/
#define ADDR_TO_MAPBASE(kaddr) NODE_MEM_MAP(KVADDR_TO_NID(kaddr))
/*
* Given a page frame number, find the owning node of the memory
* and returns the mem_map of that node.
*/
#define PFN_TO_MAPBASE(pfn) NODE_MEM_MAP(PFN_TO_NID(pfn))
#ifdef NODE_MEM_SIZE_BITS
#define NODE_MEM_SIZE_MASK ((1 << NODE_MEM_SIZE_BITS) - 1)
/*
* Given a kernel address, find the home node of the underlying memory.
*/
#define KVADDR_TO_NID(addr) \
(((unsigned long)(addr) - PAGE_OFFSET) >> NODE_MEM_SIZE_BITS)
/*
* Given a page frame number, convert it to a node id.
*/
#define PFN_TO_NID(pfn) \
(((pfn) - PHYS_PFN_OFFSET) >> (NODE_MEM_SIZE_BITS - PAGE_SHIFT))
/*
* Given a kaddr, LOCAL_MEM_MAP finds the owning node of the memory
* and returns the index corresponding to the appropriate page in the
* node's mem_map.
*/
#define LOCAL_MAP_NR(addr) \
(((unsigned long)(addr) & NODE_MEM_SIZE_MASK) >> PAGE_SHIFT)
#endif /* NODE_MEM_SIZE_BITS */
#endif /* !CONFIG_DISCONTIGMEM */
/*
include/asm-arm/pgtable-nommu.h
-1
View File
@@ -44,7 +44,6 @@
#define PAGE_READONLY __pgprot(0)
#define PAGE_KERNEL __pgprot(0)
//extern void paging_init(struct meminfo *, struct machine_desc *);
#define swapper_pg_dir ((pgd_t *) 0)
#define __swp_type(x) (0)
include/asm-arm/pgtable.h
+1 -2
View File
@@ -169,8 +169,7 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
#define L_PTE_WRITE (1 << 5)
#define L_PTE_EXEC (1 << 6)
#define L_PTE_DIRTY (1 << 7)
#define L_PTE_COHERENT (1 << 9) /* I/O coherent (xsc3) */
#define L_PTE_SHARED (1 << 10) /* shared between CPUs (v6) */
#define L_PTE_SHARED (1 << 10) /* shared(v6), coherent(xsc3) */
#define L_PTE_ASID (1 << 11) /* non-global (use ASID, v6) */
#ifndef __ASSEMBLY__
include/asm-arm/processor.h
-1
View File
@@ -20,7 +20,6 @@
#ifdef __KERNEL__
#include <asm/ptrace.h>
#include <asm/procinfo.h>
#include <asm/types.h>
union debug_insn {
include/asm-arm/procinfo.h
+5 -16
View File
@@ -10,7 +10,7 @@
#ifndef __ASM_PROCINFO_H
#define __ASM_PROCINFO_H
#ifndef __ASSEMBLY__
#ifdef __KERNEL__
struct cpu_tlb_fns;
struct cpu_user_fns;
@@ -42,19 +42,8 @@ struct proc_info_list {
struct cpu_cache_fns *cache;
};
extern unsigned int elf_hwcap;
#endif /* __ASSEMBLY__ */
#define HWCAP_SWP 1
#define HWCAP_HALF 2
#define HWCAP_THUMB 4
#define HWCAP_26BIT 8 /* Play it safe */
#define HWCAP_FAST_MULT 16
#define HWCAP_FPA 32
#define HWCAP_VFP 64
#define HWCAP_EDSP 128
#define HWCAP_JAVA 256
#define HWCAP_IWMMXT 512
#else /* __KERNEL__ */
#include <asm/elf.h>
#warning "Please include asm/elf.h instead"
#endif /* __KERNEL__ */
#endif
include/asm-arm/thread_info.h
+12 -2
View File
@@ -94,8 +94,18 @@ static inline struct thread_info *current_thread_info(void)
return (struct thread_info *)(sp & ~(THREAD_SIZE - 1));
}
extern struct thread_info *alloc_thread_info(struct task_struct *task);
extern void free_thread_info(struct thread_info *);
/* thread information allocation */
#ifdef CONFIG_DEBUG_STACK_USAGE
#define alloc_thread_info(tsk) \
((struct thread_info *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, \
THREAD_SIZE_ORDER))
#else
#define alloc_thread_info(tsk) \
((struct thread_info *)__get_free_pages(GFP_KERNEL, THREAD_SIZE_ORDER))
#endif
#define free_thread_info(info) \
free_pages((unsigned long)info, THREAD_SIZE_ORDER);
#define thread_saved_pc(tsk) \
((unsigned long)(pc_pointer(task_thread_info(tsk)->cpu_context.pc)))
include/asm-avr32/arch-at32ap/at91rm9200_pdc.h → include/asm-avr32/arch-at32ap/at91_pdc.h
+3 -3
View File
@@ -1,5 +1,5 @@
/*
* include/asm-arm/arch-at91rm9200/at91rm9200_pdc.h
* include/asm-arm/arch-at91rm9200/at91_pdc.h
*
* Copyright (C) 2005 Ivan Kokshaysky
* Copyright (C) SAN People
@@ -13,8 +13,8 @@
* (at your option) any later version.
*/
#ifndef AT91RM9200_PDC_H
#define AT91RM9200_PDC_H
#ifndef AT91_PDC_H
#define AT91_PDC_H
#define AT91_PDC_RPR 0x100 /* Receive Pointer Register */
#define AT91_PDC_RCR 0x104 /* Receive Counter Register */
include/linux/i2c-pxa.h
-31
View File
@@ -1,29 +1,6 @@
#ifndef _LINUX_I2C_ALGO_PXA_H
#define _LINUX_I2C_ALGO_PXA_H
struct i2c_eeprom_emu_watcher {
void (*write)(void *, unsigned int addr, unsigned char newval);
};
struct i2c_eeprom_emu_watch {
struct list_head node;
unsigned int start;
unsigned int end;
struct i2c_eeprom_emu_watcher *ops;
void *data;
};
#define I2C_EEPROM_EMU_SIZE (256)
struct i2c_eeprom_emu {
unsigned int size;
unsigned int ptr;
unsigned int seen_start;
struct list_head watch;
unsigned char bytes[I2C_EEPROM_EMU_SIZE];
};
typedef enum i2c_slave_event_e {
I2C_SLAVE_EVENT_START_READ,
I2C_SLAVE_EVENT_START_WRITE,
@@ -37,12 +14,4 @@ struct i2c_slave_client {
void (*write)(void *ptr, unsigned int val);
};
extern int i2c_eeprom_emu_addwatcher(struct i2c_eeprom_emu *, void *data,
unsigned int addr, unsigned int size,
struct i2c_eeprom_emu_watcher *);
extern void i2c_eeprom_emu_delwatcher(struct i2c_eeprom_emu *, void *data, struct i2c_eeprom_emu_watcher *watcher);
extern struct i2c_eeprom_emu *i2c_pxa_get_eeprom(void);
#endif /* _LINUX_I2C_ALGO_PXA_H */