From 417e24986935f6bd6afa38010cc981cf4d7a7bef Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Fri, 17 Jul 2020 18:00:24 +0100 Subject: [PATCH 01/14] pinctrl: sh-pfc: r8a7790: Add USB1 PWEN pin and group Add USB1 PWEN pin and group for USB1 interface. Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/1595005225-11519-2-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index f524401fec5f..39ba1e7cc1c3 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -3611,6 +3611,13 @@ static const unsigned int usb1_pins[] = { static const unsigned int usb1_mux[] = { USB1_PWEN_MARK, USB1_OVC_MARK, }; +static const unsigned int usb1_pwen_pins[] = { + /* PWEN */ + RCAR_GP_PIN(5, 20), +}; +static const unsigned int usb1_pwen_mux[] = { + USB1_PWEN_MARK, +}; /* - USB2 ------------------------------------------------------------------- */ static const unsigned int usb2_pins[] = { /* PWEN, OVC */ @@ -3939,7 +3946,7 @@ static const unsigned int vin3_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[289]; + struct sh_pfc_pin_group common[290]; struct sh_pfc_pin_group automotive[1]; } pinmux_groups = { .common = { @@ -4193,6 +4200,7 @@ static const struct { SH_PFC_PIN_GROUP(usb0), SH_PFC_PIN_GROUP(usb0_ovc_vbus), SH_PFC_PIN_GROUP(usb1), + SH_PFC_PIN_GROUP(usb1_pwen), SH_PFC_PIN_GROUP(usb2), VIN_DATA_PIN_GROUP(vin0_data, 24), VIN_DATA_PIN_GROUP(vin0_data, 20), @@ -4640,6 +4648,7 @@ static const char * const usb0_groups[] = { static const char * const usb1_groups[] = { "usb1", + "usb1_pwen", }; static const char * const usb2_groups[] = { From bbf369d4e59a248ed715041267951f5cd051b317 Mon Sep 17 00:00:00 2001 From: Lad Prabhakar Date: Tue, 25 Aug 2020 10:54:48 +0100 Subject: [PATCH 02/14] pinctrl: sh-pfc: r8a7790: Add CAN pins, groups and functions Add pins, groups and functions for the CAN{0,1} interface. Signed-off-by: Lad Prabhakar Reviewed-by: Chris Paterson Link: https://lore.kernel.org/r/20200825095448.13093-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/pfc-r8a7790.c | 112 ++++++++++++++++++++++++++- 1 file changed, 110 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c index 39ba1e7cc1c3..60f973c5dffe 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c @@ -1871,6 +1871,86 @@ static const unsigned int avb_gmii_mux[] = { AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK, AVB_COL_MARK, }; +/* - CAN0 ----------------------------------------------------------------- */ +static const unsigned int can0_data_pins[] = { + /* CAN0 RX */ + RCAR_GP_PIN(1, 17), + /* CAN0 TX */ + RCAR_GP_PIN(1, 19), +}; +static const unsigned int can0_data_mux[] = { + CAN0_RX_MARK, + CAN0_TX_MARK, +}; +static const unsigned int can0_data_b_pins[] = { + /* CAN0 RXB */ + RCAR_GP_PIN(4, 5), + /* CAN0 TXB */ + RCAR_GP_PIN(4, 4), +}; +static const unsigned int can0_data_b_mux[] = { + CAN0_RX_B_MARK, + CAN0_TX_B_MARK, +}; +static const unsigned int can0_data_c_pins[] = { + /* CAN0 RXC */ + RCAR_GP_PIN(4, 26), + /* CAN0 TXC */ + RCAR_GP_PIN(4, 23), +}; +static const unsigned int can0_data_c_mux[] = { + CAN0_RX_C_MARK, + CAN0_TX_C_MARK, +}; +static const unsigned int can0_data_d_pins[] = { + /* CAN0 RXD */ + RCAR_GP_PIN(4, 26), + /* CAN0 TXD */ + RCAR_GP_PIN(4, 18), +}; +static const unsigned int can0_data_d_mux[] = { + CAN0_RX_D_MARK, + CAN0_TX_D_MARK, +}; +/* - CAN1 ----------------------------------------------------------------- */ +static const unsigned int can1_data_pins[] = { + /* CAN1 RX */ + RCAR_GP_PIN(1, 22), + /* CAN1 TX */ + RCAR_GP_PIN(1, 18), +}; +static const unsigned int can1_data_mux[] = { + CAN1_RX_MARK, + CAN1_TX_MARK, +}; +static const unsigned int can1_data_b_pins[] = { + /* CAN1 RXB */ + RCAR_GP_PIN(4, 7), + /* CAN1 TXB */ + RCAR_GP_PIN(4, 6), +}; +static const unsigned int can1_data_b_mux[] = { + CAN1_RX_B_MARK, + CAN1_TX_B_MARK, +}; +/* - CAN Clock -------------------------------------------------------------- */ +static const unsigned int can_clk_pins[] = { + /* CLK */ + RCAR_GP_PIN(1, 21), +}; + +static const unsigned int can_clk_mux[] = { + CAN_CLK_MARK, +}; + +static const unsigned int can_clk_b_pins[] = { + /* CLK */ + RCAR_GP_PIN(4, 3), +}; + +static const unsigned int can_clk_b_mux[] = { + CAN_CLK_B_MARK, +}; /* - DU RGB ----------------------------------------------------------------- */ static const unsigned int du_rgb666_pins[] = { /* R[7:2], G[7:2], B[7:2] */ @@ -3946,7 +4026,7 @@ static const unsigned int vin3_clk_mux[] = { }; static const struct { - struct sh_pfc_pin_group common[290]; + struct sh_pfc_pin_group common[298]; struct sh_pfc_pin_group automotive[1]; } pinmux_groups = { .common = { @@ -3963,6 +4043,14 @@ static const struct { SH_PFC_PIN_GROUP(avb_mdio), SH_PFC_PIN_GROUP(avb_mii), SH_PFC_PIN_GROUP(avb_gmii), + SH_PFC_PIN_GROUP(can0_data), + SH_PFC_PIN_GROUP(can0_data_b), + SH_PFC_PIN_GROUP(can0_data_c), + SH_PFC_PIN_GROUP(can0_data_d), + SH_PFC_PIN_GROUP(can1_data), + SH_PFC_PIN_GROUP(can1_data_b), + SH_PFC_PIN_GROUP(can_clk), + SH_PFC_PIN_GROUP(can_clk_b), SH_PFC_PIN_GROUP(du_rgb666), SH_PFC_PIN_GROUP(du_rgb888), SH_PFC_PIN_GROUP(du_clk_out_0), @@ -4265,6 +4353,23 @@ static const char * const avb_groups[] = { "avb_gmii", }; +static const char * const can0_groups[] = { + "can0_data", + "can0_data_b", + "can0_data_c", + "can0_data_d", +}; + +static const char * const can1_groups[] = { + "can1_data", + "can1_data_b", +}; + +static const char * const can_clk_groups[] = { + "can_clk", + "can_clk_b", +}; + static const char * const du_groups[] = { "du_rgb666", "du_rgb888", @@ -4706,13 +4811,16 @@ static const char * const vin3_groups[] = { }; static const struct { - struct sh_pfc_function common[55]; + struct sh_pfc_function common[58]; struct sh_pfc_function automotive[1]; } pinmux_functions = { .common = { SH_PFC_FUNCTION(audio_clk), SH_PFC_FUNCTION(avb), SH_PFC_FUNCTION(du), + SH_PFC_FUNCTION(can0), + SH_PFC_FUNCTION(can1), + SH_PFC_FUNCTION(can_clk), SH_PFC_FUNCTION(du0), SH_PFC_FUNCTION(du1), SH_PFC_FUNCTION(du2), From 7b9ec811752c17c4c6e70d296ef8aa205a7acacd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:22:08 +0200 Subject: [PATCH 03/14] dt-bindings: pinctrl: sh-pfc: Convert to json-schema Convert the Renesas Pin Function Controller (PFC) Device Tree binding documentation to json-schema. Document missing properties. Drop deprecated and obsolete #gpio-range-cells property. Update the example to match reality. Drop consumer examples, as they do not belong here. Signed-off-by: Geert Uytterhoeven Reviewed-by: Rob Herring Reviewed-by: Linus Walleij Link: https://lore.kernel.org/r/20200821112208.5295-1-geert+renesas@glider.be --- .../bindings/pinctrl/renesas,pfc-pinctrl.txt | 188 ----------------- .../bindings/pinctrl/renesas,pfc.yaml | 193 ++++++++++++++++++ 2 files changed, 193 insertions(+), 188 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt deleted file mode 100644 index d75476e24514..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/renesas,pfc-pinctrl.txt +++ /dev/null @@ -1,188 +0,0 @@ -* Renesas Pin Function Controller (GPIO and Pin Mux/Config) - -The Pin Function Controller (PFC) is a Pin Mux/Config controller. On SH73A0, -R8A73A4 and R8A7740 it also acts as a GPIO controller. - - -Pin Control ------------ - -Required Properties: - - - compatible: should be one of the following. - - "renesas,pfc-emev2": for EMEV2 (EMMA Mobile EV2) compatible pin-controller. - - "renesas,pfc-r8a73a4": for R8A73A4 (R-Mobile APE6) compatible pin-controller. - - "renesas,pfc-r8a7740": for R8A7740 (R-Mobile A1) compatible pin-controller. - - "renesas,pfc-r8a7742": for R8A7742 (RZ/G1H) compatible pin-controller. - - "renesas,pfc-r8a7743": for R8A7743 (RZ/G1M) compatible pin-controller. - - "renesas,pfc-r8a7744": for R8A7744 (RZ/G1N) compatible pin-controller. - - "renesas,pfc-r8a7745": for R8A7745 (RZ/G1E) compatible pin-controller. - - "renesas,pfc-r8a77470": for R8A77470 (RZ/G1C) compatible pin-controller. - - "renesas,pfc-r8a774a1": for R8A774A1 (RZ/G2M) compatible pin-controller. - - "renesas,pfc-r8a774b1": for R8A774B1 (RZ/G2N) compatible pin-controller. - - "renesas,pfc-r8a774c0": for R8A774C0 (RZ/G2E) compatible pin-controller. - - "renesas,pfc-r8a774e1": for R8A774E1 (RZ/G2H) compatible pin-controller. - - "renesas,pfc-r8a7778": for R8A7778 (R-Car M1) compatible pin-controller. - - "renesas,pfc-r8a7779": for R8A7779 (R-Car H1) compatible pin-controller. - - "renesas,pfc-r8a7790": for R8A7790 (R-Car H2) compatible pin-controller. - - "renesas,pfc-r8a7791": for R8A7791 (R-Car M2-W) compatible pin-controller. - - "renesas,pfc-r8a7792": for R8A7792 (R-Car V2H) compatible pin-controller. - - "renesas,pfc-r8a7793": for R8A7793 (R-Car M2-N) compatible pin-controller. - - "renesas,pfc-r8a7794": for R8A7794 (R-Car E2) compatible pin-controller. - - "renesas,pfc-r8a7795": for R8A7795 (R-Car H3) compatible pin-controller. - - "renesas,pfc-r8a7796": for R8A77960 (R-Car M3-W) compatible pin-controller. - - "renesas,pfc-r8a77961": for R8A77961 (R-Car M3-W+) compatible pin-controller. - - "renesas,pfc-r8a77965": for R8A77965 (R-Car M3-N) compatible pin-controller. - - "renesas,pfc-r8a77970": for R8A77970 (R-Car V3M) compatible pin-controller. - - "renesas,pfc-r8a77980": for R8A77980 (R-Car V3H) compatible pin-controller. - - "renesas,pfc-r8a77990": for R8A77990 (R-Car E3) compatible pin-controller. - - "renesas,pfc-r8a77995": for R8A77995 (R-Car D3) compatible pin-controller. - - "renesas,pfc-sh73a0": for SH73A0 (SH-Mobile AG5) compatible pin-controller. - - - reg: Base address and length of each memory resource used by the pin - controller hardware module. - -Optional properties: - - - #gpio-range-cells: Mandatory when the PFC doesn't handle GPIO, forbidden - otherwise. Should be 3. - - - interrupts-extended: Specify the interrupts associated with external - IRQ pins. This property is mandatory when the PFC handles GPIOs and - forbidden otherwise. When specified, it must contain one interrupt per - external IRQ, sorted by external IRQ number. - -The PFC node also acts as a container for pin configuration nodes. Please refer -to pinctrl-bindings.txt in this directory for the definition of the term "pin -configuration node" and for the common pinctrl bindings used by client devices. - -Each pin configuration node represents a desired configuration for a pin, a -pin group, or a list of pins or pin groups. The configuration can include the -function to select on those pin(s) and pin configuration parameters (such as -pull-up and pull-down). - -Pin configuration nodes contain pin configuration properties, either directly -or grouped in child subnodes. Both pin muxing and configuration parameters can -be grouped in that way and referenced as a single pin configuration node by -client devices. - -A configuration node or subnode must reference at least one pin (through the -pins or pin groups properties) and contain at least a function or one -configuration parameter. When the function is present only pin groups can be -used to reference pins. - -All pin configuration nodes and subnodes names are ignored. All of those nodes -are parsed through phandles and processed purely based on their content. - -Pin Configuration Node Properties: - -- pins : An array of strings, each string containing the name of a pin. -- groups : An array of strings, each string containing the name of a pin - group. - -- function: A string containing the name of the function to mux to the pin - group(s) specified by the groups property. - - Valid values for pin, group and function names can be found in the group and - function arrays of the PFC data file corresponding to the SoC - (drivers/pinctrl/sh-pfc/pfc-*.c) - -The pin configuration parameters use the generic pinconf bindings defined in -pinctrl-bindings.txt in this directory. The supported parameters are -bias-disable, bias-pull-up, bias-pull-down, drive-strength and power-source. For -pins that have a configurable I/O voltage, the power-source value should be the -nominal I/O voltage in millivolts. - - -GPIO ----- - -On SH73A0, R8A73A4 and R8A7740 the PFC node is also a GPIO controller node. - -Required Properties: - - - gpio-controller: Marks the device node as a gpio controller. - - - #gpio-cells: Should be 2. The first cell is the GPIO number and the second - cell specifies GPIO flags, as defined in . Only the - GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW flags are supported. - -The syntax of the gpio specifier used by client nodes should be the following -with values derived from the SoC user manual. - - <[phandle of the gpio controller node] - [pin number within the gpio controller] - [flags]> - -On other mach-shmobile platforms GPIO is handled by the gpio-rcar driver. -Please refer to Documentation/devicetree/bindings/gpio/renesas,rcar-gpio.yaml -for documentation of the GPIO device tree bindings on those platforms. - - -Examples --------- - -Example 1: SH73A0 (SH-Mobile AG5) pin controller node - - pfc: pin-controller@e6050000 { - compatible = "renesas,pfc-sh73a0"; - reg = <0xe6050000 0x8000>, - <0xe605801c 0x1c>; - gpio-controller; - #gpio-cells = <2>; - interrupts-extended = - <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, - <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, - <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, - <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, - <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, - <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, - <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, - <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; - }; - -Example 2: A GPIO LED node that references a GPIO - - #include - - leds { - compatible = "gpio-leds"; - led1 { - gpios = <&pfc 20 GPIO_ACTIVE_LOW>; - }; - }; - -Example 3: KZM-A9-GT (SH-Mobile AG5) default pin state hog and pin control maps - for the MMCIF and SCIFA4 devices - - &pfc { - pinctrl-0 = <&scifa4_pins>; - pinctrl-names = "default"; - - mmcif_pins: mmcif { - mux { - groups = "mmc0_data8_0", "mmc0_ctrl_0"; - function = "mmc0"; - }; - cfg { - groups = "mmc0_data8_0"; - pins = "PORT279"; - bias-pull-up; - }; - }; - - scifa4_pins: scifa4 { - groups = "scifa4_data", "scifa4_ctrl"; - function = "scifa4"; - }; - }; - -Example 4: KZM-A9-GT (SH-Mobile AG5) default pin state for the MMCIF device - - &mmcif { - pinctrl-0 = <&mmcif_pins>; - pinctrl-names = "default"; - - bus-width = <8>; - vmmc-supply = <®_1p8v>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml new file mode 100644 index 000000000000..4efe117550bd --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,pfc.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,pfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas Pin Function Controller (GPIO and Pin Mux/Config) + +maintainers: + - Geert Uytterhoeven + +description: + The Pin Function Controller (PFC) is a Pin Mux/Config controller. + On SH/R-Mobile SoCs it also acts as a GPIO controller. + +properties: + compatible: + enum: + - renesas,pfc-emev2 # EMMA Mobile EV2 + - renesas,pfc-r8a73a4 # R-Mobile APE6 + - renesas,pfc-r8a7740 # R-Mobile A1 + - renesas,pfc-r8a7742 # RZ/G1H + - renesas,pfc-r8a7743 # RZ/G1M + - renesas,pfc-r8a7744 # RZ/G1N + - renesas,pfc-r8a7745 # RZ/G1E + - renesas,pfc-r8a77470 # RZ/G1C + - renesas,pfc-r8a774a1 # RZ/G2M + - renesas,pfc-r8a774b1 # RZ/G2N + - renesas,pfc-r8a774c0 # RZ/G2E + - renesas,pfc-r8a774e1 # RZ/G2H + - renesas,pfc-r8a7778 # R-Car M1 + - renesas,pfc-r8a7779 # R-Car H1 + - renesas,pfc-r8a7790 # R-Car H2 + - renesas,pfc-r8a7791 # R-Car M2-W + - renesas,pfc-r8a7792 # R-Car V2H + - renesas,pfc-r8a7793 # R-Car M2-N + - renesas,pfc-r8a7794 # R-Car E2 + - renesas,pfc-r8a7795 # R-Car H3 + - renesas,pfc-r8a7796 # R-Car M3-W + - renesas,pfc-r8a77961 # R-Car M3-W+ + - renesas,pfc-r8a77965 # R-Car M3-N + - renesas,pfc-r8a77970 # R-Car V3M + - renesas,pfc-r8a77980 # R-Car V3H + - renesas,pfc-r8a77990 # R-Car E3 + - renesas,pfc-r8a77995 # R-Car D3 + - renesas,pfc-sh73a0 # SH-Mobile AG5 + + reg: + minItems: 1 + maxItems: 2 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + minItems: 1 + maxItems: 16 + + interrupts-extended: + minItems: 32 + maxItems: 64 + description: + Specify the interrupts associated with external IRQ pins on SoCs where + the PFC acts as a GPIO controller. It must contain one interrupt per + external IRQ, sorted by external IRQ number. + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + +if: + properties: + compatible: + items: + enum: + - renesas,pfc-r8a73a4 + - renesas,pfc-r8a7740 + - renesas,pfc-sh73a0 +then: + required: + - interrupts-extended + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - power-domains + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + Pin controller client devices use pin configuration subnodes (children + and grandchildren) for desired pin configuration. + Client device subnodes use below standard properties. + + properties: + phandle: true + function: true + groups: true + pins: true + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: + enum: [ 3, 6, 9, 12, 15, 18, 21, 24 ] # Superset of supported values + power-source: + enum: [ 1800, 3300 ] + gpio-hog: true + gpios: true + input: true + output-high: true + output-low: true + + additionalProperties: false + + - type: object + properties: + phandle: true + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + +examples: + - | + pfc: pinctrl@e6050000 { + compatible = "renesas,pfc-r8a7740"; + reg = <0xe6050000 0x8000>, + <0xe605800c 0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pfc 0 0 212>; + interrupts-extended = + <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, + <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, + <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, + <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, + <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, + <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, + <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, + <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; + power-domains = <&pd_c5>; + + lcd0_mux { + /* DBGMD/LCDC0/FSIA MUX */ + gpio-hog; + gpios = <176 0>; + output-high; + }; + }; + + - | + pinctrl@e6060000 { + compatible = "renesas,pfc-r8a7795"; + reg = <0xe6060000 0x50c>; + + avb_pins: avb { + mux { + groups = "avb_link", "avb_mdio", "avb_mii"; + function = "avb"; + }; + + pins_mdio { + groups = "avb_mdio"; + drive-strength = <24>; + }; + + pins_mii_tx { + pins = "PIN_AVB_TX_CTL", "PIN_AVB_TXC", + "PIN_AVB_TD0", "PIN_AVB_TD1", "PIN_AVB_TD2", + "PIN_AVB_TD3"; + drive-strength = <12>; + }; + }; + + keys_pins: keys { + pins = "GP_5_17", "GP_5_20", "GP_5_22", "GP_2_1"; + bias-pull-up; + }; + + sdhi0_pins: sd0 { + groups = "sdhi0_data4", "sdhi0_ctrl"; + function = "sdhi0"; + power-source = <3300>; + }; + }; From aa5b0f7e0f7e8a05c5bd9bfab33d98699735762f Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 24 Aug 2020 14:49:40 +0900 Subject: [PATCH 04/14] pinctrl: sh-pfc: Tidy up Emma Mobile EV2 It is "Emma Mobile EV2" not "AV2". This patch tidies it up. Reported-by: Geert Uytterhoeven Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87lfi4y4re.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 7fdc7ed8bd2e..8b2b1e1a9047 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -66,7 +66,7 @@ config PINCTRL_SH_FUNC_GPIO This enables legacy function GPIOs for SH platforms config PINCTRL_PFC_EMEV2 - bool "Emma Mobile AV2 pin control support" if COMPILE_TEST + bool "Emma Mobile EV2 pin control support" if COMPILE_TEST config PINCTRL_PFC_R8A73A4 bool "R-Mobile APE6 pin control support" if COMPILE_TEST From af028ecd546a71b4d3937b63e1b39707ef9c3b17 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 24 Aug 2020 14:49:48 +0900 Subject: [PATCH 05/14] pinctrl: sh-pfc: Collect Renesas related CONFIGs in one place Renesas related pinctrl CONFIGs are located in many places, which is confusing. This patch collects them into the same place, grouped in a new "Renesas pinctrl drivers" menu. This patch also moves pinctrl-rz{a1,a2,n1}.c into the sh-pfc folder. Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87k0xoy4r7.wl-kuninori.morimoto.gx@renesas.com [geert: Update path in MAINTAINERS] Signed-off-by: Geert Uytterhoeven --- MAINTAINERS | 1 - drivers/pinctrl/Kconfig | 32 ------------------ drivers/pinctrl/Makefile | 3 -- drivers/pinctrl/sh-pfc/Kconfig | 36 +++++++++++++++++++++ drivers/pinctrl/sh-pfc/Makefile | 4 +++ drivers/pinctrl/{ => sh-pfc}/pinctrl-rza1.c | 8 ++--- drivers/pinctrl/{ => sh-pfc}/pinctrl-rza2.c | 4 +-- drivers/pinctrl/{ => sh-pfc}/pinctrl-rzn1.c | 6 ++-- 8 files changed, 49 insertions(+), 45 deletions(-) rename drivers/pinctrl/{ => sh-pfc}/pinctrl-rza1.c (99%) rename drivers/pinctrl/{ => sh-pfc}/pinctrl-rza2.c (99%) rename drivers/pinctrl/{ => sh-pfc}/pinctrl-rzn1.c (99%) diff --git a/MAINTAINERS b/MAINTAINERS index deaafb617361..73242e16e327 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13690,7 +13690,6 @@ L: linux-renesas-soc@vger.kernel.org S: Supported T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc F: Documentation/devicetree/bindings/pinctrl/renesas,* -F: drivers/pinctrl/pinctrl-rz* F: drivers/pinctrl/sh-pfc/ PIN CONTROLLER - SAMSUNG diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 8828613c4e0e..f63c5a04a3f7 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -213,38 +213,6 @@ config PINCTRL_ROCKCHIP select GENERIC_IRQ_CHIP select MFD_SYSCON -config PINCTRL_RZA1 - bool "Renesas RZ/A1 gpio and pinctrl driver" - depends on OF - depends on ARCH_R7S72100 || COMPILE_TEST - select GPIOLIB - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF - help - This selects pinctrl driver for Renesas RZ/A1 platforms. - -config PINCTRL_RZA2 - bool "Renesas RZ/A2 gpio and pinctrl driver" - depends on OF - depends on ARCH_R7S9210 || COMPILE_TEST - select GPIOLIB - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF - help - This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. - -config PINCTRL_RZN1 - bool "Renesas RZ/N1 pinctrl driver" - depends on OF - depends on ARCH_RZN1 || COMPILE_TEST - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF - help - This selects pinctrl driver for Renesas RZ/N1 devices. - config PINCTRL_SINGLE tristate "One-register-per-pin type device tree based pinctrl driver" depends on OF diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 1731b2154df9..1da9f28aecbd 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -30,9 +30,6 @@ obj-$(CONFIG_PINCTRL_PALMAS) += pinctrl-palmas.o obj-$(CONFIG_PINCTRL_PIC32) += pinctrl-pic32.o obj-$(CONFIG_PINCTRL_PISTACHIO) += pinctrl-pistachio.o obj-$(CONFIG_PINCTRL_ROCKCHIP) += pinctrl-rockchip.o -obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o -obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o -obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o obj-$(CONFIG_PINCTRL_SIRF) += sirf/ obj-$(CONFIG_PINCTRL_SX150X) += pinctrl-sx150x.o diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 8b2b1e1a9047..ff10bb2ed497 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -3,6 +3,8 @@ # Renesas SH and SH Mobile PINCTRL drivers # +menu "Renesas pinctrl drivers" + config PINCTRL_SH_PFC bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH) default y if ARCH_RENESAS || SUPERH @@ -53,6 +55,38 @@ config PINCTRL_SH_PFC help This enables pin control drivers for Renesas SuperH and ARM platforms +config PINCTRL_RZA1 + bool "RZ/A1 gpio and pinctrl driver" + depends on OF + depends on ARCH_R7S72100 || COMPILE_TEST + select GPIOLIB + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help + This selects pinctrl driver for Renesas RZ/A1 platforms. + +config PINCTRL_RZA2 + bool "RZ/A2 gpio and pinctrl driver" + depends on OF + depends on ARCH_R7S9210 || COMPILE_TEST + select GPIOLIB + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help + This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. + +config PINCTRL_RZN1 + bool "RZ/N1 pinctrl driver" + depends on OF + depends on ARCH_RZN1 || COMPILE_TEST + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help + This selects pinctrl driver for Renesas RZ/N1 devices. + config PINCTRL_SH_PFC_GPIO select GPIOLIB bool @@ -203,3 +237,5 @@ config PINCTRL_PFC_SH7786 config PINCTRL_PFC_SHX3 bool "SH-X3 pin control support" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO + +endmenu diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile index 7bb99187cd8e..0b5640cf457b 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/sh-pfc/Makefile @@ -43,6 +43,10 @@ obj-$(CONFIG_PINCTRL_PFC_SH7785) += pfc-sh7785.o obj-$(CONFIG_PINCTRL_PFC_SH7786) += pfc-sh7786.o obj-$(CONFIG_PINCTRL_PFC_SHX3) += pfc-shx3.o +obj-$(CONFIG_PINCTRL_RZA1) += pinctrl-rza1.o +obj-$(CONFIG_PINCTRL_RZA2) += pinctrl-rza2.o +obj-$(CONFIG_PINCTRL_RZN1) += pinctrl-rzn1.o + ifeq ($(CONFIG_COMPILE_TEST),y) CFLAGS_pfc-sh7203.o += -I$(srctree)/arch/sh/include/cpu-sh2a CFLAGS_pfc-sh7264.o += -I$(srctree)/arch/sh/include/cpu-sh2a diff --git a/drivers/pinctrl/pinctrl-rza1.c b/drivers/pinctrl/sh-pfc/pinctrl-rza1.c similarity index 99% rename from drivers/pinctrl/pinctrl-rza1.c rename to drivers/pinctrl/sh-pfc/pinctrl-rza1.c index 511f232ab7bc..a0cb586a46b7 100644 --- a/drivers/pinctrl/pinctrl-rza1.c +++ b/drivers/pinctrl/sh-pfc/pinctrl-rza1.c @@ -26,10 +26,10 @@ #include #include -#include "core.h" -#include "devicetree.h" -#include "pinconf.h" -#include "pinmux.h" +#include "../core.h" +#include "../devicetree.h" +#include "../pinconf.h" +#include "../pinmux.h" #define DRIVER_NAME "pinctrl-rza1" diff --git a/drivers/pinctrl/pinctrl-rza2.c b/drivers/pinctrl/sh-pfc/pinctrl-rza2.c similarity index 99% rename from drivers/pinctrl/pinctrl-rza2.c rename to drivers/pinctrl/sh-pfc/pinctrl-rza2.c index c5bf98c86b2b..32829eb9656c 100644 --- a/drivers/pinctrl/pinctrl-rza2.c +++ b/drivers/pinctrl/sh-pfc/pinctrl-rza2.c @@ -17,8 +17,8 @@ #include #include -#include "core.h" -#include "pinmux.h" +#include "../core.h" +#include "../pinmux.h" #define DRIVER_NAME "pinctrl-rza2" diff --git a/drivers/pinctrl/pinctrl-rzn1.c b/drivers/pinctrl/sh-pfc/pinctrl-rzn1.c similarity index 99% rename from drivers/pinctrl/pinctrl-rzn1.c rename to drivers/pinctrl/sh-pfc/pinctrl-rzn1.c index 39538d40dbf3..ef5fb25b6016 100644 --- a/drivers/pinctrl/pinctrl-rzn1.c +++ b/drivers/pinctrl/sh-pfc/pinctrl-rzn1.c @@ -17,9 +17,9 @@ #include #include #include -#include "core.h" -#include "pinconf.h" -#include "pinctrl-utils.h" +#include "../core.h" +#include "../pinconf.h" +#include "../pinctrl-utils.h" /* Field positions and masks in the pinmux registers */ #define RZN1_L1_PIN_DRIVE_STRENGTH 10 From 16261dcd7cd17409b3f1235b0b89a805338eac28 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 24 Aug 2020 14:49:52 +0900 Subject: [PATCH 06/14] pinctrl: sh-pfc: Align driver description title Now, Renesas Pin Control drivers are under menu, but current descriptions are not aligned. This patch aligns them. - RZ/A2 gpio and pinctrl driver - RZ/N1 pinctrl driver - Emma Mobile EV2 pin control support - R-Mobile APE6 pin control support - R-Mobile A1 pin control support - RZ/G1H pin control support - RZ/G1M pin control support + pin control support for RZ/A2 + pin control support for RZ/N1 + pin control support for Emma Mobile EV2 + pin control support for R-Mobile APE6 + pin control support for R-Mobile A1 + pin control support for RZ/G1H + pin control support for RZ/G1M Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87imd8y4r2.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/Kconfig | 88 +++++++++++++++++----------------- 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index ff10bb2ed497..86e4d062ef99 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -56,7 +56,7 @@ config PINCTRL_SH_PFC This enables pin control drivers for Renesas SuperH and ARM platforms config PINCTRL_RZA1 - bool "RZ/A1 gpio and pinctrl driver" + bool "pin control support for RZ/A1" depends on OF depends on ARCH_R7S72100 || COMPILE_TEST select GPIOLIB @@ -67,7 +67,7 @@ config PINCTRL_RZA1 This selects pinctrl driver for Renesas RZ/A1 platforms. config PINCTRL_RZA2 - bool "RZ/A2 gpio and pinctrl driver" + bool "pin control support for RZ/A2" depends on OF depends on ARCH_R7S9210 || COMPILE_TEST select GPIOLIB @@ -78,7 +78,7 @@ config PINCTRL_RZA2 This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. config PINCTRL_RZN1 - bool "RZ/N1 pinctrl driver" + bool "pin control support for RZ/N1" depends on OF depends on ARCH_RZN1 || COMPILE_TEST select GENERIC_PINCTRL_GROUPS @@ -100,142 +100,142 @@ config PINCTRL_SH_FUNC_GPIO This enables legacy function GPIOs for SH platforms config PINCTRL_PFC_EMEV2 - bool "Emma Mobile EV2 pin control support" if COMPILE_TEST + bool "pin control support for Emma Mobile EV2" if COMPILE_TEST config PINCTRL_PFC_R8A73A4 - bool "R-Mobile APE6 pin control support" if COMPILE_TEST + bool "pin control support for R-Mobile APE6" if COMPILE_TEST select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_R8A7740 - bool "R-Mobile A1 pin control support" if COMPILE_TEST + bool "pin control support for R-Mobile A1" if COMPILE_TEST select PINCTRL_SH_PFC_GPIO config PINCTRL_PFC_R8A7742 - bool "RZ/G1H pin control support" if COMPILE_TEST + bool "pin control support for RZ/G1H" if COMPILE_TEST config PINCTRL_PFC_R8A7743 - bool "RZ/G1M pin control support" if COMPILE_TEST + bool "pin control support for RZ/G1M" if COMPILE_TEST config PINCTRL_PFC_R8A7744 - bool "RZ/G1N pin control support" if COMPILE_TEST + bool "pin control support for RZ/G1N" if COMPILE_TEST config PINCTRL_PFC_R8A7745 - bool "RZ/G1E pin control support" if COMPILE_TEST + bool "pin control support for RZ/G1E" if COMPILE_TEST config PINCTRL_PFC_R8A77470 - bool "RZ/G1C pin control support" if COMPILE_TEST + bool "pin control support for RZ/G1C" if COMPILE_TEST config PINCTRL_PFC_R8A774A1 - bool "RZ/G2M pin control support" if COMPILE_TEST + bool "pin control support for RZ/G2M" if COMPILE_TEST config PINCTRL_PFC_R8A774B1 - bool "RZ/G2N pin control support" if COMPILE_TEST + bool "pin control support for RZ/G2N" if COMPILE_TEST config PINCTRL_PFC_R8A774C0 - bool "RZ/G2E pin control support" if COMPILE_TEST + bool "pin control support for RZ/G2E" if COMPILE_TEST config PINCTRL_PFC_R8A774E1 - bool "RZ/G2H pin control support" if COMPILE_TEST + bool "pin control support for RZ/G2H" if COMPILE_TEST config PINCTRL_PFC_R8A7778 - bool "R-Car M1A pin control support" if COMPILE_TEST + bool "pin control support for R-Car M1A" if COMPILE_TEST config PINCTRL_PFC_R8A7779 - bool "R-Car H1 pin control support" if COMPILE_TEST + bool "pin control support for R-Car H1" if COMPILE_TEST config PINCTRL_PFC_R8A7790 - bool "R-Car H2 pin control support" if COMPILE_TEST + bool "pin control support for R-Car H2" if COMPILE_TEST config PINCTRL_PFC_R8A7791 - bool "R-Car M2-W pin control support" if COMPILE_TEST + bool "pin control support for R-Car M2-W" if COMPILE_TEST config PINCTRL_PFC_R8A7792 - bool "R-Car V2H pin control support" if COMPILE_TEST + bool "pin control support for R-Car V2H" if COMPILE_TEST config PINCTRL_PFC_R8A7793 - bool "R-Car M2-N pin control support" if COMPILE_TEST + bool "pin control support for R-Car M2-N" if COMPILE_TEST config PINCTRL_PFC_R8A7794 - bool "R-Car E2 pin control support" if COMPILE_TEST + bool "pin control support for R-Car E2" if COMPILE_TEST config PINCTRL_PFC_R8A77950 - bool "R-Car H3 ES1.x pin control support" if COMPILE_TEST + bool "pin control support for R-Car H3 ES1.x" if COMPILE_TEST config PINCTRL_PFC_R8A77951 - bool "R-Car H3 ES2.0+ pin control support" if COMPILE_TEST + bool "pin control support for R-Car H3 ES2.0+" if COMPILE_TEST config PINCTRL_PFC_R8A77960 - bool "R-Car M3-W pin control support" if COMPILE_TEST + bool "pin control support for R-Car M3-W" if COMPILE_TEST config PINCTRL_PFC_R8A77961 - bool "R-Car M3-W+ pin control support" if COMPILE_TEST + bool "pin control support for R-Car M3-W+" if COMPILE_TEST config PINCTRL_PFC_R8A77965 - bool "R-Car M3-N pin control support" if COMPILE_TEST + bool "pin control support for R-Car M3-N" if COMPILE_TEST config PINCTRL_PFC_R8A77970 - bool "R-Car V3M pin control support" if COMPILE_TEST + bool "pin control support for R-Car V3M" if COMPILE_TEST config PINCTRL_PFC_R8A77980 - bool "R-Car V3H pin control support" if COMPILE_TEST + bool "pin control support for R-Car V3H" if COMPILE_TEST config PINCTRL_PFC_R8A77990 - bool "R-Car E3 pin control support" if COMPILE_TEST + bool "pin control support for R-Car E3" if COMPILE_TEST config PINCTRL_PFC_R8A77995 - bool "R-Car D3 pin control support" if COMPILE_TEST + bool "pin control support for R-Car D3" if COMPILE_TEST config PINCTRL_PFC_SH7203 - bool "SH7203 pin control support" if COMPILE_TEST + bool "pin control support for SH7203" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7264 - bool "SH7264 pin control support" if COMPILE_TEST + bool "pin control support for SH7264" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7269 - bool "SH7269 pin control support" if COMPILE_TEST + bool "pin control support for SH7269" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH73A0 - bool "SH-Mobile AG5 pin control support" if COMPILE_TEST + bool "pin control support for SH-Mobile AG5" if COMPILE_TEST select PINCTRL_SH_PFC_GPIO select REGULATOR config PINCTRL_PFC_SH7720 - bool "SH7720 pin control support" if COMPILE_TEST + bool "pin control support for SH7720" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7722 - bool "SH7722 pin control support" if COMPILE_TEST + bool "pin control support for SH7722" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7723 - bool "SH-Mobile R2 pin control support" if COMPILE_TEST + bool "pin control support for SH-Mobile R2" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7724 - bool "SH-Mobile R2R pin control support" if COMPILE_TEST + bool "pin control support for SH-Mobile R2R" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7734 - bool "SH7734 pin control support" if COMPILE_TEST + bool "pin control support for SH7734" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7757 - bool "SH7757 pin control support" if COMPILE_TEST + bool "pin control support for SH7757" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7785 - bool "SH7785 pin control support" if COMPILE_TEST + bool "pin control support for SH7785" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SH7786 - bool "SH7786 pin control support" if COMPILE_TEST + bool "pin control support for SH7786" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO config PINCTRL_PFC_SHX3 - bool "SH-X3 pin control support" if COMPILE_TEST + bool "pin control support for SH-X3" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO endmenu From d89a08f52b0dd30d8e13c91886788cd42333dba7 Mon Sep 17 00:00:00 2001 From: Kuninori Morimoto Date: Mon, 24 Aug 2020 14:49:56 +0900 Subject: [PATCH 07/14] pinctrl: sh-pfc: Tidy up driver description title Sort each driver by description title in alphabetical order. Signed-off-by: Kuninori Morimoto Link: https://lore.kernel.org/r/87h7ssy4qy.wl-kuninori.morimoto.gx@renesas.com Signed-off-by: Geert Uytterhoeven --- drivers/pinctrl/sh-pfc/Kconfig | 202 ++++++++++++++++----------------- 1 file changed, 101 insertions(+), 101 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 86e4d062ef99..2cff88684f36 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -55,6 +55,77 @@ config PINCTRL_SH_PFC help This enables pin control drivers for Renesas SuperH and ARM platforms +config PINCTRL_SH_PFC_GPIO + select GPIOLIB + bool + help + This enables pin control and GPIO drivers for SH/SH Mobile platforms + +config PINCTRL_SH_FUNC_GPIO + select PINCTRL_SH_PFC_GPIO + bool + help + This enables legacy function GPIOs for SH platforms + +config PINCTRL_PFC_EMEV2 + bool "pin control support for Emma Mobile EV2" if COMPILE_TEST + +config PINCTRL_PFC_R8A77995 + bool "pin control support for R-Car D3" if COMPILE_TEST + +config PINCTRL_PFC_R8A7794 + bool "pin control support for R-Car E2" if COMPILE_TEST + +config PINCTRL_PFC_R8A77990 + bool "pin control support for R-Car E3" if COMPILE_TEST + +config PINCTRL_PFC_R8A7779 + bool "pin control support for R-Car H1" if COMPILE_TEST + +config PINCTRL_PFC_R8A7790 + bool "pin control support for R-Car H2" if COMPILE_TEST + +config PINCTRL_PFC_R8A77950 + bool "pin control support for R-Car H3 ES1.x" if COMPILE_TEST + +config PINCTRL_PFC_R8A77951 + bool "pin control support for R-Car H3 ES2.0+" if COMPILE_TEST + +config PINCTRL_PFC_R8A7778 + bool "pin control support for R-Car M1A" if COMPILE_TEST + +config PINCTRL_PFC_R8A7793 + bool "pin control support for R-Car M2-N" if COMPILE_TEST + +config PINCTRL_PFC_R8A7791 + bool "pin control support for R-Car M2-W" if COMPILE_TEST + +config PINCTRL_PFC_R8A77965 + bool "pin control support for R-Car M3-N" if COMPILE_TEST + +config PINCTRL_PFC_R8A77960 + bool "pin control support for R-Car M3-W" if COMPILE_TEST + +config PINCTRL_PFC_R8A77961 + bool "pin control support for R-Car M3-W+" if COMPILE_TEST + +config PINCTRL_PFC_R8A7792 + bool "pin control support for R-Car V2H" if COMPILE_TEST + +config PINCTRL_PFC_R8A77980 + bool "pin control support for R-Car V3H" if COMPILE_TEST + +config PINCTRL_PFC_R8A77970 + bool "pin control support for R-Car V3M" if COMPILE_TEST + +config PINCTRL_PFC_R8A7740 + bool "pin control support for R-Mobile A1" if COMPILE_TEST + select PINCTRL_SH_PFC_GPIO + +config PINCTRL_PFC_R8A73A4 + bool "pin control support for R-Mobile APE6" if COMPILE_TEST + select PINCTRL_SH_PFC_GPIO + config PINCTRL_RZA1 bool "pin control support for RZ/A1" depends on OF @@ -77,38 +148,11 @@ config PINCTRL_RZA2 help This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. -config PINCTRL_RZN1 - bool "pin control support for RZ/N1" - depends on OF - depends on ARCH_RZN1 || COMPILE_TEST - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF - help - This selects pinctrl driver for Renesas RZ/N1 devices. +config PINCTRL_PFC_R8A77470 + bool "pin control support for RZ/G1C" if COMPILE_TEST -config PINCTRL_SH_PFC_GPIO - select GPIOLIB - bool - help - This enables pin control and GPIO drivers for SH/SH Mobile platforms - -config PINCTRL_SH_FUNC_GPIO - select PINCTRL_SH_PFC_GPIO - bool - help - This enables legacy function GPIOs for SH platforms - -config PINCTRL_PFC_EMEV2 - bool "pin control support for Emma Mobile EV2" if COMPILE_TEST - -config PINCTRL_PFC_R8A73A4 - bool "pin control support for R-Mobile APE6" if COMPILE_TEST - select PINCTRL_SH_PFC_GPIO - -config PINCTRL_PFC_R8A7740 - bool "pin control support for R-Mobile A1" if COMPILE_TEST - select PINCTRL_SH_PFC_GPIO +config PINCTRL_PFC_R8A7745 + bool "pin control support for RZ/G1E" if COMPILE_TEST config PINCTRL_PFC_R8A7742 bool "pin control support for RZ/G1H" if COMPILE_TEST @@ -119,11 +163,11 @@ config PINCTRL_PFC_R8A7743 config PINCTRL_PFC_R8A7744 bool "pin control support for RZ/G1N" if COMPILE_TEST -config PINCTRL_PFC_R8A7745 - bool "pin control support for RZ/G1E" if COMPILE_TEST +config PINCTRL_PFC_R8A774C0 + bool "pin control support for RZ/G2E" if COMPILE_TEST -config PINCTRL_PFC_R8A77470 - bool "pin control support for RZ/G1C" if COMPILE_TEST +config PINCTRL_PFC_R8A774E1 + bool "pin control support for RZ/G2H" if COMPILE_TEST config PINCTRL_PFC_R8A774A1 bool "pin control support for RZ/G2M" if COMPILE_TEST @@ -131,59 +175,15 @@ config PINCTRL_PFC_R8A774A1 config PINCTRL_PFC_R8A774B1 bool "pin control support for RZ/G2N" if COMPILE_TEST -config PINCTRL_PFC_R8A774C0 - bool "pin control support for RZ/G2E" if COMPILE_TEST - -config PINCTRL_PFC_R8A774E1 - bool "pin control support for RZ/G2H" if COMPILE_TEST - -config PINCTRL_PFC_R8A7778 - bool "pin control support for R-Car M1A" if COMPILE_TEST - -config PINCTRL_PFC_R8A7779 - bool "pin control support for R-Car H1" if COMPILE_TEST - -config PINCTRL_PFC_R8A7790 - bool "pin control support for R-Car H2" if COMPILE_TEST - -config PINCTRL_PFC_R8A7791 - bool "pin control support for R-Car M2-W" if COMPILE_TEST - -config PINCTRL_PFC_R8A7792 - bool "pin control support for R-Car V2H" if COMPILE_TEST - -config PINCTRL_PFC_R8A7793 - bool "pin control support for R-Car M2-N" if COMPILE_TEST - -config PINCTRL_PFC_R8A7794 - bool "pin control support for R-Car E2" if COMPILE_TEST - -config PINCTRL_PFC_R8A77950 - bool "pin control support for R-Car H3 ES1.x" if COMPILE_TEST - -config PINCTRL_PFC_R8A77951 - bool "pin control support for R-Car H3 ES2.0+" if COMPILE_TEST - -config PINCTRL_PFC_R8A77960 - bool "pin control support for R-Car M3-W" if COMPILE_TEST - -config PINCTRL_PFC_R8A77961 - bool "pin control support for R-Car M3-W+" if COMPILE_TEST - -config PINCTRL_PFC_R8A77965 - bool "pin control support for R-Car M3-N" if COMPILE_TEST - -config PINCTRL_PFC_R8A77970 - bool "pin control support for R-Car V3M" if COMPILE_TEST - -config PINCTRL_PFC_R8A77980 - bool "pin control support for R-Car V3H" if COMPILE_TEST - -config PINCTRL_PFC_R8A77990 - bool "pin control support for R-Car E3" if COMPILE_TEST - -config PINCTRL_PFC_R8A77995 - bool "pin control support for R-Car D3" if COMPILE_TEST +config PINCTRL_RZN1 + bool "pin control support for RZ/N1" + depends on OF + depends on ARCH_RZN1 || COMPILE_TEST + select GENERIC_PINCTRL_GROUPS + select GENERIC_PINMUX_FUNCTIONS + select GENERIC_PINCONF + help + This selects pinctrl driver for Renesas RZ/N1 devices. config PINCTRL_PFC_SH7203 bool "pin control support for SH7203" if COMPILE_TEST @@ -197,11 +197,6 @@ config PINCTRL_PFC_SH7269 bool "pin control support for SH7269" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO -config PINCTRL_PFC_SH73A0 - bool "pin control support for SH-Mobile AG5" if COMPILE_TEST - select PINCTRL_SH_PFC_GPIO - select REGULATOR - config PINCTRL_PFC_SH7720 bool "pin control support for SH7720" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO @@ -210,14 +205,6 @@ config PINCTRL_PFC_SH7722 bool "pin control support for SH7722" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO -config PINCTRL_PFC_SH7723 - bool "pin control support for SH-Mobile R2" if COMPILE_TEST - select PINCTRL_SH_FUNC_GPIO - -config PINCTRL_PFC_SH7724 - bool "pin control support for SH-Mobile R2R" if COMPILE_TEST - select PINCTRL_SH_FUNC_GPIO - config PINCTRL_PFC_SH7734 bool "pin control support for SH7734" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO @@ -234,6 +221,19 @@ config PINCTRL_PFC_SH7786 bool "pin control support for SH7786" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO +config PINCTRL_PFC_SH73A0 + bool "pin control support for SH-Mobile AG5" if COMPILE_TEST + select PINCTRL_SH_PFC_GPIO + select REGULATOR + +config PINCTRL_PFC_SH7723 + bool "pin control support for SH-Mobile R2" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO + +config PINCTRL_PFC_SH7724 + bool "pin control support for SH-Mobile R2R" if COMPILE_TEST + select PINCTRL_SH_FUNC_GPIO + config PINCTRL_PFC_SHX3 bool "pin control support for SH-X3" if COMPILE_TEST select PINCTRL_SH_FUNC_GPIO From a4eb6afa7c2c3795ec693cd806fd69593c9ecca7 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:14:01 +0200 Subject: [PATCH 08/14] pinctrl: rza1: Switch to using "output-enable" For pins requiring software driven IO output operations, the RZ/A1 Pin Controller uses either the "output-high" or "output-low" DT property to enable the corresponding output buffer. The actual line value doesn't matter, as it is ignored. Commit 425562429d4f3b13 ("pinctrl: generic: Add output-enable property") introduced a new DT property for this specific use case. Update the RZ/A1 Pin Controller DT bindings and driver to use this new property instead. Preserve backwards compatibility with old DTBs in the driver, as this comes at a very small cost. Notes: - The DT binding examples already used the new property, - There are no upstream users of the old properties. Signed-off-by: Geert Uytterhoeven Reviewed-by: Chris Brandt Acked-by: Jacopo Mondi Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200821111401.4021-1-geert+renesas@glider.be --- .../devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt | 5 ++--- drivers/pinctrl/sh-pfc/pinctrl-rza1.c | 3 ++- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt index fd3696eb36bf..38cdd23d3498 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt @@ -117,10 +117,9 @@ function or a GPIO controller alternatively. - input-enable: enable input bufer for pins requiring software driven IO input operations. - - output-high: + - output-enable: enable output buffer for pins requiring software driven IO output - operations. output-low can be used alternatively, as line value is - ignored by the driver. + operations. The hardware reference manual specifies when a pin has to be configured to work in bi-directional mode and when the IO direction has to be specified diff --git a/drivers/pinctrl/sh-pfc/pinctrl-rza1.c b/drivers/pinctrl/sh-pfc/pinctrl-rza1.c index a0cb586a46b7..15dd007700c2 100644 --- a/drivers/pinctrl/sh-pfc/pinctrl-rza1.c +++ b/drivers/pinctrl/sh-pfc/pinctrl-rza1.c @@ -928,7 +928,8 @@ static int rza1_parse_pinmux_node(struct rza1_pinctrl *rza1_pctl, case PIN_CONFIG_INPUT_ENABLE: pinmux_flags |= MUX_FLAGS_SWIO_INPUT; break; - case PIN_CONFIG_OUTPUT: + case PIN_CONFIG_OUTPUT: /* for DT backwards compatibility */ + case PIN_CONFIG_OUTPUT_ENABLE: pinmux_flags |= MUX_FLAGS_SWIO_OUTPUT; default: break; From d4691b7f6231a022f20028ea27b6c49466b2acd6 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:11:27 +0200 Subject: [PATCH 09/14] dt-bindings: pinctrl: renesas,rza2-pinctrl: Fix pin controller node name According to Devicetree Specification v0.2 and later, Section "Generic Names Recommendation", the node name for a pin controller device node should be "pinctrl". Signed-off-by: Geert Uytterhoeven Acked-by: Rob Herring Link: https://lore.kernel.org/r/20200821111127.3771-1-geert+renesas@glider.be --- .../devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml index b7911a994f3a..ce1f7343788f 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza2-pinctrl.yaml @@ -84,7 +84,7 @@ additionalProperties: false examples: - | #include - pinctrl: pin-controller@fcffe000 { + pinctrl: pinctrl@fcffe000 { compatible = "renesas,r7s9210-pinctrl"; reg = <0xfcffe000 0x1000>; From 5398b2fa464722a3bb3cf4c264a19ac765974d98 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:19:56 +0200 Subject: [PATCH 10/14] dt-bindings: pinctrl: rza1: Convert to json-schema Convert the Renesas RZ/A1 combined Pin and GPIO controller Device Tree binding documentation to json-schema. Rename "rza1-pinctrl" to "rza1-ports", to match the compatible value scheme. Use "pinctrl" generic node name. Drop generic and consumer examples, as they do not belong here. Signed-off-by: Geert Uytterhoeven Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200821111956.4989-1-geert+renesas@glider.be --- .../bindings/pinctrl/renesas,rza1-pinctrl.txt | 222 ------------------ .../bindings/pinctrl/renesas,rza1-ports.yaml | 190 +++++++++++++++ 2 files changed, 190 insertions(+), 222 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt deleted file mode 100644 index 38cdd23d3498..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-pinctrl.txt +++ /dev/null @@ -1,222 +0,0 @@ -Renesas RZ/A1 combined Pin and GPIO controller - -The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO controller, -named "Ports" in the hardware reference manual. -Pin multiplexing and GPIO configuration is performed on a per-pin basis -writing configuration values to per-port register sets. -Each "port" features up to 16 pins, each of them configurable for GPIO -function (port mode) or in alternate function mode. -Up to 8 different alternate function modes exist for each single pin. - -Pin controller node -------------------- - -Required properties: - - compatible: should be: - - "renesas,r7s72100-ports": for RZ/A1H - - "renesas,r7s72101-ports", "renesas,r7s72100-ports": for RZ/A1M - - "renesas,r7s72102-ports": for RZ/A1L - - - reg - address base and length of the memory area where the pin controller - hardware is mapped to. - -Example: -Pin controller node for RZ/A1H SoC (r7s72100) - -pinctrl: pin-controller@fcfe3000 { - compatible = "renesas,r7s72100-ports"; - - reg = <0xfcfe3000 0x4230>; -}; - -Sub-nodes ---------- - -The child nodes of the pin controller node describe a pin multiplexing -function or a GPIO controller alternatively. - -- Pin multiplexing sub-nodes: - A pin multiplexing sub-node describes how to configure a set of - (or a single) pin in some desired alternate function mode. - A single sub-node may define several pin configurations. - A few alternate function require special pin configuration flags to be - supplied along with the alternate function configuration number. - The hardware reference manual specifies when a pin function requires - "software IO driven" mode to be specified. To do so use the generic - properties from the header file - to instruct the pin controller to perform the desired pin configuration - operation. - Please refer to pinctrl-bindings.txt to get to know more on generic - pin properties usage. - - The allowed generic formats for a pin multiplexing sub-node are the - following ones: - - node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - node-2 { - sub-node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - sub-node-2 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - ... - - sub-node-n { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - }; - - Use the second format when pins part of the same logical group need to have - different generic pin configuration flags applied. - - Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle - of the most external one. - - Eg. - - client-1 { - ... - pinctrl-0 = <&node-1>; - ... - }; - - client-2 { - ... - pinctrl-0 = <&node-2>; - ... - }; - - Required properties: - - pinmux: - integer array representing pin number and pin multiplexing configuration. - When a pin has to be configured in alternate function mode, use this - property to identify the pin by its global index, and provide its - alternate function configuration number along with it. - When multiple pins are required to be configured as part of the same - alternate function they shall be specified as members of the same - argument list of a single "pinmux" property. - Helper macros to ease assembling the pin index from its position - (port where it sits on and pin number) and alternate function identifier - are provided by the pin controller header file at: - - Integers values in "pinmux" argument list are assembled as: - ((PORT * 16 + PIN) | MUX_FUNC << 16) - - Optional generic properties: - - input-enable: - enable input bufer for pins requiring software driven IO input - operations. - - output-enable: - enable output buffer for pins requiring software driven IO output - operations. - - The hardware reference manual specifies when a pin has to be configured to - work in bi-directional mode and when the IO direction has to be specified - by software. Bi-directional pins are managed by the pin controller driver - internally, while software driven IO direction has to be explicitly - selected when multiple options are available. - - Example: - A serial communication interface with a TX output pin and an RX input pin. - - &pinctrl { - scif2_pins: serial2 { - pinmux = , ; - }; - }; - - Pin #0 on port #3 is configured as alternate function #6. - Pin #2 on port #3 is configured as alternate function #4. - - Example 2: - I2c master: both SDA and SCL pins need bi-directional operations - - &pinctrl { - i2c2_pins: i2c2 { - pinmux = , ; - }; - }; - - Pin #4 on port #1 is configured as alternate function #1. - Pin #5 on port #1 is configured as alternate function #1. - Both need to work in bi-directional mode, the driver manages this internally. - - Example 3: - Multi-function timer input and output compare pins. - Configure TIOC0A as software driven input and TIOC0B as software driven - output. - - &pinctrl { - tioc0_pins: tioc0 { - tioc0_input_pins { - pinumx = ; - input-enable; - }; - - tioc0_output_pins { - pinmux = ; - output-enable; - }; - }; - }; - - &tioc0 { - ... - pinctrl-0 = <&tioc0_pins>; - ... - }; - - Pin #0 on port #4 is configured as alternate function #2 with IO direction - specified by software as input. - Pin #1 on port #4 is configured as alternate function #1 with IO direction - specified by software as output. - -- GPIO controller sub-nodes: - Each port of the r7s72100 pin controller hardware is itself a GPIO controller. - Different SoCs have different numbers of available pins per port, but - generally speaking, each of them can be configured in GPIO ("port") mode - on this hardware. - Describe GPIO controllers using sub-nodes with the following properties. - - Required properties: - - gpio-controller - empty property as defined by the GPIO bindings documentation. - - #gpio-cells - number of cells required to identify and configure a GPIO. - Shall be 2. - - gpio-ranges - Describes a GPIO controller specifying its specific pin base, the pin - base in the global pin numbering space, and the number of controlled - pins, as defined by the GPIO bindings documentation. Refer to - Documentation/devicetree/bindings/gpio/gpio.txt file for a more detailed - description. - - Example: - A GPIO controller node, controlling 16 pins indexed from 0. - The GPIO controller base in the global pin indexing space is pin 48, thus - pins [0 - 15] on this controller map to pins [48 - 63] in the global pin - indexing space. - - port3: gpio-3 { - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&pinctrl 0 48 16>; - }; - - A device node willing to use pins controlled by this GPIO controller, shall - refer to it as follows: - - led1 { - gpios = <&port3 10 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml new file mode 100644 index 000000000000..7f80578dc229 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rza1-ports.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rza1-ports.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/A1 combined Pin and GPIO controller + +maintainers: + - Jacopo Mondi + - Geert Uytterhoeven + +description: + The Renesas SoCs of the RZ/A1 family feature a combined Pin and GPIO + controller, named "Ports" in the hardware reference manual. + Pin multiplexing and GPIO configuration is performed on a per-pin basis + writing configuration values to per-port register sets. + Each "port" features up to 16 pins, each of them configurable for GPIO + function (port mode) or in alternate function mode. + Up to 8 different alternate function modes exist for each single pin. + +properties: + compatible: + oneOf: + - const: renesas,r7s72100-ports # RZ/A1H + - items: + - const: renesas,r7s72101-ports # RZ/A1M + - const: renesas,r7s72100-ports # fallback + - const: renesas,r7s72102-ports # RZ/A1L + + reg: + maxItems: 1 + +required: + - compatible + - reg + +patternProperties: + "^gpio-[0-9]*$": + type: object + + description: + Each port of the r7s72100 pin controller hardware is itself a GPIO + controller. + Different SoCs have different numbers of available pins per port, but + generally speaking, each of them can be configured in GPIO ("port") mode + on this hardware. + Describe GPIO controllers using sub-nodes with the following properties. + + properties: + gpio-controller: true + + '#gpio-cells': + const: 2 + + gpio-ranges: + maxItems: 1 + + required: + - gpio-controller + - '#gpio-cells' + - gpio-ranges + + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + A pin multiplexing sub-node describes how to configure a set of (or a + single) pin in some desired alternate function mode. + A single sub-node may define several pin configurations. + A few alternate function require special pin configuration flags to be + supplied along with the alternate function configuration number. + The hardware reference manual specifies when a pin function requires + "software IO driven" mode to be specified. To do so use the generic + properties from the header + file to instruct the pin controller to perform the desired pin + configuration operation. + The hardware reference manual specifies when a pin has to be configured + to work in bi-directional mode and when the IO direction has to be + specified by software. Bi-directional pins must be managed by the pin + controller driver internally, while software driven IO direction has to + be explicitly selected when multiple options are available. + + properties: + pinmux: + description: | + Integer array representing pin number and pin multiplexing + configuration. + When a pin has to be configured in alternate function mode, use + this property to identify the pin by its global index, and provide + its alternate function configuration number along with it. + When multiple pins are required to be configured as part of the + same alternate function they shall be specified as members of the + same argument list of a single "pinmux" property. + Helper macros to ease assembling the pin index from its position + (port where it sits on and pin number) and alternate function + identifier are provided by the pin controller header file at: + + Integers values in "pinmux" argument list are assembled as: + ((PORT * 16 + PIN) | MUX_FUNC << 16) + + phandle: true + input-enable: true + output-enable: true + + required: + - pinmux + + additionalProperties: false + + - type: object + properties: + phandle: true + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + +examples: + - | + #include + pinctrl: pinctrl@fcfe3000 { + compatible = "renesas,r7s72100-ports"; + + reg = <0xfcfe3000 0x4230>; + + /* + * A GPIO controller node, controlling 16 pins indexed from 0. + * The GPIO controller base in the global pin indexing space is pin + * 48, thus pins [0 - 15] on this controller map to pins [48 - 63] + * in the global pin indexing space. + */ + port3: gpio-3 { + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + /* + * A serial communication interface with a TX output pin and an RX + * input pin. + * Pin #0 on port #3 is configured as alternate function #6. + * Pin #2 on port #3 is configured as alternate function #4. + */ + scif2_pins: serial2 { + pinmux = , ; + }; + + + /* + * I2c master: both SDA and SCL pins need bi-directional operations + * Pin #4 on port #1 is configured as alternate function #1. + * Pin #5 on port #1 is configured as alternate function #1. + * Both need to work in bi-directional mode, the driver must manage + * this internally. + */ + i2c2_pins: i2c2 { + pinmux = , ; + }; + + + /* + * Multi-function timer input and output compare pins. + */ + tioc0_pins: tioc0 { + /* + * Configure TIOC0A as software driven input + * Pin #0 on port #4 is configured as alternate function #2 + * with IO direction specified by software as input. + */ + tioc0_input_pins { + pinmux = ; + input-enable; + }; + + /* + * Configure TIOC0B as software driven output + * Pin #1 on port #4 is configured as alternate function #1 + * with IO direction specified by software as output. + */ + tioc0_output_pins { + pinmux = ; + output-enable; + }; + }; + }; From 5f76771a4a4514277f4618ba2fe20cb1d9ed5afd Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Fri, 21 Aug 2020 13:20:59 +0200 Subject: [PATCH 11/14] dt-bindings: pinctrl: rzn1: Convert to json-schema Convert the Renesas RZ/N1 Pin controller Device Tree binding documentation to json-schema. Use "pinctrl" generic node name. Drop generic and consumer examples, as they do not belong here. Signed-off-by: Geert Uytterhoeven Tested-by: Gareth Williams Reviewed-by: Gareth Williams Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20200821112059.5133-1-geert+renesas@glider.be --- .../bindings/pinctrl/renesas,rzn1-pinctrl.txt | 153 ------------------ .../pinctrl/renesas,rzn1-pinctrl.yaml | 129 +++++++++++++++ 2 files changed, 129 insertions(+), 153 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt deleted file mode 100644 index 25e53acd523e..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.txt +++ /dev/null @@ -1,153 +0,0 @@ -Renesas RZ/N1 SoC Pinctrl node description. - -Pin controller node -------------------- -Required properties: -- compatible: SoC-specific compatible string "renesas,-pinctrl" - followed by "renesas,rzn1-pinctrl" as fallback. The SoC-specific compatible - strings must be one of: - "renesas,r9a06g032-pinctrl" for RZ/N1D - "renesas,r9a06g033-pinctrl" for RZ/N1S -- reg: Address base and length of the memory area where the pin controller - hardware is mapped to. -- clocks: phandle for the clock, see the description of clock-names below. -- clock-names: Contains the name of the clock: - "bus", the bus clock, sometimes described as pclk, for register accesses. - -Example: - pinctrl: pin-controller@40067000 { - compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; - reg = <0x40067000 0x1000>, <0x51000000 0x480>; - clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; - clock-names = "bus"; - }; - -Sub-nodes ---------- - -The child nodes of the pin controller node describe a pin multiplexing -function. - -- Pin multiplexing sub-nodes: - A pin multiplexing sub-node describes how to configure a set of - (or a single) pin in some desired alternate function mode. - A single sub-node may define several pin configurations. - Please refer to pinctrl-bindings.txt to get to know more on generic - pin properties usage. - - The allowed generic formats for a pin multiplexing sub-node are the - following ones: - - node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - node-2 { - sub-node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - sub-node-2 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - ... - - sub-node-n { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - }; - - node-3 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - - sub-node-1 { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - - ... - - sub-node-n { - pinmux = , , ... ; - GENERIC_PINCONFIG; - }; - }; - - Use the latter two formats when pins part of the same logical group need to - have different generic pin configuration flags applied. Note that the generic - pinconfig in node-3 does not apply to the sub-nodes. - - Client sub-nodes shall refer to pin multiplexing sub-nodes using the phandle - of the most external one. - - Eg. - - client-1 { - ... - pinctrl-0 = <&node-1>; - ... - }; - - client-2 { - ... - pinctrl-0 = <&node-2>; - ... - }; - - Required properties: - - pinmux: - integer array representing pin number and pin multiplexing configuration. - When a pin has to be configured in alternate function mode, use this - property to identify the pin by its global index, and provide its - alternate function configuration number along with it. - When multiple pins are required to be configured as part of the same - alternate function they shall be specified as members of the same - argument list of a single "pinmux" property. - Integers values in the "pinmux" argument list are assembled as: - (PIN | MUX_FUNC << 8) - where PIN directly corresponds to the pl_gpio pin number and MUX_FUNC is - one of the alternate function identifiers defined in: - - These identifiers collapse the IO Multiplex Configuration Level 1 and - Level 2 numbers that are detailed in the hardware reference manual into a - single number. The identifiers for Level 2 are simply offset by 10. - Additional identifiers are provided to specify the MDIO source peripheral. - - Optional generic pinconf properties: - - bias-disable - disable any pin bias - - bias-pull-up - pull up the pin with 50 KOhm - - bias-pull-down - pull down the pin with 50 KOhm - - bias-high-impedance - high impedance mode - - drive-strength - sink or source at most 4, 6, 8 or 12 mA - - Example: - A serial communication interface with a TX output pin and an RX input pin. - - &pinctrl { - pins_uart0: pins_uart0 { - pinmux = < - RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */ - RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */ - >; - }; - }; - - Example 2: - Here we set the pull up on the RXD pin of the UART. - - &pinctrl { - pins_uart0: pins_uart0 { - pinmux = ; /* TXD */ - - pins_uart6_rx { - pinmux = ; /* RXD */ - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml new file mode 100644 index 000000000000..4a43af0d6e02 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzn1-pinctrl.yaml @@ -0,0 +1,129 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,rzn1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/N1 Pin Controller + +maintainers: + - Gareth Williams + - Geert Uytterhoeven + +properties: + compatible: + items: + - enum: + - renesas,r9a06g032-pinctrl # RZ/N1D + - renesas,r9a06g033-pinctrl # RZ/N1S + - const: renesas,rzn1-pinctrl # Generic RZ/N1 + + reg: + items: + - description: GPIO Multiplexing Level1 Register Block + - description: GPIO Multiplexing Level2 Register Block + + clocks: + maxItems: 1 + + clock-names: + const: bus + description: + The bus clock, sometimes described as pclk, for register accesses. + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: + anyOf: + - type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: + A pin multiplexing sub-node describes how to configure a set of (or a + single) pin in some desired alternate function mode. + A single sub-node may define several pin configurations. + + properties: + pinmux: + description: | + Integer array representing pin number and pin multiplexing + configuration. + When a pin has to be configured in alternate function mode, use + this property to identify the pin by its global index, and provide + its alternate function configuration number along with it. + When multiple pins are required to be configured as part of the + same alternate function they shall be specified as members of the + same argument list of a single "pinmux" property. + Integers values in the "pinmux" argument list are assembled as: + (PIN | MUX_FUNC << 8) + where PIN directly corresponds to the pl_gpio pin number and + MUX_FUNC is one of the alternate function identifiers defined in: + + These identifiers collapse the IO Multiplex Configuration Level 1 + and Level 2 numbers that are detailed in the hardware reference + manual into a single number. The identifiers for Level 2 are simply + offset by 10. Additional identifiers are provided to specify the + MDIO source peripheral. + + phandle: true + bias-disable: true + bias-pull-up: + description: Pull up the pin with 50 kOhm + bias-pull-down: + description: Pull down the pin with 50 kOhm + bias-high-impedance: true + drive-strength: + enum: [ 4, 6, 8, 12 ] + + required: + - pinmux + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + + - type: object + properties: + phandle: true + + additionalProperties: + $ref: "#/additionalProperties/anyOf/0" + +examples: + - | + #include + #include + pinctrl: pinctrl@40067000 { + compatible = "renesas,r9a06g032-pinctrl", "renesas,rzn1-pinctrl"; + reg = <0x40067000 0x1000>, <0x51000000 0x480>; + clocks = <&sysctrl R9A06G032_HCLK_PINCONFIG>; + clock-names = "bus"; + + /* + * A serial communication interface with a TX output pin and an RX + * input pin. + */ + pins_uart0: pins_uart0 { + pinmux = < + RZN1_PINMUX(103, RZN1_FUNC_UART0_I) /* UART0_TXD */ + RZN1_PINMUX(104, RZN1_FUNC_UART0_I) /* UART0_RXD */ + >; + }; + + /* + * Set the pull-up on the RXD pin of the UART. + */ + pins_uart0_alt: pins_uart0_alt { + pinmux = ; + + pins_uart6_rx { + pinmux = ; + bias-pull-up; + }; + }; + }; From 1308fb4e4eae14e6189dece3b7cf5b5f453c5d02 Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 9 Sep 2020 15:15:32 +0200 Subject: [PATCH 12/14] pinctrl: rzn1: Do not select GENERIC_PIN{CTRL_GROUPS,MUX_FUNCTIONS} The RZ/N1 pin control driver does not use pin groups or pin functions, so there is no need to select GENERIC_PINCTRL_GROUPS or GENERIC_PINMUX_FUNCTIONS. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200909131534.12897-2-geert+renesas@glider.be --- drivers/pinctrl/sh-pfc/Kconfig | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig index 2cff88684f36..9eb793cb464b 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/sh-pfc/Kconfig @@ -179,8 +179,6 @@ config PINCTRL_RZN1 bool "pin control support for RZ/N1" depends on OF depends on ARCH_RZN1 || COMPILE_TEST - select GENERIC_PINCTRL_GROUPS - select GENERIC_PINMUX_FUNCTIONS select GENERIC_PINCONF help This selects pinctrl driver for Renesas RZ/N1 devices. From 077365a941166f3a7f5894017f9d26d17cdec00e Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 9 Sep 2020 15:15:33 +0200 Subject: [PATCH 13/14] pinctrl: Rename sh-pfc to renesas The drivers/pinctrl/sh-pfc subdirectory was originally created to group pin control drivers for various Renesas SuperH and SH-Mobile platforms. However, the name "sh-pfc" no longer reflects its contents, as the directory now contains pin control drivers for Renesas SuperH, ARM32, and ARM64 SoCs. Hence rename the subdirectory from drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas, and the related Kconfig symbol from PINCTRL_SH_PFC to PINCTRL_RENESAS. Rename the git branch in MAINTAINERS, too, for consistency. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be --- MAINTAINERS | 4 ++-- drivers/pinctrl/Kconfig | 2 +- drivers/pinctrl/Makefile | 2 +- drivers/pinctrl/{sh-pfc => renesas}/Kconfig | 2 +- drivers/pinctrl/{sh-pfc => renesas}/Makefile | 4 ++-- drivers/pinctrl/{sh-pfc => renesas}/core.c | 0 drivers/pinctrl/{sh-pfc => renesas}/core.h | 0 drivers/pinctrl/{sh-pfc => renesas}/gpio.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-emev2.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a73a4.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7740.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77470.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7778.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7779.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7790.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7791.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7792.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7794.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77950.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77951.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7796.c | 2 +- drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77965.c | 2 +- drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77970.c | 2 +- drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77980.c | 2 +- drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77990.c | 2 +- drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77995.c | 2 +- drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7203.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7264.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7269.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh73a0.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7720.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7722.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7723.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7724.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7734.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7757.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7785.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7786.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pfc-shx3.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pinctrl-rza1.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pinctrl-rza2.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pinctrl-rzn1.c | 0 drivers/pinctrl/{sh-pfc => renesas}/pinctrl.c | 0 drivers/pinctrl/{sh-pfc => renesas}/sh_pfc.h | 0 44 files changed, 13 insertions(+), 13 deletions(-) rename drivers/pinctrl/{sh-pfc => renesas}/Kconfig (99%) rename drivers/pinctrl/{sh-pfc => renesas}/Makefile (96%) rename drivers/pinctrl/{sh-pfc => renesas}/core.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/core.h (100%) rename drivers/pinctrl/{sh-pfc => renesas}/gpio.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-emev2.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a73a4.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7740.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77470.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7778.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7779.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7790.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7791.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7792.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7794.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77950.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77951.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a7796.c (99%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77965.c (99%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77970.c (99%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77980.c (99%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77990.c (99%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-r8a77995.c (99%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7203.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7264.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7269.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh73a0.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7720.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7722.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7723.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7724.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7734.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7757.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7785.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-sh7786.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pfc-shx3.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pinctrl-rza1.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pinctrl-rza2.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pinctrl-rzn1.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/pinctrl.c (100%) rename drivers/pinctrl/{sh-pfc => renesas}/sh_pfc.h (100%) diff --git a/MAINTAINERS b/MAINTAINERS index 73242e16e327..02c149ce75c8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13688,9 +13688,9 @@ PIN CONTROLLER - RENESAS M: Geert Uytterhoeven L: linux-renesas-soc@vger.kernel.org S: Supported -T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git sh-pfc +T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git renesas-pinctrl F: Documentation/devicetree/bindings/pinctrl/renesas,* -F: drivers/pinctrl/sh-pfc/ +F: drivers/pinctrl/renesas/ PIN CONTROLLER - SAMSUNG M: Tomasz Figa diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index f63c5a04a3f7..6ca1a6fc9756 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -383,8 +383,8 @@ source "drivers/pinctrl/nomadik/Kconfig" source "drivers/pinctrl/nuvoton/Kconfig" source "drivers/pinctrl/pxa/Kconfig" source "drivers/pinctrl/qcom/Kconfig" +source "drivers/pinctrl/renesas/Kconfig" source "drivers/pinctrl/samsung/Kconfig" -source "drivers/pinctrl/sh-pfc/Kconfig" source "drivers/pinctrl/spear/Kconfig" source "drivers/pinctrl/sprd/Kconfig" source "drivers/pinctrl/stm32/Kconfig" diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 1da9f28aecbd..113be648658f 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -59,8 +59,8 @@ obj-y += nomadik/ obj-$(CONFIG_ARCH_NPCM7XX) += nuvoton/ obj-$(CONFIG_PINCTRL_PXA) += pxa/ obj-$(CONFIG_ARCH_QCOM) += qcom/ +obj-$(CONFIG_PINCTRL_RENESAS) += renesas/ obj-$(CONFIG_PINCTRL_SAMSUNG) += samsung/ -obj-$(CONFIG_PINCTRL_SH_PFC) += sh-pfc/ obj-$(CONFIG_PINCTRL_SPEAR) += spear/ obj-y += sprd/ obj-$(CONFIG_PINCTRL_STM32) += stm32/ diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/renesas/Kconfig similarity index 99% rename from drivers/pinctrl/sh-pfc/Kconfig rename to drivers/pinctrl/renesas/Kconfig index 9eb793cb464b..fc1f2611063b 100644 --- a/drivers/pinctrl/sh-pfc/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -5,7 +5,7 @@ menu "Renesas pinctrl drivers" -config PINCTRL_SH_PFC +config PINCTRL_RENESAS bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH) default y if ARCH_RENESAS || SUPERH select PINMUX diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/renesas/Makefile similarity index 96% rename from drivers/pinctrl/sh-pfc/Makefile rename to drivers/pinctrl/renesas/Makefile index 0b5640cf457b..c96008c9ab59 100644 --- a/drivers/pinctrl/sh-pfc/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o +obj-$(CONFIG_PINCTRL_RENESAS) += core.o pinctrl.o obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o -obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o +obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o obj-$(CONFIG_PINCTRL_PFC_R8A7742) += pfc-r8a7790.o diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/renesas/core.c similarity index 100% rename from drivers/pinctrl/sh-pfc/core.c rename to drivers/pinctrl/renesas/core.c diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/renesas/core.h similarity index 100% rename from drivers/pinctrl/sh-pfc/core.h rename to drivers/pinctrl/renesas/core.h diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/renesas/gpio.c similarity index 100% rename from drivers/pinctrl/sh-pfc/gpio.c rename to drivers/pinctrl/renesas/gpio.c diff --git a/drivers/pinctrl/sh-pfc/pfc-emev2.c b/drivers/pinctrl/renesas/pfc-emev2.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-emev2.c rename to drivers/pinctrl/renesas/pfc-emev2.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/renesas/pfc-r8a73a4.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a73a4.c rename to drivers/pinctrl/renesas/pfc-r8a73a4.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/renesas/pfc-r8a7740.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a7740.c rename to drivers/pinctrl/renesas/pfc-r8a7740.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77470.c b/drivers/pinctrl/renesas/pfc-r8a77470.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a77470.c rename to drivers/pinctrl/renesas/pfc-r8a77470.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/renesas/pfc-r8a7778.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a7778.c rename to drivers/pinctrl/renesas/pfc-r8a7778.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/renesas/pfc-r8a7779.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a7779.c rename to drivers/pinctrl/renesas/pfc-r8a7779.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/renesas/pfc-r8a7790.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a7790.c rename to drivers/pinctrl/renesas/pfc-r8a7790.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/renesas/pfc-r8a7791.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a7791.c rename to drivers/pinctrl/renesas/pfc-r8a7791.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7792.c b/drivers/pinctrl/renesas/pfc-r8a7792.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a7792.c rename to drivers/pinctrl/renesas/pfc-r8a7792.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7794.c b/drivers/pinctrl/renesas/pfc-r8a7794.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a7794.c rename to drivers/pinctrl/renesas/pfc-r8a7794.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77950.c b/drivers/pinctrl/renesas/pfc-r8a77950.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a77950.c rename to drivers/pinctrl/renesas/pfc-r8a77950.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77951.c b/drivers/pinctrl/renesas/pfc-r8a77951.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-r8a77951.c rename to drivers/pinctrl/renesas/pfc-r8a77951.c diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c b/drivers/pinctrl/renesas/pfc-r8a7796.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a7796.c rename to drivers/pinctrl/renesas/pfc-r8a7796.c index a2496baca85d..55f0344a3d3e 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c +++ b/drivers/pinctrl/renesas/pfc-r8a7796.c @@ -4,7 +4,7 @@ * * Copyright (C) 2016-2019 Renesas Electronics Corp. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c * * R-Car Gen3 processor support - PFC hardware block. * diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c b/drivers/pinctrl/renesas/pfc-r8a77965.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a77965.c rename to drivers/pinctrl/renesas/pfc-r8a77965.c index 6616f5210b9d..7a50b9b69a7d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77965.c +++ b/drivers/pinctrl/renesas/pfc-r8a77965.c @@ -5,7 +5,7 @@ * Copyright (C) 2018 Jacopo Mondi * Copyright (C) 2016-2019 Renesas Electronics Corp. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c * * R-Car Gen3 processor support - PFC hardware block. * diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c b/drivers/pinctrl/renesas/pfc-r8a77970.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a77970.c rename to drivers/pinctrl/renesas/pfc-r8a77970.c index 9f7d9c9238fc..e8a0fc468eb2 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77970.c +++ b/drivers/pinctrl/renesas/pfc-r8a77970.c @@ -5,7 +5,7 @@ * Copyright (C) 2016 Renesas Electronics Corp. * Copyright (C) 2017 Cogent Embedded, Inc. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c * * R-Car Gen3 processor support - PFC hardware block. * diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c b/drivers/pinctrl/renesas/pfc-r8a77980.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a77980.c rename to drivers/pinctrl/renesas/pfc-r8a77980.c index 1055f9853404..ebd07bebaeeb 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77980.c +++ b/drivers/pinctrl/renesas/pfc-r8a77980.c @@ -5,7 +5,7 @@ * Copyright (C) 2018 Renesas Electronics Corp. * Copyright (C) 2018 Cogent Embedded, Inc. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7795.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7795.c * * R-Car Gen3 processor support - PFC hardware block. * diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c b/drivers/pinctrl/renesas/pfc-r8a77990.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a77990.c rename to drivers/pinctrl/renesas/pfc-r8a77990.c index c926a59dd21c..aed04a4c6116 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77990.c +++ b/drivers/pinctrl/renesas/pfc-r8a77990.c @@ -4,7 +4,7 @@ * * Copyright (C) 2018-2019 Renesas Electronics Corp. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c * * R8A7796 processor support - PFC hardware block. * diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c b/drivers/pinctrl/renesas/pfc-r8a77995.c similarity index 99% rename from drivers/pinctrl/sh-pfc/pfc-r8a77995.c rename to drivers/pinctrl/renesas/pfc-r8a77995.c index c10b756476b1..672251d86c2d 100644 --- a/drivers/pinctrl/sh-pfc/pfc-r8a77995.c +++ b/drivers/pinctrl/renesas/pfc-r8a77995.c @@ -4,7 +4,7 @@ * * Copyright (C) 2017 Renesas Electronics Corp. * - * This file is based on the drivers/pinctrl/sh-pfc/pfc-r8a7796.c + * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c * * R-Car Gen3 processor support - PFC hardware block. * diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/renesas/pfc-sh7203.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7203.c rename to drivers/pinctrl/renesas/pfc-sh7203.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/renesas/pfc-sh7264.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7264.c rename to drivers/pinctrl/renesas/pfc-sh7264.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/renesas/pfc-sh7269.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7269.c rename to drivers/pinctrl/renesas/pfc-sh7269.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/renesas/pfc-sh73a0.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh73a0.c rename to drivers/pinctrl/renesas/pfc-sh73a0.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/renesas/pfc-sh7720.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7720.c rename to drivers/pinctrl/renesas/pfc-sh7720.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/renesas/pfc-sh7722.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7722.c rename to drivers/pinctrl/renesas/pfc-sh7722.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/renesas/pfc-sh7723.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7723.c rename to drivers/pinctrl/renesas/pfc-sh7723.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/renesas/pfc-sh7724.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7724.c rename to drivers/pinctrl/renesas/pfc-sh7724.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/renesas/pfc-sh7734.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7734.c rename to drivers/pinctrl/renesas/pfc-sh7734.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/renesas/pfc-sh7757.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7757.c rename to drivers/pinctrl/renesas/pfc-sh7757.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/renesas/pfc-sh7785.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7785.c rename to drivers/pinctrl/renesas/pfc-sh7785.c diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/renesas/pfc-sh7786.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-sh7786.c rename to drivers/pinctrl/renesas/pfc-sh7786.c diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/renesas/pfc-shx3.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pfc-shx3.c rename to drivers/pinctrl/renesas/pfc-shx3.c diff --git a/drivers/pinctrl/sh-pfc/pinctrl-rza1.c b/drivers/pinctrl/renesas/pinctrl-rza1.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pinctrl-rza1.c rename to drivers/pinctrl/renesas/pinctrl-rza1.c diff --git a/drivers/pinctrl/sh-pfc/pinctrl-rza2.c b/drivers/pinctrl/renesas/pinctrl-rza2.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pinctrl-rza2.c rename to drivers/pinctrl/renesas/pinctrl-rza2.c diff --git a/drivers/pinctrl/sh-pfc/pinctrl-rzn1.c b/drivers/pinctrl/renesas/pinctrl-rzn1.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pinctrl-rzn1.c rename to drivers/pinctrl/renesas/pinctrl-rzn1.c diff --git a/drivers/pinctrl/sh-pfc/pinctrl.c b/drivers/pinctrl/renesas/pinctrl.c similarity index 100% rename from drivers/pinctrl/sh-pfc/pinctrl.c rename to drivers/pinctrl/renesas/pinctrl.c diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/renesas/sh_pfc.h similarity index 100% rename from drivers/pinctrl/sh-pfc/sh_pfc.h rename to drivers/pinctrl/renesas/sh_pfc.h From 540d9757cea8274a44d69cbadcff5b8c381bae8d Mon Sep 17 00:00:00 2001 From: Geert Uytterhoeven Date: Wed, 9 Sep 2020 15:15:34 +0200 Subject: [PATCH 14/14] pinctrl: renesas: Reintroduce SH_PFC for common sh-pfc code Most, but not all, Renesas pin control drivers use the "sh-pfc" pin control framework. As of commit 8449bfa9e6a9f7ec ("pinctrl: sh-pfc: Collect Renesas related CONFIGs in one place"), the code for this framework is always built when Renesas SoC pin control support is enabled, regardless of whether the enabled pin control drivers need it or not. Fix this by reintroducing the CONFIG_SH_PFC symbol to control inclusion of the "sh-pfc" framework and its dependencies, and selecting it when needed. This reduces kernel size of a typical RZ/A1 or RZ/A2 kernel by more than 6 resp. 11 KiB. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20200909131534.12897-4-geert+renesas@glider.be --- drivers/pinctrl/renesas/Kconfig | 52 ++++++++++++++++++++++++++------ drivers/pinctrl/renesas/Makefile | 2 +- 2 files changed, 43 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig index fc1f2611063b..e941b8440dbc 100644 --- a/drivers/pinctrl/renesas/Kconfig +++ b/drivers/pinctrl/renesas/Kconfig @@ -8,9 +8,6 @@ menu "Renesas pinctrl drivers" config PINCTRL_RENESAS bool "Renesas SoC pin control support" if COMPILE_TEST && !(ARCH_RENESAS || SUPERH) default y if ARCH_RENESAS || SUPERH - select PINMUX - select PINCONF - select GENERIC_PINCONF select PINCTRL_PFC_EMEV2 if ARCH_EMEV2 select PINCTRL_PFC_R8A73A4 if ARCH_R8A73A4 select PINCTRL_PFC_R8A7740 if ARCH_R8A7740 @@ -55,68 +52,95 @@ config PINCTRL_RENESAS help This enables pin control drivers for Renesas SuperH and ARM platforms -config PINCTRL_SH_PFC_GPIO - select GPIOLIB +config PINCTRL_SH_PFC bool + select GENERIC_PINCONF + select PINMUX + select PINCONF + help + This enables common pin control functionality for EMMA Mobile, R-Car, + R-Mobile, RZ/G, SH, and SH-Mobile platforms. + +config PINCTRL_SH_PFC_GPIO + bool + select GPIOLIB + select PINCTRL_SH_PFC help This enables pin control and GPIO drivers for SH/SH Mobile platforms config PINCTRL_SH_FUNC_GPIO - select PINCTRL_SH_PFC_GPIO bool + select PINCTRL_SH_PFC_GPIO help This enables legacy function GPIOs for SH platforms config PINCTRL_PFC_EMEV2 bool "pin control support for Emma Mobile EV2" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77995 bool "pin control support for R-Car D3" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7794 bool "pin control support for R-Car E2" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77990 bool "pin control support for R-Car E3" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7779 bool "pin control support for R-Car H1" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7790 bool "pin control support for R-Car H2" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77950 bool "pin control support for R-Car H3 ES1.x" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77951 bool "pin control support for R-Car H3 ES2.0+" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7778 bool "pin control support for R-Car M1A" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7793 bool "pin control support for R-Car M2-N" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7791 bool "pin control support for R-Car M2-W" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77965 bool "pin control support for R-Car M3-N" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77960 bool "pin control support for R-Car M3-W" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77961 bool "pin control support for R-Car M3-W+" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7792 bool "pin control support for R-Car V2H" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77980 bool "pin control support for R-Car V3H" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A77970 bool "pin control support for R-Car V3M" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7740 bool "pin control support for R-Mobile A1" if COMPILE_TEST @@ -130,10 +154,10 @@ config PINCTRL_RZA1 bool "pin control support for RZ/A1" depends on OF depends on ARCH_R7S72100 || COMPILE_TEST - select GPIOLIB + select GENERIC_PINCONF select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF + select GPIOLIB help This selects pinctrl driver for Renesas RZ/A1 platforms. @@ -141,39 +165,47 @@ config PINCTRL_RZA2 bool "pin control support for RZ/A2" depends on OF depends on ARCH_R7S9210 || COMPILE_TEST - select GPIOLIB select GENERIC_PINCTRL_GROUPS select GENERIC_PINMUX_FUNCTIONS - select GENERIC_PINCONF + select GPIOLIB help This selects GPIO and pinctrl driver for Renesas RZ/A2 platforms. config PINCTRL_PFC_R8A77470 bool "pin control support for RZ/G1C" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7745 bool "pin control support for RZ/G1E" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7742 bool "pin control support for RZ/G1H" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7743 bool "pin control support for RZ/G1M" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A7744 bool "pin control support for RZ/G1N" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A774C0 bool "pin control support for RZ/G2E" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A774E1 bool "pin control support for RZ/G2H" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A774A1 bool "pin control support for RZ/G2M" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_PFC_R8A774B1 bool "pin control support for RZ/G2N" if COMPILE_TEST + select PINCTRL_SH_PFC config PINCTRL_RZN1 bool "pin control support for RZ/N1" diff --git a/drivers/pinctrl/renesas/Makefile b/drivers/pinctrl/renesas/Makefile index c96008c9ab59..1f6d7dd019d8 100644 --- a/drivers/pinctrl/renesas/Makefile +++ b/drivers/pinctrl/renesas/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PINCTRL_RENESAS) += core.o pinctrl.o +obj-$(CONFIG_PINCTRL_SH_PFC) += core.o pinctrl.o obj-$(CONFIG_PINCTRL_SH_PFC_GPIO) += gpio.o obj-$(CONFIG_PINCTRL_PFC_EMEV2) += pfc-emev2.o obj-$(CONFIG_PINCTRL_PFC_R8A73A4) += pfc-r8a73a4.o